X40620 64K Dual Voltage CPU Supervisor with 64K Serial EEPROM FEATURES • Dual Voltage Detection and Reset Assertion —Three standard reset threshold settings. (3.1V/ 2.6V, 3.1V/1.7V, 2.9V/2.3V) —Adjust low voltage reset threshold voltages using special programming sequence —RESET signal valid down to VCC=1V • Watchdog Timer (150ms) • Power On Reset (150ms) • Low Power CMOS —10µA typical standby current, watchdog on —400µA typical standby current, watchdog off • 64kbit 2-Wire Serial EEPROM —1MHz serial interface speed —64-byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • 2.5 to 3.7V Power Supply Operation • 8-Lead TSSOP package DESCRIPTION The X40620 combines several functions into one device. The first is a dual voltage monitoring, power-on reset control, watchdog timer and 64Kbit serial EEPROM memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum Vtrip point. RESET is active until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit (V2MON) tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. When the second monitored voltage drops below a preset V2TRIP voltage. V2FAIL is active until V2 returns to proper operating level and above the V2TRIP voltage. Five common low voltage combinations are available, however, Xicor’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM WP Watchdog Timer Reset Write Control Logic SCL SDA Command Decode and Control Logic X Decoder HV Generation Timing and Control EEPROM Array (64Kbits) Reset & Watchdog Timebase RESET Power on and Low Voltage Reset Generation V2FAIL V2MON + - (VCC) Control Signal Y Decoder Data Register + - Xicor, Inc. 2000 Patents Pending 9900-3003.5 5/4/00 EP Powered by ICminer.com Electronic-Library Service CopyRight 2003 V2TRIP VCC VTRIP Characteristics subject to change without notice. 1 of 17 X40620 PACKAGE/PINOUTS 8L TSSOP VSS 1 8 VCC WP 2 7 SDA 3 V2MON SCL RESET 4 6 5 V2FAIL PIN NAMES VSS SDA VCC SCL WP V2MON RESET V2FAIL Ground Serial Data Power Serial Clock Write Protect Voltage monitor input Low Voltage Detect Output V2 Voltage Fail Output PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with other open drain or open collector outputs. An open drain requires the use of a pull-up resistor. Write Protect (WP) The WP pin should be tied HIGH at all time. (This WP pin is reserved for internal factory testing only). Reset Output (RESET) RESET is an active LOW, open drain output which goes active whenever VCC falls below the minimum Vtrip sense level. It will remain active until VCC rises above the minimum Vtrip sense level for 150ms. RESET goes active if the Watchdog Timer is enabled and there is no start bit before the end of the selectable Watchdog time-out period. A serial start bit will reset the Watchdog Timer. RESET also goes active on power up at 1V and remains active for 150ms after the power supply stabilizes. V2 Voltage Fail Output (V2FAIL) V2FAIL is an active LOW, open drain output which goes active whenever V2MON falls below the minimum V2trip sense level. It will remain active until V2MON rises above the minimum V2MON sense level. DEVICE OPERATION Power On Reset Application of power to the X40620 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET allowing the processor to begin executing code. Low Voltage VCC (V1) Monitoring During operation, the X40620 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. When the internal low voltage detect circuitry senses that VCC is low, the following happens: – The RESET pin goes active. – Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to complete the operation. The low VCC threshold is typically set to 3.1V for a 2.5 to 3.7V operating range. LOW VOLTAGE V2 MONITORING The X40620 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum V2TRIP. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. The V2FAIL signal remains active until the VCC drops below 1V. It also remains active until V2MON returns and exceeds V2TRIP by 0.2V Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 of 17 X40620 When the internal low voltage detect circuitry senses that V2MON is low, the V2FAIL pin goes active. Typically this would be used by the processor as an interrupt to stop the execution of the code or to do housekeeping in preparation for an impending power failure. The basic method of communication to the memory areas of the device is established by generating a start condition, then transmitting a command, followed by the address. The user must perform ACK Polling to determine the validity of the address, before starting a data transfer (see Acknowledge Polling.) The RESET and V2FAIL signals remain active until VCC voltage drops below 1V. RESET remains active until VCC returns and exceeds VTRIP for 200ms. V2FAIL remains active until immediately after V2MON returns and exceeds it’s minimum voltage. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. µC Volt Reg VCC OTP Mode Enabled Pin 1 VCC VSS V2MON WP SCL SDA RESET V2FAIL If the X40620 is in a nonvolatile write cycle a “no ACK” (SDA=HIGH) response will be issued in response to loading of the command byte. If a stop is issued prior to the start of a nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. SCL After each transaction is completed, the X40620 will reset and enter into a standby mode. SDA Figure 1. X40620 Device Operation INTR RESET Recommended Connection Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the Start bit. The microprocessor must send a start bit periodically to prevent a RESET signal. The start bit must occur prior to the expiration of the watchdog time-out period. The watchdog timer period is set at 150msec. SERIAL MEMORY OPERATION Load Command Byte Load 2 Byte Address Read/Write Data Bytes TWC or Data ACK Polling There are two primary modes of operation for the X40620; READ and WRITE of the memory arrays. Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 of 17 X40620 Figure 2. Set VTRIP Level Sequence (VCC ≥ VTRIP) VCC VTRIP VP = 15V RESET 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 D8h 00h 01h 01h sets VCC 0 1 2 3 4 5 6 7 SCL SDA 00h Figure 3. Set V2TRIP Level Sequence (VCC ≥ V2TRIP) V2TRIP V2MON VP = 15V RESET 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCL SDA D8h 0Dh 0Dh sets V2MON 00h 00h Figure 4. Reset VTRIP Level Sequence (VCC > 3V, WEL is set.) VCC VTRIP VP = 15V RESET 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCL SDA D8h 00h 03h 03h resets VCC 00h Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 of 17 X40620 Figure 5. Reset V2TRIP Level Sequence (VCC > 3V, WEL is set.) VCC VTRIP VP = 15V RESET 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCL SDA D8h 00h VCC AND V2MON THRESHOLD RESET PROCEDURE The X40620 is shipped with standard VTRIP and V2TRIP voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40620 trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP,V2TRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new voltages, apply the desired VTRIP threshold voltage to the VCC pin, the V2TRIP voltage to the V2MON pin, then tie the RESET pin to the programming voltage VP. Then, write data 01h or 0Dh at address 00h 03h 03h resets VCC 00h to program VTRIP, V2TRIP respectively. The stop bit following a valid write operation initiates the programming sequence. Bring RESET LOW to complete the operation. Note: this operation also writes 01h or 0Dh to address 00h. Resetting the VTRIP Voltage This procedure is used to set the VTRIP, the V2TRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When the threshold is reset, the new level is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the new VTRIP, V2TRIP voltage, apply the desired VTRIP or V2TRIP threshold voltage to the VCCor V2MON pin, respectively, and tie the RESET pin to the programming voltage VP. Then write 03h or 0Fh to address 00h. The stop bit of a valid write operation initiates the programming sequence. Bring RESET LOW to complete the operation. Note: this operation also writes 03h or 0Fh to address 00h of the EEPROM array. Figure 6. Sample VTRIP Reset Circuit VP Adjust V2FAIL RESET VTRIP Adj. 5 4 2 7 X40620 6 1 V2TRIP Adj. 4.7K µC 8 3 Run SCL SDA Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 of 17 X40620 VTRIP/V2TRIP Programming Execute Reset VTRIP/V2TRIP Sequence Set VCC = VCC Applied = Desired VTRIP OR Set V2MON = V2MON Applied = Desired V2TRIP, VCC>=V2Trip Execute Set VTRIP, V2TRIP Sequence New VCC or V2MON Applied = Old VCC V2MON Applied + Error New VCC/V2MON Applied = Old VCC Applied—Error Recycle VCC Power Execute Reset V2TRIP, VTRIP Sequence Apply 5V to VCC or V2MON Decrement VCC or V2MON (<50mV Step) NO RESET or V2FAIL pin goes active? YES Error < 0 Measured V(2)TRIP Desired V(2)TRIP Error > 0 Error = 0 DONE Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 of 17 X40620 Device Protocol The X40620 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X40620 will be considered a slave in all applications. After each byte written to or read from the X40620, the address pointer is incremented by 1. This allows the user to read from the entire device after sending only a single address. It also allows an entire page to be written in one operation. An exception to this address incrementation occurs during a read. After reading address 1FFFh the device goes into an idle mode, so additional reads return all “1s”. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 7 and Figure 8. Start Condition All commands are preceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X40620 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. A start bit generated while the part is outputting data is accepted as a start as long as the device is not outputting a ’zero’. Stop Condition All communications are be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are recognized while the device outputs data, as long as the data output is not a ‘zero’. Figure 7. Data Validity SCL SDA Data Stable Data Change Figure 8. Definition of Start and Stop Conditions SCL SDA Start Condition Stop Condition Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. The X40620 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X40620 will respond with an acknowledge after the receipt of each subsequent eight-bit word. Table 1. X40620 Instruction Set 1st Byte after Start 1st Byte after Command 2nd Byte after Command Command Description 1100 1000 High Address Low address Memory Array Read 1101 1000 High Address Low address Memory Array Write Notes: Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode. Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 of 17 X40620 PROGRAM OPERATIONS (or more) may be transferred. Sending more than 64 bytes results in data wrapping and over-writing previous data. After the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. Memory Array Programming The memory array program mode requires issuing the 8-bit Write command followed by the address and then the data bytes transferred as illustrated in Figure 9. Up to 64 bytes Data 63 Data 0 A7 A6 A5 A4 A3 A2 A1 A0 STOP Write Command A15 A14 A13 A12 A11 A10 A9 A8 SDA S ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X40620 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8 bits (1st byte of the protocol.) If the X40620 is still busy with the nonvolatile write operation, it will issue a “no-ACK” in response. If the nonvolatile write operation has completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol. ACK ACK ACK ACK ACK ••• ACK START Figure 9. Memory Array Programming Wait tWC S Data ACK Polling Data ACK Polling Sequence Write Sequence Completed Enter Ack Polling Issue Start Issue New Command Code ACK Returned? NO YES Proceed Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 of 17 X40620 Figure 10. Acknowledge Polling SCL 8th CLK SDA ‘ACK’ CLK 8th CLK ‘ACK’ 8th Bit ‘ACK’ CLK Start Condition MEMORY READ OPERATIONS ACK or no ACK sequential, with the data from address n followed by the data from n+1. The address counter for read operations increments all address bits, allowing the entire memory array contents to be serially read during one operation. At the end of the address space (address 1FFFh) the device goes into an idle state and a new read sequence must be initiated to continue reading at another address. Refer to Figure 12 for the address, acknowledge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been read, the host sends a stop condition with or without a preceding acknowledge. Memory read operations are initiated in the same manner as write operations but with a different command code. Random Read The master issues the start condition, then a Read instruction, then issues the word address. Once the first byte has been read, another start can be issued followed by a new 8-bit address. See Figure 11. Sequential Read The host can read sequentially within the memory array after receiving the Read Command and an address within the address space. The data output is STOP S S ACK ACK ACK ACK SDA S START A7 A6 A5 A4 A3 A2 A1 A0 Read Command A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 START Figure 11. Random Read Data 0 Data 0 STOP ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK Read Command A15 A14 A13 A12 A11 A10 A9 A8 START Figure 12. Sequential Read SDA S ACK ACK ACK S Data 0 Data X Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 of 17 X40620 ABSOLUTE MAXIMUM RATINGS listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature under bias ................... –65°c to +135°C Storage temperature ........................–65°C to +150°C Voltage on any pin with respect to VSS ..... –1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C RECOMMENDED OPERATING CONDITIONS COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those Temp Min. Max. Commercial 0°C +70°C Extended –20°C +85°C Device Supply Voltage Limits X40620 2.5V to 3.7V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Min. Limits Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA ICC2(3) VCC Supply Current (Write) 3 mA ISB1(1) VCC Supply Current (Standby) 50 µA ISB2(1) VCC Supply Current (Standby) 1 µA ILI ILO VIL1(2) VIH1(2) VIL2(2) VIH2(2) VOL Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage fSCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor V2MON = VCC fSCL = 1MHz, RESET = V2FAIL = VCC w/ pull up resistor RST = VSS VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 1MHz, fSDA = 400 KHz VSDA = VSCL = V2MON = VCC Other = GND or VCC–0.3V VIN = VSS to VCC VOUT = VSS to VCC VCC = 3.0V VCC = 3.0V VCC = 3.0V VCC = 3.0V IOL = 3mA 10 10 –0.5 VCC x 0.3 VCC x 0.7 VCC + 0.5 –0.5 VCC x 0.1 VCC x 0.9 VCC + 0.5 0.4 µA µA V V V V V CAPACITANCE (TA = +25°C, F = 1MHZ, VCC = 3V) Symbol (3) COUT CIN(3) Test Max. Units Conditions Output Capacitance (SDA) Input Capacitance (WP, SCL, V2MON) 8 6 pF pF VI/O = 0V VIN = 0V Notes: (1) Must perform a stop command after a read command prior to measurement (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 of 17 X40620 EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS 3V 1.3KΩ Output Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Output load 100pF 100pF AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions) Symbol fSCL Parameter Min. SCL Clock Frequency Typ.(1) 0 Max. Units 1000 KHz 0.55 µs tIN Pulse width of spikes which must be suppressed by the input filter tAA SCL LOW to SDA Data Out Valid 0.05 10 ns tBUF Time the bus must be free before a new transmit can start 0.5 µs tLOW Clock LOW Time 0.6 µs tHIGH Clock HIGH Time 0.4 µs tSU:STA Start Condition Setup Time 0.25 µs tHD:STA Start Condition Hold Time 0.25 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.25 µs Data Output Hold Time 0 tR SDA and SCL Rise Time (10% to 90% of VCC) 10 100 ns tF SDA and SCL Fall Time 10 100 ns tDH 100 ns RESET AC SPECIFICATIONS Nonvolatile Write Cycle Timing Symbol (1) tWC Parameter Write Cycle Time Min. Typ.(1) Max. Units 5 10 mS Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 of 17 X40620 TIMING DIAGRAMS Bus Timing tR tHIGH tF SCL tLOW tSU:DAT tSU:STA tHD:DAT tHD:STA SDA IN tSU:STO tAA tDH tBUF SDA OUT Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition Start Condition GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS 100ns Max Rise Time Pull Up Resistance in KΩ R 10 V – 0.4 CCMAX = ----------------------------------------- = 1100 Ω I OLMIN – t RMAX --------------------------------------- R PMAX C BUS V IH = Vcc 1 – e 8 6 MIN RPMAX 4 For VIH = 0.9VCC 2 RMIN 10 20 30 40 50 R t R = ------------------------------PMAX 2.3 ( C ) BUS Bus capacitance in pF tRMAX = maximum allowable SDA rise time Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 of 17 X40620 POWER-UP AND POWER-DOWN TIMING RESET Output Timing VVTRIP VVTRIP VCC tPURST 0 Volts tPURST tFV tRV tDVC RESET V2FAIL Output Timing V2MON V2TRIP 0 Volts V2TRIP tRB tFB tDVB V2FAIL Symbol Parameter Min. Typ. Max. Units VTRIP RESET Trip Point Voltage 2.4 – 3.5 V V2TRIP V2FAIL Trip Point Voltage 1.7 – 3.5 V VTH VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 40 mV V2TA V2TRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 40 mV tPURST Power-up Reset Timeout 225 ms tDVC(5) Detect VCC Low Voltage to Reset Output (VCC = 2.3V) 65 µs Detect V2MON Low Voltage to Reset Output (VCC = 2.5-3.7V) 100 µs (5) tDVB 75 150 (5) VCC Fall Time 100 µs (5) VCC Rise Time 100 µs (5) V2MON Fall Time 500 ns (5) V2MON Rise Time 500 ns 1 V tFV tRV tFB tRB VRVALID Reset Valid VCC Notes: (5) This parameter is periodically sampled and not 100% tested. (6) Typical values not tested. Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 13 of 17 X40620 Start Bit vs. RESET Timing SCL tSU:STO tSU:STA SDA tWDR RESET tWDO tRST tWDO tRST RESET Output Timing Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period 75 150 225 ms tWDR SDA LOW duration (Reset the Watchdog) 400 tRST Reset Timeout 75 150 225 ms ns Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 of 17 X40620 PACKAGING INFORMATION 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° – 8° Seating Plane .019 (.50) .029 (.75) (4.16) (7.72) Detail A (20X) (1.78) .031 (.80) .041 (1.05) (0.42) (0.65) All Measurements Are Typical See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 15 of 17 X40620 Ordering Information VCC Range VTRIP V2TRIP Package 2.5–3.7V 3.1 2.6 8L TSSOP 2.5–3.7V 2.5–3.7V 3.1 2.9 1.7 2.3 8L TSSOP 8L TSSOP Operating Temperature Range Part Number 0°C–70°C X40620V8-3.1 -20°C–85°C X40620V8E-3.1 0°C–70°C X40620V8-3.1A -20°C–85°C X40620V8E3.1A 0°C–70°C X40620V8-2.9 -20°C–85°C X40620V8E-2.9 Notes: Tolerance for VTRIP and V2TRIP are +/-5% Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 of 17 X40620 Part Mark Convention 8-Lead TSSOP EYWW XXXX XX 4062 AR = 4062 AS = 4062 AT = 4062 AU = 4062 AV = 4062 AW = VTRIP 3.1 3.1 3.1 3.1 2.9 2.9 V2TRIP Temp 2.6 0 to 70°C 2.6 -20 to 85°C 1.7 0 to 70°C 1.7 -20 to 85°C 2.3 0 to 70°C 2.3 -20 to 85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Characteristics subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 17 of 17