MC-XIL-USB11DEV USB 1.1 Device Controller May 20, 2002 Product Specification AllianceCORE™ Facts Powered by 0HPHF&RUHTM Product Line 9980 Huennekens Street San Diego, CA 92121 Americas:+1 888-360-9044 Europe: +1 41 (0) 32 374 32 00 Asia: +(852) 2410 2720 E-mail: [email protected] URL: www.memedesign.com Features • • • • • • • • • • • • • Available under terms of the SignOnce IP License Complies with USB protocol revision 1.1 Supports VCI to the application bus Supports full-speed (12 Mbps) signaling bit rate Supports low-speed (1.5 Mbps) signaling bit rate Handles USB protocol Handles USB device states Clock and data recovery from USB Microprocessor independent Includes Suspend/Resume logic Performs cyclic redundancy checks (CRC) with CRC5 checking, and CRC16 generation and checking Supports up to fifteen configurations, with each configuration supporting fifteen interfaces and each interface handling up to fifteen alternate settings Enables physical endpoint number programming and supports up to 16 bidirectional logical endpoints Core Specifics See Table 1 Provided with Core Documentation User manual, Implementation guide, data sheet Design File Formats NGO netlist Verification Simulation model Constraints File .ucf Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items Warranty by MemecCore Design Tool Requirements Synthesis Tool Synplify Pro 6.0 Simulation ModelSim 5.4e Support Core support provided by MemecCore Additional customization provided by Memec Design Features (contd) • • • • • • Maintains data toggle bits Enables user-configured endpoint information Provides understanding and decoding of standard USB commands to endpoint zero Provides the option to decode the Get Descriptor command or to pass the command to the application for decoding Supports class/vendor commands by passing the Setup transactions to the application Supports up to 15 string descriptors Table 1: Core Implementation Data1 Supported Family Virtex™-II Spartan™-II Virtex™-E Device Tested XC2V1000-5 XC2S200-5 XCV300E-8 CLB Slices 1036 1029 1029 Clock IOBs2 2 2 2 IOBs2 117 117 117 Performance (MHz)3 12 12 12 Xilinx Tools Alliance 3.3iSP8 Alliance 3.3iSP8 Alliance 3.3iSP8 Special Features None None None Notes: 1. These numbers reached with the following options, with the sample design: hard-coded registers, application and UDC using same clock, the core does not decode get_descriptor, 1 interface, 1 alternate, 1 additional endpoint (bulk out), endpoint 0 maxpktsize is 8 bytes, endpoint 1 maxpktsize is 8 bytes 2. Assuming all core signals are routed off-chip. 3. Minimum guaranteed speed. May 20, 2002 1 MC-XIL-USB11DEV USB 1.1 Device Controller Figure 1: USB 1.1 Device Controller Block Diagram 2 May 20, 2002 Memec Design Applications USB Bridge Layer (UBL) Block • • • The UBL block handles the error recovery mechanism during transactions and interfaces to the device logic. It also maintains all endpoint information supported by the device. The UBL also handles all of the control transfers addressed to endpoint 0. The UBL block is further sub-divided into the protocol layer (PL) and endpoint (EP) layer blocks. The PL block controls the SIE block by providing the necessary handshake signals to the SIE and talks to the device interface logic. It also has the mechanism for error recovery if the device interface violates the data transfer protocol. The EP block has all the endpoint-related information and handles all the control transfers to endpoint 0. The EP block handles all of the USB standard commands. Scanners Printers Mass Storage General Description The Universal Serial Bus (USB) Device Controller core provides an interface between the USB Function Device and the USB Host Controller. This FPGA implementation is based upon inSilicon's highly successful USB Core. The core supports both full-speed and low-speed modes. The application interface is inSilicon’s TymeWare™ Virtual Component Interface (VCI), which is fully compliant with the VSI Alliance™ Virtual Component Interface Standard (OCB 2 1.0). The USB core handles all USB protocol and provides a simple read/write protocol for the function interface (application bus). The USB core does not have FIFOs built in, enabling you to define FIFO requirements. Functional Description Phase Lock Loop (PLL) Block The PLL block is a digital phase lock loop, which extracts the clock and data from the USB cable. Input to the PLL block is from the USB differential transceiver. Serial Interface Engine (SIE) Block The SIE block handles the front-end functions of the USB protocol such as SyncField identification, NRZI-NRZ conversion, token packet decoding, bit stripping, bit stuffing NRZ-NRZI conversion, CRC-5 checking, and CRC-16 generation and checking. The SIE block also converts the serial data coming in the data packet into 8-bit parallel data. May 20, 2002 Virtual Component Interface (VCI) Block inSilicon's TymeWare VCI block provides the VSI Allianceapproved interface to the application or system bus. The VCI contains two sub-blocks: the Control/Status register (CSR) and VCI State Machine. The CSR contains all the Control and Status registers that are essential for core operation. It also contains the EEPROM controller for reading external EEPROM and programming the registers. This block stores each endpoint's information regarding packet size, type, and direction. It also registers the pointers from where the descriptors are to be read when the Get Descriptor command is received. The VCI State Machine transfers data from/to the application with VCI read/write commands. This device runs on the application interface system clock provided by the user. The VCI generates read cycles to fetch endpoint data from the application, transfers the received data from the core to the application by generating write cycles, and generates a Status write to the application. 3 MC-XIL-USB11DEV USB 1.1 Device Controller Pinout The pinout of the USB 1.1 Device Controller core has not been fixed to specific FPGA I/O, allowing flexibility with a user’s application. The signal names are shown in Figure 1 and described in Table 2. Table 2: Core Signal Pinout Signal Name Direction Clock and Reset signals app_clk In dev_clk rst_appclk In In rst_dev_clk clk_4x In In clk_1x pll_clock_out pll_clk_in pll_reset Out Out In In DPLL and Transceiver Interface Signals dpls In dmns In xver_data In udcvci_txdpls udcvci_txdmns udcvci_txen Out Out Out app_resume app_stall Strap Signals app_speed In In app_rmtwkup app_self_pwr app_setdesc_sup app_synccmd_sup app_ram_if_sup Data Interface Signals udcvci_cmdvalid udcvci_addr[15:0] udcvci_rnw In In In In In Out Out Out udcvci_data[31:0] udcvci_ben[3:0] udcvci_burst Out Out Out 4 In Description This is the free-running system clock provided by the application. The signal on the application bus are synchronous to this clock. This is the 12-/1.5-Mhz clock input This reset signal is synchronous to the application clock. When rst_appclk is asserted, all core flip-flops and registers that run on the application clock switch to the default state. This reset signal is synchronous to the dev_clk signal. This is the external clock used in the DPLL to extract clock and data information from the USB cable. This clock is obtained by dividing the clk_4x by four in the DPLL block. This is the recovered clock for the DPLL. The user must connect the pll_clk_out signal to this input. This signal resets the clock extraction and the clk_1x generation logic in the DPLL block. This is the D+ (dpls) signal from the USB. This is the D- (dmns) signal from the USB. This is the data from the differential receiver. The dpls and dmns signals are passed through the differential receivers to extract the data. The is the data to be driven on dpls. This is the data to be driven on dmns. This is the transmission-enable signal to drive the ucvi_txdpls and udcvci_txdpls and udcvci_txdmns signals onto the cable. This is the Resume generation signal from the application. This is the STALL generation signal indication from the application. This indicates the application speed. HIGH indicates full-speed operation (12 Mbps) and LOW indicates low-speed operation (1.5 Mbps) This is the device Remote Wakeup capability input pin. This is the power status signal. Supports the Set Descriptor command. Synch Frame command support Initializes incremental address interface support. This is asserted by the core to indicate the start of a transaction. This is the encoded address pointer for the current data transfer. This indicates whether the current transaction is a read or a write transaction. This is the write data for the VCI transaction. This indicates the valid bytes in the 32 bits of udcvci_data. This indicates that the current transaction is a Burst transaction. May 20, 2002 Memec Design Table 2: Core Signal Pinout (cont.) Signal Name app_ack Direction In app_err In app_abort In app_data[31:0] In app_databen[3:0] In Control/Status Register Interface Signals app_csrcmdvalid In Description The application asserts this signal to indicate the completion of data transfer. The application asserts this error signal during a data write, either to stop the current burst transfer without transferring data, or to indicate to the core that the application cannot complete the current transfer at this time, and the core should retry the transaction at a later time. The application asserts this signal to indicate that it is aborting the current packet. This is the data bus for read transactions. This is the byte enable control for app_data[31:0]. udcvci_csrack Out udcvci_csrerr udcvci_csrabort Out Out udcvci_csrdata[31:0] EEPROM Interface Signals udcvci_eepsk udcvci_eepcs udcvci_eepdi eep_do Event Notification Signals udcvci_suspend udcvci_usbreset udcvci_sof ucvci_timestamp[10:0] Debugging Signals udcvci_cfg[3:0] Out This signal is asserted by the application to access the Control/Status Register (CSR) of the core. This indicates the address of the register transaction is a read or write transaction. This indicates whether the current transaction is a read or write operation. This indicates a burst transaction; the application should never assert this signal. This indicates which bytes are valid on the 32-bit app_crsdata bus. This is the write data to be written to the addressed register during the current transaction. The core asserts this signal to acknowledge a successful data transfer to the CSR. This error indicates the start of a frame (SOF). This signal should never be asserted by the core for CSR transactions. It is tied to zero in the core. The core provides this read data for CSR transactions. Out Out Out In The core generates the low-speed clock signal to activate the EEPROM. The core generates this chip select signal to enable the EEPROM. This is the data signal input to the EEPROM. This is the data signal input to the core. Out Out Out Out This is the Suspend indication from the UDCVCI core to the application. This is the Reset indication from the UDCVCI core to the application. This signal indicates the start of a frame (SOF). This indicates the SOF frame number. Out udcvci_intf[3:0] Out udcvci_altintf[3:0] udcvci_hst_setcfg udcvci_hst_setintf Out Out Out The signal indicates the current configuration the UDCVCI core is running. This indicates the current interface that is switched to a different alternate value. This it the current alternate value for the interface. This is the qualifying signal for sampling udcvcu_cfg[3:0]. This the qualifying signal for sampling udcvci_intf[3:0] and ucvci_altinf[3:0]. app_csraddr[15:0] In app_csrrnw In app_csrburst In app_csrben[3:0] app_csrdata[31:0] In In May 20, 2002 5 MC-XIL-USB11DEV USB 1.1 Device Controller Verification Methods Related Information This core has been extensively hardware verified in ASICs by inSilicon™, and hardware verified in FPGAs by MemecCore and Insight Design Services. This core was also verified by simulation with test benches. Universal Serial Bus Specification Version 1.1 Recommended Design Experience Users should be familiar with Xilinx Foundation or Alliance tools, Synplicity tools, and ModelSim. Users should have experience instantiating black boxes into designs. Users should have some knowledge of USB functionality Ordering Information This AllianceCORE product is available from Xilinx AllianceCORE partner, Memec Design, under terms of the SignOnce IP License. To learn about the SignOnce IP License program, contact Memec Design, visit www.xilinx.com/ipcenter/signonce.htm, or write to [email protected]. Xilinx Programmable Logic For information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or: Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com For general Xilinx literature, contact: Phone: E-mail: +1 800-231-3386 (inside the US) +1 408-879-5017 (outside the US) [email protected] The USB 1.1 Device Controller is provided under license from Memec Design for use in Xilinx programmable logic devices. Please contact Memec Design for pricing and more information. Information furnished by Memec Design is believed to be accurate and reliable. Memec Design reserves the right to change specifications detailed in this data sheet at any time, without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Memec Design does not make any commitment to update this information. Memec Design assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Memec Design will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Memec Design does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Memec Design. MemecCore products are not intended for use in life support appliances, devices, or systems. Use of a MemecCore product in such application without the written consent of the appropriate Memec Design officer is prohibited. All trademarks, registered trademarks, or servicemarks are property of their respective owners. 6 May 20, 2002