AvnetCore: Datasheet Version 1.0, July 2006 Double Data Rate SDRAM Controller Intended Use: — — — — Supports All Standard DDR SDRAM Memory Types High-Speed Networking Embedded Computing Digital Video Features: reset ddr_clk ddr_clk_fb clk_module sys_cmd sys_cmd_ack read_en ctlr_ready ddr_addr smp_clk smp_delay fpga_clk clkx2 ddr_dm ddr_bank fpga_clk ddr_ras controller Control and Status ddr_cas ddr_we fpga_clk ddr_interface ddr_dqs ddr_cs DDR SDRAM Interface sys_clk DDR SDRAM ddr_cke sys_data_o sys_data_valid sys_data_i sys_data_m sys_addr ddr_dq — DDR SDRAM dynamic burst length support for burst lengths of 2, 4, or 8 per access — Supports DRAM data path widths of 16, 32, 64, and 72 bits — Supports multiple bank interleaving with read and write commands, and all read and write commands are issued at the earliest possible time with maximum efficiency — CAS latency 2.0 support — Support for the following commands: NOP, LOAD_MODE, READ, READ w/ AUTO_PRECHARGE, WRITE, WRITE w/ AUTO_PRECHARGE, and AUTO_REFRESH — Data mask support for write operations — Support for 4 internal banks — Controller provides automatic management of all four SDRAM memory banks simultaneously Targeted Devices: — Axcelerator® Family — ProASIC®3 Family Core Deliverables: Block Diagram This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. Please consult the appropriate standards document for all external signaling. The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) controller pro-vides the user with a simplified interface to industry standard memory devices. The controller has been targeted to the Actel Axcelerator® and ProASIC®3 families of platform FPGAs and can be reconfigured to provide a solution customized to the user’s needs based on system and memory-specific requirements. The DDR SDRAM controller offers full support for SDRAM bank and row management, supports four bank interleaving between commands, and executes all commands with maximum efficiency. The extensive feature list makes this an extremely flexible and efficient core to use. — Netlist Version > Netlist compatible with the Actel Designer place and route tool — RTL Version > VHDL Source Code > Test Bench — All > User Guide Synthesis and Simulation Support: — Synthesis: Synplicity® — Simulation: ModelSim® — Other tools supported upon request Verification: — Test Bench — Test Vectors Functional Description The DDR SDRAM Controller core is partitioned into modules as shown in the block diagram and as described below. CONTROLLER The Controller module contains the main state machine, which controls the SDRAM accesses. The Controller is responsible for SDRAM bus arbitration, command interpreting, bank-interleaving, and timing issues. The Controller instructs the ddr_interface module when to perform writes and reads from the DDR data bus. DDR INTERFACE The DDR Interface (ddr_interface) module is responsible for maintaining the bi-directional ddr_data bus, and for asserting all address and command signals to the SDRAM. For a write operation, this module reads from the larger sys_data bus and, using the 2x clock and muxes, constructs the DDR data bus, writing out a new value on every rising edge of the 2x clock which is strobed into the DDR SDRAM with ddr_dqs. For read operations, the opposite must occur. The Data Path reads in the DDR data using sys_clk_fb rising edge as the time reference, and de-muxes the data into two separate 1x clock pipelines. These two 1x clock pipelines are then concatenated to form the larger sys_data bus, which is provided to the user. CLOCK MODULE The Clock module (clk_module) instantiates all of the PLLs and global clocks required for the DDR Core. One PLL creates a 1x de-skewed clock that is fed to most of the logic in the core, plus it also creates a 2x clock which generates the 2X DDR related clocks used for write-related operations. The other PLL generates a delayed clock that is used in the read-related operations. sys_clk ddr_clk reset sys_addr ddr_addr sys_data_i ddr_dm sys_data_m ddr_bank sys_cmd ddr_ras ddr_cas fpga_clk ddr_we sys_cmd_ack ddr_dqs sys_data_o ddr_cs sys_data_valid ddr_cke ctlr_ready ddr_dq read_en smp_delay DDR SDRAM Interface System Interface ddr_clkb ddr_clk_fb Figure 1: MC-ACT-SDRAMDDR Logic Symbol Family Axcelerator Device AX250-2 Utilization Performance COMB SEQ Total 20% 40% 27% Table 1: Device Utilization and Performance 100 MHz Verification and Compliance Functional and timing simulation has been performed on the DDR SDRAM Controller using VHDL Test Benches. Simulation vectors used for verification are provided with the core. Signal Descriptions The following signal descriptions define the IO signals. Signal Global Signals Direction Width SYS_CLK Input 1 System clock DDR_CLK_FB Input 1 ddr_clk from DDR SDRAM Output 1 primary H-CLOCK clock used by core and available for host interface RESET Input 1 Active high system reset SYS_DATA_I Input SYS_DATA_BITS System write data SYS_DATA_M Input SYS_MASK_BITS System write data mask SYS_ADDR Input SYS_ADDR_BITS System address FPGA_CLK Interface to System SYS_CMD Interface to DDR SDRAM Description Input 7 SYS_DATA_O Output SYS_DATA_BITS DDR command bus SYS_DATA_VALID Output 1 High when sys_data_o is valid SYS_CMD_ACK Output 1 High when command is accepted CTLR_READY Output 1 High when controller can accept a cmd READ_EN Output 1 When high, controller needs new data in 2 clocks DDR_ADDR Output DDR_ADDR_BITS DDR SDRAM address bus DDR_DQ Output DDR_DATA_BITS DDR_DQS Input/Output 8 DDR SDRAM data strobe DDR_RAS Input/Output 1 DDR SDRAM row address strobe DDR_CAS Output 1 DDR SDRAM column address strobe DDR_WE Output 1 DDR SDRAM write enable DDR_BANK Output DDR_BANK_BITS DDR_CLK Output 1 DDR SDRAM clock DDR_CLKB Output 1 DDR SDRAM inverted clock DDR_CS Output 1 DDR SDRAM chip select DDR_CKE Output 1 DDR SDRAM clock enable DDR_DM Output System read data DDR SDRAM data bus DDR SDRAM bank bus DDR_MASK_BITS DDR SDRAM data mask bus Table 2: Core I/O Signals Timing All timing diagrams assume that all banks were previously closed, and that BURST-4 accesses were issued. All timing is based on a 100 MHz sys_clk. 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns sys_clk[0] sys_cmd[0] nop read sys_addr[0] nop Address sys_cmd_ack[0] ctlr_ready[0] sys_data_i[0] sys_data_m[0] read_en[0] sys_data_o[0] Data 0 Data 1 sys_data_valid[0] Figure 3: Read Command 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns sys_clk[0] sys_cmd[0] sys_addr[0] nop write nop Address sys_cmd_ack[0] ctlr_ready[0] read_en[0] Data 0 Data 1 sys_data_i[0] sys_data_m[0] sys_data_o[0] sys_data_valid[0] Figure 4: Write Command Recommended Design Experience For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero Integrated Design Environment (IDE) and preferably with Synplify and ModelSim. Users should also have experience with microprocessor systems and asynchronous communication controllers. Ordering Information The CORE is provided under license from Avnet Memec for use in Actel programmable logic devices. Please contact Avnet Memec for pricing and more information. Information furnished by Avnet Memec is believed to be accurate and reliable. Avnet Memec reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Avnet Memec does not make any commitment to update this information. Avnet Memec assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Avnet Memec will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Avnet Memec does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Avnet Memec. Avnet Memec products are not intended for use in life support appliances, devices, or systems. Use of a Avnet Memec product in such application without the written consent of the appropriate Avnet Memec officer is prohibited. All trademarks, registered trademarks, or service marks are property of their respective owners. Contact Information: North America 10805 Rancho Bernardo Road Suite 100 San Diego, California 92127 United States of America TEL: +1 858 385 7500 FAX: +1 858 385 7770 Europe, Middle East & Africa Mattenstrasse 6a CH-2555 Brügg BE Switzerland TEL: +41 0 32 374 32 00 FAX: +41 0 32 374 32 01 Ordering Information: Part Number MC-ACT-SDRAMDDR-NET MC-ACT-SDRAMDDR-VHDL Hardware Actel DDR SDRAM Controller Netlist Actel DDR SDRAM Controller VHDL Resale Contact for pricing Contact for pricing www.em.avnet.com/actel Copyright © 2006 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners. AEM-MC-ACT-SDRAMDDR-DS v.1.0-July 2006