LP5952 350mA Dual Rail Linear Regulator General Description Features The LP5952 is a Dual Supply Rail Linear Regulator optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3 cell NiMH/NiCd batteries. In the typical post regulation application VBATT is directly connected to the battery (range 2.5V...5.5V) and VIN is supplied by the output voltage of the DC-DC Converter (range 0.7V... 4.5V). The device offers superior dropout and transient features combined with very low quiescent currents. In shutdown mode (Enable pin pulled low) the device turns off and reduces battery consumption to 0.1µA (typ.). The LP5952 also features internal protection against overtemperature, over-current and under-voltage conditions. Performance is specified for a -40°C to 125°C junction temperature range. The device is available in a tiny 5-bump micro SMD and a 6pin Chip On Lead LLP package, lead free. The device is available in fixed output voltages in the range of 0.5V to 2.0V. For availability, please contact your local NSC sales office. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Excellent load transient response: ±15mV typical Excellent line transient response: ±1mV typical 0.7V ≤ VIN ≤ 4.5V 2.5V ≤ VBATT ≤ 5.5V 0.5V ≤ VOUT ≤ 2.0V For ILOAD = 350mA: VBATT ≥ VOUT(NOM) + 1.5V or 2.5V whichever is higher For ILOAD = 150mA: VBATT ≥ VOUT(NOM) + 1.3V or 2.5V whichever is higher 50µA typical quiescent current from VBATT 10µA typical quiescent current from VIN 0.1µA typical quiescent current in shutdown Guaranteed 350mA output current Noise voltage = 100µVRMS typical Operates from a single Li-Ion cell or 3 cell NiMH/NiCd batteries Only one or two tiny surface-mount external components required depending on application Small, thin 5-bump micro SMD package and 6-pin Chip On Lead LLP package, lead free Thermal-overload and short-circuit protection -40°C to +125°C junction temperature range Applications ■ ■ ■ ■ ■ ■ Mobile Phones Hand-Held Radios Personal Digital Assistants Palm-Top PCs Portable Instruments Battery Powered Devices Typical Application Circuit 20208501 FIGURE 1. Typical Application Circuit with DC-DC Converter as Pre-Regulator for VIN © 2008 National Semiconductor Corporation 202085 www.national.com LP5952 350mA Dual Rail Linear Regulator June 10, 2008 LP5952 20208502 FIGURE 2. Typical Application Circuit Connection Diagrams 5-Bump Micro SMD Package 20208503 Connection Diagram 5-Bump Thin Micro SMD Package, Large Bump, 0.5mm Pitch See NS Package Number TLA05 Package Marking 20208506 www.national.com 2 LP5952 LLP-6 Package 20208524 Connection Diagram 6-Pin Chip On Lead LLP package, 0.5mm pitch See NS Package Number LCA06B Note: The actual physical placement of the package marking will vary from part to part. The package marking “X” designates the date code. “T” is a NSC internal code for die traceability. Both will vary considerably. “U” identifies the device (part number, option, etc.). Pin Descriptions Pin Number Micro SMD Pin Number LLP Pin Name Description Power input voltage; input range: 0.7V to 4.5V, VIN ≤ VBATT A1 3 VIN A3 4 VOUT Regulated output voltage B2 2 GND Ground C1 1 VBATT Bias input voltage; input range: 2.5V to 5.5V C3 6 EN Enable pin logic input: low = shutdown, high = active, normal operation. This pin should not be left floating. Tie to VBATT if this function is not used. 5 NC Do not make connections to this pin Order Information (5-bump micro SMD) Output Voltage (V) LP5952 Supplied as 250 Units, Tape and Reel, lead free LP5952 Supplied as 3000 Units, Tape and Reel, lead free Flow Package Marking 0.7 LP5952TL-0.7 LP5952TLX-0.7 NOPB 4 1.0 LP5952TL-1.0 LP5952TLX-1.0 NOPB L 1.2 LP5952TL-1.2 LP5952TLX-1.2 NOPB 7 1.3 LP5952TL-1.3 LP5952TLX-1.3 NOPB U 1.4 LP5952TL-1.4 LP5952TLX-1.4 NOPB A 1.5 LP5952TL-1.5 LP5952TLX-1.5 NOPB T 1.6 LP5952TL-1.6 LP5952TLX-1.6 NOPB B 1.8 LP5952TL-1.8 LP5952TLX-1.8 NOPB 8 2.0 LP5952TL-2.0 LP5952TLX-2.0 NOPB 5 3 www.national.com LP5952 Order Information (COL LLP-6) Output Voltage (V) LP5952 Supplied as 1000 Units, Tape and Reel, lead free LP5952 Supplied as 4500 Units, Tape and Reel, lead free Flow Package Marking 1.2 LP5952LC-1.2 LP5952LCX-1.2 NOPB L28 1.3 LP5952LC-1.3 LP5952LCX-1.3 NOPB L43 1.5 LP5952LC-1.5 LP5952LCX-1.5 NOPB L25 1.8 LP5952LC-1.8 LP5952LCX-1.8 NOPB L29 www.national.com 4 Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage Range VIN Input Voltage Range VBATT VIN, VBATT pins: Voltage to GND, VIN ≤ VBATT: VBATT pin to VIN pin: EN pin, Voltage to GND: Continuous Power Dissipation (Note 3): Junction Temperature (TJ-MAX ): Storage Temperature Range: Package Peak Reflow Temperature (Pb-free, 10-20 sec.) (Note 4): ESD Rating (Note 5): Human Body Model: Machine Model: 0.7V to 4.5V 2.5V to 5.5V VEN Input Voltage Recommended Load Current Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 6) -0.2V to 6.0V 0.2V -0.2V to 6.0V Internally Limited 150°C -65°C to + 150°C 0 to VBATT 0mA to 350mA -40°C to + 125°C -40°C to + 85°C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) TLA05 package (Note 7) LCA06B package (Note 7) 260°C 95°C/W 150°C/W 2.0kV 200V ESD Caution Notice National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling techniques can result in damage. Electrical Characteristics (Notes 2, 8, 11) Typical values and limits appearing in standard typeface are for TA = 25°C. Limits appearing in boldface type apply over the full operating temperature range: -40°C ≤ TJ ≤ +125°C. Unless otherwise noted, specifications apply to the typical application circuit with VIN = VOUT(NOM) + 1.0V, VBATT = VOUT(NOM) + 1.5V or 2.5V, whichever is higher, IOUT = 1mA, CVIN = 1.0µF, COUT = 2.2µF, VEN = VBATT. Symbol ΔVOUT / VOUT ΔVOUT / ΔVIN Parameter Units Max -1.5 -2.0 1.5 2.0 % % mV/V 0.3 1.0 Line Regulation Error VIN = VOUT(NOM) + 0.3V to 4.5V, VBATT = 4.5V VBATT = VOUT(NOM) + 1.5V (≥ 2.5V) to 5.5V 0.5 2.2 IOUT = 1mA to 350mA, micro SMD package 15 30 µV/mA IOUT = 1mA to 350mA, LLP-6 package 43 60 µV/mA VOUT = 0V, VEN = VIN = VBATT = VOUT (NOM) + 1.5V 500 IOUT = 350mA, VIN = VOUT(NOM) + 0.3V, micro SMD package 1.07 1.5 V IOUT = 350mA, VIN = VOUT(NOM) + 0.3V, LLP-6 package 1.08 1.5 V IOUT = 150mA, VIN = VOUT(NOM) + 0.3V, micro SMD package 0.96 1.3 V IOUT = 150mA, VIN = VOUT(NOM) + 0.3V, LLP-6 package 0.97 1.3 V IOUT = 350mA, VBATT = VOUT(NOM) + 1.5V or 2.5V, micro SMD package 88 200 mV IOUT = 350mA, VBATT = VOUT(NOM) + 1.5V or 2.5V, LLP-6 package 128 250 mV 10Hz to 100kHz 100 Load Regulation Error ISC Output Current (short circuit) EN Limit Min VIN = VOUT(NOM) + 0.3V ΔVOUT / ΔmA VDO_VIN Typ Output Voltage Tolerance ΔVOUT / ΔVBATT VDO_VBATT (Note 10) Condition Output Voltage Dropout VBATT (Note 9) Output Voltage Dropout VIN Output Noise 5 mA 350 µVRMS www.national.com LP5952 Absolute Maximum Ratings (Notes 1, 2) LP5952 Symbol PSRR Parameter Power Supply Rejection Ratio Condition Typ Limit Min Max Units Sine modulated VBATT f = 10Hz f = 100Hz f = 1kHz 70 65 45 dB dB dB Sine modulated VIN f = 10Hz f = 100Hz f = 1kHz f = 10kHz f = 100kHz 80 90 95 85 64 dB dB dB dB dB Quiescent Currents Symbol Parameter Condition Typ Limit Min Max Units IQ_VBATT Current into VBATT ILOAD = 0...350mA 50 100 µA IQ_VIN Current into VIN ILOAD = 0 11 28 µA Shutdown Currents Symbol Parameter Condition Typ Limit Min Max Units IQ_VBATT Current into VBATT VEN = 0V 0.1 1 µA IQ_VIN Current into VIN VEN = 0V 0.1 1 µA Enable Control Characteristics Symbol Parameter IEN Maximum Input Current at VEN Input VIL Low Input Threshold (shutdown) VIH High Input Threshold (enable) Conditions Typ Limit Min Max 0.01 Units 1 µA 0.4 V V 1.0 Thermal Protection Symbol Parameter Conditions Typ Limit Min Max Units TSHDN Thermal-Shutdown Temperature 165 °C ΔTSHDN Thermal-Shutdown Hysteresis 20 °C www.national.com 6 LP5952 Transient Characteristics Symbol Parameter Conditions Typ Limit Min Max Units ΔVOUT Dynamic Line Transient Response VIN VIN = VOUT(NOM) + 0.3V to VOUT(NOM) + 0.9V; tr, tf = 10µs ±1 mV ΔVOUT Dynamic Line Transient Response VBATT VBATT = VOUT(NOM) + 1.5V to VOUT(NOM) + 2.1V; tr, tf = 10µs ±15 mV Dynamic Load Transient Response Pulsed load 0 ...300mA, di/dt = 300mA/ 1µs micro SMD package ±15 mV Pulsed load 0 ...300mA, di/dt = 300mA/ 1µs LLP-6 package -35/ +15 mV ΔVOUT TSTARTUP Startup Time EN to 0.95 * VOUT 70 µs 150 Input and Output Capacitors, Recommended Specification Symbol COUT CVIN Parameter Output Capacitance Input Capacitance at VIN Conditions Capacitance (Note 12) Nom 2.2 ESR Capacitance (Note 12), not needed in typ post regulation application, see Figure 1 ESR 1 Limit Min Max Units 1.5 10 µF 3 300 mΩ 0.47 3 µF 300 mΩ Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and disengages at TJ = 145°C (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1112: Micro SMD Wafer Level Chip Scale Package (AN-1112) and Application Note 1187: Leadless Leadframe Package (LLP) (AN-1187). Note 5: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. (MIL-STD-883 3015.7) Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special attention must be paid to thermal dissipation issues in board design. Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical (Typ) numbers are not guaranteed, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = VOUT(NOM) + 1.0V, VBATT= VOUT(NOM) + 1.5V or 2.5V, whichever is higher, TA = 25° C. Note 9: Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output voltage. Note 10: This specification does not apply if the battery voltage VBATT needs to be decreased below the minimum operating limit of 2.5V during this test. Note 11: VOUT(NOM) is the stated output voltage option Note 12: The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. The shown minimum limit represents real minimum capacitance, including all tolerances and must be maintained over temperature and dc bias voltage (See capacitor section in Applications Hints) 7 www.national.com LP5952 Block Diagram 20208505 www.national.com 8 Load Transient Response, 0.7V Option Load Transient Response, 1.5V Option 20208509 20208510 Line Transient Response VIN, 1.5V Option Line Transient Response VBATT, 1.5V Option 20208512 20208511 Enable Start-up Time, 0.7V Option Enable Start-up Time, 1.5V Option 20208514 20208513 9 www.national.com LP5952 Typical Performance Characteristics Unless otherwise specified, CIN = 1.0µF ceramic, COUT = 2.2µF ceramic, VIN = VOUT(NOM) + 1V, VBATT = VOUT(NOM) + 1.5V, TA = 25°C, Enable pin is tied to VBATT. Micro SMD package. LP5952 Output Voltage Change vs Temperature Dropout VIN vs Temperature, ILOAD = 350mA 20208515 20208516 Inrush Current VIN, 1.5V Option Quiescent Current IQ_VBATT vs VBATT 20208517 20208522 Ground Current vs VBATT / VIN Ground Current vs Load Current 20208523 20208519 www.national.com 10 LP5952 Power Supply Rejection Ratio VIN, 1.5V Option Power Supply Rejection Ratio VBATT, 1.5V Option 20208521 20208520 This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. As an example, to keep full load current capability of 350mA for a 1.5V output voltage option at a high ambient temperature of 85°C, VIN has to be kept ≤ 2.7V (for micro SMD package): VIN ≤ PD / IOUT + VOUT = 421mW / 350mA + 1.5V = 2.7V. Figure 3 shows the output current derating due to these considerations: Application Hints DUAL RAIL SUPPLY The LP5952 requires two different supply voltages: •VIN, the power input voltage, is regulated to the fixed output voltage •VBATT, the bias input voltage, supplies internal circuitry. It's important that VIN does not exceed VBATT at any time. If the device is used in the typical post regulation application as shown in Figure 1, the sequencing of the two power supplies is not an issue as VBATT supplies both, the DC-DC regulator and the LP5952. The output voltage of the DC-DC regulator will take some time to rise up and supply VIN of LP5952. In this application VIN will always ramp up more slowly than VBATT. In case VIN is shorted to VBATT, the voltages at the two supply pins will ramp up simultaneously causing no problem. Only in applications with two independent supplies connected to the LP5952 special care must be taken to guarantee that VIN is always ≤ VBATT. POWER DISSIPATION AND DEVICE OPERATION The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in the electrical specification section, the allowable power dissipation for the device in a given package can be calculated using the equation: 20208525 FIGURE 3. Maximum Load Current vs VIN - VOUT, TA = 85°C, VOUT = 1.5V, θJA(MICROSMD) = 95°C/W, θJA(LLP) = 150°C/W, PD = (TJ(MAX) - TA) / θJA The typical contribution of the bias input voltage supply VBATT to the power dissipation can be neglected: PD_VBATT = VBATT * IQVBATT = 5.5V * 50µA = 0.275mW typical. With a θJA = 95°C/W, the device in the 5 bump micro SMD package returns a value of 1053mW with a maximum junction temperature of 125°C at TA of 25°C or 421mW at TA of 85°C. The actual power dissipation across the device can be estimated by the following equation: EXTERNAL CAPACITORS As is common with most regulators, the LP5952 requires external capacitors to ensure stable operation. The LP5952 is specifically designed for portable applications requiring minimum board space and the smallest size components. These capacitors must be correctly selected for good performance. PD = (VIN - VOUT) * IOUT 11 www.national.com LP5952 INPUT CAPACITOR If the LP5952 is used stand alone, an input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the LP5952 power voltage input pin VIN and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the VIN pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. A capacitor at VBATT is not required if the distance to the supply does not exceed 5cm. If the device is used in the typical application as post regulator after a DC-DC regulator, no input capacitors are required at all as the capacitors of the DC-DC regulator (CIN and COUT) are sufficient if both components are mounted close to each other and a proper GND plane is used. If the distance between the output capacitor of the DC-DC regulator and the VIN pin of the LP5952 is larger than 5cm, it's recommended to add the mentioned input capacitor at VIN. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. The ESR (Equivalent Series Resistance) of the input capacitor should be in the range of 3mΩ to 300mΩ. The tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain ≥ 470nF over the entire operating temperature range. are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. The example shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.47/1.5µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. OUTPUT CAPACITOR The LP5952 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types X7R, Z5U, or Y5V) in the 2.2µF range (up to 10µF) and with an ESR between 3mΩ to 300mΩ is suitable as COUT in the LP5952 application circuit. This capacitor must be located a distance of not more than 1cm from the VOUT pin and returned to a clean analogue ground. It is also possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). FIGURE 4. Graph Showing A Typical Variation In Capacitance vs DC Bias 20208507 The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55°C to +85°C. Many large value ceramic capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed. CAPACITOR CHARACTERISTICS The LP5952 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 1µF to 4.7µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1µF ceramic capacitor is in the range of 3mΩ to 40mΩ, which easily meets the ESR requirement for stability for the LP5952. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters www.national.com NO-LOAD STABILITY The LP5952 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. 12 REVERSE CURRENT PATH The internal NFET pass device in LP5952 has an inherent parasitic body diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 50mA. For currents above this limit an external Schottky diode must be connected from VOUT to VIN (cathode on VIN, anode on VOUT). FAST TURN ON Fast turn-on is guaranteed by an optimized architecture allowing a fast ramp of the output voltage to reach the target voltage while the inrush current is controlled low at 120mA typical (for a COUT of 2.2µF). SHORT-CIRCUIT PROTECTION The LP5952 is short circuit protected and in the event of a peak over-current condition, the output current through the NFET pass device will be limited. If the over-current condition exists for a longer time, the average power dissipation will increase depending on the input to output voltage difference until the thermal shutdown circuitry will turn off the NFET. Please refer to the section on thermal information for power dissipation calculations. EVALUATION BOARDS For availability of evaluation boards please refer to the Product Folder of LP5952 at www.national.com. For information regarding evaluation boards, please refer to Application Note: AN-1531. THERMAL-OVERLOAD PROTECTION Thermal-Overload Protection limits the total power dissipation in the LP5952. When the junction temperature exceeds TJ = 13 www.national.com LP5952 165°C typ., the shutdown logic is triggered and the NFET is turned off, allowing the device to cool down. After the junction temperature dropped by 20°C (temperature hysteresis) typical, the NFET is activated again. This results in a pulsed output voltage during continuous thermal-overload conditions. The Thermal-Overload Protection is designed to protect the LP5952 in the event of a fault condition. For normal, continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = +150°C (see Absolute Maximum Ratings). ENABLE OPERATION The LP5952 may be switched ON or OFF by a logic input at the Enable pin, VEN. A logic high at this pin will turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 0.1µA. If the application does not require the Enable switching feature, the VEN pin should be tied to VBATT to keep the regulator output permanently on. To ensure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under Enable Control Characteristics, VIL and VIH. LP5952 Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number TLA05Z1A X1 = 955 µm ±30µm X2 = 1335µm ±30µm X3 = 600µm ±75µm 5-Bump Thin Micro SMD Package, Large Bump NS Package Number LCA06B 6-Pin Chip On Lead LLP Package, 0.5mm Pitch For most accurate revision please refer to www.national.com/packaging/parts/ www.national.com 14 LP5952 Notes 15 www.national.com LP5952 350mA Dual Rail Linear Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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