MOTOROLA Order this document by: DSP56007/D SEMICONDUCTOR TECHNICAL DATA DSP56007 SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS Motorola designed the Symphony family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by Motorola for integration into products like audio/video receivers, televisions, and automotive sound systems with such user-developed features as digital equalization and sound field processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core, program and data memories, various peripherals optimized for audio, and support circuitry. As illustrated in Figure 1, the DSP56000 core family compatible DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE) port. The DSP56007 has significantly more on-chip memory than the DSP56004. ˇ 4 General Purpose Input/ Output 9 5 Serial Audio Interface (SAI) Serial Host Interface (SHI) DSP56000 Core Y Data Memory* PDB XDB YDB OnCETM Port Interrupt Control Clock Gen. 3 X Data Memory* Program Memory* Interface (EMI) GDB Internal Data Bus Switch PLL External Memory PAB XAB YAB Address Generation Unit 24-Bit 16-Bit Bus 24-Bit Bus 29 4 Program Program Address Decode Generator Controller Program Control Unit 4 Data ALU 24 × 24 + 56 → 56-Bit MAC Two 56-Bit Accumulators * Refer to Table 1 for memory configurations. IRQA, IRQB, NMI, RESET Figure 1 DSP56007 Block Diagram ©1996, 1997 MOTOROLA, INC. AA0248 TABLE OF CONTENTS SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FOR TECHNICAL ASSISTANCE: Telephone: 1-800-521-6274 Email: [email protected] Internet: http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Note: ii Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. DSP56007/D MOTOROLA DSP56007 Features FEATURES Digital Signal Processing Core • Efficient, object code compatible with the 24-bit DSP56000 core family engine • Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte • Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) • Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles • 56-bit addition/subtraction in 1 instruction cycle • Fractional and integer arithmetic with support for multiprecision arithmetic • Hardware support for block floating-point Fast Fourier Transforms (FFT) • Hardware nested DO loops • Zero-overhead fast interrupts (2 instruction cycles) • Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories • Fabricated in high-density CMOS • On-chip modified Harvard architecture, which permits simultaneous accesses to program and two data memories • Bootstrap loading from Serial Host Interface or External Memory Interface Memory Table 1 Memory Configuration (Word width is 24 bits) Mode MOTOROLA Program X Data Y Data PE ROM RAM ROM RAM ROM RAM Bootstrap ROM 0 1 6400 5120 None 1024 512 512 1024 1024 512 512 2176 1152 52 52 DSP56007/D iii DSP56007 Features Peripheral and Support Circuits iv • Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, implementation of I2S, Sony, and Matsushita audio protocols; and two sets of SAI interrupt vectors • Serial Host Interface (SHI) features single master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words • External Memory Interface (EMI), implemented as a peripheral supporting: – Page-mode DRAMs (one or two chips): 64 K × 4, 256 K × 4, and 4 M × 4 bits – SRAMs (one to four): 256 K × 8 bits – Data bus may be 4 or 8 bits wide – Data words may be 8, 12, 16, 20, or 24 bits wide • Four dedicated, independent, programmable General Purpose Input/Output (GPIO) lines • On-chip peripheral registers memory mapped in data memory space • Three external interrupt request pins • On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging • Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the core clock • Power-saving Wait and Stop modes • Fully static, HCMOS design for operating frequencies down to DC • 80-pin plastic Quad Flat Pack surface-mount package; 14 × 14 × 2.20 mm (2.15–2.45 mm range); 0.65 mm lead pitch • Complete pinout compatibility between DSP56009, DSP56004, DSP56004ROM, and DSP56007 for easy upgrades • 5 V power supply DSP56007/D MOTOROLA DSP56007 Product Documentation PRODUCT DOCUMENTATION Table 2 lists the documents that provide a complete description of the DSP56007 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 2 DSP56007 Documentation Document Name Description of Content Order Number DSP56000 Family Manual DSP56000 core family architecture and the 24-bit core processor and instruction set DSP56KFAMUM/AD DSP56007 User’s Manual Memory, peripherals, and interfaces DSP56007UM/AD DSP56007 Technical Data Electrical and timing specifications, and pin and package descriptions DSP56007/D MOTOROLA DSP56007/D v DSP56007 Product Documentation vi DSP56007/D MOTOROLA SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The DSP56007 input and output signals are organized into the nine functional groups, as shown in Table 1-1. The individual signals are illustrated in Figure 1-1. Table 1-1 DSP56007 Functional Group Signal Allocations Functional Group Number of Signals Detailed Description Power (VCC) 9 Table 1-2 Ground (GND) 13 Table 1-3 Phase Lock Loop (PLL) 3 Table 1-4 External Memory Interface (EMI) 29 Table 1-5 and Table 1-6 Interrupt and Mode Control 4 Table 1-7 Serial Host Interface (SHI) 5 Table 1-8 Serial Audio Interface (SAI) 9 Table 1-9 and Table 1-10 General Purpose Input/Output (GPIO) 4 Table 1-11 On-Chip Emulation (OnCE) port 4 Table 1-12 Total MOTOROLA 80 DSP56007/D 1-1 Signal/Connection Descriptions Signal Groupings Power Inputs VCCP 3 VCCQ 2 VCCA VCCD 2 VCCS Ground GNDP GNDQ GNDA GNDD GNDS DSP56007 MOSI/HA0 SS/HA2 Port B Serial Host Interface MISO/SDA SCK/SCL HREQ 3 4 2 3 Port C Serial Audio Interface WSR PCAP SCKR PINIT PLL Rec0 Rec1 EXTAL SDI0 SDI1 WST MA0–MA14 MD0–MD7 SCKT 15 8 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS MCS0 Tran0 SDO0 Tran1 SDO1 Tran2 SDO2 Port A External Memory Interface GPIO MWR 4 GPIO0–GPIO3 MRD DSCK/OS1 MODC/NMI MODB/IRQB MODA/IRQA RESET Mode/Interrupt Control OnCE™ Port Reset DSI/OS0 DSO DR 80 signals AA0249G Figure 1-1 DSP56007 SIgnals 1-2 DSP56007/D MOTOROLA Signal/Connection Descriptions Power POWER Table 1-2 Power Inputs Power Name Description VCCP PLL Power—VCCP provides isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCQ Quiet Power—VCCQ provides isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. VCCA Address Bus Power—VCCA provides isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. VCCD Data Bus Power—VCCD provides isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. VCCS Serial Interface Power—VCCS provides isolated power for the SHI and SAI. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. GROUND Table 1-3 Grounds Ground Name Description GNDP PLL Ground—GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package. GNDQ Quiet Ground—GNDQ provides isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDA Address Bus Ground—GNDA provides isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDD Data Bus Ground—GNDD provides isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDS Serial Interface Ground—GNDS provides isolated ground for the SHI and SAI. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. MOTOROLA DSP56007/D 1-3 Signal/Connection Descriptions Clock and PLL signals CLOCK AND PLL SIGNALS Note: While the PLL on this DSP is identical to the PLL described in the DSP56000 Family Manual, two of the signals have not been implemented externally. Specifically, there is no PLOCK signal or CKOUT signal available. Therefore, the internal clock is not directly accessible and there is no external indication that the PLL is locked. These signals were omitted to reduce the number of pins and allow this DSP to be put in a smaller, less expensive package. Table 1-4 Clock and PLL Signals Signal Type State during Reset EXTAL Input Input External Clock/Crystal—This input should be connected to an external clock source. If the PLL is enabled, this signal is internally connected to the on-chip PLL. The PLL can multiply the frequency on the EXTAL pin to generate the internal DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock. PCAP Input Input PLL Filter Capacitor—This input is used to connect a highquality (high “Q” factor) external capacitor needed for the PLL filter. The capacitor should be as close as possible to the DSP with heavy, short traces connecting one terminal of the capacitor to PCAP and the other terminal to VCCP. The required capacitor value is specified in Table 2-6 on page 2-6. Signal Name Signal Description Note: When short lock time is critical, low dielectric absorption capacitors such as polystyrene, polypropylene, or teflon are recommended. If the PLL is not used (i.e., it remains disabled at all times), there is no need to connect a capacitor to the PCAP pin. It may remain unconnected, or be tied to either Vcc or GND. PINIT 1-4 Input Input PLL Initialization (PINIT)—During the assertion of hardware reset, the value on the PINIT line is written into the PEN bit of the PCTL register. When set, the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output. When the bit is cleared, the PLL is disabled and the DSP’s internal clocks are derived from the clock connected to the EXTAL signal. After hardware RESET is deasserted, the PINIT signal is ignored. DSP56007/D MOTOROLA Signal/Connection Descriptions External Memory Interface (EMI) EXTERNAL MEMORY INTERFACE (EMI) Table 1-5 External Memory Interface (EMI) Signals Signal Name Signal Type State during Reset MA0–MA14 Output Table 1-6 Memory Address Lines 0–14—The MA0–MA10 lines provide the multiplexed row/column addresses for DRAM accesses. Lines MA0–MA14 provide the non-multiplexed address lines 0–14 for SRAM accesses. MA15 Output Table 1-6 Memory Address Line 15 (MA15)—This line functions as the non-multiplexed address line 15. Memory Chip Select 3 (MCS3)—For SRAM accesses, this line functions as memory chip select 3. MCS3 MA16 Signal Description Output Table 1-6 Memory Address Line 16 (MA16)—This line functions as the non-multiplexed address line 16 or as memory chip select 2 for SRAM accesses. MCS2 Memory Chip Select 2 (MCS2)—For SRAM access, this line functions as memory chip select 2. MCAS Memory Column Address Strobe (MCAS)—This line functions as the Memory Column Address Strobe (MCAS) during DRAM accesses. MA17 Output Table 1-6 Memory Address Line 17 (MA17)—This line functions as the non-multiplexed address line 17. MCS1 Memory Chip Select 1 (MCS1)—This line functions as chip select 1 for SRAM accesses. MRAS Memory Row Address Strobe (MRAS)—This line also functions as the Memory Row Address Strobe during DRAM accesses. MCS0 Output Table 1-6 Memory Chip Select 0—This line functions as memory chip select 0 for SRAM accesses. MWR Output Table 1-6 Memory Write Strobe—This line is asserted when writing to external memory. MRD Output Table 1-6 Memory Read Strobe—This line is asserted when reading external memory. MOTOROLA DSP56007/D 1-5 Signal/Connection Descriptions External Memory Interface (EMI) Table 1-5 External Memory Interface (EMI) Signals (Continued) Signal Name MD0–MD7 Signal Type State during Reset Bidirectional Tri-stated Signal Description Data Bus—These signals provide the bidirectional data bus for EMI accesses. They are inputs during reads from external memory, outputs during writes to external memory, and tristated if no external access is taking place. If the data bus width is defined as four bits wide, only signals MD0–MD3 are active, while signals MD4–MD7 remain tri-stated. While tri-stated, MD0–MD7 are disconnected from the pins and do not require external pull-ups. . Table 1-6 EMI States during Reset and Stop States Operating Mode Signal Hardware Reset Software Reset Individual Reset Stop Mode MA0–MA14 Driven High Previous State Previous State Previous State MA15 Driven High Driven High Previous State Previous State MCS3 Driven High Driven High Driven High Driven High MA16 Driven High Driven High Previous State Previous State MCS2 Driven High Driven High Driven High Driven High MCAS: DRAM refresh disabled DRAM refresh enabled Driven High Driven High Driven High Driven High Driven High Driven Low Driven High Driven High MA17 Driven High Driven High Previous State Previous State MCS1 Driven High Driven High Driven High Driven High DRAM refresh enabled Driven High Driven High Driven High Driven High Driven High Driven Low Driven High Driven High MCS0 Driven High Driven High Driven High Driven High MWR Driven High Driven High Driven High Driven High MRD Driven High Driven High Driven High Driven High MRAS: DRAM refresh disabled 1-6 DSP56007/D MOTOROLA Signal/Connection Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the DSP’s operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset. Table 1-7 Interrupt and Mode Control Signals Signal Name Signal Type MODA Input State during Reset Signal Description Input (MODA) Mode Select A—This input signal has three functions: • • • to work with the MODB and MODC signals to select the DSP’s initial operating mode, to allow an external device to request a DSP interrupt after internal synchronization, and to turn on the internal clock generator when the DSP is in the Stop processing state, causing the DSP to resume processing. MODA is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODA signal changes to the external interrupt request IRQA. The DSP operating mode can be changed by software after reset. IRQA External Interrupt Request A (IRQA)—The IRQA input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases. While the DSP is in the Stop mode, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to function as MODA. MOTOROLA DSP56007/D 1-7 Signal/Connection Descriptions Interrupt and Mode Control Table 1-7 Interrupt and Mode Control Signals (Continued) Signal Name Signal Type MODB Input State during Reset Signal Description Input (MODB) Mode Select B—This input signal has two functions: • • to work with the MODA and MODC signals to select the DSP’s initial operating mode, and to allow an external device to request a DSP interrupt after internal synchronization. MODB is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODB signal changes to the external interrupt request IRQB. The DSP operating mode can be changed by software after reset. IRQB 1-8 External Interrupt Request B (IRQB)—The IRQB input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB. DSP56007/D MOTOROLA Signal/Connection Descriptions Interrupt and Mode Control Table 1-7 Interrupt and Mode Control Signals (Continued) Signal Name MODC Signal Type Input, edgetriggered State during Reset Signal Description Input (MODC) Mode Select C—This input signal has two functions: • • to work with the MODA and MODB signals to select the DSP’s initial operating mode, and to allow an external device to request a DSP interrupt after internal synchronization. MODC is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODC signal changes to the Non-Maskable Interrupt request, NMI. The DSP operating mode can be changed by software after reset. Non-Maskable Interrupt Request—The NMI input is a negative-edge-triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to function as MODC. NMI RESET input active RESET—This input causes a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the Reset state. A Schmitt-trigger input is used for noise immunity. When the reset signal is deasserted, the initial DSP operating mode is latched from the MODA, MODB, and MODC signals. The DSP also samples the PINIT signal and writes its status into the PEN bit of the PLL Control Register. When the DSP comes out of the Reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal. For proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware Reset state. MOTOROLA DSP56007/D 1-9 Signal/Connection Descriptions Serial Host Interface (SHI) SERIAL HOST INTERFACE (SHI) The Serial Host Interface (SHI) has five I/O signals, which may be configured to operate in either SPI or I2C mode. Table 1-8 lists the SHI signals. Table 1-8 Serial Host Interface (SHI) signals Signal Name Signal Type SCK Input or Output SCL Input or Output 1-10 State during Reset Tri-stated Signal Description SPI Serial Clock (SCK)—The SCK signal is an output when the SPI is configured as a master, and a Schmitttrigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock (SCL)—SCL carries the clock for bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. The maximum allowed internally generated bit clock frequency is Fosc/4 for the SPI mode and Fosc/6 for the I2C mode where Fosc is the clock on EXTAL. The maximum allowed externally generated bit clock frequency is Fosc/3 for the SPI mode and Fosc/5 for the I2C mode. This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). DSP56007/D MOTOROLA Signal/Connection Descriptions Serial Host Interface (SHI) Table 1-8 Serial Host Interface (SHI) signals (Continued) Signal Name Signal Type MISO Input or Output SDA Input or Output State during Reset Tri-stated Signal Description SPI Master-In-Slave-Out (MISO)—When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. I2C Serial Data and Acknowledge (SDA)—In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of Start and Stop events. A high-to-low transition of the SDA line while SCL is high is an unique situation, and is defined as the Start event. A low-to-high transition of SDA while SCL is high is an unique situation, and is defined as the Stop event. Note: MOSI Input or Output HA0 Input Tri-stated SPI Master-Out-Slave-In (MOSI)—When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0 (HA0)—This signal uses a Schmitttrigger input when configured for the I2C mode. When configured for I2C Slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when the SHI is configured for the I2C Master mode. Note: MOTOROLA This line is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). DSP56007/D 1-11 Signal/Connection Descriptions Serial Host Interface (SHI) Table 1-8 Serial Host Interface (SHI) signals (Continued) Signal Type State during Reset SS Input Tri-stated HA2 Input Signal Name Signal Description SPI Slave Select (SS)—This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted. If it is asserted while configured as SPI master, a bus error condition will be flagged. I2C Slave Address 2 (HA2)—This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C Master mode. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. Note: HREQ Input or Output Tri-stated Host Request—This signal is an active low Schmitttrigger input when configured for the Master mode, but an active low output when configured for the Slave mode. When configured for the Slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the Master mode, HREQ is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. Note: 1-12 This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). This signal is tri-stated during hardware, software, individual reset, or when the HREQ[1:0] bits (in the HCSR) are cleared (no need for external pull-up in this state). DSP56007/D MOTOROLA Signal/Connection Descriptions Serial Audio Interface (SAI) SERIAL AUDIO INTERFACE (SAI) The SAI is composed of separate receiver and transmitter sections. SAI Receiver Section Table 1-9 Serial Audio Interface (SAI) Receiver signals Signal Name SDI0 Signal Type State during Reset Input Tri-stated Signal Description Serial Data Input 0—While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI0 is the serial data input for receiver 0. Note: SDI1 Input Tri-stated Serial Data Input 1—While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI1 is the serial data input for receiver 1. Note: SCKR Input or Output Tri-stated This signal is high impedance during hardware or software reset, while receiver 1 is disabled (R1EN = 0), or while the DSP is in the Stop state. Receive Serial Clock—SCKR is an output if the receiver section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. Note: MOTOROLA This signal is high impedance during hardware or software reset, while receiver 0 is disabled (R0EN = 0), or while the DSP is in the Stop state. SCKR is high impedance if all receivers are disabled (individual reset) and during hardware or software reset, or while the DSP is in the Stop state. DSP56007/D 1-13 Signal/Connection Descriptions Serial Audio Interface (SAI) Table 1-9 Serial Audio Interface (SAI) Receiver signals (Continued) Signal Name WSR Signal Type State during Reset Input or Output Tri-stated Signal Description Word Select Receive (WSR)—WSR is an output if the receiver section is configured as a master, and a Schmitt-trigger input if configured as a slave. WSR is used to synchronize the data word and to select the left/right portion of the data sample. Note: 1-14 WSR is high impedance if all receivers are disabled (individual reset), during hardware reset, during software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary. DSP56007/D MOTOROLA Signal/Connection Descriptions Serial Audio Interface (SAI) SAI Transmitter Section Table 1-10 Serial Audio Interface (SAI) Transmitter signals Signal Name Signal Type State during Reset Signal Description SDO0 Output Driven High Serial Data Output 0 (SDO0)—SDO0 is the serial output for transmitter 0. SDO0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the DSP is in the Stop state. SDO1 Output Driven High Serial Data Output 1 (SDO1)—SDO1 is the serial output for transmitter 1. SDO1 is driven high if transmitter 1 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state. SDO2 Output Driven High Serial Data Output 2 (SDO2)—SDO2 is the serial output for transmitter 2. SDO2 is driven high if transmitter 2 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state. SCKT Input or Output Tri-stated Serial Clock Transmit (SCKT)—This signal provides the clock for the SAI. SCKT can be an output if the transmit section is configured as a master, or a Schmitt-trigger input if the transmit section is configured as a slave. When the SCKT is an output, it provides an internally generated SAI transmit clock to external circuitry. When the SCKT is an input, it allows external circuitry to clock data out of the SAI. Note: WST Input or Output Tri-stated Word Select Transmit (WST)—WST is an output if the transmit section is programmed as a master, and a Schmitttrigger input if it is programmed as a slave. WST is used to synchronize the data word and select the left/right portion of the data sample. Note: MOTOROLA SCKT is high impedance if all transmitters are disabled (individual reset), during hardware reset, software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. WST is high impedance if all transmitters are disabled (individual reset), during hardware or software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. DSP56007/D 1-15 Signal/Connection Descriptions General Purpose I/O GENERAL PURPOSE I/O Table 1-11 General Purpose I/O (GPIO) Signals Signal Name GPIO0– GPIO3 Signal Type State during Reset Standard Output, Open-drain Output, or Input Disconnected Signal Description GPIO lines can be used for control and handshake functions between the DSP and external circuitry. Each GPIO line can be configured individually as disconnected, open-drain output, standard output, or an input. Note: Hardware reset or software reset configures all the GPIO lines as disconnected (external circuitry connected to these pins may need pullups until the pins are configured for operation). ON-CHIP EMULATION (OnCETM) PORT There are four signals associated with the OnCE port controller and its serial interface. Table 1-12 On-Chip Emulation Port Signals Signal Name Signal Type State during Reset DSI Input Output, Driven Low OS0 Output Signal Description Debug Serial Input (DSI)—The DSI signal is the signal through which serial data or commands are provided to the OnCE port controller. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE port Most Significant Bit (MSB) first. Operating Status 0 (OS0)—When the DSP is not in the Debug mode, the OS0 signal provides information about the DSP status if it is an output and used in conjunction with the OS1 signal. When switching from output to input, the signal is tri-stated. Note: 1-16 If the OnCE port is in use, an external pull-down resistor should be attached to the DSI/OS0 signal. If the OnCE port is not in use, the resistor is not required. DSP56007/D MOTOROLA Signal/Connection Descriptions On-Chip Emulation (OnCETM) Port Table 1-12 On-Chip Emulation Port Signals (Continued) Signal Name DSCK OS1 Signal Type State during Reset Input Output, Driven Low Output Signal Description Debug Serial Clock (DSCK)—The DSCK/OS1 signal, when an input, is the signal through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE port on the rising edge. Operating Status 1 (OS1)—If the OS1 signal is an output and used in conjunction with the OS0 signal, it provides information about the DSP status when the DSP is not in the Debug mode. The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The signal is tri-stated when it is changing from input to output. Note: DSO Output Driven High If the OnCE port is in use, an external pull-down resistor should be attached to the DSCK/OS1 pin. If the OnCE port is not in use, the resistor is not required. Debug Serial Output (DSO)—The DSO line provides the data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. The Most Significant Bit (MSB) of the data word is always shifted out of the OnCE port first. Data is clocked out of the OnCE port on the rising edge of DSCK. The DSO line also provides acknowledge pulses to the external command controller. When the DSP enters the Debug mode, the DSO line will be pulsed low to indicate that the OnCE port is waiting for commands. After receiving a read command, the DSO line will be pulsed low to indicate that the requested data is available and the OnCE port is ready to receive clock pulses in order to deliver the data. After receiving a write command, the DSO line will be pulsed low to indicate that the OnCE port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. Note: MOTOROLA During hardware reset and when idle, the DSO line is held high. DSP56007/D 1-17 Signal/Connection Descriptions On-Chip Emulation (OnCETM) Port Table 1-12 On-Chip Emulation Port Signals (Continued) Signal Name DR Signal Type State during Reset Input Input Signal Description Debug Request (DR)—The debug request input provides a means of entering the Debug mode of operation. This signal, when asserted (pulled low), will cause the DSP to finish the current instruction being executed, to save the instruction pipeline information, to enter the Debug mode, and to wait for commands to be entered from the debug serial input line. While the DSP is in the Debug mode, the user can reset the OnCE port controller by asserting DR, waiting for an acknowledge pulse on DSO, and then deasserting DR. It may be necessary to reset the OnCE port controller in cases where synchronization between the OnCE port controller and external circuitry is lost. Asserting DR when the DSP is in the Wait or the Stop mode, and keeping it asserted until an acknowledge pulse in the DSP is produced, puts the DSP into the Debug mode. After receiving the acknowledge pulse, DR must be deasserted before sending the first OnCE port command. For more information, see Methods Of Entering The Debug Mode in the DSP56000 Family Manual. Note: 1-18 If the OnCE port is not in use, an external pull-up resistor should be attached to the DR line. DSP56007/D MOTOROLA SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56007 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA DSP56007/D 2-1 Specifications Thermal characteristics Table 2-1 Maximum Ratings (GND = 0 Vdc) Rating Symbol Value Unit Supply Voltage VCC –0.3 to +7.0 V All Input Voltages VIN (GND – 0.25) to (VCC + 0.25) V Current Drain per Pin excluding VCC and GND I 10 mA Operating Temperature Range: • 50 and 66 MHz • 88 MHz TJ –40 to +125 –40 to +110 °C °C –55 to +125 °C Storage Temperature TSTG THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Characteristic Symbol QFP Value3 QFP Value4 Unit Junction-to-ambient thermal resistance1 RθJA or θJA 61.5 37 ˚C/W Junction-to-case thermal resistance2 RθJC or θJC 11.8 — ˚C/W Thermal characterization parameter ΨJT 2.7 — ˚C/W Notes: 1. 2. 3. 4. 2-2 Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088, with the exception that the cold plate temperature is used for the case temperature. These are measured values. See note 1 for test board conditions. These are measured values; testing is not complete. Values were measured on a non-standard four-layer thermal test board (two internal planes) at one watt in a horizontal configuration. DSP56007/D MOTOROLA Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Supply voltage Input high voltage • EXTAL • RESET • MODA, MODB, MODC • SHI inputs1 • All other inputs Input low voltage • EXTAL • MODA, MODB, MODC • SHI inputs1 • All other inputs 50 MHz 66 MHz 88 MHz Min Typ Max Min Typ Max Min Typ Max VCC 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 V VIHC VIHR VIHM 4.0 2.5 3.5 — — — VCC VCC VCC 4.0 2.5 3.5 — — — VCC VCC VCC 4.0 2.5 3.5 — — — VCC VCC VCC V V V VIHS — VCC VCC VCC V VCC — VCC 0.7 × VCC 2.0 — — 0.7 × VCC 2.0 — VIH 0.7 × VCC 2.0 — VCC V VILC VILM –0.5 –0.5 — — 0.4 2.0 –0.5 –0.5 — — 0.4 2.0 –0.5 –0.5 — — 0.4 2.0 V V VILS –0.5 — –0.5 — — — –0.5 — –0.5 — 0.3 × VCC 0.8 V –0.5 0.3 × VCC 0.8 –0.5 VIL 0.3 × VCC 0.8 –1 — 1 –1 — 1 –1 — 1 µA –10 — 10 –10 — 10 –10 — 10 µA Symbol Unit V Input leakage current • EXTAL, RESET, MODA, MODB, MODC, DR • Other Input Pins (@ 2.4 V/0.4 V) IIN High impedance (off-state) input current (@ 2.4 V / 0.4 V) ITSI –10 — 10 –10 — 10 –10 — 10 µA Output high voltage (IOH = –0.4 mA) VOH 2.4 — — 2.4 — — 2.4 — — V Output low voltage (IOL = 3.2 mA) SCK/SCL IOL = 6.7 mA MISO/SDA IOL = 6.7 mA HREQ IOL = 6.7 mA VOL — — 0.4 — — 0.4 — — 0.4 V ICCI ICCW ICCS — — — 80 14 5 1054 25 110 — — — 110 18 5 1304 30 110 — — — 147 24 5 1694 33 110 mA mA µA Internal Supply Current • Normal mode • Wait mode • Stop mode2 MOTOROLA DSP56007/D 2-3 Specifications AC Electrical Characteristics Table 2-3 DC Electrical Characteristics (Continued) Characteristics PLL supply current Input Notes: capacitance3 1. 2. 3. 4. 50 MHz 66 MHz 88 MHz Min Typ Max Min Typ Max Min Typ Max Symbol CIN Unit — 0.7 1.1 — 1.0 1.5 — 1.3 2.2 mA — 10 — — 10 — — 10 — pF The SHI inputs are: MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, and HREQ. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are disabled during Stop state. Periodically sampled and not 100% tested Maximum values are derived using the methodology described in Section 4. Actual maximums are application dependent and may vary widely from these numbers. AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB, MODC, and SHI pins (MOSI/HA0, SS/HA2, MISO/SDA, SCK/ SCL, HREQ). These pins are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56007 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. All output delays are given for a 50 pF load unless otherwise specified. For load capacitance greater than 50 pF, the drive capability of the output pins typically decreases linearly: 1. At 1.5 ns per 10 pF of additional capacitance at all output pins except MOSI/HA0, MISO/SDA, SCK/SCL, HREQ 2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/HA0, MISO/SDA, SCK/SCL, HREQ (in SPI mode only) 2-4 DSP56007/D MOTOROLA Specifications Internal Clocks INTERNAL CLOCKS For each occurrence of TH, TL, TC, or ICYC, substitute with the numbers in Table 2-4. Table 2-4 Internal Clocks Characteristics Symbol Expression Internal Operation Frequency f — Internal Clock High Period • with PLL disabled • with PLL enabled and MF ≤ 4 TH ETH (Min) 0.48 × TC (Max) 0.52 × TC (Min) 0.467 × TC (Max) 0.533 × TC • with PLL enabled and MF > 4 Internal Clock Low Period • with PLL disabled • with PLL enabled and MF ≤ 4 TL ETL (Min) 0.48 × TC (Max) 0.52 × TC (Min) 0.467 × TC (Max) 0.533 × TC • with PLL enabled and MF > 4 Internal Clock Cycle Time Instruction Cycle Time TC (DF /MF) × ETC ICYC 2 × TC EXTERNAL CLOCK (EXTAL PIN) The DSP56007 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times of 3 ns maximum. Table 2-5 External Clock (EXTAL Pin) 50 MHz No. Characteristics — Frequency of External Clock (EXTAL Pin) 1 External Clock Input High—EXTAL • with PLL disabled (46.7%–53.3% duty cycle) • with PLL enabled (42.5%–57.5% duty cycle) MOTOROLA 66 MHz 88 MHz Sym. Pin1 Ef ETH Unit Min Max Min Max Min Max 0 50 0 66 0 88 MHz 9.3 ∞ 7.1 ∞ 5.3 ∞ ns 8.5 235500 6.4 235500 4.8 235500 ns DSP56007/D 2-5 Specifications Phase Lock Loop (PLL) Characteristics Table 2-5 External Clock (EXTAL Pin) (Continued) 50 MHz No. 2 3 4 Characteristics External Clock Input Low—EXTAL Pin1 • with PLL disabled (46.7%–53.3% duty cycle) • with PLL enabled (42.5%–57.5% duty cycle) ETL External Clock Cycle Time1 • with PLL disabled • with PLL enabled ETC Instruction Cycle Time = Icyc = 2 × TC1 • with PLL disabled • with PLL enabled Icyc Note: 1. 66 MHz 88 MHz Sym. Unit Min Max Min Max Min Max 9.3 ∞ 7.1 ∞ 5.4 ∞ ns 8.5 235500 6.4 235500 4.8 235500 ns 20 20 ∞ 15.15 ∞ 11.4 ∞ 409600 15.15 409600 11.4 409600 ns ns 40 40 ∞ 819200 ns ns 30.3 30.3 ∞ 22.7 ∞ 819200 22.7 819200 External Clock Input High and External Clock Input Low are measured at 50% of the input transition. EXTAL 1 2 ETH 3 ETC ETL 4 AA0250 Figure 2-1 External Clock Timing PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6 Phase Lock Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled PLL external capacitor (PCAP pin to VCCP) Note: 2-6 1. Expression MF × Ef MF × CPCAP1 @ MF ≤ 4 @ MF > 4 Min Max Unit 10 f1 MHz MF × 340 MF × 380 MF × 480 MF × 970 pF pF Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1. The recommended value for Cpcap is 400 pF for MF ≤ 4 and 540 pF for MF > 4. The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4. DSP56007/D MOTOROLA Specifications RESET, Stop, Mode Select, and Interrupt Timing RESET, STOP, MODE SELECT, AND INTERRUPT TIMING Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (CL = 50 pF + 2 TTL Loads) No. Characteristics 10 Minimum RESET assertion width: • PLL disabled • PLL enabled1 Min Max Unit 25 × TC 2500 × ETC — — ns ns 14 Mode Select Setup Time 21 — ns 15 Mode Select Hold Time 0 — ns 16 Minimum Edge-triggered Interrupt Request Assertion Width 13 — ns 13 — ns 12 × TC + TH — ns TL – 31 (2 × TC) + TL – 31 ns ns 12 — ns 6 × TC + TL 12 — — ns ns 16a Minimum Edge-triggered Interrupt Request Deassertation Width 18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid Caused by First Interrupt Instruction Execution 22 Delay from General Purpose Output Valid to Interrupt Request Deassertation for Level Sensitive Fast Interrupts—If Second Interrupt Instruction is: 2 • Single Cycle • Two Cycles 25 Duration of IRQA Assertion for Recovery from Stop State 27 Duration for Level Sensitive IRQA Assertion to ensure interrupt service (when exiting “STOP”) • Stable External Clock, OMR Bit 6 = 1 • Stable External Clock, PCTL Bit 17 = 1 Note: 1. 2. This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP pin. For capacitor values less than or equal to 2 nF, asserting RESET according to this timing requirement will ensure proper processor initialization for capacitors with a deltaC/C less than 0.5%. (This is typical for ceramic capacitors.) For capacitor values greater than 2 nF, asserting RESET according to this timing requirement will ensure proper processor initialization for capacitors with a deltaC/C less than 0.01%. (This is typical for Teflon, polystyrene, and polypropylene capacitors.) However, capacitors with values greater than 2 nF with a deltaC/C greater than 0.01% may require longer RESET assertion to ensure proper initialization. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. VIHR RESET 10 AA0251 Figure 2-2 Reset Timing MOTOROLA DSP56007/D 2-7 Specifications RESET, Stop, Mode Select, and Interrupt Timing VIHR RESET 14 VIHM 15 VIH MODA, MODB MODC IRQA, IRQB, NMI VILM VIL AA0252 Figure 2-3 Operating Mode Select Timing IRQA, IRQB, NMI 16 IRQA, IRQB, NMI 16A AA0253 Figure 2-4 External Interrupt Timing (Negative Edge-triggered) General Purpose I/O (Output) 18 22 IRQA IRQB NMI General Purpose I/O AA0254 Figure 2-5 External Level-sensitive Fast Interrupt Timing 25 IRQA AA0255 Figure 2-6 Recovery from Stop State Using IRQA 27 IRQA AA0256 Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service 2-8 DSP56007/D MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING (CL = 50 pF + 2 TTL Loads) Table 2-8 External Memory Interface (EMI) DRAM Timing No. Characteristics Symbol 50 MHz Timing Mode Expression 66 MHz 88 MHz Unit Min Max Min Max Min Max 41 Page Mode Cycle Time tPC slow fast 4 × TC 3 × TC 80 60 — — 61 46 — — 45.5 34.1 — — ns ns 42 RAS or RD Assertion to Data Valid tRAC, tGA slow fast 7 × TC – 16 5 × TC – 16 — — 124 84 — — 90 60 — — 63.5 40.8 ns ns 43 CAS Assertion to Data Valid TCAC slow fast 3 × TC – 10 2 × TC – 10 — — 50 30 — — 35 20 — — 24.1 12.7 ns ns 44 Column Address Valid to Data Valid tAA slow fast 3 × TC + TL – 7 2 × TC + TL – 7 — — 63 43 — — 46 30 — — 32.8 21.4 ns ns 45 CAS Assertion to Data Active TCLZ 0 0 — 0 — 0 — ns 46 RAS Assertion Pulse Width1 (Page Mode Access Only) tRASP 3 × TC –11 + n × 4 × TC 2 × TC –11 + n × 3 × TC 209 — 156 — 114 — ns 149 — 110 — 79.9 — ns 47 RAS Assertion Pulse Width (Single Access Only) tRAS slow fast 7 × TC – 11 5 × TC – 11 129 89 — — 95 65 — — 68.5 45.8 — — ns ns 48 RAS or CAS Deassertation to RAS Assertion tRP, TCRP slow fast 5 × TC – 5 3 × TC – 5 95 55 — — 70 40 — — 51.8 29.1 — — ns ns 49 CAS Assertion Pulse Width TCAS slow fast 3 × TC – 10 2 × TC – 10 50 30 — — 35 20 — — 24.1 12.7 — — ns ns 50 Last CAS Assertion to RAS Deassertation (Page Mode Access Only) tRSH slow fast 3 × TC – 15 2 × TC – 15 45 25 — — 30 15 — — 19.1 7.7 — — ns ns 51 RAS or WR Assertion to CAS Deassertation TCSH, TCWL slow fast 7 × TC – 15 5 × TC – 15 125 85 — — 91 61 — — 64.5 41.8 — — ns ns 52 RAS Assertion to CAS Assertion tRCD slow fast 4 × TC – 13 3 × TC – 13 67 47 — — 47 32 — — 32.5 21.1 — — ns ns 53 RAS Assertion to Column Address Valid tRAD slow 3 × TC + TH – 13 2 × TC + TH – 13 57 — 40 — 26.8 — ns 37 — 25 — 15.4 — ns slow fast fast MOTOROLA DSP56007/D 2-9 Specifications External Memory Interface (EMI) DRAM Timing Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics Symbol Timing Mode 50 MHz 66 MHz 88 MHz Expression Unit Min Max Min Max Min Max 54 CAS Deassertation Pulse Width (Page Mode Access Only) TCP TC – 5 15 — 10 — 6.4 — ns 55 Row Address Valid to RAS Assertion (Row Address Setup Time) tASR TL – 6 4 — 2 — 0.1 — ns 56 RAS Assertion to ROW Address Not Valid (Row Address Hold Time) tRAH 3 × TC + TH – 14 2 × TC + TH – 14 56 — 39 — 25.8 — ns 36 — 24 — 14.4 — ns 57 Column Address Valid to CAS Assertion (Column Address Setup Time) tASC TL – 6 4 — 2 — 0.1 — ns 58 CAS Assertion to Column Address Not Valid (Column Address Hold Time) TCAH 3 × TC + TH – 14 2 × TC + TH – 14 56 — 39 — 25.8 — ns 36 — 24 — 14.4 — ns 59 Last CAS Assertion to Column Address Not Valid (Column Address Hold Time) TCAH 7 × TC + TH – 136 14 4 × TC + TH – 76 14 — 100 — 71.2 — ns — 54 — 37.1 — ns 7 × TC + TH – 136 14 5 × TC + TH – 96 14 — 100 — 71.2 — ns — 69 — 48.5 — ns slow fast slow fast slow fast 60 RAS Assertion to Column Address Not Valid tAR 61 Column Address Valid to RAS Deassertation tRAL slow fast 3 × TC + TL – 7 2 × TC + TL – 7 63 43 — — 46 30 — — 32.8 21.2 — — ns ns 62 CAS, RAS, RD, or WR Deassertation to WR or RD Assertion tRCH, tRRH slow fast 5 × TC – 11 3 × TC – 11 89 49 — — 65 35 — — 45.8 23.1 — — ns ns 63 CAS or RD Deassertation to Data Not Valid (Data Hold Time) tOFF, tGZ 0 0 — 0 — 0 — ns 2-10 slow fast DSP56007/D MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics Symbol 50 MHz Timing Mode Expression 66 MHz 88 MHz Unit Min Max Min Max Min Max 64 Random Read or Write Cycle Time (Single Access Only) tRC slow fast 12 × TC 8 × TC 240 98.8 — — 182 121 — — 136.4 91.0 — — ns ns 65 WR Deassertation to CAS Assertion tRCS slow fast 9 × TC – 11 6 × TC – 11 169 109 — — 125 80 — — 91.3 57.2 — — ns ns 66 CAS Assertion to WR Deassertation tWCH slow fast 3 × TC – 13 2 × TC – 13 47 27 — — 32 17 — — 21.1 9.7 — — ns ns TL – 6 4 — 2 — 0.1 — ns 3 × TC + TH – 14 2 × TC + TH – 14 56 — 39 — 25.8 — ns 36 — 24 — 14.4 — ns 7 × TC + TH – 136 14 5 × TC + TH – 96 14 — 100 — 71.2 — ns — 69 — 48.5 — ns 67 Data Valid to CAS Assertion (Data Setup Time) tDS 68 CAS Assertion to Data Not Valid (Data Hold Time) tDH 69 RAS Assertion to Data Not Valid tDHR slow fast slow fast 70 WR Assertion to CAS Assertion tWCS slow fast 4 × TC – 14 3 × TC – 14 66 46 — — 47 31 — — 31.4 20.1 — — ns ns 71 WR Assertion Pulse Width (Single Cycle Only) tWP slow fast 7 × TC – 9 5 × TC – 9 131 91 — — 97 67 — — 70.5 47.8 — — ns ns tWCR slow fast 7 × TC – 15 5 × TC – 15 125 85 — — 91 61 — — 64.5 41.8 — — ns ns slow 3 × TC + TH – 13 2 × TC + TH – 13 57 — 40 — 26.8 — ns 37 — 25 — 15.4 — ns 7 × TC – 13 5 × TC – 13 127 87 — — 93 63 — — 66.5 43.8 — — ns ns 72 RAS Assertion to WR Deassertation (Single Cycle Only) 73 WR Assertion to Data Active fast 74 RD or WR Assertion to RAS Deassertation (Single Cycle Only) Note: 1. tROH, tRWL slow fast n is the number of successive accesses. n = 2, 3, 4, or 6. MOTOROLA DSP56007/D 2-11 Specifications External Memory Interface (EMI) DRAM Timing 48 48 47 64 MRAS 74 52 50 65 49 MCAS 55 53 59 60 MA0–MA10 Row Address 56 Last Column Address 57 MWR 62 44 61 43 MRD 42 63 45 Data In MD0–MD7 AA0257 Figure 2-8 DRAM Single Read Cycle 2-12 DSP56007/D MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing 48 46 48 60 50 MRAS 65 41 54 54 52 49 49 49 MCAS 51 61 55 53 MA0–MA10 58 Row Address 58 Col. Address Col. Address 56 59 Last Column Address 57 57 MWR 62 57 44 44 44 43 43 MRD 43 42 45 MD0–MD7 63 63 45 Data In 63 45 Data In Data In AA0263 Figure 2-9 DRAM Page Mode Read Cycle MOTOROLA DSP56007/D 2-13 Specifications External Memory Interface (EMI) DRAM Timing 64 48 47 48 MRAS 74 52 50 65 49 MCAS 55 61 53 59 60 MA0–MA10 Row Address Column Address 56 57 70 66 62 72 MWR 71 MRD 69 67 68 73 MD0–MD7 Data Out AA0264 Figure 2-10 DRAM Single Write Cycle 2-14 DSP56007/D MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing 48 46 48 60 50 MRAS 65 41 54 54 52 49 49 49 MCAS 51 61 55 53 MA0–MA10 58 Row Address Col. Address 58 Col. Address 56 59 Last Column Address 66 57 57 57 70 62 MWR MRD 69 67 73 MD0–MD7 68 68 68 67 Data Out 67 Data Out Data Out AA0265 Figure 2-11 DRAM Page Mode Write Cycle MOTOROLA DSP56007/D 2-15 Specifications External Memory Interface (EMI) DRAM Refresh Timing EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING (CL = 50pF + 2 TTL Loads) Table 2-9 External Memory Interface (EMI) DRAM Refresh Timing No. Characteristics Sym. 50 MHz Timing Mode Exp. 66 MHz 88 MHz Unit Min Max Min Max Min Max 81 RAS Deassertation to RAS Assertion tRP slow fast1 6 × TC – 7 4 × TC – 7 113 73 — — 84 — — — 61.2 — — — ns ns 82 CAS Deassertation to CAS Assertion TCPN slow fast1 5 × TC – 7 3 × TC – 7 93 53 — — 71 — — — 49.8 — — — ns ns 83 Refresh Cycle Time tRC slow fast1 13 × TC 9 × TC 260 180 — — 197 — — 147.7 — — — — ns ns 84 RAS Assertion Pulse Width tRAS slow fast1 7 × TC – 9 5 × TC – 9 131 91 — — 97 — — — 70.5 — — — ns ns 85 RAS Deassertation to RAS Assertion for Refresh Cycle2 tRP slow fast1 5 × TC – 5 3 × TC – 5 95 55 — — 70 — — — 51.8 — — — ns ns 86 CAS Assertion to RAS Assertion on Refresh Cycle TCSR TC – 7 13 — 8 — 4.4 — ns 87 RAS Assertion to CAS Deassertation on Refresh Cycle TCHR slow fast1 7 × TC – 15 5 × TC – 15 125 85 — — 91 — — — 64.5 — — — ns ns 88 RAS Deassertation to CAS Assertion on a Refresh Cycle tRPC slow fast1 5 × TC – 11 3 × TC – 11 89 49 — — 65 — — — 45.8 — — — ns ns 89 CAS Deassertation to Data Not Valid tOFF 0 0 — 0 — 0 — ns Note: 2-16 1. 2. Fast mode is not available for operating frequencies above 50 MHz. This happens when a Refresh Cycle is followed by an Access Cycle. DSP56007/D MOTOROLA Specifications External Memory Interface (EMI) SRAM Timing 83 81 84 85 MRAS 88 82 87 MCAS 86 89 MD0–MD7 Data In AA0266 Figure 2-12 CAS before RAS Refresh Cycle EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING (CL = 50pF + 2 TTL Loads) Table 2-10 External Memory Interface (EMI) SRAM Timing 50 MHz No. Characteristics Symbol 66 MHz 88 MHz Expression Unit Min Max Min Max Min Max tRC, tWC 4 × TC – 11 + Ws × TC 69 — 50 — 34.5 — ns 92 Address Valid to RD or WR Assertion tAS TC + TL – 13 17 — 10 — 4.4 — ns 93 RD or WR Assertion Pulse Width tWP 2 × TC – 5 + Ws × TC 35 — 23 — 17.7 — ns 94 RD or WR Deassertation to RD or WR Assertion — 2 × TC – 11 29 — 19 — 11.7 — ns 95 RD or WR Deassertation to Address not Valid tWR TH – 6 4 — 2 — 0.1 — ns 3 × TC + TL –15 + Ws × TC — 55 — 38 — 24.8 ns 91 Address Valid and CS Assertion Pulse Width 96 Address Valid to Input Data tAA, tAC Valid 97 RD Assertion to Input Data Valid tOE 2 × TC – 15 + Ws × TC — 25 — 15 — 7.7 ns 98 RD Deassertation to Data Not Valid (Data Hold Time) tOHZ 0 0 — 0 — 0 — ns MOTOROLA DSP56007/D 2-17 Specifications External Memory Interface (EMI) SRAM Timing Table 2-10 External Memory Interface (EMI) SRAM Timing 50 MHz No. Characteristics Symbol 66 MHz 88 MHz Expression Unit Min Max Min Max Min Max 99 Address Valid to WR Deassertation TCW, tAW 3 × TC + TL –14 + Ws × TC 56 — 39 — 25.8 — ns 100 Data Setup Time to WR Deassertation tDS (tDW) TC + TL – 5 + Ws × TC 25 — 18 — 12.0 — ns tDH TH – 6 4 — 2 — 0.1 — ns 102 WR Assertion to Data Valid — TH + 4 — 14 — 12 — 9.7 ns 103 WR Deassertation to Data high impedance1 — TH + 10 — 20 — 18 — 15.7 ns 104 WR Assertion to Data Active — TH – 6 4 — 2 — 0.1 — ns 101 Data Hold Time from WR Deassertation Note: 1. This value is periodically sampled and not 100% tested. MA0–MA14 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS 91 92 MCS0 95 94 93 RD 94 WR 97 98 96 Data In MD0–MD7 AA0267 Figure 2-13 SRAM Read Cycle 2-18 DSP56007/D MOTOROLA Specifications External Memory Interface (EMI) SRAM Timing MA0–MA14 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS 91 MCS0 99 95 93 92 WR 94 94 RD 100 102 103 Data Out MD0–MD7 104 101 AA0268 Figure 2-14 SRAM Write Cycle MOTOROLA DSP56007/D 2-19 Specifications Serial Audio Interface (SAI) Timing SERIAL AUDIO INTERFACE (SAI) TIMING (CL = 50pF + 2 TTL Loads) Table 2-11 Serial Audio Interface (SAI) Timing 50 MHz No. Characteristics Mode 66 MHz 81 MHz Expression Unit Min Max Min Max Min Max 111 Minimum Serial Clock Cycle = tSAICC (min) master slave 4 × TC 3 × TC + 5 80 65 — — 61 51 — — 45.5 39.1 — — ns ns 112 Serial Clock High Period master slave 0.5 × tSAICC – 8 0.35 × tSAICC 32 23 — — 22 18 — — 14.7 13.7 — — ns ns 113 Serial Clock Low Period master slave 0.5 × tSAICC – 8 0.35 × tSAICC 32 23 — — 22 18 — — 14.8 13.7 — — ns ns 114 Serial Clock Rise/Fall Time master slave 8 0.15 × tSAICC — — 8 10 — — 8 8 — — 8.0 5.9 ns ns 115 Data In Valid to SCKR edge (Data In Set-up Time) master slave 26 4 26 4 — — 26 4 — — 26 4 — — ns ns 116 SCKR Edge to Data In Not Valid (Data In Hold Time) master slave 0 14 0 14 — — 0 14 — — 0 14 — — ns ns 117 SCKR Edge to Word Select Out master Valid (WSR Out Delay Time) 20 — 20 — 20 — 20 ns 118 Word Select In Valid to SCKR Edge (WSR In Set-up Time) slave 12 12 — 12 — 12 — ns 119 SCKR Edge to Word Select In Not Valid (WSR In Hold Time) slave 12 12 — 12 — 12 — ns master slave1 slave2 13 40 TH + 34 — — — 13 40 44 — — — 13 40 41 — — — 13 40 39.7 ns ns ns 122 SCKT Edge to Word Select Out master Valid (WST Out Delay Time) 19 — 19 — 19 — 19 ns 123 Word Select In Valid to SCKT Edge (WST In Set-up Time) slave 12 12 — 12 — 12 — ns 124 SCKT Edge to Word Select In Not Valid (WST In Hold Time) slave 12 12 — 12 — 12 — ns 121 SCKT Edge to Data Out Valid (Data Out Delay Time) Note: 2-20 1. 2. When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater When the Frequency Ratio between Parallel and Serial clocks is 1:3 – 1:4 DSP56007/D MOTOROLA Specifications Serial Audio Interface (SAI) Timing 111 112 114 114 113 SCKR (RCKP = 1) 111 113 114 SCKR (RCKP = 0) 114 112 115 116 SDI0–SDI1 (Data Input) Valid 119 118 WSR (Input) Valid 117 WSR (Output) AA0269 Figure 2-15 SAI Receiver Timing MOTOROLA DSP56007/D 2-21 Specifications Serial Audio Interface (SAI) Timing 111 112 114 114 113 SCKT (TCKP = 1) 111 113 114 SCKT (TCKP = 0) 114 112 121 SDO0–SDO2 (Data Output) 124 123 WST (Input) Valid 122 WST (Output) AA0270 Figure 2-16 SAI Transmitter Timing 2-22 DSP56007/D MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING (CL = 50 pF; VIHS = 0.7 × VCC, VILS = 0.3 × VCC) Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing No. Characteristics Mode Tolerable Spike Width on Clock or Data In 50 MHz Filter Mode 66 MHz 88 MHz Expression Unit Min Max Min Max Min bypassed narrow wide Max — — — 0 20 100 — — — 0 20 100 — — — 0 20 100 ns ns ns 4 × TC — — — — — — ns 6 × TC 1000 2000 3 × TC 3 × TC + 25 3 × TC + 85 3 × TC + 79 3 × TC + 431 3 × TC + 1022 120 1000 2000 60 85 145 139 491 1082 — — — — — — — — — 91 1000 2000 45 70 130 124 476 1067 — — — — — — — — — 68.2 1000 2000 34.1 59.1 119.1 113.1 465.1 1056.1 — — — — — — — — — ns ns ns ns ns ns ns ns ns 142 Serial Clock High Period master CPHA = 0, CPHA = 12 slave bypassed narrow CPHA = 1 wide slave bypassed narrow wide 0.5 × tSPICC –10 50 — 35 — 24.1 — ns TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 28 51 63 70 246 541 — — — — — — 23 46 58 63 239 534 — — — — — — 19.4 42.4 54.4 57.0 233.0 528.0 — — — — — — ns ns ns ns ns ns 143 Serial Clock Low Period master CPHA = 0, CPHA = 12 slave bypassed narrow CPHA = 1 wide slave bypassed narrow wide 0.5 × tSPICC –10 50 — 35 — 24.1 — ns TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 28 51 63 70 246 541 — — — — — — 23 46 58 63 239 534 — — — — — — 19.4 42.4 54.4 57.0 233.0 528.0 — — — — — — ns ns ns ns ns ns 10 2000 — — 10 2000 — — 10 2000 — — 10 2000 ns ns 141 Minimum Serial Clock Cycle = tSPICC(min) For frequency below 33 master bypassed MHz1 For frequency above 33 MHz1 bypassed narrow CPHA = 0, CPHA = 12 wide slave bypassed narrow CPHA = 1 wide slave bypassed narrow wide 144 Serial Clock Rise/Fall Time MOTOROLA master slave DSP56007/D 2-23 Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics 146 SS Assertion to First SCK Edge CPHA = 0 CPHA = 1 147 Last SCK Edge to SS Not Asserted CPHA = 0 CPHA = 13 148 Data In Valid to SCK Edge (Data In Set-up Time) Mode slave slave slave slave 50 MHz 66 MHz 88 MHz Filter Mode Expression bypassed narrow wide bypassed narrow wide TC + TH + 35 TC + TH + 35 TC + TH + 35 6 0 0 65 65 65 6 0 0 — — — — — — 58 58 58 6 0 0 — — — — — — 52.0 52.0 52.0 6 0 0 — — — — — — ns ns ns ns ns ns bypassed narrow wide bypassed narrow wide TC + 6 TC + 70 TC + 197 2 66 193 26 90 217 2 66 193 — — — — — — 21 85 212 2 66 193 — — — — — — 17.4 81.4 208.4 2 66 193 — — — — — — ns ns ns ns ns ns 0 17 — — 0 22 — — 0 25.6 — — ns ns 32 — 37 — 40.6 — ns 0 18 — — 0 23 — — 0 26.6 — — ns ns 33 — 38 — 41.6 — ns 57 58 68 57 58 68 — — — — — — 47 48 58 47 48 58 — — — — — — 39.7 40.7 50.7 39.7 40.7 50.7 — — — — — — ns ns ns ns ns ns Unit Min Max Min Max Min master bypassed 0 narrow MAX {(37 –TC), 0} MAX {(52 –TC), 0} 0 wide MAX {(38 –TC), 0} slave bypassed MAX {(53 –TC), 0} narrow wide 149 SCK Edge to Data In Not master bypassed Valid narrow (Data In Hold Time) wide slave bypassed narrow wide 2 2 2 2 2 2 × × × × × × TC + 17 TC + 18 TC + 28 TC + 17 TC + 18 TC + 28 Max 150 SS Assertion to Data Out slave Active 4 4 — 4 — 4 — ns 151 SS Deassertation to Data high impedance4 24 — 24 — 24 — 24 ns 41 214 504 41 214 504 TC + TH + 40 TC + TH + 216 TC + TH + 511 — — — — — — — — — 41 214 504 41 214 504 70 246 541 — — — — — — — — — 41 214 504 41 214 504 63 239 534 — — — — — — — — — 41 214 504 41 214 504 57.0 233 528 ns ns ns ns ns ns ns ns ns 152 SCK Edge to Data Out Valid (Data Out Delay Time) CPHA = 0, CPHA = 12 CPHA = 1 2-24 slave master bypassed narrow wide slave bypassed narrow wide slave bypassed narrow wide DSP56007/D MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics 153 SCK Edge to Data Out Not Valid (Data Out Hold Time) Mode slave 158 Last SCK Sampling Edge slave to HREQ Output Not Deasserted CPHA = 1 66 MHz 88 MHz Expression Unit Min Max Min Max Min master bypassed narrow wide slave bypassed narrow wide 154 SS Assertion to Data Out slave Valid CPHA = 0 157 First SCK Sampling Edge to HREQ Output Deassertation 50 MHz Filter Mode Max 0 57 163 0 57 163 0 57 163 0 57 163 — — — — — — 0 57 163 0 57 163 — — — — — — 0 57 163 0 57 163 — — — — — — ns ns ns ns ns ns TC + TH + 35 — 65 — 58 — 52.0 ns — — — 102 279 577 — — — 85 262 560 — — — 71.8 ns 248.8 ns 546.8 ns bypassed 2 × TC + TH + 6 56 narrow 2 × TC + TH + 63 113 wide 2 × TC + TH + 169 219 — — — 44 101 207 — — — 34.4 91.4 197.4 bypassed 3 × TC + TH + 32 narrow 3 × TC + TH + 209 wide 3 × TC + TH + 507 — — — ns ns ns 159 SS Deassertation to HREQ Output Not Deasserted CPHA = 0 slave 2 × TC + TH + 7 57 160 SS Deassertation Pulse Width CPHA = 0 slave TC + 4 24 — 19 — 15.4 — ns 161 HREQ In Assertion to First SCK Edge master 0.5 × tSPICC+ 2 × TC + 6 106 — 82 — 62.8 — ns 162 HREQ In Deassertation to Last SCK Sampling Edge (HREQ In Set-up Time) CPHA = 1 master 0 0 — 0 — 0 — ns 163 First SCK Edge to HREQ master In Not Asserted (HREQ In Hold Time) 0 0 — 0 — 0 — ns Note: 1. 2. 3. 4. 5. 45 35.4 ns For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency ratio is 6:1. In CPHA = 1 mode, the SPI slave supports data transfers at tSPICC = 3 × TC, if the user assures that the HTX is written at least TC ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave supports data transfers at tSPICC = 3 × TC, if the user assures that the HTX is written at least TC ns before the first edge of SCK of each word. When CPHA = 1, the SS line may remain active low between successive transfers. Periodically sampled, not 100% tested Refer to the DSP56007 User’s Manual for a detailed description of how to use the different filtering modes. MOTOROLA DSP56007/D 2-25 Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 141 142 144 144 SCK (CPOL = 0) (Output) 142 144 143 141 144 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid LSB Valid 152 MOSI (Output) 149 148 153 MSB 161 LSB 163 HREQ (Input) AA0271 Figure 2-17 SPI Master Timing (CPHA = 0) 2-26 DSP56007/D MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 141 142 144 144 SCK (CPOL = 0) (Output) 142 141 144 143 SCK (CPOL = 1) (Output) 144 148 148 149 MISO (Input) 149 MSB Valid LSB Valid 152 MOSI (Output) 153 MSB LSB 161 162 163 HREQ (Input) AA0272 Figure 2-18 SPI Master Timing (CPHA = 1) MOTOROLA DSP56007/D 2-27 Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 141 142 144 147 144 160 SCK (CPOL = 0) (Input) 146 142 143 141 144 144 SCK (CPOL = 1) (Input) 154 152 153 153 150 MISO (Output) 151 MSB 148 LSB 148 149 MOSI (Input) MSB Valid 149 LSB Valid 157 159 HREQ (Output) AA0273 Figure 2-19 SPI Slave Timing (CPHA = 0) 2-28 DSP56007/D MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 141 142 144 147 144 SCK (CPOL = 0) (Input) 146 142 143 144 144 SCK (CPOL = 1) (Input) 152 152 153 150 MISO (Output) 151 MSB LSB 148 148 149 MOSI (Input) MSB Valid 149 LSB Valid 157 158 HREQ (Output) AA0274 Figure 2-20 SPI Slave Timing (CPHA = 1) MOTOROLA DSP56007/D 2-29 Specifications Serial Host Interface (SHI) I2C Protocol Timing SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING (VIHS = 0.7 × VCC, VILS = 0.3 × VCC) (VOHS = 0.8 × VCC, VOLS = 0.2 × VCC) (RP (min) = 1.5 kΩ) Table 2-13 SHI I2C Protocol Timing Standard I2C (CL = 400 pF, RP = 2 kΩ, 100 kHz) All frequencies No. — Characteristics Symbol Tolerable Spike Width on SCL or SDA Filters Bypassed Narrow Filters Enabled Wide Filters Enabled Unit Min Max — — — 0 20 100 ns ns ns 171 Minimum SCL Serial Clock Cycle tSCL 10.0 — µs 172 Bus Free Time tBUF 4.7 — µs 173 Start Condition Set-up Time tSU;STA 4.7 — µs 174 Start Condition Hold Time tHD;STA 4.0 — µs 175 SCL Low Period tLOW 4.7 — µs 176 SCL High Period tHIGH 4.0 — µs 177 SCL and SDA Rise Time tr — 1.0 µs 178 SCL and SDA Fall Time tf — 0.3 µs 179 Data Set-up Time tSU;DAT 250 — ns 180 Data Hold Time tHD;DAT 0.0 — ns 182 SCL Low to Data Out Valid tVD;DAT — 3.4 µs 183 Stop Condition Set-up Time tSU;STO 4.0 — µs Note: 2-30 Refer to the DSP56007 modes. User’s Manual for a detailed description of how to use the different filtering DSP56007/D MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing The Programmed Serial Clock Cycle, t I2CCP , is specified by the value of the HDM5– HDM0 and HRS bits of the HCKR (SHI Clock control Register). The expression for t I2CCP is: t 2 I CCP = [ Tc × 2 × ( HDM[5:0] + 1 ) × ( 7 × ( 1 – HRS ) + 1 ) ] where • HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-byeight prescaler is operational. When HRS is set, the prescaler is bypassed. • HDM5–HDM0 are the Divider Modulus Select bits. • A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected. In I2C mode, you may select a value for the Programmed Serial Clock Cycle from (HDM5–HDM0 = 2, HRS = 1) to 6 × TC (HDM5–HDM0 = $3F, HRS = 0). 1024 × TC The DSP56007 provides an improved I2C bus protocol. In addition to supporting the 100 kHz I2C bus protocol, the SHI in I2C mode supports data transfers at up to 1000 kHz. The actual maximum frequency is limited by the bus capacitances (CL),the pullup resistors (RP), (which affect the rise and fall time of SDA and SCL, (see table below)), and by the input filters. Consideration for programming the SHI Clock Control Register (HCKR)—Clock Divide Ratio: the master must generate a bus free time greater than T172 slave when operating with a DSP56007 SHI I2C slave. The table below describes a few examples: Table 2-14 Considerations for Programming the SHI Clock control Register (HCKR) Conditions to be Considered Bus Load CL = 50 pF, RP = 2 kΩ MOTOROLA Master Operating Freq. Slave Operating Freq. 88 MHz 88 MHz Master Filter Mode Bypassed Narrow Wide Resulting Limitations Slave Filter Mode T172 Slave Bypassed 36 ns Narrow 60 ns Wide 95 ns DSP56007/D Min. Permissible tI CCP T172 Master Maximum I2C Serial Frequency 56 × TC 60 × TC 66 × TC 41 ns 66 ns 103 ns 1010 kHz 825 kHz 634 kHz 2 2-31 Specifications Serial Host Interface (SHI) I2C Protocol Timing Example: for CL = 50 pF, RP = 2 kΩ, f = 88 MHz, Bypassed Filter mode: The master, when operating with a DSP56007 SHI I2C slave with an 88 MHz operating frequency, must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum permissible tI2CCP is 56 × TC which gives a bus free time of at least 41 ns (T172 master). This implies a maximum I2C serial frequency of 1010 kHz. In general, bus performance may be calculated from the CL and RP of the bus, the Input Filter modes and operating frequencies of the master and the slave. Table 2-15 contains the expressions required to calculate all relevant performance timing for a given CL and RP. Table 2-15 SHI Improved I2C Protocol Timing Improved I2C (CL = 50 pF, RP = 2 kΩ) No. Char. Sym. Mode — Tolerable Spike Width on SCL or SDA 171 SCL Serial Clock Cycle tSCL master bypassed narrow wide — — — 0 20 100 — — — 0 ns 20 ns 100 ns 2 — 1007 — 981 — ns 2 — 1225 — 1199 — ns 2 — 1591 — 1557 — ns — 478 — 461 — ns — 672 — 655 — ns — 954 — 937 — ns slave bypassed narrow wide slave bypassed narrow wide 12 50 150 bypassed wide U n Min Max Min Max Min Max i t t I CCP + 3 × TC + 1050 72 + tr t I CCP + 3 × TC + 1263 245 + tr t I CCP + 3 × TC + 1593 535 + tr 4 × TC + TH + 500 172 + tr 4 × TC + TH + 694 366 + tr 4 × TC + TH + 976 648 + tr 0.5 × t I CCP – 42 – tr 0.5 × t I CCP – 42 – tr 0.5 × t I CCP – 42 – tr 2 × TC + 11 2 × TC + 35 2 × TC + 70 master narrow 2-32 0 20 100 0 20 100 bypassed tSU;STA — — — bypassed narrow wide slave 173 Start Condition Set-up Time 88 MHz4 Expression wide tBUF 66 MHz3 Filter Mode narrow 172 Bus Free Time 50 MHz2 2 60 — 46 — 38.2 — ns 2 80 — 68 — 60.9 — ns 2 100 — 102 — 95 — ns 51 75 110 — — — 41 65 100 — — — 33.7 57.7 92.7 — — — ns ns ns 12 50 150 — — — 12 50 150 — — — 12 50 150 — — — ns ns ns DSP56007/D MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 kΩ) No. Char. 174 Start Condition Hold Time Sym. Mode tHD;STA master Filter Mode bypassed narrow wide 175 SCL Low Period tLOW slave bypassed narrow wide master bypassed narrow wide 176 SCL High Period tHIGH slave bypassed narrow wide master bypassed narrow wide slave 177 SCL Rise Time Output1 bypassed narrow wide tr Input 178 SCL Fall Time Output1 tf Input 179 Data Set-up Time tSU;DAT MOTOROLA bypassed narrow wide 50 MHz2 66 MHz3 88 MHz4 0.5 × t I CCP + 12 – tf 0.5 × t I CCP + 12 – tf 0.5 × t I CCP + 12 – tf 2 × TC + TH + 21 2 × TC + TH + 100 2 × TC + TH + 200 2 332 — 318 — 310 — ns 2 352 — 340 — 333 — ns 2 372 — 378 — 367 — ns 71 150 250 — — — 59 138 238 — — — 49.4 128 228 — — — ns ns ns 0.5 × t I CCP + 18 – tf 0.5 × t I CCP + 18 – tf 0.5 × t I CCP + 18 – tf 2 × TC + 74 + tr 2 × TC + 286 + tr 2 × TC + 586 + tr 2 338 324 — ns 358 339 — ns 2 378 — — — — — — 316 2 — — — — — — 373 — ns 335 534 847 — — — ns ns ns 0.5 × t I CCP + 2 × TC + 19 0.5 × t I CCP + 2 × TC + 144 0.5 × t I CCP + 2 × TC + 356 2 × TC + TH – 1 2 × TC + TH + 18 2 × TC + TH + 30 379 — 375 — 360 — ns 2 544 — 523 — 507 — ns 2 776 — 773 — 754 — ns 49 68 80 — — — 37 56 68 — — — 27.4 46.4 58.4 — — — ns ns ns 1.7 × RP × (CL + 20) 2000 — 238 — 238 — 238 ns — 2000 — 2000 — 2000 ns 20 + 0.1 × (CL– 50) 2000 — 20 — 20 — — 2000 — 2000 — TC + 8 TC + 60 TC + 74 28 80 94 — — — 23 75 89 — — — 19.4 71.4 85.4 Expression 2 DSP56007/D U n Min Max Min Max Min Max i t 346 384 342 554 854 352 564 864 20 ns 2000 ns — — — 2-33 ns ns ns Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 kΩ) 50 MHz2 66 MHz3 88 MHz4 U n Min Max Min Max Min Max i t Filter Mode Expression tHD;DAT bypassed narrow wide 0 0 0 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 182 SCL Low to Data tVD;DAT Out Valid bypassed narrow wide 2 × TC + 71 + tr 2 × TC + 244 + tr 2 × TC + 535 + tr — — — 349 522 813 — — — 339 512 803 — — — 332 ns 505 ns 796 ns bypassed 2 381 — 359 — 346 — ns 2 459 — 440 — 427 — ns 2 613 — 592 — 575 — ns 11 50 150 — — — 11 50 150 — — — 11 50 150 — — — ns ns ns ns ns ns No. Char. 180 Data Hold Time Sym. Mode ns ns ns slave bypassed narrow wide 0.5 × t I CCP + TC + TH + 11 0.5 × t I CCP + TC + TH + 69 0.5 × t I CCP + TC + TH + 183 11 50 150 184 HREQ In Deassertation to Last SCL Edge (HREQ In Set-up Time) master bypassed narrow wide 0 0 0 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 186 First SCL Sampling Edge to HREQ Output Deassertation slave bypassed narrow wide 3 × TC + TH + 32 3 × TC + TH + 209 3 × TC + TH + 507 — — — 102 279 577 — — — 85 262 560 — — — 72 ns 249 ns 547 ns 187 Last SCL Edge to HREQ Output Not Deasserted slave bypassed narrow wide 2 × TC + TH + 6 56 2 × TC + TH + 63 113 2 × TC + TH + 169 219 — — — 44 101 207 — — — 34.4 91.4 197.4 — — — ns ns ns 188 HREQ In Assertion to First SCL Edge master bypassed narrow wide t I CCP + 2 × TC + 6 726 t I CCP + 2 × TC + 6 766 t I CCP + 2 × TC + 6 846 — — — 688 733 809 — — — 665 711 779 — — — ns ns ns 189 First SCL Edge to HREQ In Not Asserted (HREQ In Hold Time) master — 0 — 0 — ns 183 Stop Condition Set-up Time tSU;STO master narrow wide 2-34 2 2 2 0 DSP56007/D 0 MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 kΩ) 50 MHz2 No. Note: Char. 1. 2. Sym. Filter Mode Mode Expression 66 MHz3 88 MHz4 U n Min Max Min Max Min Max i t CL is in pF, RP is in kΩ, and result is in ns. A t I CCP of 34 × TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed Filter mode. A t I CCP of 36 × TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow Filter mode. A t I CCP of 40 × TC (the maximum permitted for the given bus load) was used for the calculations in the Wide Filter mode. A t I CCP of 43 × TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed Filter mode. A t I CCP of 46 × TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow Filter mode. A t I CCP of 51 × TC (the maximum permitted for the given bus load) was used for the calculations in the Wide Filter mode. A t I CCP of 56 × TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed Filter mode. A t I CCP of 60 × TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow Filter mode. A t I CCP of 66 × TC (the maximum permitted for the given bus load) was used for the calculations in the Wide Filter mode. Refer to the DSP56007 User’s Manual for a detailed description of how to use the different filtering modes. 2 2 2 3. 2 2 2 4. 2 2 2 5. 171 173 176 175 SCL 177 SDA Stop 180 178 172 179 Start MSB 174 188 LSB 186 189 182 ACK Stop 183 184 187 HREQ AA0275 Figure 2-21 I2C Timing MOTOROLA DSP56007/D 2-35 Specifications General Purpose I/O (GPIO) Timing GENERAL PURPOSE I/O (GPIO) TIMING (CL = 50 pF + 2 TTL Loads) Table 2-16 GPIO Timing 50/66/88 MHz No. Characteristics Expression Unit Min Max 201 EXTAL Edge to GPIO Out Valid (GPIO Out Delay Time) 26 — 26 ns 202 EXTAL Edge to GPIO Out Not Valid (GPIO Out Hold Time) 2 2 — ns 203 GPIO In Valid to EXTAL Edge (GPIO In Set-up Time) 10 10 — ns 204 EXTAL Edge to GPIO In Not Valid (GPIO In Hold Time) 6 6 — ns EXTAL (Input) (Note 1) 201 202 GPIO(0:3) (Output) 203 GPIO(0:3) (Input) Note: 204 Valid 1. Valid when the ratio between EXTAL frequency and internal clock frequency equals 1 AA0276 Figure 2-22 GPIO Timing 2-36 DSP56007/D MOTOROLA Specifications On-Chip Emulation (OnCE) Timing ON-CHIP EMULATION (OnCE) TIMING (CL = 50 pF + 2 TTL Loads) Table 2-17 OnCE Timing 50/66/88 MHz No. Characteristics Unit Min Max 230 DSCK Low 40 — ns 231 DSCK High 40 — ns 232 DSCK Cycle Time 200 — ns 233 DR Asserted to DSO (ACK) Asserted 5 TC — ns 234 DSCK High to DSO Valid — 42 ns 235 DSCK High to DSO Invalid 3 — ns 236 DSI Valid to DSCK Low (Set-up) 15 — ns 237 DSCK Low to DSI Invalid (Hold) 3 — ns 238 Last DSCK Low to OS0–OS1, ACK Active 3 TC + TL — ns 239 DSO (ACK) Asserted to First DSCK High 2 TC — ns 240 DSO (ACK) Assertion Width 4 TC + TH – 3 5 TC + 7 ns 241 DSO (ACK) Asserted to OS0–OS1 High Impedance1 — 0 ns 242 OS0–OS1 Valid to EXTAL Transition #2 T C – 21 — ns 243 EXTAL Transition #2 to OS0–OS1 Invalid 0 — ns 244 Last DSCK Low of Read Register to First DSCK High of Next Command 7 TC + 10 — ns 245 Last DSCK Low to DSO Invalid (Hold) 3 — ns 246 DR Assertion to EXTAL Transition #2 for Wake Up from WAIT State 10 TC – 10 ns 247 EXTAL Transition #2 to DSO After Wake Up from WAIT State 17 TC — ns MOTOROLA DSP56007/D 2-37 Specifications On-Chip Emulation (OnCE) Timing Table 2-17 OnCE Timing (Continued) 50/66/88 MHz No. 248 249 250A 250B 251 Note: Characteristics Unit Min Max 15 13 TC + 15 12 TC – 15 — ns ns 17 TC — ns 15 15 15 65548 TC + TL 20 TC + TL 13 TC + TL ns ns ns DR Assertion Width to Recover from STOP and enter Debug mode2 • Stable External Clock, OMR Bit 6 = 0 • Stable External Clock, OMR Bit 6 = 1 • Stable External Clock, PCTL Bit 17 = 1 65549 TC + TL 21 TC + TL 14 TC + TL — — — ns ns ns DR Assertion to DSO (ACK) Valid (Enter Debug mode) After Recovery from STOP State2 • Stable External Clock, OMR Bit 6 = 0 • Stable External Clock, OMR Bit 6 = 1 • Stable External Clock, PCTL Bit 17 = 1 65553 TC + TL 25 TC + TL 18 TC + TL — — — ns ns ns DR Assertion Width • to recover from WAIT • to recover from WAIT and enter Debug mode DR Assertion to DSO (ACK) Valid (Enter Debug mode) After Asynchronous Recovery from WAIT State DR Assertion Width to Recover from STOP2 • Stable External Clock, OMR Bit 6 = 0 • Stable External Clock, OMR Bit 6 = 1 • Stable External Clock, PCTL Bit 17 = 1 1. 2. Maximum TL Periodically sampled, not 100% tested 246 246 230 DSCK (input) 231 232 AA0277 Figure 2-23 DSP56007 OnCE Serial Clock Timing 2-38 DSP56007/D MOTOROLA Specifications On-Chip Emulation (OnCE) Timing DR (Input) 233 240 DSO (Output) ACK AA0278 Figure 2-24 DSP56007 OnCE Acknowledge Timing DSCK (Input) (Last) (OS1) DSO (Output) 236 237 (ACK) 238 DSI (Input) Note: (OS0) (Note 1) 1. High Impedance, external pull-down resistor AA0279 Figure 2-25 DSP56007 OnCE Data I/O to Status Timing DSCK (Input) (Last) 234 235 (Note 1) 245 DSO (Output) Note: (OS0) 1. High Impedance, external pull-down resistor AA0280 Figure 2-26 DSP56007 OnCE Read Timing 239 OS1 (Output) (Note 1) 241 (DSCK Input) 240 DSO (Output) (DSO Output) (DSI Input) OS0 (Output) 241 Note: (Note 1) 236 237 1. High Impedance, external pull-down resistor AA0281 Figure 2-27 DSP56007 OnCE Data I/O Status Timing MOTOROLA DSP56007/D 2-39 Specifications On-Chip Emulation (OnCE) Timing EXTAL (Note 2) 242 OS0–OS1 (Output) (Note 1) Note: 243 1. High Impedance, external pull-down resistor 2. Valid when the ratio between EXTAL frequency and clock frequency equals 1 AA0282 Figure 2-28 DSP56007 OnCE EXTAL to Status Timing DSCK (Input) (Next Command) 244 AA0283 Figure 2-29 DSP56007 OnCE DSCK Next Command After Read Register Timing EXTAL T0, T2 T1, T3 248 DR (Input) 246 247 DSO (Output) AA0284 Figure 2-30 Synchronous Recovery from WAIT State 248 DR (Input) 249 DSO (Output) AA0285 Figure 2-31 Asynchronous Recovery from WAIT State 2-40 DSP56007/D MOTOROLA Specifications On-Chip Emulation (OnCE) Timing 250 DR (Input) 251 DSO (Output) AA0286 Figure 2-32 Asynchronous Recovery from STOP State MOTOROLA DSP56007/D 2-41 Specifications On-Chip Emulation (OnCE) Timing 2-42 DSP56007/D MOTOROLA SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56007 is available in an 80-pin Quad Flat Pack (QFP) package. MOTOROLA DSP56007/D 3-1 Packaging Pin-out and Package Information QFP Package Description DSCK/OS1 DSI/OS0 DSO SDI0 SDI1 WSR GNDS VCCQ GNDQ SCKR WST SCKT VCCS SDO0 SDO1 SDO2 GNDS HREQ SS/HA2 MOSI/HA0 Top and bottom views of the QFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. 41 61 (Top View) Orientation Mark 21 1 VCCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GNDS VCCP PCAP GNDP PINIT GNDQ VCCQ EXTAL SCK/SCL MA0 MA1 MA2 MA3 GNDA GNDA MCS0 MA15/MCS3 MA14 MA13 VCCA MA12 GNDA VCCQ GNDQ MA11 MA10 MA9 MA8 GNDA MA7 VCCA MA6 MA5 MA4 DR MD7 MD6 MD5 MD4 GNDD MD3 MD2 MD1 VCCD MD0 GNDD GPIO3 GPIO2 GPIO1 GPIO0 MRD MWR MA17/MCS1/MRAS MA16/MCS2/MCAS Note: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-1 Top View 3-2 DSP56007/D MOTOROLA Packaging MOSI/HA0 SS/HA2 HREQ GNDS SDO2 SDO1 SDO0 VCCS SCKT WST SCKR GNDQ VCCQ GNDS WSR SDI1 SDI0 DSO DSI/OS0 DSCK/OS1 Pin-out and Package Information 41 61 (Bottom View) Orientation Mark 21 1 DR MD7 MD6 MD5 MD4 GNDD MD3 MD2 MD1 VCCD MD0 GNDD GPIO3 GPIO2 GPIO1 GPIO0 MRD MWR MA17/MCS1/MRAS MA16/MCS2/MCAS VCCA MA7 GNDA MA8 MA9 MA10 MA11 GNDQ VCCQ GNDA MA12 VCCA MA13 MA14 MA15/MCS3 MCS0 GNDA MA4 MA5 MA6 VCCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GNDS VCCP PCAP GNDP PINIT GNDQ VCCQ EXTAL SCK/SCL MA0 MA1 MA2 MA3 GNDA Note: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-2 Bottom View MOTOROLA DSP56007/D 3-3 Packaging Pin-out and Package Information Table 3-1 DSP56007 Pin Identification by Pin Number Pin # Signal Name Pin # Signal Name Pin # Signal Name 1 GNDA 28 VCCQ 55 WSR 2 MCS0 29 GNDQ 56 SDI1 3 MA15/MCS3 30 PINIT 57 SDI0 4 MA14 31 GNDP 58 DSO 5 MA13 32 PCAP 59 DSI/OS0 6 VCCA 33 VCCP 60 DSCK/OS1 7 MA12 34 GNDS 61 DR 8 GNDA 35 MISO/SDA 62 MD7 9 VCCQ 36 RESET 63 MD6 10 GNDQ 37 MODA/IRQA 64 MD5 11 MA11 38 MODB/IRQB 65 MD4 12 MA10 39 MODC/NMI 66 GNDD 13 MA9 40 VCCS 67 MD3 14 MA8 41 MOSI/HA0 68 MD2 15 GNDA 42 SS/HA2 69 MD1 16 MA7 43 HREQ 70 VCCD 17 VCCA 44 GNDS 71 MD0 18 MA6 45 SDO2 72 GNDD 19 MA5 46 SDO1 73 GPIO3 20 MA4 47 SDO0 74 GPIO2 21 GNDA 48 VCCS 75 GPIO1 22 MA3 49 SCKT 76 GPIO0 23 MA2 50 WST 77 MRD 24 MA1 51 SCKR 78 MWR 25 MA0 52 GNDQ 79 MA17/MCS1/ MRAS 26 SCK/SCL 53 VCCQ 80 MA16/MCS2/ MCAS 27 EXTAL 54 GNDS 3-4 DSP56007/D MOTOROLA Packaging Pin-out and Package Information Table 3-2 DSP56007 Pin Identification by Signal Name Signal Name Pin # Signal Name Pin # Signal Name Pin # DR 61 MA5 19 MRD 77 DSCK 60 MA6 18 MWR 78 DSI 59 MA7 16 NMI 39 DSO 58 MA8 14 OS0 59 EXTAL 27 MA9 13 OS1 60 GNDA 1 MA10 12 PCAP 32 GNDA 8 MA11 11 PINIT 30 GNDA 15 MA12 7 RESET 36 GNDA 21 MA13 5 SCK 26 GNDD 66 MA14 4 SCKR 51 GNDD 72 MA15 3 SCKT 49 GNDP 31 MA16 80 SCL 26 GNDQ 10 MA17 79 SDA 35 GNDQ 29 MCAS 80 SDI0 57 GNDQ 52 MCS0 2 SDI1 56 GNDS 34 MCS1 79 SDO0 47 GNDS 44 MCS2 80 SDO1 46 GNDS 54 MCS3 3 SDO2 45 GPIO0 76 MD0 71 SS 42 GPIO1 75 MD1 69 VCCA 6 GPIO2 74 MD2 68 VCCA 17 GPIO3 73 MD3 67 VCCD 70 HA0 41 MD4 65 VCCP 33 HA2 42 MD5 64 VCCQ 9 HREQ 43 MD6 63 VCCQ 28 IRQA 37 MD7 62 VCCQ 53 IRQB 38 MISO 35 VCCS 40 MA0 25 MODA 37 VCCS 48 MA1 24 MODB 38 WSR 55 MA2 23 MODC 39 WST 50 MA3 22 MOSI 41 MA4 20 MRAS 79 MOTOROLA DSP56007/D 3-5 Packaging Pin-out and Package Information Table 3-3 DSP56007 Power Supply Pins Pin # 6 Signal Name VCCA Circuit Supplied Address Bus Buffers 17 1 GNDA 8 15 21 70 VCCD 66 GNDD Data Bus Buffers 72 9 VCCQ Internal Logic 28 53 10 GNDQ 29 52 33 VCCP 31 GNDP 40 VCCS PLL Serial Ports 48 34 GNDS 44 54 3-6 DSP56007/D MOTOROLA Packaging Pin-out and Package Information L 60 41 61 S D M V P H A-B S A-B M B A-B L C -B- -A- B B S S D 40 0.20 DETAIL A 0.05 0.20 -A,B,D- 21 80 1 F 20 -D- A 0.20 M 0.05 A-B C A-B 0.20 M S D S S D S H A-B D M E DETAIL C C -H- DATUM PLANE 0.20 M C A-B S D S SECTION B-B 0.01 H SEATING PLANE M G CASE 841B-01 ISSUE O U T DATUM PLANE N J S -C- DETAIL A -H- R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC 0.25 0.13 0.23 0.65 0.95 12.35 BSC 55 105 0.13 0.17 0.325 BSC 05 75 0.13 0.30 16.95 17.45 0.13 05 16.95 17.45 0.35 0.45 1.6 REF Figure 3-3 80-pin Quad Flat Pack (QFP) Mechanical Information MOTOROLA DSP56007/D 3-7 Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56007 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: (602) 244-6591 The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • The caller’s Personal Identification Number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. • The type of information requested: – Instructions for using the system – A literature order form – Specific part technical information or data sheets – Other information described by the system messages A total of three documents may be ordered per call. The DSP56007 80-pin QFP package mechanical drawing is referenced as 841B-01. 3-8 DSP56007/D MOTOROLA SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: T J = T A + ( P D × R θJA ) Where: TA = ambient temperature ˚C RθJA = package junction-to-ambient thermal resistance ˚C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R θJA = R θJC + R θCA Where: RθJA = package junction-to-ambient thermal resistance ˚C/W RθJC = package junction-to-case thermal resistance ˚C/W RθCA = package case-to-ambient thermal resistance ˚C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. MOTOROLA DSP56007/D 4-1 Design Considerations Thermal Design Considerations The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. • To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. • If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ – TT)/PD. As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4-2 DSP56007/D MOTOROLA Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Use the following list of recommendations to assure correct DSP operation: MOTOROLA • Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. • Use at least four 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 in per capacitor lead. • Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND. • Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, and NMI pins. Maximum Printed Circuit Board (PCB) trace lengths on the order of 6 inches are recommended. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. • All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except as noted in Section 1. • Take special care to minimize noise levels on the VCCP and GNDP pins. • If multiple DSP56007 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. DSP56007/D 4-3 Design Considerations Power Consumption Considerations POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the formula: Equation 3: I = C × V × f where: C = node/pin capacitance in farads V = voltage swing f = frequency of node/pin toggle in hertz Example 4-1 Current Consumption For an I/O pin loaded with 50 pF capacitance, operating at 5.25 V, and with a 88 MHz clock, toggling at its maximum possible rate (22 MHz), the current consumption is: Equation 4: I = 50 × 10 – 12 6 × 5.25 × 22 × 10 = 5.78mA The Maximum Internal Current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The Typical Internal Current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption: 4-4 • Minimize the number of pins that are switching. • Minimize the capacitive load on the pins. • Connect the unused inputs to pull-up or pull-down resistors. • Disable unused peripherals. • Disable unused pin activity. DSP56007/D MOTOROLA Design Considerations Power Consumption Considerations Current consumption test code: org TP1 MOTOROLA p:RESET jmp org movep move move move move nop rep move rep mov clr move rep mac move jmp nop jmp MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF,m0 #$00FF,m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 a,p:(r5) TP1 y:(r4)+,y0 MAIN DSP56007/D 4-5 Design Considerations Power-Up Considerations POWER-UP CONSIDERATIONS To power-up the device properly, ensure that the following conditions are met: • Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics). • The external clock oscillator is active and stable. • RESET is asserted according to the specifications in Table 2-7 (Reset, Stop, Mode Select, and Interrupt Timing). • The following input pins are driven to valid voltage levels: DR, PINIT, MODA, MODB, and MODC. Care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on Table 2-1 (Maximum Ratings), at all phases of the power-up procedure. This may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip. At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state. 4-6 DSP56007/D MOTOROLA SECTION 5 ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information Supply Voltage Part DSPB560071 DSPE560072 Note: 1. 2. 5V 5V Package Type Pin Count Frequency (MHz) Order Number 80 50 DSPB56007FJ50 66 DSPB56007FJ66 88 DSPB56007FJ88 50 DSPE56007FJ50 66 DSPE56007FJ66 88 DSPE56007FJ88 Quad Flat Pack (QFP) Quad Flat Pack (QFP) 80 The DSPB56007 includes a generic factory-programmed ROM and may be used for RAM-based applications. For additional information on future part development, or to request specific ROMbased support, call your local Motorola Semiconductor sales office or authorized distributor. The DSPE56007 includes factory-programmed ROM containing support for Dolby Pro Logic and Lucasfilm THX applications. This part can be used only be customers licensed for Dolby Pro Logic and Lucasfilm THX. To request specific support for this chip, call your local Motorola Semiconductor sales office or authorized distributor. MOTOROLA DSP56007/D 5-1 OnCE, Mfax, and Symphony are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447 Mfax™: [email protected] TOUCHTONE (602) 244-6609 US & Canada ONLY (800) 774-1848 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC 6F Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 81-3-3521-8315 Technical Resource Center: 1 (800) 521-6274 DSP Helpline [email protected] Internet: http://www.motorola-dsp.com