® ADS7833 10-Channel, 12-Bit DATA ACQUISITION SYSTEM FEATURES APPLICATIONS ● 3 SIMULTANEOUS SAMPLED CHANNELS ● AC MOTOR SPEED CONTROLS ● THREE PHASE POWER CONTROL ● 3 SYNCHRONIZED 12-BIT ADCs ● 6.6µs THROUGHPUT RATE ● UNINTERRUPTABLE POWER SUPPLIES ● VIBRATION ANALYSIS ● PC DATA ACQUISITION ● FULLY DIFFERENTIAL MUX INPUTS ● DIGITALLY SELECTABLE INPUT RANGES ● MEDICAL INSTRUMENTATION ● ±5V POWER SUPPLIES ● SERIAL DIGITAL INPUT/OUTPUTS ● 2 SIMULTANEOUS SAMPLED AUXILIARY CHANNELS ● DIRECT INTERFACE TO MOTOROLA’S DSP56004/7 2 V1-1 2 V1-2 SH1 PGA1 ADC1 12-Bit Serial Out1 SH2 PGA2 ADC2 12-Bit Serial Out2 SH3 PGA3 ADC3 12-Bit Serial Out3 2 V1-3 DESCRIPTION MUX1 2 V2-1 The ADS7833 consists of three 12-bit analog-to-digital converters preceded by three simultaneously operating sample-hold amplifiers, and multiplexers for 10 differential inputs. The ADCs have simultaneous serial outputs for high speed data transfer and data processing. 2 V2-2 2 V2-3 MUX2 2 V3-1 V3-2 V3-3 The ADS7833 also offers a programmable gain amplifier with programmable gains of 1.0V/V, 1.25V/V, 2.5V/V, and 5.0V/V. Channel selection and gain selection are selectable through the serial input control word. The high through put rate is maintained by simultaneously clocking in the 13-bit input control word for the next conversion while the present conversions are clocked out. V3-4 2 2 2 MUX3 2.5V Ref Input Select Control Logic Input Setup Register DAC CAP Gain Select Serial IN DAC 8-Bit Voltage Out Clock Convert Busy The part also contains an 8-bit digital-to-analog converter whose digital input is supplied as part of the input control word. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1994 Burr-Brown Corporation PDS-1235C 1 ADS7833 Printed in U.S.A. May, 1997 SPECIFICATIONS At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V, and TA = –40°C to +85°C, using internal reference, fCLOCK = 2.1MHz. ANALOG-TO-DIGITAL CONVERTER CHANNELS ADS7833N PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 12 ANALOG INPUT Full Scale Voltage, Differential G = 1.0V/V G = 1.25V/V G = 2.5V/V G = 5.0V/V ±0.5 Common-Mode Voltage Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity - ADC Differential Linearity - ADC No Missing Codes Integral Linearity - Asynchronous, Synchronous Differential Linearity - Asynchronous, Synchronous Full Scale Error Full Scale Error Other Gains Full Scale Error Drift Zero Error - ADC Zero Error - Asynchronous, Synchronous Zero Error Drift AC ACCURACY Total Harmonic Distortion fIN = 1kHz fIN = 1MHz CMR ±2.5 ±2.0 ±1.0 ±0.5 See Table VII 1012 20 200 µs µs kHz 150 0.1 0.5 50 50 3 µV/µs µs ns ps ns ±0.5 ±0.5 ±2 0.5 0.5 ±3 ±3 2 4 ±100 ±100 ±15 ±20 12 G = 1.0V/V G G G G G = = = = = ±10 ±10 ±0.5 ±0.5 ±0.5 1.0V/V 2.5V/V 1.0V/V 1.0V/V 1.0V/V VCM = 1V, fCM = 1MHz 2.25 LSB LSB Bits LSB LSB % of FSR % of FSR ppm/°C ppm/°C LSB LSB ppm/°C 92 72 40 dB dB dB 2.5 ±0.25 ±10 10 2.5 V % ppm/°C µA V 2.75 µA 10 0 +3.5 At All Digital Input Pins DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance V V V V V Ω pF 6.1 6.6 REFERENCE Internal Reference Voltage Internal Reference Accuracy Internal Reference Drift Internal Reference Source Current External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance Bit CLK = 2.1MHz Acquire and Convert SAMPLING DYNAMICS S/H Droop Rate S/H Acquisition Time S/H Aperture Delay S/H Aperture Jitter Sampling Skew, Channel-to-Channel UNITS 1.5 +5 ±10 ±10 15 V V µA µA pF 0.4 5 ±5 15 V V µA pF 12-Bit Serial BTC ISINK = 1.6mA ISOURCE = 500µA 0 4.2 At All Digital Output Pins The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7833 2 SPECIFICATIONS (CONT) At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V, and TA = –40°C to +85°C, using internal reference, fCLOCK = 2.1MHz. ANALOG-TO-DIGITAL CONVERTER CHANNELS ADS7833N PARAMETER CONDITIONS POWER SUPPLIES VANA+ VANA– VDIG+ VDIG– IANA+ IANA– IDIG+ IDIG– Power Dissipation MIN TYP MAX UNITS +4.75 –4.75 +4.75 –4.75 +5.0 –5.0 +5.0 –5.0 15 8 3 1 125 +5.25 –5.25 +5.25 –5.25 25 10 5 2 V V V V mA mA mA mA mW +85 +125 +150 °C °C °C MAX UNITS +2.5 1 ±1 ±1 V µs LSB LSB µA mV % Specified Performance TEMPERATURE RANGE Specified Performance Derated Performance Storage –40 –55 –65 DIGITAL-TO-ANALOG CONVERTER ADS7833N PARAMETER CONDITIONS RESOLUTION Output Range Output Settling Time Linearity Error Differential Linearity Output Current Offset Error Full Scale Error MIN TYP 8-Bits 0 To 0.5LSB 200 ±1 ABSOLUTE MAXIMUM RATINGS 10 2 REFIN VANA– REFGND VANA+ AGND 2 1 68 67 66 65 64 63 62 61 NC 3 AOUT 4 CAP V3-4P 5 V3-4N 6 V3-3P 7 V3-3N 8 V3-2P NC 9 V3-2N V3-1P Analog Input Voltage ............................................... .......................... ±25V Ground Voltage Difference: AGND and DGND ................................. ±0.3V Power Supply Voltages: VANA+ ................................................................................................. +7V VANA– ................................................................................................. –7V VDIG+ ................................................................................................. +7V VDIG– ................................................................................................. –7V Digital Inputs .............................................................. –0.3V to VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ............................................... +300°C V3-1N PIN CONFIGURATION NC 10 60 NC V2-1N 11 59 V1-1N V2-1P 12 58 V1-1P NC 13 57 NC V2-2N 14 56 V1-2N V2-2P 15 55 V1-2P NC 16 CONVERSION AND DATA TIMING 54 NC V2-3N 17 53 V1-3N V2-3P 18 SYMBOL DESCRIPTION tCONV A/D Conversion Time 6.6 4.0 µs CLK A/D Conversion Clock 2.1 2.8 MHz t1 Setup Time for Conversion Before Rising Edge of Clock 50 Hold Time for Conversion After Rising Edge of Clock 50 ns ns t3 Setup Time for Serial Out t4 Setup Time for Serial Input 30 ns t5 Hold Time for Serial Input 30 ns 51 NC NC 20 50 NC NC 21 49 NC NC 22 48 NC NC 23 47 NC NC 24 46 NC NC 25 45 NC NC 26 44 NC ns NC NC BUSY DCLOCK ASH SERIN CLK CONV SOUT1 SOUT3 NC SOUT2 VDIG– VDIG+ DGND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 TP2 25 52 V1-3P NC 19 TP1 t2 MIN TYP MAX UNITS ADS7833N PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ADS7833N 68-Lead PLCC 312 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 ADS7833 PIN DEFINITIONS PIN NO NAME TYPE(1) DESCRIPTION PIN NO NAME TYPE(1) DESCRIPTION 35 36 37 SOUT1 CLK CONV DO DI DI Serial Digital Output, Channel 1 Clock for A/D Converters Start A/D Converters. When CONV goes to “0” (low) the next rising edge of CLK starts the conversion. 38 ASH DI Digital Control for Asynchronous Sample Hold. If signal is “1” (high), signals are sampled. 39 40 SERIN BUSY DI DO Serial Digital Input for Input Control Word A/D Converters Busy. Busy if signal is “0” (low). 41 DCLOCK DO A Delayed and Truncated Version of the CLK Signals. It is Delayed 50ns from the CLK Signal and Stays Low after 13 DCLOCK Cycles. 42 43 44 45 46 47 48 49 50 51 52 NC NC NC NC NC NC NC NC NC NC V1–3P — — — — — — — — — — AI No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection Voltage Input, Channel 1, Mux I/P 3, Positive Side 1 V3–4N AI Voltage Input, Channel 3, Mux I/P 4, Negative Side 2 V3–4P AI Voltage Input, Channel 3, Mux IP 4, Positive Side 3 V3–3N AI Voltage Input, Channel 3, Mux I/P 3, Negative Side 4 V3–3P AI Voltage Input, Channel 3, Mux I/P 3, Positive Side 5 V3–2N AI Voltage Input, Channel 3, Mux I/P 2, Negative Side 6 V3–2P AI Voltage Input, Channel 3, Mux I/P 2, Positive Side 7 8 NC V3–1N — AI No Connection Voltage Input, Channel 3, Mux I/P 1, Negative Side 9 V3–1P AI Voltage Input, Channel 3, Mux I/P 1, Positive Side 10 11 NC V2–1N — AI No Connection Voltage Input, Channel 2, Mux I/P 1, Negative Side 12 V2–1P AI Voltage Input, Channel 2, Mux I/P 1, Positive Side 13 14 NC V2–2N — AI No Connection Voltage Input, Channel 2, Mux I/P 2, Negative Side 15 V2–2P AI Voltage Input, Channel 2, Mux I/P 2, Positive Side 53 V1–3N AI 16 17 NC V2–3N — AI No Connection Voltage Input, Channel 2, Mux I/P 3, Negative Side. Voltage Input, Channel 1, Mux I/P 3, Negative Side 54 55 NC V1–2P — AI 18 V2–3P AI Voltage Input, Channel 2, Mux I/P 3, Positive Side No Connection Voltage Input, Channel 1, Mux I/P 2, Positive Side 56 V1–2N AI 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NC NC NC NC NC NC NC NC TP1 TP2 VDIG+ DGND VDIG– NC SOUT2 SOUT3 — — — — — — — — — — P P P — DO DO No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection Test Point 1, Make No Connection Test Point 2, Make No Connection Digital Supply Voltage, +5V Digital Supply Voltage, Ground Digital Supply Voltage, –5V No Connection Serial Digital Output, Channel 2 Serial Digital Output, Channel 3 Voltage Input, Channel 1, Mux I/P 2, Negative Side 57 58 NC V1–1P — AI No Connection Voltage Input, Channel 1, Mux I/P 1, Positive Side 59 V1–1N AI Voltage Input, Channel 1, Mux I/P 1, Negative Side 60 61 62 63 64 65 66 67 68 NC NC AOUT CAP REFIN REFGND VANA– AGND VANA+ — — AO AO AI P P P P No Connection No Connection Output of DAC Decoupling Point for Internal Reference Input Pin for External Reference Ground Pin for External Reference Analog Supply Voltage, –5V Analog Supply Voltage, Ground Analog Supply Voltage, +5V NOTE: (1) AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, P is Power Supply Connection. ® ADS7833 4 TYPICAL PERFORMANCE CURVES At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V and TA = 25°C, using internal reference, fCLOCK = 2.1MHz. FULL SCALE vs TEMPERATURE OFFSET vs TEMPERATURE 0.9 1.4 0.8 1.2 0.7 Full Scale (%) Offset (LSB) 1.0 0.8 0.6 0.6 0.5 0.4 0.3 0.4 0.2 0.2 0.1 0 0 –55 –40 –25 0 25 70 85 –55 125 –40 –25 25 70 85 125 DIFFERENTIAL LINEARITY (MAX) vs TEMPERATURE 0.000 0.40 –0.100 0.35 Differential Linearity (LSB) Differential Linearity (LSB) DIFFERENTIAL LINEARITY (MIN) vs TEMPERATURE –0.200 –0.300 –0.400 –0.500 –0.600 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.700 –55 –40 –25 0 25 70 85 125 –55 –40 –25 Temperature (°C) 0 25 70 85 125 Temperature (°C) INTEGRAL LINEARITY (MIN) vs TEMPERATURE INTEGRAL LINEARITY (MAX) vs TEMPERATURE 0.000 0.45 –0.050 0.40 –0.100 0.35 Integral Linearity (LSB) Integral Linearity (LSB) 0 Temperature (°C) Temperature (°C) –0.150 –0.200 –0.250 –0.300 –0.350 –0.400 0.30 0.25 0.20 0.15 0.10 0.05 –0.450 0 –55 –40 –25 0 25 70 85 125 –55 Temperature (°C) –40 –25 0 25 70 85 125 Temperature (°C) ® 5 ADS7833 TYPICAL PERFORMANCE CURVES (CONT) At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V and TA = 25°C, using internal reference, fCLOCK = 2.1MHz. DAC OFFSET vs TEMPERATURE DAC FULL SCALE vs TEMPERATURE 3.5 0 –0.05 3.0 DAC Full Scale (%) DAC Offset (mV) –0.10 2.5 2.0 1.5 1.0 –0.15 –0.20 –0.25 –0.30 –0.35 0.5 –0.40 0 –0.45 –55 –40 –25 0 25 70 85 125 –55 –40 –25 Temperature (°C) 0 25 Temperature (°C) BASIC CIRCUIT CONFIGURATION 100nF 2.2µF REFOUT 100nF REFIN 2.2µF REFGND 4.7µF 68 67 66 65 64 63 62 61 AOUT 1 NC 2 VANA– VANA+ 3 4.7µF AGND 4 GND V3-4P 5 –5V GND V3-4N 6 V3-3P 7 V3-3N 8 V3-2P NC 9 V3-1N V3-1P V3-1N +5V NC 10 60 NC V2-1N 11 59 V1-1N IN– V2-1P 12 58 V1-1P IN+ NC 13 57 NC V2-2N 14 56 V1-2N V2-2P 15 55 V1-2P NC 16 V2-3N 54 NC 53 V1-1N 17 V2-3P 18 52 V1-1N ADS7833N NC 19 51 NC NC 20 50 NC NC 21 49 NC NC 22 48 NC NC 23 47 NC NC 24 46 NC NC 25 45 NC NC 26 44 NC 4.7µF 100nF + 100nF NC NC DCLOCK BUS ASH SERIN CLK CONV SOUT1 SOUT3 NC 4.7µF SOUT2 VDIG– VDIG+ DGND TP2 TP1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Ground Plane +5V GND –5V ® ADS7833 6 70 85 125 FUNCTIONAL DESCRIPTION ships). The ADCs are preceded by programmable gain amplifiers. (Table II gives gain select information). For channels one and two, the PGAs are effective for all three analog inputs. For the third channel, only the V3–1 input is gain changed by the PGA. Inputs V3–2, V3-3, and V3-4 are connected to ADC3 at a fixed gain of 1V/V regardless of the Gain Select value. (See Figure 1) ADCs AND PGAs The ADS7833 contains three signal channels each with a 12-bit analog-to-digital converter output. The ADCs operate synchronously and their serial outputs occur simultaneously. (Table VI gives the analog input/digital output relation- V1-1 V1-2 V1-3 2 2 2 2 2 SH6 SH1 2 2 2 SH2 2 2 PGA1 2 ADC1 SOUT1 Ref Conv ASH V2-1 V2-2 V2-3 2 2 2 2 2 SH7 SH3 2 2 2 SH4 2 V3-3 V3-4 ADC2 2 SOUT2 Ref Conv V3-2 Through V3-4 ASH V3-1 V3-2 2 PGA2 2 2 2 2 2 SH5 2 PGA3 ADC3 SOUT3 V3-1 Only 2 Input Gain Select Select Ref CAP REFIN 2.5V Ref Ref Conv Decoder Conv 3 Sample Input Setup Register DAC Input Control Logic 2 8 SERIN DAC 8-Bit AOUT ASH CLK CONV BUSY DCLOCK FIGURE 1. Functional Diagram. SAMPLE HOLDS The ADS7833 contains seven sample holds. Five of them (SH1 through SH5) sample simultaneously and have their sample/hold timing internally synchronized. (The timing is shown in Figure 2). the quadrature inputs of a given position sensor at the same time (even though they are converted on successive conversion cycles) (see Table III), so that their values are captured at the same shaft position. Three of the sample holds (SH1, SH3, and SH5) are connected to the input multiplexers so that they can provide simultaneous sampling for all of their channels inputs. In addition, SH2 and SH4 simultaneously sample the third input of their channels (Vl–3 and V2–3, respectively). This is useful in motor control applications where V1-2 and Vl-3 are the quadrature inputs for one position sensor, and V2-2 and V2-3 are the quadrature inputs for a second position sensor (see Figure 6). In that application, it is desirable to sample The ADS7833 also has the capability for limited asynchronous sampling. The sampling of SH6 and SH7 is controlled asynchronously by the control signal ASH (see Table III). This allows two inputs each on channel 1 and channel 2 (see Table IV) to be sampled asynchronously from the timing of the other sample holds. This can be useful in motor control applications where the two inputs for each channel come from a position sensor and it is desired to sample based on position sensor timing rather than system clock timing. ® 7 ADS7833 MULTIPLEXERS The ADS7833 also contains several multiplexers that are used to select the desired analog inputs and connect the proper sample hold outputs to the PGAs and ADCs. The MUXs are driven by a decoder which receives its inputs from the Input Setup Register. (See Table III and Table IV for information on input channel selection). The input multiplexers can take full differential input signals (see Figure 3 and Table VII). The analog signals stay differential through the sample holds and the PGAs all the way to the inputs of the ADSs. This is done to provide the best possible high frequency noise rejection. connected at the REFIN pins. This then overrides the internal 2.5V reference, is connected to the ADCs and is available buffered at the CAP pin. OTHER DIGITAL INPUTS AND OUTPUTS Sampling and conversion is controlled by the CONV input (see Figure 2). The ADS7833 is designed to operate from an external clock supplied at the CLK input. This allows the conversion to be done synchronously with system timing so that transient noise effects can be minimized. The CLK signal may run continuously or may be supplied only during convert sequences. The BUSY and DCLOCK signals are internally generated and are supplied to make interfaces with microprocessors easier (see Figures 2, 4, and 6). INPUT SETUP As the ADCs are converting and transmitted their serial digital data for one conversion cycle, a setup word is being received to be used for the next conversion cycle. The 13-bit word is supplied at the SERIN pin (see Figure 1), and is stored in the buffered Input Setup Register. The Input Select and Gain Select portions of the word are decoded and determine the state of the multiplexers and PGAs (see CONFIGURABLE PARAMETERS section). CONFIGURABLE PARAMETERS Configurable parameters are: • PGA Gain • Input multiplexer and sample/hold selection • DAC output voltage Configuration information for these parameters is contained in the SERIN word (See Figure 2). As one conversion is taking place, the configuration for the next conversion is being loaded into the buffered Input Setup Register via the SERIN word. Table I shows information regarding these parameters. DIGITAL-TO-ANALOG CONVERTER An 8-bit DAC provides 256 output voltage levels from 0V to 2.5V (see Table V for input/output relationships). The DAC is controlled by the DAC Input portion of the input setup word. The DAC Input portion of the word is strobed into the DAC at the end of the conversion cycle (14th CLK pulse in Figure 2). CLOCK POSITIONS(1) DESCRIPTION FUNCTIONS DAC Input0-7 Sets DAC Output Voltage 2-9 10-11 Gain Select0-1 Sets PGA Gains VOLTAGE REFERENCE 12-14 Input Select0-2 The ADS7833 contains an internal 2.5V voltage reference. It is available externally through an output buffer amplifier. If it is desired to use an external reference, one may be Determines Multiplexers Conditions NOTE: (1) See Figure 2. “Clock Pulse Reference No.” CLOCK AND CONTROL SIGNALS(1) Clock Pulse Reference No. CLK (Input)(2) 1 2 3 4 5 6 TABLE I. Description of Configurable Parameters. 7 8 9 10 11 12 13 14 DCLOCK (Output) t1 t2 CONV (Input) SAMPLE (Internal) tCONV BUSY (Output) t3 A-to-D CONVERTER OUTPUTS SERIAL OUT1 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 LSB SERIAL OUT2 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 LSB SERIAL OUT3 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 LSB CONTROL WORD INPUT SERIN How Used t4 t5 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 7 6 5 4 3 2 1 0 1 0 Gain Select 0-1 DAC Input 0-7 NOTE: (1) See the specification table for timing specifications. (2) 50% duty cycle. FIGURE 2. Timing Diagram. ® ADS7833 Bit 9 Bit 10 Bit 11 Bit 12 8 2 1 Input Select 0-2 0 1 2 PGA GAIN The PGA gain is determined by the Gain Select portion (bits 8 and 9) in the SERIN word (see Figure 2). There is one gain input that sets the same gain for all three PGAs. The gain values and allowable full scale inputs are shown in Table II. For channels one and two the PGAs set the gain for all three analog inputs. For the third channel, only the V3-1 input is gain changed by the PGA. Inputs V3-2, V3-3 and V3-4 are connected to ADC3 at a fixed gain of 1V/V regardless of the Gain Select value. GAIN SELECT0-1 0H 1H 2H 3H GAIN SETTING FULL SCALE INPUT 5.0V/V 2.5V/V 1.25V/V 1.0V/V ±0.5V ±1.0V ±2.0V ±2.5V Input Select = 3H—Convert V1-3 via SH2, V2-3 via SH4, and V3-3 (V1-3 and V2-3 are from the value sampled in a preceding conversion cycle with Input Select = 4H, 5H or 6H). Input Select = 2H—Convert V1-3 via SH1, V2-3 via SH3, and V3-3 (V1-3 is sampled on SH2 in this conversion cycle). Input Select = 1H—Input V3-4 is converted by PGA3/ ADC3. The output of the asynchronous sample holds, SH6 and SH7, are converted by PGA1/ADC1 and PGA2/ADC2, respectively. Note that the inputs to SH6 and SH7 are determined by previous Input Select values (see Table IV). Thus, to properly convert the output of one of the asynchronous sample holds it is first necessary to choose its input with a previous conversion cycle. Also, the output of SH6 or SH7 will only be converted if ASH goes low before the CONV command is received. Input Select = 0H—V3-4 is converted by PGA3/ADC3. The inputs to PGA1/ADC1 and PGA2/ADC2 are undefined. TABLE II. Gain Select Information. INPUT MULTIPLEXER AND SAMPLE HOLD SELECTION CONVERSIONS FROM THE ASYNCHRONOUS SAMPLE HOLDS Decoding the Input Select value also determines which inputs are applied to the two asynchronously controlled sample holds SH6 and SH7. (See Table IV.) One of the three possible inputs is selected by the Input Select value being 4, 5, or 6. The Input Select portion of the SERIN word (bits 10, 11 and 12) (see Figure 2) are decoded and determine the open/closed condition of the multiplexer switches. This in turn determines which input signals are connected to the sample holds and which sample holds are connected to the PGAs/ADCs. The “No Effect” states indicate that these values of Input Select have no effect on the multiplexers at the input of SH6 and SH7. When one of the “No Effect” values of Input Select is presented, the multiplexers will not be changed (i.e., their condition is determined by the last 4, 5, or 6 value of Input Select that existed prior to the “No Effect” state). INPUT SIGNALS FOR PGAs/ADCs Table III shows the relationships between the value of Input Select0-2 and the signals that are converted. INPUT SELECT0-2 HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H ANALOG SIGNAL CONNECTED TO PGAX/ADCX BINARY CODE PGA1/ADC1 PGA2/ADC2 PGA3/ADC2 000 001 010 011 100 101 110 111 Undefined V1-X via SH6(1) V1-3 via SH1 V1-3 via SH2 V1-2 V1-2 V1-2 V1-1 Undefined V2-X via SH7(1) V2-3 via SH3 V2-3 via SH4 V2-2 V2-2 V2-2 V2-1 V3-4 V3-4 V3-3 V3-3 V3-2 V3-2 V3-2 V3-1 Note that Input Select = 1H presents the output of SH6 and SH7 (1ASHX and 2ASHX) to PGA1/ADCl and PGA2/ADC2, respectively (see Table III). Therefore, in order to properly convert the asynchronous sampled signals, it is first necessary to choose an input signal (Input Select equal 5 or 6 in Table IV) with one load/convert cycle and then convert the sample hold output (Input Select = 4 in Table III) in a following conversion cycle. NOTE: (1) See Table IV for Operation. INPUT SELECT0-2 TABLE III. Input Controls for Synchronous Sample Holds. HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H Input Select = 7H—Synchronously sample and convert input signals V1-1, V2-1, and V3-1. Input Select = 4H, 5H, 6H—Synchronously sample and convert input signals V1-2, V2-2, and V3-2. These codes also cause SH2 and SH4 to sample their inputs. Values 4H, 5H, 6H have different effects on the inputs to SH6 and SH7 (see Table IV). BINARY CODE 000 001 010 011 100 101 110 111 ANALOG SIGNAL CONNECTED TO SH6 SH7 No Effect No Effect No Effect No Effect Open V1-3 V1-2 No Effect No Effect No Effect No Effect No Effect Open V2-3 V1-2 No Effect TABLE IV. Input Controls for Asynchronous Sample Holds. ® 9 ADS7833 DAC OUTPUT VOLTAGE The value of the DAC output voltage is determined by the DAC Input portion of the SERIN word (bits 0 through 7—see Figure 2). The 8-bit DAC has 256 possible output voltages from 0V to +2.49V. The value of 1 LSB is 0.0098V. As is common with most differential input semiconductor devices, there are compound restrictions on the combination of differential and common-mode input voltages. This matter is made slightly more complicated by the fact that most of the analog inputs are capable of being affected by the programmable gain function. The possible differential and single ended configurations are shown in Figures 3a and 3b. The maximum differential and common mode restrictions are shown in Table VII. ANALOG-TO-DIGITAL CONVERTERS ARCHITECTURE The ADCs are 12-bit, successive approximation types implemented with a switched capacitor circuitry. GAIN SELECT CODE SPEED The clock for the ADC conversion is supplied externally at the CLK pin. Maximum clock frequency for specified accuracy is 2.1MHz. This results in a complete conversion cycle (S/H acquisition and A/D conversion) of 6.6µs. 0 1 2 3 Gain 5.0V/V 2.5V/V 1.25V/V 1.0V/V Full Scale Range (VD with VCM = 0) ±0.5V ±1.0V ±2.0V ±2.5V Largest Positive Common Mode Voltage, VCM+ +2.7V +2.4V +1.9V +1.6V Largest Negative Common Mode Voltage, VCM– –2.7V –2.4V –1.9V –1.6V TABLE VII. Differential and Common Mode Voltage Restrictions. INPUT/OUTPUT The ADS7833 is designed for bipolar input voltages and uses a binary two’s complement digital output code. A programmable gain function is associated with each ADC. This changes the full scale analog input range and the analog resolution of the converter. Details are shown in Table VI. (A) V1 – 1 + V1 – 1P + VD 2 DIFFERENTIAL AND COMMON-MODE INPUT VOLTAGES The ADS7833 is designed with full differential signal paths all the way from the multiplexer inputs through to the input of the ADCs. This was done to provide superior high frequency noise rejection. – + – V1 – 1 – + VD 2 V1 – 1N (B) V1 – 1 V1 – 1P VD VD VCM – HEX CODE BINARY CODE 00H 01H 0000 0000 0000 0001 0V +0.0098V • • • • • • • • • FFH 1111 1111 +2.499 V1 – 1N + VCM – FIGURE 3. (a) Differential Signal Source, and (b) Single Ended Signal Source. TABLE V. DAC Input/Output Relationships. DESCRIPTION ANALOG INPUT DIGITAL OUTPUT 0 1 2 3 GAIN 5V/V 2.5V/V 1.25V/V 1.0V/V FULL SCALE RANGE ±0.5V ±1.0V ±2.0V ±2.5V HEX CODE +0.49976 +0.244mV 0V –0.244V –0.500V +0.9995V +0.488mV 0V –0.488mV –1.000V +1.999V +0.976mV 0V –0.976mV –2.000V +2.499 +1.22mV 0V –1.22mV –2.500V 7FFH 001H 000H FFFH 800H +Full Scale (FS –1LSB) One Bit above Mid-Scale Mid-Scale One Bit Below Mid-Scale –Full Scale VCM VD 2 – ANALOG OUTPUT GAIN SELECT CODE VCM VCM + DIGITAL INPUT DAC INPUT0-7 VD 2 BINARY TWO’S COMPLIMENT FORMAT BINARY CODE 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0001 0000 1111 0000 NOTE: The programmable gain function applies to all three input channels for ADC1 and ADC2. However, the programmable gain function only applies to the first input (V3-1) for ADC3. The other three inputs (V3-2, V3-3, and V3-4) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus have a fixed ±2.5V full scale input range. TABLE VI. Analog Input - Digital Output Relationships. ® ADS7833 10 MICROPROCESSOR INTERFACE The internal logic of the ADS7833 is designed for easy control and data interface with microprocessors. Figure 4 shows the interface for loading the input control word from the microprocessor data bus into the serial input of the ADS7833. While this is one of the most useful, the DSP56004/7 is flexible enough to allow various other configurations. These will free up the serial outputs for use with other serial peripherals, such as DACs. TYPICAL ISOLATED ANALOG INPUT Figure 5 shows an ISO130 used to isolate the current measurement in a motor speed control application. This amplifier is well suited for this application because of its high transient immunity (l0kV/µs). Its differential output feature is well suited to the differential input of the ADS7833. Keeping the signal transmission differential helps to preserve the high frequency noise rejection of the system. Table VIII provides a sample assembly code and Figure 4 shows the connection diagram for connecting an ADS7833 to the DSP56004N—or DSP56007 a Motorola Digital Signal Processor. This configuration allows for full control of the ADS7833 as well as receiving all three conversion results simultaneously. The start of conversion is generated by the DSP56004 as well as the sample time of the asynchronous sample/holds. DSP56004/7 ADS7833 SDO0 CONV V1-1 SDO1 SERIN V1-2 SOI0 SOUT1 V1-3 SOI1 SOUT2 MOSI/HA0 MISO/NAU A unique characteristic of the ISO130 is that it has a common mode output voltage of approximately 2.39V. To accept this level of CMV, the ADS7833 must be operated at a gain of 5V/V (±0.5V full scale differential input). (See Figure 3 and Table VII). Since the ISO130 has a gain of 8V/V, the maximum value of VSENSE is 62.5mV. Thus, the value of RSENSE is chosen to scale VSENSE to this maximum value. (optional) SCKT SOUT3 V2-1 ASH V2-2 CLK V2-3 POWER-UP INITIALIZATION When power is applied to the ADS7833, two conversion cycles are required for initialization and valid digital data is transmitted on the third cycle. The first conversion after power is applied is performed with indeterminate configuration values in the double buffer output of the Input Setup Register. The second conversion cycle loads the desired values into the register. The third conversion uses those values to perform proper conversions and output valid digital data from each of the ADCs. SCKR SCK/SCL V3-1 WST V3-2 WSR V3-3 SS/HA2 V3-4 SDO2 AOUT FIGURE 4. Microprocessor Interface for Motorola DSP56004/7. wait data movep movep movep ; movep movep movep movep movep #>$0,x:$ffe4 #>$0,x:$ffe1 #>$0,x:$fff1 ; Disable SAI transmit port ; Disable SAI receive port ; Disable SHI port #>$dfff00,x:$ffe5 #>$101f00,x:$ffe6 #>$0,x:$ffe7 #>$10d,x:$ffe0 #>$3,x:$ffe1 ; ; ; ; ; movep movep movep ; btst jcs btst jcc movep move movep move move movep #>$2001,x:$fff0 #>$5,x:$fff1 #>$f,x:$ffe4 ; Set narrow spike filter, CPOL=0, CPHA=1 ; Enable SHI (slave, no fifo, 16-bits) ; Enable SAI trans (rsng edge, MSB 1st, 16-bits, mstr) #14,x:$ffe1 data #15,x:$ffe1 wait x:$ffe2,x0 x0,x:$00 x:$ffe3,x0 x0,x:$01 x:$fff3,x0 x0,x:$02 ; Look for a receive flag (left or right) ; ; ; ; ; ; Convert command DAC to midscale, G=1V/V, Channel 1 all ADCs For SS pin—enables SHI at proper time Divide by 1 pre, divide by 13—96kHz conv @ 40MHz Enable SAI recv (rsng edge, MSB 1st, 16-bits, slave) Get Sout1 Save it Get Sout2 Save it Get Sout3 Save it TABLE VIII. Sample Code for Motorola DSP56004/7. ® 11 ADS7833 HV+ ••• +V +5V In 78L05 Out 0.1µF 1 0.1µF 2 0.1µF ADS7833 8 + 7 ISO130 G = 8V/V V1 – 1P V1 – 1 0.01µF V1 – 1N – 6 Typical Analog Input 5 3 VSENSE + ••• 4 V1 – 1CMV = 2.5V V1– 1DIFF ≤ ±500mV – RSENSE VSENSE ≤ ±62.5mV ••• HV– FIGURE 5. Typical Isolated Differential Analog Input. ADS7833 ISO130 Phase A DSP56004 CLK SCKT CONV SCKR V1 – 1 SCK/SCL SDO0 ASH MISO/HAO ISO130 Phase B SOUT1 SOI0 SOUT2 SOI1 SOUT3 MOSI/HA0 V2 – 1 ISO130 Phase C V3 – 1 V1 – 2 Position Sensor V1 – 3 V2 – 2 Position Sensor V2 – 3 IREF RTD V3 – 2 REF 200 V3 – 3 V3 – 4 DC Link Voltage SERIN Aux Input ISO122 FIGURE 6. Motor Control Application Using Position Sensors. ® ADS7833 12 SDO1