Edge672
500 MHz Pin Electronics
Window Comparator and Load
PRELIMINARY
EDGE HIGH-PERFORMANCE PRODUCTS
Description
Features
• 11V Common Mode Range
• Programmable to ±35 mA
• Comparator Input Tracking > 6 V/ns with
< ±25 ps dispersion
• Low Leakage (L+C) < 1 µA
• Comparator Input Power Down Mode
(for extremely low leakage operation < 250 nA)
• Small footprint (32 pin TQFP)
The Edge672 is a monolithic ATE pin electronics
comparator and load solution manufactured in a highperformance complementary bipolar process. In
automatic test equipment, the Edge672 incorporates a
dynamic load and window comparator suitable for very
fast, bidirectional channels in Memory, VLSI, and MixedSignal test systems.
The three-statable load is capable of sourcing and sinking
35 mA over an 11V common mode range. Source and
sink currents are independently programmable. The load
is configurable to support a clamping function, a
termination function, plus any custom load
configurations.
Functional Block Diagram
The comparator is capable of tracking very fast edges
and passing sub-ns pulses over a 11V common mode
range while maintaining excellent timing accuracy. The
differential digital outputs are adjustable to
accommodate ECL levels, PECL levels, or custom levels
to interface directly with a CMOS ASIC.
ISOURCE
ISCIN
X 40
The inclusion of a high performance load and comparator
in a 32 pin TQFP (7 mm X 7 mm) package offers a
highly integrated solution traditionally implemented with
multiple integrated circuits or discrete components.
BRIDGE
SOURCE
VCMOUT
LOAD
VCMIN
BRIDGE
SINK
ISINK
ISKIN
X –40
LDEN
LDEN*
QA*
–
A
QA
CVA
+
IPD
VINP
QB
+
B
QB*
–
CVB
PECL
Revision 1/ June 13, 2000
1
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Name
Pin #
PRELIMINARY
Description
Load
VCMIN
28
Analog input that programs the commutating voltage.
ISCIN
ISKIN
31
29
Analog current inputs that program the load source and sink currents.
LDEN
LDEN*
1
2
Wide voltage differential input pins that turn the load on and off.
VCMCOMP
27
Analog input pin. A .01 µF or greater caacitor to ground should be connected.
LOAD
21
Load diode bridge output.
VCMOUT
26
Analog voltage which drives the diode bridge.
BRIDGE SOURCE
BRIDGE SINK
25
24
Upper and lower half (respectively) of the diode bridge.
VINP
19
Analog voltage input for the window comparator. The VINP connects to both of
the noninver ting (+) inputs of the comparators.
QA / QA*
QB / QB*
4, 5
8, 7
Differential output pins from the window comparator.
CVA, CVB
15, 16
IPD
14
VEE
6, 18, 23, 32
Negative power supply.
VCC
3, 9, 17, 20
Positive power supply.
GND
10, 22, 30
Device ground.
PECL
11
Analog power supply which sets the comparator output levels.
12
13
Cathode and anode ends of a series of diodes used to monitor the die
temperature.
Comparator
Analog input pins used to set the high and low levels for the window
comparator.
TTl compatible input which activates the input power down mode of the window
comparator.
Power
Test Pins
CATHODE
ANODE
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Edge672
BRIDGE SOURCE
VCM OUT
VCMIN
VCM COMP
PRELIMINARY
ISKIN
GND
ISCIN
VEE
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description (continued)
25
32
1
BRIDGE SINK
LD EN
LD EN*
VEE
VCC
GND
LOAD
QA
QA*
VCC
VEE
VINP
QB*
VEE
VCC
QB
17
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CVB
CVA
IPD
ANODE
CATHODE
PECL
GND
VCC
9
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
PRELIMINARY
Load
Commutating Voltage
Introduction
The load section is capable of sourcing and sinking up
to 35 mA, both statically and dynamically, or being placed
in a high impedance state.
Load Enable
The load is controlled by the load enable input (LDEN /
LDEN*). If LDEN is more positive than LDEN*, the output
diode bridge will be active. If LDEN is more negative
than LDEN*, the LOAD pin will be placed in a high
impedance state.
VCMIN is a high input impedance voltage input node
that sets the voltage level at which the diode bridge
switches from sourcing to sinking currents. If LOAD is
more positive than VCMIN, the bridge will sink current
from the DUT into the Edge672 (see Figure 1). If LOAD
is more negative than VCMIN, the bridge will source
current from the Edge672 into the DUT (see Figure 2).
ISOURCE
LOAD
DUT
VCMIN
ISINK
Source and Sink Levels
The amount of current that the diode bridge can source
and sink is adjustable from 0 mA to 35 mA. The source
and sink levels are separate and independent.
Figure 1. LOAD > VCMIN
The Edge 672 sinks DUT current.
ISOURCE
ISCIN is a current input node which programs the bridge
source current. There is a gain of 40 between the ISCIN
current and the bridge source current. ISKIN is a current
input node that programs the bridge sink current. There
is a gain of –40 between the ISKIN current and the bridge
sink current.
LOAD
DUT
VCMIN
ISINK
Figure 2. LOAD < VCMIN
The Edge 672 sources DUT current.
ISOURCE = 40 * ISCIN
ISINK = –40 * ISKIN
Commutating Voltage Compensation
Caution: The ISKIN and ISCIN inputs are designed for
positive current between 0 mA and .875 mA flowing into
the Edge672. Care should be taken to insure that current
is never required to flow out of the Edge672 on these two
nodes.
VCMIN
The VCMCOMP pin is an analog output pin that requires
a fixed .01 µF chip capacitor (with good high frequency
characteristics) to ground (See Figure 3). This capacitor
is used to compensate an internal node on the on-chip
op amp used to buffer the commutating voltage input.
LOAD
VCMCOMP
VCMOUT
.01 µF
.01 µF
The VCMOUT pin is the actual commutation voltage seen
by the load diode bridge (see Figure 3). This node
requires a fixed .01 µF capacitor (with good high
frequency characteristics) to ground.
BRIDGE BRIDGE
SINK
SOURCE
Figure 3. Commutating Voltage Compensation
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
PRELIMINARY
Load Configuration
Clamping Function
The load is flexible in that VCMOUT, BRIDGE SINK, and
BRIDGE SOURCE are all brought out to separate pins.
This flexibility allows the load to be configured in several
different ways.
The load can also act as set of programmable clamps
that can absorb any DUT overshoot that would normally
be present when the pin electronics are receiving a DUT
signal. By connecting VCMOUT and BRIDGE SINK
together, and then bringing in an externally buffered
voltage to BRIDGE SOURCE (see Figure 5), VCMIN
becomes the low voltage clamp and the external voltage
becomes the high voltage clamp.
The standard load topology, where VCMOUT, BRIDGE
SINK, and BRIDGE SOURCE are all connected together
(see Figure 4), behaves like the traditional active load.
VCMIN
LOAD
VCMIN
(V clamp Lo)
VCMOUT BRIDGE BRIDGE
SINK SOURCE
LOAD
VCMOUT BRIDGE
SINK
BRIDGE
SOURCE
VCMIN
Figure 4. Standard Active Load Configuration
Figure 5. Load as a Programmable Clamp
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
PRELIMINARY
Window Comparator
allowing any noise present to cause repeated threshold
crossings.
Introduction
The Edge672 has two comparators connected on-chip
as a window comparator to determine whether the DUT
is in a high, low, or indeterminate state.
Functionality
The VINP pin is tied to the positive inputs of both
comparators (see Figure 6).
The Edge672 is designed with 4 mV of hysteresis. This
hysteresis is nonadjustable and requires no external
support. The amount of hysteresis was chosen to allow
stable and reliable transitions in most system
environments, without noticeably affecting the
comparator performance.
Actual Threshold Voltage
2 mV
4 mV
Input Condition
VINP > CVA
VINP < CVA
VINP > CVB
VINP < CVB
Output Condition
QA = High; QA* = Low
QA = Low; QA* = High
QB = High; QB* = Low
QB = Low; QB* = High
QA*
–
QA
+
+
QB
Programmed Threshold
Voltage
Figure 7. Hysteresis
The effects of hysteresis are visible in two categories offset voltage and propagation delay. The amount of
hysteresis must be large enough to overcome the system
noise floor, yet small enough not to increase offset
voltage effects significantly.
CVA
VINP
–
QB*
CVB
Input Protection
Figure 6. Comparator Functionality
Thresholds
CVA and CVB are the two comparator threshold levels.
These inputs are high impedance voltage controlled
inputs that determine at which VINP input voltage the
comparator will change states.
The VINP pin has an internal 50Ω series resistor and
two over-voltage diodes capable of shunting up to 100
mA (see Figure 8) and, therefore, requires no external
protection circuitry. The over-voltage input range that
the comparator can withstand is determined by the power
supply rails and the following equations:
VEE – .7 – (100 mA * 50Ω) < VINP <
VCC + .7 + (100 mA * 50Ω)
Hysteresis
or
Hysteresis is a measure of the change in threshold
voltage as a function of the comparator output state
(see Figure 7). Typically, hysteresis is used to prevent
multiple comparator output transitions due to slow input
slew rates in a noisy environment. These slower inputs
remain in the transition region for longer periods of time,
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VEE – 5.7V < VINP < VCC + 5.7V.
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
VCC
and can no longer track fast edges, in particular, fast
falling edges.
The IPD pin is a TTL compatible input which controls the
two modes. With IPD = low, the comparator is in its
normal high speed mode, supporting maximum AC
performance.
–
50
PRELIMINARY
+
VINP
+
–
VEE
Figure 8. Input Protection
For a wider protected input range, an additional external
series resistor may be added.
Comparator PECL Output Capability
PECL is a variable analog voltage power supply that
determines the common mode voltage of the comparator
digital outputs. With PECL connected to ground, the
outputs generate standard differential ECL levels.
However, the outputs will track the PECL input, remaining
one diode drop below it as PECL is varied between ground
and +5V. By setting PECL appropriately, a fully differential
comparator output may interface directly to a CMOS ASIC
without any translators.
With IPD = high, the comparator is in Power Down Mode.
The input bias current decreases to < 250 nA. The
comparator still functions, but can track edges only up
to 25 mV/ns.
Thermal Monitor
An on-chip thermal monitor is accessible through the
CATHODE and ANODE pins. These nodes connect to
five diodes in series (see Figure 9) and may be used to
accurately measure the junction temperature at any time.
An external bias current of 100 µA is injected through
the string, and the measured voltage corresponds to a
specific junction temperature with the following equation:
Tj[°C] = {(ANODE - CATHODE)/5 - .7} / (-.00208).
ANODE
Bias Current
Input Power Down
Temperature coefficient = –10 mV/ C
˚
The comparator has a mechanism where it can drastically
reduce the input bias current flowing into the VINP pin,
while still maintaining a functional comparator. In this
mode, however, the comparator slows down significantly
CATHODE
Figure 9. Thermal Diode String
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
PRELIMINARY
Delay Dispersion
Given a constant temperature and voltage environment
(within the bounds of the recommended operating
conditions), the propagation delay dispersion (TSD)
indicates how much variation in propagation delay time
can be expected for one comparator over a wide range
of input conditions. Thus, the propagation delay of a
comparator can be described as:
Tpd ± TSD
where TPD is the nominal delay that will vary with
temperature and voltage, and part-to-part. In many ATE
applications, Tpd is calibrated or compensated for on a
channel-by-channel basis. TSD includes factors that
normally may be difficult to calibrate, and therefore
directly impact overall system timing accuracy.
Propagation delay dispersion is defined as the maximum
deviation of the propagation delay taken at the eight
measurement points (see Figure 10) for 1V and 3 V
input signals described below. The parameters of interest
are:
•
•
•
•
Slew rate
Edge direction
Overdrive
Common mode voltage.
Low dispersion numbers indicate the accuracy of a
system under a variety of input conditions, and are an
important figure of merit for any comparator.
While not production tested, the Edg672 is designed
specifically to exhibit low dispersion. The typical Edge672
will show less than 25 ps Tpd dispersion.
3V
2.7 V
3V
INPUT
THRESHOLD
LEVELS
3V / NS
SLEW RATE
1V / NS
SLEW RATE
.3 V
0V
-0.8 V
-1.0 V
INPUT
THRESHOLD
LEVELS
1V
3V / NS
SLEW RATE
1V / NS
SLEW RATE
-1.6 V
-1.8 V
Figure 10. Dispersion Measurement Conditions
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information
PRELIMINARY
32-Pin TQFP
7 mm x 7 mm
TOP VIEW
PIN Descriptions
4
D
D/2
b
3
e
E
N / 4 TIPS
0.20
C
4
E/2
A–B
D
SEE DETAIL "A"
4X
BOTTOM VIEW
5
7
D1
D1 / 2
E1 / 2
5
7
E1
C
OO
4X
2000 Semtech Corp.
0.20
H
A–B
D
9
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information (continued)
PRELIMINARY
DETAIL "A"
DETAIL "B"
0 MIN.
3
–
e/2
0.05
S
A1
0.08 / 0.20 R.
DATUM
PLANE
0.25
–H–
GAUGE PLANE
A2
C.08
R. MIN.
b
0–7
0.20 MIN.
L
1.00 REF.
SECTION C–C
;;;
;;;
ddd
9
8 PLACES
11 / 13
b
A
–H–
0.05
2
//
0.10 C
ccc
0.09 / 0.20
–C–
M
SEE DETAIL "B"
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D S
WITH LEAD FINISH
0.09 / 0.16
b
Notes:
1.
All dimensions and tolerances conform to ANSI Y14.5-1982.
2.
Datum plane -H- located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting
line.
3.
Datums A-B and -D- to be determined at centerline between
leads where leads exit plastic body at datum plane -H-.
4.
To be determined at seating plane -C-.
5.
Dimensions D1 and E1 do not include mold protrusion.
6.
“N” is the total # of terminals.
7.
These dimensions to be determined at the datum plane -H-.
8.
Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
9.
Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius or the foot.
10. Controlling dimension: millimeter.
11. Maximum allowable die thickness to be assembled in this
package family is 0.30 millimeters.
12. This outline conforms to JEDEC publication 95, registration
MO-136, variations AC, AE, and AF.
M C A–B S
Lead
Cross Section
1
BASE METAL
JEDEC VARIATION
AC
Sym
Min
Nom
A
Max
Note
1.60
A1
0.05
A2
1.35
0.10
0.15
1.40
1.45
D
9.00 BSC
4
D1
7.00 BSC
7, 8
E
9.00 BSC
4
E1
7.00 BSC
7, 8
L
0.45
M
0.15
0.60
N
32
e
0.80 BSC
0.75
b
0.30
0.37
0.45
b1
0.30
0.35
0.40
ccc
0.10
ddd
0.20
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Recommended Operating Conditions
Parameter
PRELIMINARY
Symbol
Min
Typ
Max
Units
Positive Power Supply
VCC
8.5
11.5
12.0
V
Negative Power Supply
VEE
-8.5
-5.2
-4.5
V
VCC - VEE
13.0
16.7
17.0
V
PECL
0
3.3
5.0
V
+110
oC
Total Analog Supply
Comparator Output Positive Supply
Junction Temperature
TJ
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
VCC
VEE
VCC - VEE
PECL
0
-9.0
0
+13.0
0
+20.0
+6.0
V
V
V
V
Digital Input Voltages
LDEN, LDEN*
VEE
+6.0
V
Differential Digital Input Voltages
LDEN - LDEN*
-5.0
+5.0
V
QA, QA*, QB, QB*
0
50
mA
Comparator Input to Threshold
VINP - CVA
VINP - CVB
-13
-13
+13
+13
V
V
Load to Commutating Voltage
LOAD - VCMIN
-10
+10
V
VCMIN
LOAD, VINP
CVA, CVB
BRIDGE SOURCE
BRIDGE SINK
VEE
VEE
VEE
VEE
VEE
VCC
VCC
VCC
VCC
VCC
V
V
V
V
V
ISCIN
ISKIN
0
0
2.0
2.0
mA
mA
TA
TS
TJ
-55
-65
+125
+150
+150
+160
oC
Positive Supply (Relative to GND)
Negative Supply (Relative to GND)
Total Power Supply
Comparator Output Positive Supply
Digital Output Currents
Analog Voltages
Analog Input Currents
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Process Temperature (< 30 hours)
Typ
oC
oC
oC
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these, or any other conditions
beyond those listed in the operational sections of this specification are not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics
Parameter
PRELIMINARY
Symbol
Min
LOAD - VCMIN
VCMIN
VCOUT - VCMIN
-6.0
VEE + 2.9
-100
-100
Typ
Max
Units
5
+6.0
VCC - 2.9
+100
+100
V
V
mV
µA
+150
+4
40
42
.875
µA
µA
mA
+600
µA
Load
Commutating Voltage
Differential Load Range
Programmable Range
Offset Voltage
VCMIN Input Current
Accuracy
ISC Offset (Note 1)
ISK Offset (Note 1)
Gain (sourcing current)
Gain (sinking current)
Input Currents
Linearity (Note 2)
ILOAD / ISCIN
ILOAD / ISKIN
INL
HiZ Leakage (LDEN = False) (Note 3)
Output Impedance (Note 4)
ROUT
Digital Inputs
Input Current
Input Voltage Range
Differential Input Swing
LDEN, LDEN*
Programming Current Input
Voltage Compliance (Note 5)
V_ISKIN, V_ISCIN
+4
-150
35
35
0
+100
-100
37
39
-600
-1
±.1
+1
µA
5.0
7.5
15
Ω
-500
0.0
0.25
+500
+3.5
+3.0
µA
V
V
-100
+100
mV
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1: Offset is measured with ISCIN or ISKIN equal to 6 µA, producing an absolute output current of
100 µA nominal.
Note 2: Error = Measured IOUT vs. calculated IOUT. Calculated IOUT = (I * LSB) + Offset.
LSB = (Fullscale – Offset) / 9. I = Index = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
Index
ISCIN, ISKIN
0
6 µA
1
100 µA
2
200 µA
3
300 µA
4
400 µA
5
500 µA
6
600 µA
7
700 µA
8
800 µA
9
900 µA
Note 3: Tested @
1) LOAD = –3V, VCMIN = +3V
2) LOAD = +6.5V, VCMIN = +0.5V.
Note 4: Tested @ LOAD = +2V, IOUT = 5 mA and 15 mA.
Note 5: Tested @ ISCIN, ISKIN = 6 µA, 50 µA, 100 µA, 875 µA.
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics (continued)
Parameter
PRELIMINARY
Symbol
Min
CVA, CVB
VINP
VINP - CVA, B
Typ
Max
Units
VEE + 2.9
VEE + 2.9
-11
VCC - 2.9
VCC - 2.9
+11
V
V
V
-50
-150
+50
+10
µA
µA
Comparator
Threshold voltage
Input Voltage Range
Input Differential Voltage
Threshold Input Current
IPD Pin Input Current
VINP Input Current
Normal Operation IPD = 0 (Note 1)
VINP = VCC - 2.9V, CVA,B = VCC - 13.9V
VINP = VEE + 2.9V, CVA,B = VEE + 13.9V
IBIAS
IBIAS
IBIAS
-1
-3
-3
+1
+3
+3
µA
µA
µA
Offset Voltage
VOS
-50
+50
mV
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Comparator Hysteresis
Digital Output Swing
Common Mode Voltage
CMRR
PSRR
60
60
4
|QA - QA*|
|QB - QB*|
600
600
(QA + QA*) / 2
(QB + QB*) / 2
PECL - 1.5
PECL - 1.5
ICC
IEE
IDD
35
55
35
700
700
dB
dB
mV
1,000
1,000
mV
mV
PECL - 1.1
PECL - 1.1
V
V
75
95
90
mA
mA
mA
Power Supply (Load + Comp)
Positive Supply Current
Negative Supply Current
PECL Supply Current
50
75
55
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1:
Tested @ VINP = +7.0V and –1.0V.
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
AC Characteristics
PRELIMINARY
Parameter
Symbol
Min
Typ
Max
Units
Tpd (on)
Tpd (off)
1.0
1.0
3.0
3.0
5.0
5.0
ns
ns
Load
Propagation Delay
Inhibit to Iout (Note 2)
Iout to Inhibit (Note 2)
Output Capacitance
Load Active
Load Off
Cout
Cout
5.5
2.5
pf
pF
Comparator
Propagation Delay (Notes 1, 2)
Tpd
1.0
2.0
4.0
ns
Propagation Delay Dispersion (Note 2)
800 mV
3V
5V
-100
-100
-100
<±25
<±25
<±25
+100
+100
+100
ps
ps
ps
Input Slew Rate Tracking (Note 2)
IPD = 0
IPD = 1
5.0
25
6.0
V/ns
mV/ns
Cin
1.5
pF
Tr, Tf
250
ps
Input Capacitance
Output Rise and Fall Times (20% to 80%)
Minimum Pulse Width (Note 2)
1.5
ns
DC test conditions (unless otherwise specified): "Recommended Operating Conditions".
Note 1: Assumes normal operating mode of IPD = 0.
Note 2: Guaranteed by characterization. This parameter is not production tested.
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Edge672
EDGE HIGH-PERFORMANCE PRODUCTS
Ordering Information
PRELIMINARY
Model Number
Package
E672BTF
32-Pin 7mm x 7mm TQFP
EVM672BTF
Evaluation Module
Contact Information
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
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