HB56UW1673E-F 128MB Buffered EDO DRAM DIMM 16-Mword × 72-bit, 4k Refresh, 1 Bank Module (18 pcs of 16M × 4 components) E0101H10 (1st edition) (Previous ADE-203-1123A (Z)) Jan. 31, 2001 Description The HB56UW1673E belongs to 8-byte DIMM (Dual in-line Memory Module) family , and have been developed an optimized main memory solution for 4 and 8-byte processor applications. The HB56UW1673E is a 16 M × 72 Dynamic RAM Module, mounted 18 pieces of 64-Mbit DRAM (HM5165405) sealed in TSOP package and 2 pieces of 16-bit line driver sealed in TSSOP package. The HB56UW1673E offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56UW1673E is 168-pin socket type package (dual lead out). Therefore, the HB56UW1673E makes high density mounting possible without surface mount technology. The HB56UW1673E provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board. Features • 168-pin socket type package (Dual lead out) Lead pitch : 1.27 mm • Single 3.3 V supply : 3.3 ± 0.3 V • High speed Access time: tRAC = 50 ns/60 ns (max) Access time: tCAC = 18 ns/20 ns (max) • Low power dissipation Active mode: 8.46 W/7.16 W (max) Standby mode (TTL): 166 mW (max) • Buffered input except RAS and DQ • 4 byte interleave enabled, dual address input (A0/B0) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HB56UW1673E-F • • • • JEDEC standard outline buffered 8-byte DIMM EDO page mode capability 4096 refresh cycles: 64 ms 2 variations of refresh RAS-only refresh CAS-before-RAS refresh Ordering Information Type No. Access time Package Contact pad HB56UW1673E-5F HB56UW1673E-6F 50 ns 60 ns 168-pin dual lead out socket type Gold Pin Arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 85 pin 94 pin 95 pin 124 pin 125 pin Pin No. Signal name Pin No. 1 VSS 2 84 pin 168 pin Signal name Pin No. Signal name Pin No. Signal name 43 VSS 85 VSS 127 VSS DQ0 44 OE2 86 DQ36 128 NC 3 DQ1 45 RE2 87 DQ37 129 NC 4 DQ2 46 CE4 88 DQ38 130 NC 5 DQ3 47 NC 89 DQ39 131 NC 6 VCC 48 WE2 90 VCC 132 PDE 7 DQ4 49 VCC 91 DQ40 133 VCC 8 DQ5 50 NC 92 DQ41 134 NC 9 DQ6 51 NC 93 DQ42 135 NC 10 DQ7 52 DQ18 94 DQ43 136 DQ54 11 DQ8 53 DQ19 95 DQ44 137 DQ55 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ20 97 DQ45 139 DQ56 14 DQ10 56 DQ21 98 DQ46 140 DQ57 15 DQ11 57 DQ22 99 DQ47 141 DQ58 Data Sheet E0101H10 2 HB56UW1673E-F Pin Arrangement (cont) Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 16 DQ12 58 DQ23 100 DQ48 142 DQ59 17 DQ13 59 VCC 101 DQ49 143 VCC 18 VCC 60 DQ24 102 VCC 144 DQ60 19 DQ14 61 NC 103 DQ50 145 NC 20 DQ15 62 NC 104 DQ51 146 NC 21 DQ16 63 NC 105 DQ52 147 NC 22 DQ17 64 NC 106 DQ53 148 NC 23 VSS 65 DQ25 107 VSS 149 DQ61 24 NC 66 DQ26 108 NC 150 DQ62 25 NC 67 DQ27 109 NC 151 DQ63 26 VCC 68 VSS 110 VCC 152 VSS 27 WE0 69 DQ28 111 NC 153 DQ64 28 CE0 70 DQ29 112 NC 154 DQ65 29 NC 71 DQ30 113 NC 155 DQ66 30 RE0 72 DQ31 114 NC 156 DQ67 31 OE0 73 VCC 115 NC 157 VCC 32 VSS 74 DQ32 116 VSS 158 DQ68 33 A0 75 DQ33 117 A1 159 DQ69 34 A2 76 DQ34 118 A3 160 DQ70 35 A4 77 DQ35 119 A5 161 DQ71 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 PD1 121 A9 163 PD2 38 A10 80 PD3 122 A11 164 PD4 39 NC 81 PD5 123 NC 165 PD6 40 VCC 82 PD7 124 VCC 166 PD8 41 NC 83 ID0(VSS ) 125 NC 167 ID1 (VSS) 42 NC 84 VCC 126 B0 168 VCC Data Sheet E0101H10 3 HB56UW1673E-F Pin Description Pin name Function A0 to A11, B0 Address input Row address A0 to A11, B0 Column address A0 to A11, B0 Refresh address A0 to A11, B0 DQ0 to DQ71 Data input/output RE0, RE2 Row address strobe (RAS) CE0, CE4 Column address strobe (CAS) WE0, WE2 Read/Write enable OE0, OE2 Output enable PD1 to PD8 Presence detect ID0, ID1 ID bit PDE Presence detect Enable VCC Power supply VSS Ground NC No connection Presence Detect Pin Assignment (Controlled by PDE pin) PDE = Low PDE = High Pin name Pin No. 50 ns 60 ns All PD1 79 1 1 High-Z PD2 163 1 1 High-Z PD3 80 1 1 High-Z PD4 164 1 1 High-Z PD5 81 1 1 High-Z PD6 165 0 1 High-Z PD7 82 0 1 High-Z PD8 166 0 0 High-Z 1 : High level (driver output) 0 : Low level (driver output) Data Sheet E0101H10 4 HB56UW1673E-F Block Diagram RE0 CE0 WE0 OE0 A0 B0 A1 to A11 VCC VSS RE2 CE4 WE2 OE2 DQ0 DQ1 DQ2 DQ3 CAS RAS WE OE I/O I/O D0 I/O I/O DQ36 DQ37 DQ38 DQ39 CAS RAS WE OE I/O I/O D9 I/O I/O DQ4 DQ5 DQ6 DQ7 CAS RAS WE OE I/O I/O D1 I/O I/O DQ40 DQ41 DQ42 DQ43 CAS RAS WE OE I/O I/O D10 I/O I/O DQ8 DQ9 DQ10 DQ11 CAS RAS WE OE I/O I/O D2 I/O I/O DQ44 DQ45 DQ46 DQ47 CAS RAS WE OE I/O I/O D11 I/O I/O DQ12 DQ13 DQ14 DQ15 CAS RAS WE OE I/O I/O D3 I/O I/O DQ48 DQ49 DQ50 DQ51 CAS RAS WE OE I/O I/O D12 I/O I/O DQ16 DQ17 DQ18 DQ19 CAS RAS WE OE I/O I/O D4 I/O I/O DQ52 DQ53 DQ54 DQ55 CAS RAS WE OE I/O I/O D13 I/O I/O DQ20 DQ21 DQ22 DQ23 CAS RAS WE OE I/O I/O D5 I/O I/O DQ56 DQ57 DQ58 DQ59 CAS RAS WE OE I/O I/O D14 I/O I/O DQ24 DQ25 DQ26 DQ27 CAS RAS WE OE I/O I/O D6 I/O I/O DQ60 DQ61 DQ62 DQ63 CAS RAS WE OE I/O I/O D15 I/O I/O DQ28 DQ29 DQ30 DQ31 CAS RAS WE OE I/O I/O D7 I/O I/O DQ64 DQ65 DQ66 DQ67 CAS RAS WE OE I/O I/O D16 I/O I/O DQ32 DQ33 DQ34 DQ35 CAS RAS WE OE I/O I/O D8 I/O I/O DQ68 DQ69 DQ70 DQ71 CAS RAS WE OE I/O I/O D17 I/O I/O D0 to D8 D9 to D17 D0 to D17 D0 to D17,16-bit line driver PD1 to PD8 VCC VCC VCC VCC D0 to D17, 16-bit line driver VCC 0.22 µF × 20 pcs VCC VSS *D0 to D17: HM5165405 VCC : 16-bit line driver VSS VSS PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Data Sheet E0101H10 5 HB56UW1673E-F Absolute Maximum Ratings Parameter Symbol Value Unit Terminal voltage on any pin relative to V SS VT –0.5 to +4.6 V Power supply voltage relative to V SS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 19 W Storage temperature range Tstg –55 to +125 °C DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 3.0 3.3 3.6 V 1, 2 VSS 0 0 0 V 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Ambient temperature range Ta 0 — 70 °C Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Data Sheet E0101H10 6 HB56UW1673E-F DC Characteristics HB56UW1673E 50 ns Parameter 60 ns Symbol Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 2350 — 1990 mA t RC = min Standby current I CC2 — 46 — 46 mA TTL interface RAS, CAS = VIH Dout = High-Z — 19 — 19 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 2350 — 1990 mA t RC = min Standby current* I CC5 — 100 — 100 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 2350 — 1990 mA t RC = min EDO page mode current*1, * 3 I CC7 — 1990 — 1810 mA RAS = VIL , CAS cycle, t HPC = tHPC min Input leakage current I LI –5 5 –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –5 5 –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA 1 RAS-only refresh current*2 1 Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 20 pF 1 Input capacitance (CAS, WE, OE) CI2 — 20 pF 1 Input capacitance (RAS) CI3 — 78 pF 1 I/O capacitance (DQ) CI/O — 20 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. Data Sheet E0101H10 7 HB56UW1673E-F AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2 ,*19 Test Conditions • • • • • Input rise and fall times: 2 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — ns RAS precharge time t RP 30 — 40 — ns CAS precharge time t CP 8 — 10 — ns RAS pulse width t RAS 50 10000 60 10000 ns CAS pulse width t CAS 8 10000 10 10000 ns Row address setup time t ASR 5 — 5 — ns Row address hold time t RAH 8 — 10 — ns Column address setup time t ASC 0 — 0 — ns Column address hold time t CAH 8 — 10 — ns RAS to CAS delay time t RCD 12 32 14 40 ns 3 RAS to column address delay time t RAD 10 20 12 25 ns 4 RAS hold time t RSH 18 — 20 — ns CAS hold time t CSH 38 — 40 — ns CAS to RAS precharge time t CRP 10 — 10 — ns OE to Din delay time t OED 18 — 20 — ns 5 OE delay time from Din t DZO 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — ns 6 Transition time (rise and fall) tT 2 50 2 50 ns 7 Data Sheet E0101H10 8 Notes HB56UW1673E-F Read Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 ns 8, 9 Access time from CAS t CAC — 18 — 20 ns 9, 10, 17 Access time from address t AA — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 18 — 20 ns 9 Read command setup time t RCS 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — ns Read command hold time from RAS t RCHR 50 — 60 — ns Read command hold time to RAS t RRH 0 — 0 — ns Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — ns CAS to output in low-Z t CLZ 2 — 2 — ns Output data hold time t OH 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — ns Output buffer turn-off time t OFF — 18 — 20 ns 13, 21 Output buffer turn-off to OE t OEZ — 18 — 20 ns 13 CAS to Din delay time t CDD 18 — 20 — ns 5 Output data hold time from RAS t OHR 3 — 3 — ns 21 Output buffer turn-off to RAS t OFR — 13 — 15 ns 13, 21 Output buffer turn-off to WE t WEZ — 18 — 20 ns 13 WE to Din delay time t WED 18 — 20 — ns RAS to Din delay time t RDD 13 — 15 — ns 12 12 21 Write Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — ns 14 Write command hold time t WCH 8 — 10 — ns Write command pulse width t WP 8 — 10 — ns Write command to RAS lead time t RWL 18 — 20 — ns Write command to CAS lead time t CWL 8 — 10 — ns Data-in setup time t DS 0 — 0 — ns 15 Data-in hold time t DH 13 — 15 — ns 15 Data Sheet E0101H10 9 HB56UW1673E-F Read-Modify-Write Cycle HB56UW1673E 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 116 — 140 — ns RAS to WE delay time t RWD 72 — 84 — ns 14 CAS to WE delay time t CWD 30 — 34 — ns 14 Column address to WE delay time t AWD 42 — 49 — ns 14 OE hold time from WE t OEH 13 — 15 — ns Refresh Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 8 — 10 — ns WE setup time (CBR refresh cycle) t WRP 5 — 5 — ns WE hold time (CBR refresh cycle) t WRH 8 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 5 — ns Notes EDO Page Mode Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 — ns 20 EDO page mode RAS pulse width t RASP — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 33 — 40 ns 9, 17 RAS hold time from CAS precharge t CPRH 33 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — ns CAS hold time referred OE t COL 8 — 10 — ns CAS to OE setup time t COP 5 — 5 — ns Read command hold time from CAS precharge t RCHC 28 — 35 — ns Write pulse width during CAS precharge t WPE 8 — 10 — ns OE precharge time 8 — 10 — ns t OEP Data Sheet E0101H10 10 9, 22 HB56UW1673E-F EDO Page Mode Read-Modify-Write Cycle 50 ns 60 ns Parameter Symbol Min Max Min Max Unit EDO page mode read- modify-write cycle time t HPRWC 57 — 68 — ns WE delay time from CAS precharge t CPW 45 — 54 — ns Notes 14 Refresh Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 4096 cycles Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. Data Sheet E0101H10 11 HB56UW1673E-F 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. 22. t DOH defines the time at which the output level go cross. V OL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Data Sheet E0101H10 12 HB56UW1673E-F Timing Waveforms*23 Read Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tT tRSH tCAS CAS tRAD tASR Address tRAH tRAL tCAL tASC tCAH Column Row tRRH tRCHR tRCS tRCH WE tDZC tCDD tWED tRDD High-Z ; Din tDZO tOEA tOED OE tOEZ tOHO tOFF tOH tOFR tOHR tCAC tAA tRAC tCLZ tWEZ Dout Dout Data Sheet E0101H10 13 HB56UW1673E-F Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din tDH Din High-Z* Dout * t WCS Data Sheet E0101H10 14 t WCS (min) HB56UW1673E-F Delayed Write Cycle*18 tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC High-Z Din ; Din tDH tOED tDZO tOEH tOEP OE tOEZ tCLZ High-Z Dout Invalid Dout Data Sheet E0101H10 15 HB56UW1673E-F Read-Modify-Write Cycle*18 tRWC tRAS tRP RAS tT tRCD tCAS tCRP CAS tRAD tASR Address tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din ; Din tDH tOED tDZO tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout tCLZ Data Sheet E0101H10 16 High-Z HB56UW1673E-F RAS-Only Refresh Cycle tRC tRAS tRP RAS tT tRPC tCRP tCRP CAS tASR tRAH Row Address tOFR tOFF High-Z ; Dout Data Sheet E0101H10 17 HB56UW1673E-F CAS-Before-RAS Refresh Cycle tRC tRP tRC tRP tRAS tRAS tRP RAS tT tRPC tCP tRPC tCSR tCHR tWRP tWRH tCP tCRP tCSR tCHR CAS tWRP WE Address tOFR tOFF High-Z ; Dout Data Sheet E0101H10 18 tWRH HB56UW1673E-F EDO Page Mode Read Cycle (1) t RP t HPC t RASP RAS tT t CSH t CP t HPC t CAS CAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t WPE t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tAA tCAC tCPA tAA tCAC tOEZ tOHO tAA tOEZ ; tCAC tAA tOFR tOHR tOEZ tCPA tCPA tOEA tWEZ tOEA tRAC Dout tDOH Dout 1 Dout 2 Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 Data Sheet E0101H10 19 HB56UW1673E-F EDO Page Mode Read Cycle (2) t RP t RASP RAS tT t CSH t CP t HPC t CAS CAS tHPC t CP t HPC t CP t CAS t CAS t CRP tRSH tCAS t RCHC t RRH t RCH t RCS WE tASR Address tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 t CAL t RAL t CAH tASC Column 3 t CAL t WED Column 4 t CAL tRDD t CAL tDZC tCDD High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tOEA tCPA tAA tCAC tCPA tAA tCAC tOEZ tAA ; tCAC tAA tOFR tOHR tOEZ tCPA tDOH tRAC Dout tOHO tOEA tDOH tOHO Dout 1 Dout 2 Data Sheet E0101H10 20 tOEZ Dout 2 Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 HB56UW1673E-F EDO Page Mode Early Write Cycle tRASP tRP RAS tT tCSH tHPC tCAS tRCD tCP tRSH tCAS tCP tCAS tCRP CAS tASR Address Row tRAH tASC tCAH Column 1 tWCS tWCH tASC tCAH Column 2 tWCS tWCH tASC tCAH Column N tWCS tWCH WE tDS Din Dout tDH Din 1 tDS tDH Din 2 tDS tDH Din N High-Z* * t WCS t WCS (min) Data Sheet E0101H10 21 HB56UW1673E-F EDO Page Mode Delayed Write Cycle*18 tRASP tRP RAS tT tCP tRCD tCRP tCP tCSH tHPC tCAS tCAS tRSH tCAS CAS tRAD tASR tASC tCAH tASC tCAH Column 1 Column 2 tRAH Address Row tASC tCAH tCWL Column N tCWL tCWL tRWL tRCS tRCS tRCS WE tWP tDZC tDS tWP tDZC tDS tWP tDZC tDS tDH tDH Din 1 Din tDZO tOED tDH Din 2 tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH ; tOEP tOEH Din N OE tCLZ tCLZ tOEZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout Data Sheet E0101H10 22 Invalid Dout High-Z HB56UW1673E-F EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t HPRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t CPW t AWD t RCS t CWD Column N t CWL t AWD t RCS t CWD t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t OEP t OEH t DH Din 2 t OED t DZO t OEP t OEH Din N t OED t DZO t OEP t OEH OE t OHO t OHO ; ; t OHO t OEA t CAC t OEA t CAC t AA t OEA t CAC t AA t CPA t RAC t OEZ t CLZ t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N Data Sheet E0101H10 23 HB56UW1673E-F EDO Page Mode Mix Cycle (1)∗20 t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS t CSH tCAS tCWL tRSH t RCD t WCS t WCH tCPW tAWD WE t ASC tRAH tASR Address Row tCAH Column 1 t RRH t RCH t RCS t RCS t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RAL t CAH Column 4 t CAL t DS Din Din 1 tRDD tCDD t CAL t DH t DH t DS High-Z Din 3 ; tOED tOEP tWED OE tCPA tAA tCAC Dout t DOH Dout 2 Data Sheet E0101H10 24 tOFR tWEZ tCPA tCPA tAA tOEA t OEZ tCAC t OHO Dout 3 tAA tOEZ tCAC tOHO tOEA tOFF tOH Dout 4 HB56UW1673E-F EDO Page Mode Mix Cycle (2)∗20 t RP t RASP RAS tT t CSH t CAS CAS t RCD t CAS tCAS t RCHR t RCS t RCH tWCS t WCH Address tCAS tCWL Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t RRH t RCH tWP tCPW t ASC tRAH tRSH t RCS t RCS WE tASR t CRP t CP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS t DS High-Z Din t DH tRDD tCDD t DH Din 2 Din 3 t OEP t OEP tOED tOED tCOP tWED tCOL OE t OEA tAA tOEA tCAC tOEZ tCPA tAA tCAC tRAC tOEZ t OHO t OHO Dout Dout 1 tOFR tWEZ tCPA Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 Data Sheet E0101H10 25 HB56UW1673E-F Physical Outline HB56UW1673E Series Unit: mm inch Front side 133.35 5.250 4.00 max 0.157 max 127.35 5.014 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Front) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 84 B C 11.43 8.89 0.350 0.450 4.00 min 0.157 min 3.00 0.118 3.00 0.118 ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;; A 36.83 1.450 1.27 ± 0.10 0.050 ±0.004 54.61 2.150 Back side 85 3.175 0.125 3.125 ± 0.125 0.123 ± 0.005 0.25 max 0.010 max 2.54 min 0.100 min 1.00 ± 0.05 0.039 ± 0.002 Detail B and C 1.27 0.050 Data Sheet E0101H10 26 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 31.75 1.250 168 Detail A 4.00 0.157 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Back) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 17.78 0.700 2 – φ 3.00 2 – φ 0.118 HB56UW1673E-F Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. Data Sheet E0101H10 27