ETC HD6417729

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various
means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams,
charts, programs, and algorithms, please be sure to evaluate all information as a total system before
making a final decision on the applicability of the information and products. Renesas Technology
Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be
exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products
contained therein.
SH Graphics/Speech Processing
Demonstration System
NAV-DS4
Application Note
ADE-502-058
Rev. 1.0
Preliminary
3/5/03
Hitachi, Ltd.
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole
or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents
or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics
and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for
any intellectual property claims or other problems that may result from applications based on
the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third
party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
Preface
This Application Note covers the hardware and software of the NAV-DS4 navigation SH
graphics/speech processing demonstration system developed by Hitachi, Ltd. It includes a number
of practical examples intended for use as reference material when designing a navigation system
using an SH3 microcomputer and Q2 graphics renderer (however, note that NAV-DS4 does not
support GPS (Global Positioning System)).
The NAV-DS4 uses a variety of Hitachi semiconductor devices, including an SH3 (SH7708) 32bit RISC processor, Q2 (HD64411) 2-dimensional (2D) graphics renderer, 16M DRAM
(HM51W18165), and 8M flash memory (HN29WT800).
Demonstration application software provided with the NAV-DS4 comprises map drawing and
display, ∆YUV natural image display, ADPCM speech output. All of this software runs on an HISH77 real-time operating system conforming to the µITRON standard.
Operation, performance, and standards as a product are not guaranteed for the NAV-DS4. The
operation of the electronic circuits and software included in this Application Note must be
evaluated and confirmed by the user before use in an actual application system.
Contents
Section 1
1.1
1.2
1.3
1.4
1.5
1.6
Overview............................................................................................................ 1
System Specifications ........................................................................................................ 1
System Configuration ........................................................................................................ 3
Drawing and Display Processing Procedure...................................................................... 4
External Appearance of NAV-DS4.................................................................................... 6
Operating Procedures ......................................................................................................... 7
Usage Notes ....................................................................................................................... 13
Section 2
2.1
2.2
2.3
2.4
NAV-DS4 Software .......................................................................................
Overview of Demonstration System..................................................................................
Overall Software Configuration.........................................................................................
Task Configuration ............................................................................................................
Task Functions ...................................................................................................................
Section 3
3.1
3.2
3.3
3.4
3.5
3.6
NAV-DS4 Hardware ......................................................................................
Hardware Configuration ....................................................................................................
Operation of Mother Board and Daughter Board ..............................................................
SH7708 Operating Conditions ...........................................................................................
Q2 Operating Conditions ...................................................................................................
Interfaces between SH7708 and Peripherals......................................................................
SH7708 and Peripheral Timing Charts ..............................................................................
15
15
18
19
20
21
21
23
23
35
48
63
i
Section 1 Overview
1.1
System Specifications
Table 1.1 summarizes the specifications of the navigation graphics demonstration system covered
in this Application Note.
Table 1.1
Navigation Graphics Demonstration System Specifications
Item
Specifications
Product code
NAV-DS4
Product name
Navigation graphics demonstration
system
Mother board
CPU
SH-3 (SH7708)
RAM
EDO-DRAM (4 Mbyte) * 1
Notes
Internal operating
frequency: 60 MHz
SRAM (256 kbyte) * 2
ROM
Daughter board Graphics
renderer
UGM
Flash memory (8 Mbyte)
Q2 * 3
Operating frequency:
30 MHz
EDO-DRAM (4 Mbyte)
CD-ROM drive
Max. 10X (SCSI) * 4
Data transfer speed:
1.5 Mbytes/sec
Embedded OS
HI-SH77
Real-time multitasking OS
conforming to µITRON
specifications Ver. 2.02
Graphics
processing
Map data
Conforms to Navigation System
Researcher’s Association unified
standard
Display colors 8 bits/pixel: 256 of 260,000 colors
16 bits/pixel: 60,000 colors
Display size
320 × 240
Functions
5-level reduction/enlargement
4-directional smooth scrolling
Dot units (up/down/left/right)
360-degree rotation
Degree units (left rotation/
right rotation)
Restoration and playback of ∆YUV- Q2 hardware
compressed natural images
1
Table 1.1
Navigation Graphics Demonstration System Specifications (cont)
Item
Speech
processing
Notes: 1.
2.
3.
4.
5.
Functions
Specifications
Notes
Restoration and playback of
ADPCM-compressed speech * 6
SH3 software
EDO: Extended Data Out—Dynamic Random Access Memory
SRAM: Static Random Access Memory
Q2: Quick 2D Graphics Renderer
SCSI: Small Computer System Interface
TRON: The Real Time Operating System Nucleus
µITRON: Micro Industrial TRON
6. ADPCM: Adaptive Delta Pulse Code Modulation
2
1.2
System Configuration
Figure 1.1 shows the system configuration.
PC
TV
screen
EDODRAM
(16 Mbit × 2)
SCI
I/F
Q2
(HD64411)
DAC
SH-3
(HD6417708)
Key input
block
Video output
block
Display
monitor
Data bus
Address bus
SCI
I/F
FLASH
(8 Mbit × 8)
EDODRAM
(16 Mbit × 2)
Speech
I/F
DAC
Line
input
CD-ROM
drive with
built-in speaker
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
Figure 1.1 System Configuration
This demonstration system consists of a mother board holding a 32-bit RISC processor (SH7708:
60 MHz operation), a daughter board holding a graphics renderer (Q2: 30 MHz operation), and a
CD-ROM drive that reads map data from a CD-ROM.
In graphics processing, the SH7708 handles geometrical operations while the Q2 is responsible for
rendering (drawing) operations. This reduces the processing load on the SH processor and
improves system bus utilization.
In speech processing, real-time regeneration of ADPCM speech data is possible by means of highspeed processing using the SH7708, enabling the number of dedicated devices used, and system
cost, to be reduced.
A real-time multitasking OS (operating system) conforming the µITRON specifications is
incorporated, enabling both independent and parallel processing, and increasing the real-time
capabilities of the system.
3
1.3
Drawing and Display Processing Procedure
Figure 1.2 shows the map drawing flow in the NAV-DS4. The procedure is outlined below.
1. Management information, text, and map data are read from CD-ROM and stored in DRAM.
2. The SH7708 performs coordinate conversion on the map data and transfers the converted data
to DRAM.
3. The SH7708 regenerates the display list (list of Q2 drawing commands) from the coordinate
map data in DRAM, and transfers this to the Q2’s UGM.
4. The SH7708 enables drawing execution by the Q2. The Q2. performs drawing in accordance
with the display list. The SH7708 can execute other tasks while the Q2 is drawing.
5. The Q2 uses a double-buffering system with a drawing plane and a display plane , so that the
display plane can be displayed during drawing. Display control is performed by the Q2 itself,
without involving the SH7708.
6. When drawing ends, the drawing plane and display plane are switched. Screen switching
control by the Q2 or the SH7708 can be selected.
7. In 8-bit/pixel mode, dot-unit data is converted to any of 256 colors from among 260,000 colors
with the color palette (CPLT: ColPalet). In 16-bit/pixel mode, 60,000 colors can be displayed.
4
Figure 1.2 Drawing and Display Processing Flow
5
Display
7 RGB signal output
Q2
Display processing
UGM (DRAM)
Data after drawing
processing
6 Drawing in UGM
Q2
Drawing processing
5 Display list transfer
before drawing
SH microcomputer
Display list regeneration
processing
4 Transfer of data
DRAM
Coordinate-converted
map data before drawing
coordinate conversion
3 Transfer of data after
SH microcomputer
Coordinate conversion
processing
2 Map data transfer
Flash memory
4
2
Drawing library
Application
OS (HI-SH77)
POLYGON4C
..
LINE
..
Display list (example)
SH
microcomputer
BSC
Cache
CPU
1 Map data, text, management
information data transfer
DRAM
Map data, text,
management information
CD-ROM
Map data, text,
management information
3
CD-ROM
Data bus
Coordinateconverted map
data
Map data
(vector
data
format)
1
5
Text data
management
information
DRAM
7
UGM (DRAM)
Drawing
frame
Display
unit
CPLT
Display list
Display
frame
6
Rendering
unit
I/F
Q2
D/A
R G B
Monitor
1.4
External Appearance of NAV-DS4
Figure 1.3 shows an external view of the NAV-DS4. The NAV-DS4 consists of a mother board, a
daughter board, a CD-ROM drive, and a monitor. The system is operated by means of operating
key switches on the mother board. The operating keys are shown in figure 1.4.
,,,
,,,
,,,
,,,
,,,
,,,
,,,
,,,
CD-ROM drive
with built-in
speaker
SCSI cable
Q2
Mother board
Daughter board
SH7708
Monitor
Operating key
switches
Figure 1.3 External View of NAV-DS4
SW0
SW1
SW2
SW3
Menu
SW4
SW5
SW6
SW7
SW8
SW9
SW10
SW11
Wide
area
Enter
SW12
SW13
SW14
SW15
Detail
Figure 1.4 NAV-DS4 Operating Key Panel Layout
6
1.5
Operating Procedures
NAV-DS4 operating procedures are described here. Be sure to read the Usage Notes in the
following section before operating the NAV-DS4.
(1) Demonstration System Setup Procedure (See Figure 1.5)
1. Place the mother board, CD-ROM drive, and monitor on a table, desk, or similar flat surface as
shown in the figure below.
2. Connect the daughter board to the mother board connector as shown in the figure.
3. Connect the SCSI cable and monitor cable.
4. Connect the power cords to the CD-ROM drive and monitor, plug them into a 100 VAC power
outlet, and turn on the power.
5. Insert a Navigation System Research Association format CD-ROM in the prescribed position
in the CD-ROM drive, and turn on the CD-ROM drive power.
6. Check steps 2 to 5 again, then plug the power cord connected to the mother board into a 100
VAC power outlet, and turn on the power.
CD-ROM
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
CD-ROM drive
,,,,
,,,,
,,,,
Graphics processing
unit power cable
,,,,
,,,,
,,,,
SCSI cable
Power cord
Power switch
Q2
Monitor cable
Mother board
Daughter board
SH7708
Monitor
Reset switch
Figure 1.5 NAV-DS4 Setup Procedure Diagram
7
(2) Operations after Setup (Examples)
Display Screen
SW Board Operations
Description
Initial screen on powering on
No operation
necessary
Initial screen
When power is turned on,
the initial screen is
displayed. (Automatic)
Menu
SuperH
Enter
RISC engine
Map screen display
No operation
necessary
Map screen is displayed
After the initial screen is
displayed, map data is
read from the CD-ROM,
drawing is performed,
and the result is
displayed on the screen.
(Automatic)
Menu
Enter
Map screen scrolling
Up
Menu
Left
Enter
Down
8
Right
Scrolling (in any of 4
directions) continues
while the up, down, left,
or right key is pressed on
the SW board, and stops
when the key is released.
Display Screen
Description
SW Board Operations
Map screen enlargement/reduction
Menu
Enter
Wide
area
Detail
Pressing the Detail key in
the SW board displays a
Reduce
map enlarged by one
level; pressing the Wide
Area key displays a map
reduced by one level.
(5 enlargement/reduction
levels available)
Enlarge
Map screen rotation
Right rotation
Left rotation
Menu
Enter
Wide
area
Detail
The map is rotated (in
degree units) about the
center of the screen while
a rotation key on the SW
board is pressed.
Rotation stops when the
key is released.
Setting after rotation
Menu
Menu screen
North-up display setting
Up
Menu
Enter
∆YUV
MENU
ADPCM
Enter
Wide
area
Detail
After a map rotation
demonstration, press the
Menu key on the SW
board, select “North-up
display setting,” and
press the Enter key. The
display will return to its
state prior to the rotation.
Down
9
(3) ∆YUV Demonstration Operations
Display Screen
SW Board Operations
Description
Starting ∆YUV demonstration
Menu
Up
Fixed-north
∆YUV
MENU
Menu
Enter
ADPCM
Enter
Wide
area
Detail
Press the menu key to
display the menu screen,
and move the cursor to
“∆YUV” with the up/down
keys. The ∆YUV
demonstration is started
by pressing the Enter key.
Down
∆YUV demonstration
Menu
Enter
Wide
area
The ∆YUV natural image
display demonstration is
an automatic demonstration (no key input
required).
Detail
End of ∆YUV demonstration
Menu
Enter
Wide
area
Detail
10
The automatic
demonstration ends after
approximately one
minute, and the map
screen is displayed again.
(4) ADPCM Demonstration Operations
Display Screen
SW Board Operations
Description
Starting ADPCM demonstration
Menu
Up
Menu
Fixed-north
Enter
∆YUV
MENU
ADPCM
Wide
area
Enter
Detail
Down
Press the menu key to
display the menu screen,
and move the cursor to
“ADPCM” with the
up/down keys. The
ADPCM demonstration is
started by pressing the
Enter key.
Phrase playback
: Phrase playback keys
0
∆YUV
MENU
1
2
3
6
7
Menu
Fixed-north
4
5
8
9
ADPCM
Wide
area
Enter
10
11
Detail
12
13
14
15
Keys and corresponding phrases
Key
No.
Phrase
Meaning
2
Pin-pon
Chimes
4
O-yo-so
Approximately
5
Ko-no-sa-ki
Ahead
6
Ryou-ki-n-jo-no-sa-ki
Beyond the tollbooth
8
Ichi-ki-ro-mei-to-ru-de 1 km
10
Ni-ki-ro-mei-to-ru-de
2 km
12
Ji-ta-ku-de-su
Your home
13
Mo-ku-te-ki-chi-de-su Your destination
14
De-gu-chi-de-su
Pressing a phrase
playback key plays the
phrase assigned to that
key. The phrase playback
keys arranged so that a
sentence can be
constructed from four
phrases (including
chimes) by selecting a
phrase from each row in
turn, starting at the top
row and moving
downward. (The phrase
arrangement is shown on
the left.)
The exit
11
Display Screen
SW Board Operations
Description
Phrase recording/deletion
Menu
Fixed-north
∆YUV
MENU
ADPCM
Enter
Wide
area
Detail
Deletion
Phrase
recording
Pressing the record key
(Detail) will record the
phrase played
immediately before. The
maximum number of
recordings is set at 5.
Pressing the delete key
(Wide Area) will delete the
phrase recorded
immediately before. This
is used to delete a phrase
recorded by mistake.
Sentence playback
Pressing the sentence
playback key (Enter) will
play the recorded
phrases as a sentence.
Menu
Fixed-north
∆YUV
MENU
ADPCM
Enter
Wide
area
Detail
Sentence playback
Ending ADPCM demonstration
Menu
End
Enter
Wide
area
Detail
12
Pressing the end key
(menu) will end the
ADPCM demonstration
and display the map
screen again.
1.6
Usage Notes
1. The power supply must be 100 VAC. The NAV-DS4 can be used in both 50 Hz and 60 Hz
regions.
2. Always grip the plug when connecting or removing a power cord.
3. System damage, fire, or electric shock may result if a power cord, power cable, or flat cable is
stretched, bent, extended, touched with wet hands, or inserted the wrong way round.
3. This system is a navigation demonstration unit, and is not covered by the same after-sales
service warranty as other Hitachi products.
5. This system has been developed for use under normal environmental conditions (normal
temperature and humidity). Special consideration has not been given to variations in
environmental conditions or secular change.
6. If a demonstration does not operate normally (fails to work when power is turned on) or halts,
press the Reset button. If this does not restore normal operation, disconnect and the reconnect
the mother board power supply. If repeated use of these methods fails to restore normal
operation, consult the manufacturer.
7. If the CD-ROM drive races out of control, turn of the power immediately.
8. Remove any dust from CD-ROM disks before use, as this may prevent data from being read.
13
Section 2 NAV-DS4 Software
2.1
Overview of Demonstration System
The NAV-DS4 can execute the following four kinds of demonstration.
1. Map drawing and display demonstration (scrolling, zooming, rotation)
Map data is read from a Navigation System Researcher’s Association format CD-ROM and
drawing and display are performed. The drawn map can be scrolled up, down, left, or right in
dot units, enlarged or reduced in 5 stages, and rotated through 360 degrees.
2. Natural image (∆YUV image) display demonstration
Natural image data that has undergone ∆YUV compression is read from a Navigation System
Researcher’s Association format CD-ROM, high-speed conversion from ∆YUV data to RGB
data is performed using the Q2, and the result is displayed. During display, the converted data
is enlarged/reduced, transformed, rotated, etc., using the high-speed drawing functions of the
Q2.
3. ADPCM speech playback demonstration
Speech data that has undergone ADPCM compression is read from a Navigation System
Researcher’s Association format CD-ROM, restored using ADPCM restoration middleware,
and played via the speaker.
Operations for these demonstrations are carried out by means of the key switches on the board.
Table 2.1 lists the key functions, and figure 2.1 shows the overall NAV-DS4 demonstration
software configuration.
15
Table 2.1
Key Functions
Key
Function
Mark
Scrolling
Rotation
Enlargement/
reduction
Wide
area
Detail
Menu selection
Enter
MENU
Other
Assigned
No.
Functions
In Map Drawing
In Menu
Selection
In ADPCM
Demonstration
5
To look above
display map screen
Selects item
above
Reads ADPCM
speech data
d
To look below
display map screen
Selects item
below
Reads ADPCM
speech data
8
To look to left of
display map screen
—
Reads ADPCM
speech data
a
To look to right of
display map screen
—
Reads ADPCM
speech data
7
Left (anticlockwise)
rotation
—
—
3
Right (clockwise)
rotation
—
—
b
Reduces display
map
—
Deletes data
recorded
immediately before
f
Enlarges display
map
—
Records selected
data
9
—
Starts selected
application
Outputs recorded
data as sentence
1
Displays menu
screen
—
Ends ADPCM
demonstration
2
—
—
Reads ADPCM
speech data
4
—
—
Reads ADPCM
speech data
6
—
—
Reads ADPCM
speech data
c
—
—
Reads ADPCM
speech data
e
—
—
Reads ADPCM
speech data
0
—
—
—
—: Invalid (pressing this key has no effect).
16
Start of
demonstration
Initialization
NAV-DS4
demonstration
CPU register
settings
Q2 register
settings
Set map display
coordinate initial
values
Set mode decision
variable to map
mode
Initial screen
display
Read CD-ROM
Disk label
Drawing
parameters
Unit management
information
Scroll keys
Read CD-ROM
Unit data
Map drawing
and display
Key input
Until demonstration selection
input
Zoom keys
Enlargement/
reduction
processing
Rotate keys
Until Menu key
input
Until reset or
power-off
End of
demonstration
Scroll processing
Rotation
processing
Menu display
Fixed-north display
∆YUV demonstration
Demonstration
selection input
∆YUV automatic
demonstration
ADPCM demonstration
Until key input
Menu display
Phrase output
Until Menu key
input
Phrase recording
Key input
Recorded phrase
deletion
Continuous
playback of
recorded phrases
Figure 2.1 Overall NAV-DS4 Demonstration Software Configuration
17
2.2
Overall Software Configuration
The NAV-DS4 incorporates an HI-SH77 real-time multitasking operating system conforming to
the µITRON standard. Application programs are divided into processing units which are recorded
in the kernel as “tasks.” A maximum of 1023 tasks can be recorded. The kernel identifies and
manages each task by means of a number from 1 to 1023 called the task ID. Tasks are activated
via the kernel by means of asynchronously generated events such as key input operations.
Interrupt handlers are also created to handle processing by interrupts. When an interrupt occurs,
control is passed to an interrupt handler via an exception service routine in the kernel. The NAVDS4 uses a variety of interrupts, including key input, SCSI protocol control, and CD-ROM drive
data reads.
Having the operating system manage and control program flow in this way enables efficient, realtime demonstration operations to be implemented. The relationship between tasks and the kernel
in the NAV-DS4 is illustrated in figure 2.2. For detailed specifications of the HI-SH77 operating
system, refer to the HI-SH77 User’s Manual and Construction Manual.
Events
Execution
Interrupt handler
Key input
Kernel
SCSI control
Execution
System calls
Execution
System
calls
Task 2
Task 1
Application
Application
Figure 2.2 Relationship Between Tasks and Kernel
18
2.3
Task Configuration
Figure 2.3 shows the configuration of the tasks and interrupt handlers recorded in the kernel by the
NAV-DS4.
Kernel
Key input
control tasks
Menu
control task
Scroll
control task
Rotation
control task
Enlargement/
reduction
control task
ADPCM
control task
Activation
Menu
control task
Drawing/
display
control block
CD-ROM
control block
Mode
control block
Drawing/
display
control block
Drawing/
display
control block
CD-ROM
control block
CD-ROM
control block
Drawing/
display
control block
ADPCM
control block
Activation
Scroll
control task
Activation
Rotation
control task
Interrupt handlers
Activation
Enlargement/
reduction
control task
Activation
ADPCM
control task
Activation
SCSI
control block
CD-ROM
data read
Key input
control task
Speech
output control
Key no.
Read
∆YUV
control block
Activation
: Indicates that the task is activated by issuance of a processing
request (system call) to the kernel.
Figure 2.3 Task and Interrupt Handler Configuration
19
2.4
Task Functions
Table 2.2 summarizes the functions of the tasks and interrupt handlers recorded in the kernel by
the NAV-DS4.
Table 2.2
Summary of Functions (1/3)
Task Name
Function
Key input control
Issues a processing request (system call) to the kernel according to the key
input, activating a task. The meaning of the keys depends on the key input
mode.
1. In map mode (normal mode)
Performs scroll control task activation by means of the up/down/left/right
arrow keys, rotation control task activation by means of the rotate keys,
enlargement/reduction control task activation by means of the Wide Area
and Detail keys, and menu control task activation by means of the Menu
key.
2. In menu operation mode
Selects a menu display item by means of the up/down arrow keys, and
activated the task corresponding to the item.
3. In ADPCM mode
Performs activation of ADPCM control tasks corresponding to the
up/down/left/right arrow keys, rotate keys, Wide Area and Detail keys, and
Enter and Menu keys.
Menu selection
control
Draws the menu screen, and sets the menu operation mode, ADPCM
demonstration mode, or speech synthesis demonstration mode from map
mode according to the menu display items
Scroll control
Reads map data from the CD-ROM, creates a display list, and draws a map in
the Q2’s multi-valued source area. In scroll movement processing, drawing is
performed while updating coordinate locations from the multi-valued source
area to the display area at each Q2 vertical sync signal.
Rotation control
Performs coordinate conversion of map data by means of affine
transformation processing, creates a display list, and draws in the display
area with the Q2.
Enlargement/
reduction control
Reads wide-area or detailed map data from the CD-ROM, creates a display
list, and draws in the display area with the Q2.
ADPCM control
Reads ADPCM data from the CD-ROM, and performs data expansion
processing.
20
Section 3 NAV-DS4 Hardware
3.1
Hardware Configuration
The NAV-DS4 mother board consists of an SH7708 32-bit RISC microcomputer, various kinds of
memory (an HM51W18165AJ-6 2-Mbyte DRAM, HN29WB800T-8 8-Mbyte flash memory, and
HN67W1664-JP-12 256-kbyte static RAM), an HD151015 level shifter, Hitachi HD74LVC Series
CMOS logic semiconductor devices, an RS-232C control IC, SCSI control IC, D/A converter, and
three FPGAs (field programmable gate arrays) for key input control, SCSI control, and speech
control. The daughter board comprises an HD64411F (Q2), HM5118165ATT-7 2-Mbyte DRAM,
and HD153510 F50 (DAC) Hitachi semiconductor devices, and an RGB encoder. Tables 3.1 and
3.2 list the functions of the LSIs mounted on the NAV-DS4’s mother board and daughter board,
and figure 3.1 shows the hardware configuration.
Table 3.1
Functions of LSIs Mounted on Mother Board
Mounted LSI
Device Function
HD6417708F60A (SH7708)
32-bit RISC microcomputer
HM51W18165AJ-6
16Mbit-EDO-DRAM
HM67W1664-JP-12
1Mbit-SRAM
HN29WB800T-8
8Mbit-FLASH MEMORY
HD151015
Level shifter
HD74LVC244A
Unidirectional level shifter
HD74LVC245A
Bidirectional level shifter
HD74LVC08
AND gate
HD74LVC00
NAND gate
HD74LVC32
OR gate
HD74LVC04
Inverter (NOT)
HD74LVC14
Schmitt trigger inverter
EPF8282ATC100-3
Key input control (FPGA)
EPF8452ATC100-3
Speech output (FPGA)
EPM7032LC44-6
SCSI control (FPGA)
SYM53CF96-2
SCSI controller
µPD6376GS
DAC
MAX233ACWP
RS-232C controller
LTI086CT-3.3
DD conversion LSI
LTI086CT-5
DD conversion LSI
21
Table 3.2
Functions of LSIs Mounted on Daughter Board
Mounted LSI
Device Function
HD64411F (Q2)
Quick 2D Graphics Renderer
HM5118165ATT-7
16Mbit-EDO-DRAM
HD153510F50
8bit-3chDAC
HD74LS04FP
Inverter (NOT)
CXA1645
RGB encoder
Daughter board
Personal
computer
RS-232C
interface
Mother board
4 Mbytes
UGM: DRAM
(EDO mode)
SCI
Image
output block
16 Mbits
RGB
encoder
TV
monitor
16 Mbits
CD-ROM
drive
SCSI
controller
CPU
SH7708
Q2
SCSI
control
FPGA
RGB
monitor
DAC
Address bus
Data bus (32-bit)
4 Mbytes
DRAM
(EDO mode)
8 Mbits
SRAM
1 Mbit
1 Mbit
8 Mbits
16 Mbits
8 Mbits
8 Mbits
Key input
FPGA
Speech
output block
DAC
Expansion
connector
Expansion
unit
16 Mbits
8 Mbits
256 kbytes
Speech output
FPGA
8 Mbytes
Flash
memory
Speaker
8 Mbits
8 Mbits
8 Mbits
Key input block
Note: The mother and daughter boards are connected by a board-to-board connector.
Figure 3.1 Hardware Configuration
22
3.2
Operation of Mother Board and Daughter Board
Mother board operations are as follows:
1.
2.
3.
4.
5.
6.
The mother board is controlled by the SH7708.
Controls the Q2 on the daughter board.
Controls the external CD-ROM drive connected via a SCSI interface.
Controls the 16 keys.
Outputs 16-bit stereo speech data.
When a PC is connected to the SCI connector, performs serial data communication with the
PC.
Daughter board operations are as follows:
1. Controls drawing processing and display processing by the Q2.
2. Outputs images to the TV monitor and RGB monitor.
3.3
SH7708 Operating Conditions
(1) Operating Clock: In the NAV-DS4, a 30 MHz crystal oscillator is used for the SH7708’s
external input clock. The clock operating mode is set to mode 0 by external switching of the mode
pins (MD0, MD1, and MD2). The frequency multiplication ratio of the SH7708’s on-chip PLL
circuit is set to ×2, and the internal clock and peripheral clock division ratios are set to ×1 and
×1/2, respectively, in the frequency control register (FRQCR), so that the SH7708’s internal clock
(Iø) is 60 MHz and its peripheral clock (Pø) is 30 MHz. The SH7708 clock operating mode pin
settings and corresponding operations used in the NAV-DS4 are shown in table 3.3, and the
frequency control register (FRQCR) settings and corresponding operations in figure 3.2.
Table 3.3
Clock Operating Mode Pin Settings and Operations
Pin Names
Clock
Input/
Output
Clock
Operating
Mode
MD2 MD1 MD0
Supply
Source/
Output
PLL
Circuit 1 Divider 1 CKI0
On/Off Input
Frequency Internal Clock
Mode 0
EXTAL/
CKIO
ON
0
0
0
PLL
circuit 1
output
EXTAL
Frequency resulting
from applying PLL
circuit 1 frequency
multiplication ratio
and divider 1
division ratio to CKI0
23
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
CKO PLL P
STC STC
EN
EN STBY 1
0
3
2
IFC
1
IFC
0
1
0
PFC PFC
1
0
—
—
—
—
—
—
—
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Set
value
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
• CKOEN = 1
• PLLEN = 0
• PSTBY = 0
: Clock is output from CKI0 pin.
: PLL circuit 1 is not used. (As clock operating mode 0 is used, this bit is invalid.)
: PLL standby is not performed. (As clock operating mode 0 is used, this bit is
invalid.)
• STC1, 0 = 01 : PLL circuit 1 frequency multiplication ratio is ×2.
• IFC1, 0 = 00 : Internal clock frequency division ratio is ×1.
• PFC1, 0 = 01 : Peripheral clock frequency division ratio is ×1/2.
Figure 3.2 Frequency Control Register (FRQCR) Settings and Operations
(2) Pin Functions: The SH7708 has a number of multiplex pins. The multiplex pins and pin
functions used by the NAV-DS4 are listed in table 3.4.
24
Table 3.4
Multiplex Pins and Pin Functions
Function
Pin No.
Pin Name
On Reset (in
)
On Recovery after
Reset (in
)
(After elapse of 50 [ns])
5
D23
PORT7
Data bus
Data bus
8
D22
PORT6
Data bus
Data bus
9
D21
PORT5
Data bus
Data bus
10
D20
PORT4
Data bus
Data bus
11
D19
PORT3
Data bus
Data bus
12
D18
PORT2
Data bus
Data bus
13
D17
PORT1
Data bus
Data bus
14
D16
PORT0
Data bus
Data bus
84
MD2
RXD
Operating mode (clock operating Serial data reception and break
mode setting)
state detection
85
MD1
TXD
Operating mode (clock operating Serial data transmission and
mode setting)
break state sending
86
MD0
SCK
Operating mode (clock operating Serial clock input/output and
mode setting)
I/O port
103
MD4
_CE2B
Operating mode (area 0 bus
width setting)
Operating mode (area 0 bus
width setting)
104
MD3
_CE2A
Operating mode (area 0 bus
width setting)
Operating mode (area 0 bus
width setting)
108
_CS6
_CE1B
Chip select 6
Chip select 6
109
_CS5
_CE1A
Chip select 5
Chip select 5
117
_WE3
DQMUU _ICIOWR
Write strobe signal for D31–D24
Write strobe signal for D31–D24
118
_WE2
DQMUL
Write strobe signal for D23–D16
Write strobe signal for D23–D16
119
_CASHH _CAS2H
CAS signal for D31–D24
CAS signal for D31–D24
120
_CASHL _CAS2L
CAS signal for D23–D16
CAS signal for D23–D16
123
_WE1
DQMLU
Write strobe signal for D15–D8
Write strobe signal for D15–D8
124
_WE0
DQMLL
Write strobe signal for D7–D0
Write strobe signal for D7–D0
126
_CASLL
_CAS
CAS signal for D7–D0
CAS signal for D7–D0
129
_RAS
_CE
RAS signal
RAS signal
130
MD5
_RAS2
Operating mode (entire-space
endian setting)
Operating mode (entire-space
endian setting)
_ICIORD
_OE
25
(3) Interrupt Handling: The NAV-DS4 uses IRL interrupts. The key input FPGA has an
interrupt priority encoder function, and inputs levels to pins _IRL3–_IRL0 according to the
_INRQ15–_INRQ0 pin priority levels shown in table 3.5. Figure 3.3 shows the interrupt priority
encoder peripheral block diagram.
Table 3.5
_INRQ15–_INRQ0 Pins and Interrupt Priority Order
Pin
Interrupt Priority
Level
_IRL3
_IRL2
_IRL1
_IRL0
Interrupt Priority
Order
_INRQ15
15
0
0
0
0
High
_INRQ14
14
0
0
0
1
_INRQ13
13
0
0
1
0
_INRQ12
12
0
0
1
1
_INRQ11
11
0
1
0
0
_INRQ10
10
0
1
0
1
_INRQ9
9
0
1
1
0
_INRQ8
8
0
1
1
1
_INRQ7
7
1
0
0
0
_INRQ6
6
1
0
0
1
_INRQ5
5
1
0
1
0
_INRQ4
4
1
0
1
1
_INRQ3
3
1
1
0
0
_INRQ2
2
1
1
0
1
_INRQ1
1
1
1
1
0
26
Low
_INRQ15
Interrupt requests
_INRQ14
Expansion connector
_INRQ13
SCSI
_INRQ10
_INRQ9
_INRQ8
Key input FPGA
_INRQ7
_INRQ6
_IRL3
_IRL2
_IRL1
CPU: SH7708
Speech output FPGA
_INRQ11
Interrupt priority encoder
_INRQ12
Q2 (daughter board)
_IRL0
_INRQ5
SCSI control FPGA
_INRQ4
_INRQ3
_INRQ2
_INRQ1
Figure 3.3 Interrupt Priority Encoder Peripheral Block Diagram
27
(4) Address Map: In the SH7708, the physical address space can be managed as seven separate
areas, numbered 0 to 6, each of up to 64 Mbytes in size. The address map of the NAV-DS4 is
shown in figure 3.4. The function and bus cycle state of each area are set with the bus control
register (BCR1). Bus control register (BCR1) settings and corresponding operations are shown in
figure 3.5.
Data bus width
set value [bits]
H'00000000
Flash memory
8 Mbytes
Area 0
Use
• Programs
• Character fonts
• Monitor program
32
H'007FFFFF
H'03FFFFFF
H'04000000
H'04000041
SCSI
Area 1
16
H'07FFFFFF
H'08000000
H'0803FFFF
32
H'0BFFFFFF
H'0C000000
Area 4
Area 5
32
H'0FFFFFFF
H'10000000
H'103FFFFF
UGM (DRAM)
4 Mbytes
H'11000000
H'110005FF
Q2 1536 bytes
H'13FFFFFF
H'14000000
H'14000007
H'14000013
H'14000023
Terminal address
depends on what
is connected.
• Program work area
• Map data
DRAM
4 Mbytes
H'0C3FFFFF
H'17FFFFFF
H'18000000
Area 6
• Monitor program work area
SRAM 256 kbytes
Area 2
Area 3
• CD-ROM data reading
• Display list
• Source/work area
• Frame buffers
16
• Speech data output
Speech output FPGA
Key input FPGA
32
• Key input control
• Interrupt priority encoder
• Expansion ROM connection
• Speech recognition unit
connection
Expansion connector
32
H'1BFFFFFF
Figure 3.4 NAV-DS4 Address Map
28
• Q2 on-chip registers
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DRAM DRAM DRAM A5
A6
HIZ ENDI A0
A0
A5
A5
A6
A6
CNT AN BST1 BST0 BST1 BST0 BST1 BST0 TP2 TP1 TP0 PCM PCM
—
—
—
Initial
value
0
0
0
0
0/1
0
0
0
0
0
0
0
0
0
0
0
Set
value
0
0
0
0
—
0
0
0
0
0
0
1
0
0
0
0
• HIZCNT = 0
•
•
•
•
•
•
: _RAS and _CAS signals become high-impedance in standby mode and
when bus is released.
A0BST1, 0 = 00
: Area 0 is accessed as ordinary memory.
A5BST1, 0 = 00
: Area 5 is accessed as ordinary memory.
A6BST1, 0 = 00
: Area 6 is accessed as ordinary memory.
DRAMTP2, 1, 0 = 100 : Area 2 is accessed as ordinary memory, and area 3 as DRAM.
A5PCM = 0
: Area 5 is accessed as ordinary memory.
A6PCM = 0
: Area 6 is accessed as ordinary memory.
Figure 3.5 Bus Control Register (BCR1) Settings and Operations
(5) Memory Bus Width and Data Format: The SH7708’s memory bus width is set for each
space. Flash memory is connected to area 0, and mode pins MD3 and MD4 are set by an external
switch to give a 32-bit bus width. The MD5 mode pin is set by an external switch to designate a
big-endian data format. Mode pin settings and the corresponding operations are shown in table
3.6.
The bus width of areas 1 to 6 is set in bus control register 2 (BCR2). Bus control register 2
(BCR2) settings and the corresponding operations are shown in table 3.6. However, the DRAM
interface bus width is set in the individual memory control register (MCR). See (7) below for
details of this register.
Table 3.6
Mode Pin Settings and States
Pin Name
Description
MD5
MD4
MD3
Endian
Area 0 Bus Width
0
1
1
Big
32 bits
29
Bit:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
A6
SZ1
A6
SZ0
A5
SZ1
A5
SZ0
A4
SZ1
A4
SZ0
A3
SZ1
A3
SZ0
A2
SZ1
A2
SZ0
A1
SZ1
A1
SZ0
—
PORT
EN
Initial
value
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
Set
value
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
•
•
•
•
•
•
•
15
A6SZ1, 0 = 11
A5SZ1, 0 = 11
A4SZ1, 0 = 10
A3SZ1, 0 = 11
A2SZ1, 0 = 11
A1SZ1, 0 = 10
PORTEN = 0
:
:
:
:
:
:
:
Area 6 bus width is set to 32 bits.
Area 5 bus width is set to 32 bits.
Area 4 bus width is set to 16 bits.
Area 3 bus width is set to 32 bits.
Area 2 bus width is set to 32 bits.
Area 1 bus width is set to 16 bits.
D23–D16 are not used as port pins.
Figure 3.6 Bus Control Register 2 (BCR2) Settings and Operations
(6) Wait Control: With some peripheral devices, data bus drive is not immediately switched off
when the read signal from the SH7708 is switched off. Therefore, when consecutive accesses that
span a number of areas are performed, or when a switch is made to write access immediately after
read access, for example, there is a possibility of a data collision on the data bus. For this reason,
wait control register 1 (WCR1) is set to provide automatic idle cycle insertion. Wait control
register 1 (WCR1) settings and the corresponding operations are shown in figure 3.7.
Wait state insertion cycle specifications for each area are made in wait control register 2 (WCR2).
The data access pitch specification for burst access is also made in this register. The flash memory
(HN29WB800T-8) connected to area 0, can be accessed in four cycles with two wait states
inserted. Wait control register 2 (WCR2) settings and the corresponding operations are shown in
figure 3.8.
30
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
A6
IW1
A6
IW0
A5
IW1
A5
IW0
A4
IW1
A4
IW0
A3
IW1
A3
IW0
A2
IW1
A2
IW0
A1
IW1
A1
IW0
A0
IW1
A0
IW0
Initial
value
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Set
value
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
When switching from one area to another, or when switching from read access to write access in
the same area
•
•
•
•
•
•
•
A6IW1, 0 = 01
A5IW1, 0 = 01
A4IW1, 0 = 01
A3IW1, 0 = 01
A2IW1, 0 = 01
A1IW1, 0 = 01
A0IW1, 0 = 01
:
:
:
:
:
:
:
For area 6, one idle cycle is inserted.
For area 5, one idle cycle is inserted.
For area 4, one idle cycle is inserted.
For area 3, one idle cycle is inserted.
For area 2, one idle cycle is inserted.
For area 1, one idle cycle is inserted.
For area 0, one idle cycle is inserted.
Figure 3.7 Wait Control Register 1 (WCR1) Settings and Operations
Bit:
15
14
13
12
11
10
9
8
7
6
5
A6
W2
A6
W1
A6
W0
A5
W2
A5
W1
A5
W0
A4
W2
A4
W1
A4
W0
A3
W1
A3
W0
Initial
value
1
1
1
1
1
1
1
1
1
1
1
1
1
Set
value
1
1
1
0
0
1
1
0
0
0
0
0
1
•
•
•
•
•
•
A6W2, 1, 0 = 111
A5W2, 1, 0 = 001
A4W2, 1, 0 = 100
A3W1, 0 = 00
A1–2W1, 0 = 01
A0W2, 1, 0 = 010
:
:
:
:
:
:
4
3
2
1
0
A0
W1
A0
W0
1
1
1
0
1
0
A1–2 A1–2 A0
W1 W0
W2
Number of wait states inserted for area 6 = 10
Number of wait states inserted for area 5 = 1
Number of wait states inserted for area 4 = 4
DRAM _CAS assertion width = 1 state
Number of wait states inserted for areas 1 and 2 = 1
Number of wait states inserted for area 0 = 2
Figure 3.8 Wait Control Register 2 (WCR2) Settings and Operations
31
(7) Memory Control: In the NAV-DS4, EDO mode 16-Mbit DRAM (HM51W18165AJ-6) is
connected to area 3. DRAM access in EDO mode requires a maximum of six cycles, with Tr and
Trw cycles inserted, and a minimum of two cycles when consecutive addresses are accessed
(using burst access). CAS-before-RAS refreshing is used. The _RAS and _CAS timing, burst
control, address multiplex specifications, and refresh control specifications are made in the
individual memory control register (MCR). Individual memory control register (MCR) settings
and the corresponding operations are shown in table 3.9.
The refresh period, presence or absence of interrupt generation, and the interrupt generation
period, are specified in the refresh timer control/status register (RTCSR). The upper limit of the
refresh timer counter (RTCNT) is set in the refresh timer constant register (RCTOR). Refresh
timer control/status register (RTCSR) settings and the corresponding operations are shown in
figure 3.10, and refresh timer constant register (RCTOR) settings and operations in figure 3.11.
Bit:
15
14
13
12
11
10
9
8
TCP1 TCP0 RCD1 RCD0 TRWL TRWL TRAS TRAS
1
0
1
0
7
—
6
BE
5
4
3
2
1
0
SZ AMX1 AMX0 RFSH RMO EDO
DE
MODE
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Set
value
0
1
0
1
0
0
0
1
0
1
1
1
0
1
0
1
Settings when DRAM is connected to area 3
•
•
•
•
•
•
•
•
•
•
TPC1, 0 = 01
RCD1, 0 = 01
TRWL1, 0 = 00
TRAS1, 0 = 01
BE =1
SZ = 1
AMX1, 0 = 10
RFSH = 1
RMODE = 0
EDOMODE = 1
:
:
:
:
:
:
:
:
:
:
Minimum number of cycles until _RAS is next asserted after being negated = 2
_RAS–_CAS assertion delay time = 2 cycles
Not set
_RAS assertion period in _CAS-before-_RAS refreshing = 3 cycles
Burst access is performed
Bus size is 32 bits.
Address multiplex setting = 10-bit column address product used
Refresh control specification = refresh performed
_CAS-before-_RAS refreshing is performed.
Set to EDO mode. (Data sampling timing for read cycle is CKI0 rise.
_RAS signal negation timing is 1/2 machine cycle after CKI0.)
Figure 3.9 Individual Memory Control Register (MCR) Settings and Operations
32
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Set
value
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS
• CMF = 0
•
•
•
•
•
: Status flag indicating that the refresh timer counter (RTCNT) and refresh time
constant register (RTCOR) values match.
CMIE = 0
: Interrupt requests by CMF are disabled.
CKS2, 1, 0 = 001 : Selects refresh timer counter (RTCNT) input clock. (CKI0/4)
OVF = 0
: Status flag indicating that the number of refresh requests indicated in the
refresh count register (RFCR) has exceeded the number indicated by LMTS.
OVIE = 0
: Interrupt requests by OVF are disabled.
LMTS = 0
: Count limit value compared with the number of refresh requests indicated in
the refresh count register (RFCR) (the count limit value is set to 1024).
Figure 3.10 Refresh Timer Control/Status Register (RTCSR) Settings and Operations
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Set
value
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
• Sets the upper limit of the RTCNT counter. (Lower 8 bits)
• Calculation formula:
RTCNT value =
=
DRAM refresh period [s]
refresh timer counter (RTCNT) period [s]
16 × 10–3 [s]
1024 [cycles]
1
(CKI0/4) [cycles]
=
30 × 106
16 × 10–3
×
= 117.1875 ≈ H'75
1024
4
Figure 3.11 Refresh Time Constant Register (RTCOR) Setting and Calculation Formula
33
(8) Cache Memory: The SH7708 has on-chip cache memory. Use of 8-kbyte cache (normal
mode) or 4-kbyte cache and 4-kbyte RAM (RAM mode) can be selected. A mixed
instructions/data type 4-way set-associative configuration (normal mode) or 2-way set-associative
configuration (RAM mode) can be selected. With the NAV-DS4, normal mode, using 8-kbyte
cache memory, is set. The operating mode is set in the cache control register (CCR). Cache control
register (CCR) settings and the corresponding operations are shown in table 3.12.
Bit:
31
5
4
3
2
1
0
—
—
RA
0
CF
—
WT
CE
Initial
value
0
0
0
0
0
0
0
0
Set
value
0
0
0
0
1
0
0
1
•
•
•
•
RA = 0
CF = 1
WT = 0
CE = 1
:
:
:
:
Normal mode (8-kbyte cache)
V, U, and LRU bits of all cache entries are cleared to 0.
Write-back mode
Cache is used.
Figure 3.12 Cache Control Register (CCR) Settings and Operations
34
3.4
Q2 Operating Conditions
(1) Operating Clocks: There are two Q2 clocks, the drawing clock (CLK0) and the display clock
(CLK1). The SH7708’s CKI0 (30 MHz) output is input via a level shifter as the drawing clock
(CLK0). For the clock operating mode, the mode pins (Mode0, Mode1, are Mode2) are set to
mode 3 by means of an external switch. The Q2 clock operating mode pin settings used by the
NAV-DS4, and the corresponding operations, are shown in table 3.3.
The Q2 display clock (CLK1) is provided by a 14.318 MHz crystal oscillator. A display dot clock
of 7.15 MHz (1/2 the CLK1 clock frequency) provided by the Q2’s on-chip frequency divider is
set by means of the Q2’s display mode register (DSMR). See (2) below for details of this register.
Table 3.3
Clock Operating Mode Pin Settings and States
Pin Names
Clock Operating
Mode
MD2
MD1
MD0
Operation
Multiplication
On/Off
Mode 3
0
1
1
Normal
Off
operating state
Internal Clock
Same as external
input clock
(2) Interface Control: Overall Q2 control is performed by settings in a group of registers called
the interface control registers (FRQCR). These registers are as follows:
•
•
•
•
•
•
•
•
System control register (SYSR): Sets Q2 system operation.
Status register (SR): Reads the Q2’s internal status externally (read-only).
Status register clear register (SRCR): Clears the corresponding status register contents.
Interrupt enable register (IER): Sets the conditions for interrupt generation from the Q2 to the
CPU.
Memory mode register (MEMR): Sets the size and number of UGM memories.
Display mode register (DSMR): Settings related to Q2 display operations.
Rendering mode register (REMR): Settings related to Q2 drawing operations.
Input data conversion mode register (IEMR): Settings related to format conversion of input
data from the CPU.
Interface control register (FRQCR) settings used by the NAV-DS4, and the corresponding
operations, are shown in figures 3.13 to 3.18.
35
Bit:
15
14
13
SRES DRES DEN
Set
value
0
0
• SRES = 0
• DRES = 0
DEN = 1
• DC = 0
=1
• RS = 0
=1
• DBM = 01
= 10
• DMA = 00
• CCM = 0000
1
12
11
10
9
8
—
—
—
DC
RS
0
0
0
7
6
5
DBM
4
3
2
DMA
0 or 1 0 or 1 0 or 1 1 or 0
0
1
0
CCM
0
0
0
0
0
: Command execution is enabled.
: Display synchronization operation is started. The values stored in the UGM are
output from the DD pin as display data.
: Display frame buffer switching is not performed in manual display change mode.
: Display frame buffer switching is performed in manual display change mode.
: Rendering is not started.
: Rendering is started.
: Auto rendering mode is set.
: Manual display change mode is set.
: Normal mode is set.
: Normal mode is set.
Note: The values of DC, RS, and DBM are changed according to the processing executed.
Figure 3.13 System Control Register (SYSR) Settings and Operations
Bit:
15
14
13
12
11
10
9
TVE FRE DME CEE VBE TRE CSE
Set
value
•
•
•
•
•
0
TVE = 0
FRE = 0
DME = 0
CEE = 0
VBE = 0
=1
• TRE = 0
• CSE = 0
0
0
:
:
:
:
:
:
:
:
0
0 or 1
0
0
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
TV synchronization error flag interrupt is not enabled.
Frame flag interrupt is not enabled.
DMA flag interrupt is not enabled.
Command error flag interrupt is not enabled.
Vertical blanking flag interrupt is not enabled.
Vertical blanking flag interrupt is enabled.
Trap flag interrupt is not enabled.
Command suspend flag interrupt is not enabled.
Note: The value of VBE is changed according to the processing executed.
Figure 3.14 Interrupt Enable Register (IER) Settings and Operations
36
Bit:
Set
value
15
14
13
12
11
10
9
8
7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
• MES = 010
• MEA = 01
6
5
4
3
MES
0
2
MEA
1
1
0
1
0
—
—
0
0
1
0
0
1
1
: Two 16-Mbit DRAMs are used for the UGM.
: Number of row address bits = 10
Figure 3.15 Memory Mode Register (MEMR) Settings and Operations
Bit:
Set
value
15
14
13
12
11
10
—
—
—
—
—
—
0
0
0
0
0
0
9
8
7
1
5
TVM
YCM DOT
0
6
0
4
3
2
SCM
0
0 or 1
REF
0
0
1
• YCM = 0
• DOT = 1
: RGB/YCrCb conversion is not performed.
: 1/2 the frequency of the clock input from the CLK1 pin is used as the display dot
clock.
• TVM = 0
: Sets master mode in which HSYNC, VSYNC, and ODDF are output.
• SCM = 00
: Display output is set to non-interlace.
= 10
: Interlace sync set for video monitor output.
• REF = 0101 : Refresh timing set to 5 cycles.
Note: The value of SCM is changed according to the processing executed.
Figure 3.16 Display Mode Register (DSMR) Settings and Operations
Bit:
Set
value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
MWX
—
—
—
—
—
GBM
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0 or 1
• MWX = 1
• GBM = 0
=1
: The UGM X-direction logical coordinate space is set to 1024 pixels.
: Rendering data bit configuration is set to 8 bits/pixel (in map data processing).
: Rendering data bit configuration is set to 16 bits/pixel (in natural image data
processing).
Note: The value of GBM is changed according to the processing executed.
Figure 3.17 Rendering Mode Register (REMR) Settings and Operations
37
Bit:
Set
value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• YUV = 00
= 10
1
0
YUV
0 or 1
0
: Sets normal mode in which data conversion is not performed.
: Sets mode in which ∆YUV–RGB data conversion is performed.
(In ∆YUV data processing)
Note: The value of YUV is changed according to the processing executed.
Figure 3.18 Input Data Conversion Mode Register (IEMR) Settings and Operations
(3) Memory Control: The Q2 uses a UGM (unified graphics memory) architecture, in which data
of different formats (such as frame buffer area data and font pattern area data) is stored and
managed in the same memory. The configuration of the UGM connected to the Q2 is determined
by settings in a group of registers called the memory control registers (MECR). These registers are
as follows:
•
•
•
•
•
•
Display size register (DSR): Sets the display screen size.
Display start address register (DSAR): Sets the frame buffer area.
Display list start address register (DLSAR): Sets the display list area.
Multi-valued source area start address register (SSAR): Sets the multi-valued source area.
Work area start address register (WSAR): Sets the work area.
DMA transfer start address register (DMASR): Sets the transfer destination UGM address in
DMA transfer.
• DMA transfer word count register (DMAWR): Sets the number of words to be transferred in
DMA transfer.
Since DMA transfer is not used by the NAV-DS4, no DMA transfer start address register
(DMASR) or DMA transfer word count register (DMAWR) settings are made. Memory control
register (MECR) settings, and the corresponding operations, are shown in figures 3.19 to 3.23.
UGM memory maps are shown in figure 3.24, and 3.25.
38
Bit:
Set
value
Bit:
Set
value
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
—
—
0
0
0
0
0
0
0
5
4
3
2
1
0
1
1
1
1
1
1
5
4
3
2
1
0
1
1
1
1
DSX
DSY
0
1
1
1
0
• DSX = 0100111111 : The number of display screen dots in the horizontal direction (X direction)
is set to 320.
• DSY = 011101111 : The number of display screen dots in the vertical direction (Y direction) is
set to 240.
Figure 3.19 Display Size Register (DSR) Settings and Operations
Bit:
Set
value
Bit:
Set
value
15
14
13
12
11
10
9
8
7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
• DSA0 = 0000000
• DSA1 = 0000100
6
5
4
3
2
1
0
0
0
0
0
3
2
1
0
1
0
0
DSA0
DSA1
0
0
0
0
: The frame buffer 0 start address is set to UGM address 0h.
: The frame buffer 1 start address is set to UGM address 40000h
(in 8-bit/pixel mode).
Note: The values of the frame buffer 0 and 1 start addresses are changed according to the
processing executed.
Figure 3.20 Display Start Address Register (DSAR) Settings and Operations
39
Bit:
Set
value
Bit:
15
14
13
12
11
10
9
8
7
6
5
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
0
3
2
1
0
1
0
0
1
4
3
2
1
0
—
—
—
—
—
0
0
0
0
0
DLSAH
DLSAL
Set
value
4
0
0
• DLSAH = 0001001
: Bits A22 to A16 of the display list start address.
• DLSAL = 00000000000 : Bits A15 to A5 of the display list start address.
The display list start address is set to UGM address 90000h
(in initialization).
Note: The value of the display list start address is changed according to the processing executed.
Figure 3.21 Display List Start Address Register (DLSAR) Settings and Operations
Bit:
Set
value
15
14
13
12
11
10
9
8
7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
SSAH
0
0
1
0
0
—
0
0
0
• SSAH = 001000 : The multi-valued source area start address is set to UGM address 100000h
(in 8-bit/pixel data processing).
= 000000 : The multi-valued source area start address is set to UGM address 0h
(in natural image data processing).
Note: The value of SSAH is changed according to the processing executed.
Figure 3.22 Multi-Valued Source Area Start Address Register (SSAR) Settings and
Operations
Bit:
Set
value
15
14
13
12
11
10
9
8
7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
WSAH
0
0
0
1
• WSAH = 0001000 : The work area start address is set to UGM address 80000h (in 8-bit/pixel
data processing).
= 0011000 : The work area start address is set to UGM address 180000h (in natural
image data processing).
Note: The value of WSAH is changed according to the processing executed.
Figure 3.23 Work Area Start Address Register (WSAR) Settings and Operations
40
8 bits/pixel, screen size = 320 × 240, 16-Mbit memory × 1
319
1023
H'00000
F0
H'40000
240
256
Binary source
F1
H'80000
H'90000
H'100000
496
512,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Work
576,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Display list
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
1024,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
0
319
639
959
1
1264
239
5
6
479
Multi-valued
source
7
1744
3
Buffer area
4
1504
2
8
9
719
2047
Figure 3.24 UGM Memory Map (8-Bit/Pixel Mode)
41
16 bits/pixel, screen size = 320 × 240, 16-Mbit memory × 1
319
679
1023
H'00000
H'80000
F0
∆YUV data
expansion area 1
F1
∆YUV data
expansion area 2
240
256
Multi-valued
source
496
512
752
768,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Work
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
784,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Display list
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Binary source
H'1FFFFE 1023,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
H'180000
H'188000
Figure 3.25 UGM Memory Map (16-Bit/Pixel Mode)
(4) Display Control: The Q2 performs double-buffering control that switches alternately between
the display area and drawing area located in the UGM, making it possible to alternate between
high-speed drawing processing and display processing. Q2-controlled display timing settings are
made in a group of registers called the display control registers (DSCR). These registers are as
follows:
• Display window register (DSWR): Sets display screen horizontal and vertical output timing.
• Horizontal synchronization pulse width register (HSWR): Sets the low-level pulse width of the
horizontal sync signal.
• Horizontal scan cycle register (HCR): Sets the horizontal scan cycle.
• Vertical synchronization position register (VSPR): Sets the start position of the vertical sync
signal.
• Vertical scan cycle register (VCR): Sets the vertical scan cycle.
• Display off output register (DOOR): Sets the display data to be output when the display is off.
• Color detection register (CDER): Detects display color data.
Display control register (DSCR) settings used by the NAV-DS4, and the corresponding
operations, are shown in figures 3.26 to 3.31.
42
Bit:
Set
value
Bit:
Set
value
Bit:
Set
value
Bit:
Set
value
•
•
•
•
15
14
13
12
11
10
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
HDS = 0001011110
HDE = 0110011110
VDS = 0000010000
VDE = 0100000000
:
:
:
:
9
8
7
6
5
4
3
2
1
0
0
1
1
1
1
0
5
4
3
2
1
0
0
1
1
1
1
0
5
4
3
2
1
0
0
1
0
0
0
0
5
4
3
2
1
0
0
0
0
0
0
2
1
0
1
1
1
HDS
HDE
VDS
VDE
0
1
0
0
0
The horizontal display start position is set to 5eh.
The horizontal display end position is set to 19eh.
The vertical display start position is set to 10h.
The vertical display end position is set to 100h.
Note: HDS and HDE are set in dot clock units, and VDS and VDE in raster line units.
Figure 3.26 Display Window Register (DSWR) Settings and Operations
Bit:
Set
value
15
14
13
12
11
10
9
8
7
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
6
5
4
3
HSW
0
0
1
1
• HSW = 0011111 : The low-level pulse width of the horizontal sync signal is set to 1fh.
Note: HSW is set in dot clock units.
Figure 3.27 Horizontal Synchronization Pulse Width Register (HSWR) Settings and
Operations
43
Bit:
Set
value
15
14
13
12
11
—
—
—
—
—
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
0
HC
0
0
1
1
1
0
• HC = 111000110 : One horizontal scan cycle, including the horizontal retrace line interval, is set
to 1c6h.
Note: HC is set in dot clock units.
Figure 3.28 Horizontal Scan Cycle Register (HCR) Settings and Operations
Bit:
Set
value
15
14
13
12
11
10
—
—
—
—
—
—
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
VSP
0
1
0
0
0
• VSP = 0100000011: The start position of the vertical sync signal is set to 103h.
Note: VSP is set in dot clock units.
Figure 3.29 Vertical Synchronization Position Register (VSPR) Settings and Operations
Bit:
Set
value
15
14
13
12
11
10
—
—
—
—
—
—
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
1
1
0
VC
0
1
0
0
0
• VC = 100000110 : One vertical scan cycle, including the vertical retrace line interval, is set to
106h.
Note: VC is set in raster line units.
Figure 3.30 Vertical Scan Cycle Register (VCR) Settings and Operations
44
Bit:
Set
value
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
—
—
0
0
DOG
Set
value
0
0
• DOR = 000000
• DOG = 000000
• DOB = 011111
0
0
0
0
7
6
5
4
3
2
1
0
—
—
0
0
0
2
1
0
—
—
0
0
DOR
DOB
0
1
1
1
1
1
: The R component of the data output in the display-off state is set to 0h.
: The G component of the data output in the display-off state is set to 0h.
: The B component of the data output in the display-off state is set to 1fh.
Figure 3.31 Display Off Output Register (DOOR) Settings and Operations
(5) Input Data Control: The NAV-DS4 uses the ∆YUV–RGB data conversion function of the
Q2 to implement high-speed natural image drawing. To control ∆YUV data conversion by the Q2,
settings are made in a group of registers called the input data control registers (IDCR). These
registers are as follows:
• Image data transfer start address register (ISAR): Sets the transfer destination address for
image data transfer.
• Image data size register (IDSR): Sets the image data size.
• Image data entry register (HCR): Used to input the image data to be converted,
Input data control register (IDCR) settings used by the NAV-DS4, and the corresponding
operations, are shown in figures 3.32 to 3.34.
45
Bit:
Set
value
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
3
2
1
0
ISAH
ISAL
Set
value
0
0
1
0
1
0
0
0
—
0
0
0
0
0
0
0
0
• ISAH = 0000000
: Image data transfer destination physical address bits A22 to A16
are set to 0h.
• ISAL = 001010000000000 : Image data transfer destination physical address bits A15 to A0
are set to 2800h.
Note: The values of ISAH and ISAL are changed according to the processing executed.
Figure 3.32 Image Data Transfer Start Address Register (ISAR) Settings and Operations
Bit:
Set
value
Bit:
Set
value
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
0
0
0
0
0
0
0
1
0
1
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
5
4
3
2
1
0
1
0
1
0
0
0
5
4
3
2
1
0
0
0
0
0
0
1
0
IDSX
IDSY
1
0
0
1
0
• IDSX = 00101101000 : The image data X-direction size is set to 360 dots.
• IDSY = 1001000000 : The image data Y-direction size is set to 240 dots.
Note: IDSX and IDSY are set in pixel units.
Figure 3.33 Image Data Size Register (IDSR) Settings and Operations
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
IDE
Set
value
• IDE : Used to input image data.
Figure 3.34 Image Data Entry Register (IDER) Setting and Operation
46
(6) Color Palette: The NAV-DS4 uses the Q2’s on-chip color palette for map drawing in 8bit/pixel mode, enabling simultaneous display of 256 colors out of a total of 260,000. Color palette
settings are made using a group of 256 registers called color palette registers (CP000–CP255).
Colors are set using 6 bits for each of R, G, and B. Color palette register values are cleared when
drawing is performed after changing from 8-bit/pixel mode to 16-bit/pixel mode, so the settings
must be made again when returning to 8-bit/pixel mode. Color palette register (CP000–CP255)
settings used by the NAV-DS4 are shown in figure 3.35.
Bit:
Set
value
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
—
—
G000
Set
value
Bit:
Set
value
Bit:
6
5
4
3
2
1
0
—
—
0
0
0
2
1
0
—
—
R000
B000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
0
0
0
0
G255
Set
value
7
0
0
0
0
0
0
R255
B255
0
0
0
0
0
0
Note: Due to space limitations, it is not possible to show all the color palette set values.
Figure 3.35 Color Palette Register (CP000–CP255) Settings
47
3.5
Interfaces between SH7708 and Peripherals
(1) Interface to 5 V Operation Units: The NAV-DS4 includes both 5 V and 3.3 V operation
units. As the SH7708 operates at 3.3 V, it is connected directly to the 3.3 V operation units, but is
connected to the 5 V operation units via a level shifter. A decoder using TLL circuitry is provided
to prevent signal contact between the 3.3 V and 5 V operation units (bidirectional bus only).
Figure 3.36 shows a block diagram of the interface between the SH7708 and the 5 V operation
units.
3.3 V
Output bus
A
Input bus
Y
_1G and _2G are fixed at
GND so that the 5 V units
can be accessed at all times
(access is always enabled).
Bidirectional bus
_1G
_2G
B
RD/_WR
T/_R
_CS6
_CS5
_CS1
_OE
VccB
_G
B0
Y
A
3.3 V
Vcc
A
3.3 V
Vcc
Decoder
Figure 3.36 Block Diagram of Interface to 5 V Operation Units
48
5 V units
A0
Unidirectional level shifter:
HD74LVC244A
CPU: SH7708
CKIO
Bidirectional level shifter:
HD74LVC245A
VccA
DiR
Level shifter:
HD151015
5V
_CE
_OE
_CE
_CE
_FLAOE0
_FLAOE1
(A2:21)
(D0:7)
Flash memory:
HN29WB800T-8
(A2:21)
_CE
A-1:18
I/O 0:7
_CE
(D24:31)
(D0:7)
(LH-1)
(LH-0)
A-1:18
I/O 0:7
_OE
_OE
Address bus
A22, A23 _RD
(D8:15)
(A2:21)
(D8:15)
Flash memory:
HN29WB800T-8
(A2:21)
_CE
A-1:18
I/O 0:7
Flash memory:
HN29WB800T-8
(HL-1)
(HL-0)
A-1:18
I/O 0:7
_OE
_OE
CSO
(D16:23)
A-1:18
I/O 0:7
Flash memory:
HN29WB800T-8
(A2:21)
(HH-1)
(D16:23)
Flash memory:
HN29WB800T-8
(A2:21)
CPU: SH7708
_CE
I/O 0:7
_OE
(HH-0)
A-1:18
Flash memory:
HN29WB800T-8
(A2:21)
A-1:18
I/O 0:7
Flash memory:
HN29WB800T-8
_CE
(D24:31)
A-1:18
Flash memory:
HN29WB800T-8
Data bus
D0:31
Address bus
A2:21
(A2:21)
(2) Flash Memory Interface: The NAV-DS4 is equipped with 8 Mbytes of flash memory
(HN29WB800T-8), used in byte mode, to hold programs and character fonts. Figure 3.37 shows a
block diagram of the interface between the SH7708 and the flash memory. A TTL decoder is
provided to allow separate access to the upper 4 Mbytes and lower 4 Mbytes of the 8-Mbyte
memory. Figure 3.38 shows a logic diagram of the flash memory decoder, and table 3.8 gives the
corresponding truth table.
I/O 0:7
_OE
_OE
(LL-0)
(LL-1)
Decoder
Figure 3.37 Block Diagram of Flash Memory Interface
49
CPU: SH7708
_RD
A23
_FLAOE0
Flash memory:
HN29WB800T-8
_FLAOE0
Flash memory:
HN29WB800T-8
_FLAOE0
Flash memory:
HN29WB800T-8
_FLAOE0
Flash memory:
HN29WB800T-8
Addresses
_FLAOE1
Flash memory:
HN29WB800T-8
_FLAOE1
Flash memory:
HN29WB800T-8
_FLAOE1
Flash memory:
HN29WB800T-8
_FLAOE1
Flash memory:
HN29WB800T-8
A22
Decoder
H'00000000 to
H'003FFFFF
Addresses H'00400000 to
H'007FFFFF
Figure 3.38 Flash Memory Decoder Logic Diagram
Table 3.8
Flash Memory Decoder Truth Table
Input
50
Output
_RD
A23
A22
_FLAOE0 _FLOE1
L
L
L
L
H
← Address H'00000000–H'003FFFFF selection
L
L
H
H
L
←Address H'00400000–H'007FFFFF selection
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
(3) DRAM Interface: The NAV-DS4 is equipped with two EDO mode 16-Mbit DRAMs
(HM51W18165AJ-6), giving a total of 4 Mbytes, for use as working memory, used with a 32-bit
bus width. CAS-before-RAS mode is used for refreshing. Figure 3.39 shows a block diagram of
the interface between the SH7708 and the DRAMs.
Data bus
D0:31
_WE
RD/_WR
_CASHH
_UCAS
_LCAS
_OE
I/O 0:15
A0:9
_RAS
_WE
_CASLH
_CASLL
_UCAS
_LCAS
_OE
(D16: 15)
(A2:11)
CPU: SH7708
_CASHL
I/O 0:15
(D16: 31)
_RAS
_RAS
DRAM: HM51W18165AJ-6
A0:9
DRAM: HM51W18165AJ-6
(A2:11)
Address bus
A2:11
Figure 3.39 Block Diagram of EDO-DRAM Interface
51
(4) SRAM Interface: The NAV-DS4 is equipped with two 1-Mbit SRAMs (HM67W1664JP-12),
giving a total of 256 kbytes, for use as working memory, used with a 32-bit bus width. Figure 3.40
shows a block diagram of the interface between the SH7708 and the SRAMs.
Data bus
D0:31
_CS
_RD
RD/_WR
_OE
_WE
_UB
_LB
_WE2
I/O 9:16
I/O 1:8
_OE
_WE
_UB
_WE1
_LB
_WE0
Note: The area inside the dotted line is TTL circuitry.
Figure 3.40 Block Diagram of SRAM Interface
52
(D8:15)
_CS
I/O 9:16
(D0:7)
A0:15
SRAM: HM67W1664JP-12
(A2:17)
CPU: SH7708
_WE3
(D24:31)
_CS2
(D16:23)
A0:15
SRAM: HM67W1664JP-12
(A2:17)
Address bus
A2:17
I/O 1:8
(5) Q2-UGM Interface: The NAV-DS4 has a Q2 (HD64411F) and two EDO mode 16-Mbit
DRAMs (HM5118165ATT-7) (4 Mbytes), used as the UGM, mounted on its daughter board. A 30
MHz clock is supplied from the SH7708 on the mother board as the drawing clock (CLK0).
Accesses from the SH7708 to the Q2 are of two kinds: UGM accesses and accesses to the Q2’s
on-chip registers. The decoder for access selection consists of TTL circuitry. Figure 3.41 shows a
logic diagram of the UGM/Q2 on-chip register selection decoder, and table 3.9 gives the
corresponding truth table. As UGM access is performed by CPU transfer, and does not use the
DMA controller, the Q2’s _DACK pin is fixed high and the _DREQ pin is left open. Figure 3.42
shows a block diagram of the Q2 peripheral interface.
_CS4
A24
_CS1
Q2: HD64411F
CPU: SH7708
_CS0
Decoder
Figure 3.41 UGM/Q2 On-Chip Register Selection Decoder Logic Diagram
Table 3.9
UGM/Q2 On-Chip Register Selection Decoder Truth Table
Input
Output
_CS4
A24
_CS0
_CS1
L
L
L
H
← UGM selection
L
H
H
L
←Q2 on-chip register selection
H
L
H
H
H
H
H
H
53
A1:22
D0:15
A1:22
D0:15
_CS4
A24
_CS0
_CS1
DISP
CDE
ODDF
_HSYNC/_EXHSYNC
_VSYNC/_EXVSYNC
_RD
_CSYNC
_WE0
DD0:17
_WE1
FCLK
DCLK
Decoder
*1
_RD
_WE0
_WE1
3.3 V
_DACK
_DREQ
Open
Display unit
MD0:15
MA0:11
A0:9,
NC6:7
_MWE
Pull-up resistor
10 kΩ
MODE0
MODE1
H
H
L
Open
CKIO
MODE2
TEST
Level 30 MHz
CLK0
shifter
Crystal
oscillator
Q2: HD64411F
CPU: SH7708
5V
_WE
_MUCAS
_UCAS
_MLCAS
_LCAS
_MOE
_MRAS0
_OE
_RAS
470 pF
D0:15
CAP0
A0:9,
NC6:7
Interrupt
priority
encoder
_WE
_IRL
_UCAS
_LCAS
_RESET
_RESET
3.3 V
_OE
CPUVcc
5V
RESET
switch
D0:15
CLK1
14.31818 MHz
_IRL0
_IRL1
_IRL2
_IRL3
DRAM: HM5118165ATT-7
*2
DRAM: HM5118165ATT-7
_WAIT
_WAIT
Vcc
_MRAS1
_RAS
PLLVcc
CPUGND
GND
PLLGND
Notes: 1. UGM/Q2 on-chip register selection decoder
2. Wait signal from expansion connector
Figure 3.42 Block Diagram of Q2 Peripheral Interface
54
UGM
(6) Q2-display Unit Interface: An 8-bit 3-channel DAC (HD153510F50) and an RGB/video
encoder (CXA1645) are mounted on the daughter board, and connected to the Q2, as the display
unit. The display unit generates analog RGB signals and NTSC video signals from the 18-bit
output from Q2 pins DD0 to DD17. Control of the resolution, the horizontal and vertical sync
signals, etc., is performed by the Q2. A 14.318 MHz signal is supplied from the crystal oscillator
on the daughter board as the display clock (CLK1). Figure 3.42 shows a block diagram of the
display unit.
RGB
output
_HSYNC/_EXHSYNC
_VSYNC/_EXVSYNC
A Vcc
R_IN
G_IN
_CSYNC
SYNC_IN
SC_IN
FCLK
GND
R_OUT
TV monitor
G_OUT
B_OUT
CV_OUT
Video output
YTRAP
C2; 33 pF
DD0:17
CLK1
DA2:7
DB2:7
DC2:7
DISP
_BLANK
DCLK
DOTCK
8-bit DAC: FHD153510F50
Q2: HD64411F
B_IN
RGB encoder: CXA1645M
C1; 0.1 µF
IOA
IOB
IOC
Crystal oscillator
14.31818 MHz
• Connect C1 (0.1 µF) and C2 (33 PF) between AVcc and GND and to the YTRAP pin. If C1 and
C2 are not provided, color drift may occur in NTSC display images.
• With NTSC video output, set bit 5 = 1 and bit 4 = 0 (interlace sync mode) as the scan mode
(SCM) setting in the Q2 display mode register (DSMR).
Figure 3.43 Q2 Display Unit Block Diagram
55
(7) Speech Output: Using the FPGA, the NAV-DS4’s speech output unit converts 32-bit stereo
speech data (16 bits each for left and right channels) transferred from the SH7708 into serial
speech data, which it outputs via a DAC. The devices used are a µPD6376GS (manufactured by
NEC) for the DAC and an EPF8452ATC100-3 for the FPGA. Figure 3.44 shows the speech output
unit peripheral block diagram, and figure 3.45 shows an internal block diagram of the speech
output FPGA.
The main components of the FPGA are a clock generator, an interrupt controller, and a parallel-toserial converter. The clock generator generates clocks LRCK (selected by the status register) and
CLK (7.5 MHz) for output to the DAC, using CLK_SH (30 MHz). The interrupt controller issues
interrupt requests to the SH7708 in synchronization with LRCK. Each time an interrupt is
generated, the SH7708 transfers parallel data to the 32-bit buffer in the FPGA. The transferred
data is converted to serial data by the parallel-to-serial converter in synchronization with CLK.
Then data synthesis is performed, and serial speech data is output to the DAC.
Figure 3.46 and 3.47 show the functions of the speech output FPGA registers. Figure 3.48 shows
the speech output unit timing chart.
D0:31
D0:31
_CS5
_CS5
_RD
_RD
_WE0
_WR
CKIO
_IRL0
_IRL1
_IRL2
_IRL3
_RESET
30 MHz
CLK_SH
Interrupt _INRQ11
_IRL
priority
encoder
_RESET
LRCK
CLK
SI
Digital
circuitry
5V
Analog
circuitry
5V
D.Vdd
A.Vdd
LRCK
CLK
SI
D.GND
DAC:
µPD6376GS
A0, A2:7
Speech output FPGA:
EPF8452ATC100-3
CPU: SH7708
A0:7
A.GND
RESET
switch
Figure 3.44 Speech Output Unit Peripheral Block Diagram
56
Speaker
Board side Off-board
Interrupt
request
signal
_INRQ11
Serial data left/right
identification signal
44.1/22.025
11.025/8.0 kHz
LRCK
Interrupt controller
Clock generator
7.5 MHz CLK
Serial data read
clock
Upper 16-bit
parallel-to-serial
converter
D0:31
32-bit
buffer
Speech data /
FPGA internal
register read/
write data
Data
synthesis
Lower 16-bit
parallel-to-serial
converter
SI
Serial speech
data
Figure 3.45 Speech Output FPGA Internal Block Diagram
Bit
Bit name
Initial value
D31
D30
D29 . . . D2
D1
D0
DR31
DR30
...
DR1
DR0
0
0
...
0
0
The receive register is used to input speech data. It is a write-only register, and _IRL is
cleared after data is written.
Figure 3.46 Receive Register Function
57
Bit
Bit name
D31 . . . D4
D3
D2
D1
D0
Not used
11E
22E
44E
DAE
0
0
0
0
0
Initial value
The status register is used for LRCK signal selection (see table below). DAE is used as
ADPCM_SW.
11E 22E 44E DAE
Set value
Function
0
0
0
0
LRCK signal is not output. (ADPCM_SW: Off)
0
0
0
1
LRCK signal is output at 8 [kHz].
1
0
0
1
LRCK signal is output at 11.025 [kHz].
—
1
0
1
LRCK signal is output at 22.05 [kHz].
—
—
1
1
LRCK signal is output at 44.1 [kHz].
Figure 3.47 Status Register Settings and Functions
30.0 MHz
CLK_SH
APSD_SW
44.1 kHz, 22,05 kHz, 11,05 kHz, or 8.0 kHz
LRCK
_IRL
Transmit data =
16 bits
Transmit data =
16 bits
CLK
7.5 MHz
SI
D31
D16
D15
D0
D31
ADPCM_SW is generated by setting the DAE flag in the status register. LRCK, CLK, and _IRL are
generated using CLK_SH.
Figure 3.48 Speech Output Unit Timing Chart
58
(8) SCSI Interface: The NAV-DS4 reads map data from a an external CD-ROM drive containing
a navigation CD-ROM, and performs drawing and display based on this data. A SCSI interface is
used for the external CD-ROM drive, and CPU transfer is used for data transfer. An SYM53CF962 (manufactured by Symbiosis Logic) is used for the SCSI controller, and an EPM7032LC44-6
(manufactured by Altera) is mounted as the control FPGA. Since the SCSI interface uses littleendian mode, the upper and lower bytes of the device are reversed for connection to the SH7708.
Figure 3.49 shows the SCSI controller peripheral block diagram. A half-pitch 50-pin connector
(female, shielded) is mounted, and single-end connection is used.
CPU data D0:15
15 14 13 12 11 10 9
Board side
7
PAD0:7
DB0:7
A0:3
5
4
3
2
1
0
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
8
0
7
6
5
4
3
2
D0:7
1
Data bus
D0:15
D0:7
Upper and lower data bytes
reversed
D8:15
A1:4
Address bus
A0:25
_RD
Pull-up resistor
10 kΩ
_WR
A0, A2:7
_CS
_DBWR
_DACK
DREQ
Mode0
Mode1
_INT
CLK
_CS
DWE
_DACK
DREQ
A0,A2:7
SCSI control FPGA:
EPM7032LC44-6
SCSI: SYM53CF96-2
SCSI connector: NHS050-032-BS2
CD-ROM drive
DB8:15
Set to mode 3 DIP switch
6
SCSI data DB0:15
15 14 13 12 11 10 9
5V
7
CPU: SH7708
Off-board
8
_CS1
_CS1
_RD
_RD
_WE0
_WE0
_WE1
_WE1
_INRQ4
Interrupt
priority
encoder
_INRQ10
INT
30 MHz
RESET
_IRL0
_IRL1
_IRL2
_IRL3
CKIO
_RESET
RESET
switch
Figure 3.49 SCSI Controller Peripheral Block Diagram
59
(9) Key Input Interface: The NAV-DS4 is equipped with 16 switches mounted on the mother
board, with an EPF8282ATC100-3 (manufactured by Altera) used as the control FPGA.
Momentary switching is used, in which the on-state is maintained while the switch is pressed. The
FPGA has an interrupt priority encoder function. Figure 3.50 shows the key input FPGA
peripheral block diagram.
5V
Pull-up resistors
10 kΩ × 16
Switch layout
on board
0
1
2
SW0:15
3
4
5
6
7
8
9
10
11
12
13
14
15
SW0
...
AD0:5
SW15
D0:7
Address bus
A0:5
Data bus
D0:7
DIP
switch
...
5V
Pull-up resistors
10 kΩ × 15
RD
_RD
CS5
_CS5
CPU: SH7708
DSW0:7
Key input FPGA: EPF8282ATC100-3
5V
Pull-up resistors
10 kΩ × 8
_INRQ1
..
..
_INRQ15
Interrupt priority encoder
Interrupt requests
...
_IRL3
_IRL2
_IRL1
_IRL0
Figure 3.50 Key Input FPGA Peripheral Block Diagram
60
(10) Serial Communication Interface (SCI): The NAV-DS4 can perform serial data exchange
with a PC using the SH7708’s on-chip SCI. An MAX233ACWP (manufactured by Maxim) is
used as the RS-232C driver. An RS-232C standard D-sub 9-pin (male) connector is used. A DIP
switch allows switching between cross and straight connection. Figure 3.51 shows the SCI
peripheral block diagram.
T1OUT
TxD
DTR
Cross/
straight
switching
5V
RI
T2IN
R2IN
C2+
DSR
CTS
R1IN
Vcc
GND
RTS
T1IN
10 µF
+
–
C2+
C2–
C2–
GND
R1OUT
R2OUT
C1+
C1–
V–
MD1/TXD
MD2/RXD
CPU: SH7708
RxD
T2OUT
SCI
DCD
DIP
switch
RS-232C driver: MAX233
ACWP
SCI connector (RS-232C): 17AE-23090A-9750 (male)
Personal computer SCI interface
Off-board (female) Board (male) side
V–
V+
GND
Figure 3.51 SCI Peripheral Block Diagram
61
(11) Expansion Connectors: The NAV-DS4 is equipped with board-to-board expansion
connectors that provide for functional expansion by means of hardware. The expansion connectors
are intended for connection to 5 V systems, and a level shifter is used between the connected
system and the SH7708. Two HIF7C-80PA-1.27DSAL connectors (80-pin plug type,
manufactured by Hirose) are used, and HIF7C-80DA-1.27DSAL units are required on the
receptacle side. Figure 3.52 shows the expansion connector peripheral block diagram.
Address bus
A0:25
_IRQOUT
CKIO
_BS
RD/_WR
_RD
_CS0
_CS1
_CS2
_CS5
_CS6
_WE3
_WE2
_CASHH
_CASHL
_WE1
_WE0
_CASLH
_CASLL
_RAS
CKE
_RESET
5V
_IRQOUT
CKIO
_BS
RD/_WR
_RD
_CS0
_CS1
_CS2
_CS5
_CS6
_WE3
_WE2
_CASHH
_CASHL
_WE1
_WE0
_CASLH
_CASLL
_RAS
CKE
_RESET
RESET
switch
Data bus
D0:31
Data bus
D0:31
_IOIS16
_IOIS16
_WAIT
_WAIT
_IRL0
_IRL1
_IRL2
_IRL3
Wait signal
from Q2
Interrupt
priority
encoder
_INRQ2
_INRQ7
_INRQ13
5V
Expansion connector B: HIF7C-80PA-1.27DSAL
CPU: SH7708
Address bus
A0:25
Expansion connector A: HIF7C-80PA-1.27DSAL
Board (plug) side Off-board (receptacle)
Figure 3.52 Expansion Connector Peripheral Block Diagram
62
3.6
SH7708 and Peripheral Timing Charts
(1) SH7708 Flash Memory Read Timing
T1
33.3ns
Tw1
33.3ns
Tw2
33.3ns
T2
33.3ns
CKIO
tAD
15ns
A25:0
(c) CPU data
hold time
_CS0
tRSD
14ns
CPU
tRDH1
0ns
tCSD1
14ns
tRDH1
0ns
_RD
tRDS1
12ns
(a) Time until CPU data read setup
D31:0
104.55 ns
tACC
80ns(max)
tCE
80ns(max)
(d) Flash memory
data hold time
tOH
0ns
tOE
40ns(max)
_OE
(_FLAOE)
Flash memory
_CE
Decode circuit delay: 12 ns
I/O
(b) Time until flash memory outputs data
95 [ns] (worst case)
63
In case of 2-wait/4-cycle access to SH7708 flash memory:
1) Data setup time:
(a) Time until CPU data read setup
T1 + Tw1 + Tw2 + (T2/2) – tRDS1 = 33.3 + 33.3 + 33.3 + (33.3/2) – 12 = 104.55 [ns]
(b) Time until flash memory outputs data
Viewed from address: t AD + tACC = 15 + 80 = 95 [ns] ← Worst case
Viewed from _CE: tCSD1 + tCE = 14 + 80 = 94 [ns]
Viewed from _OE: (T1/2) + tRSD + decode circuit delay + t OE = (33.3/2) + 14 + 12 + 40 =
82.65 [ns]
Thus, (b) < (a), and the CPU setup time is satisfied.
2) Data hold time:
(c) CPU data hold time tRDH1 = 0 [ns]
(d) Flash memory data hold time tOH = 0 [ns]
Thus, (d) ≥ (c), and the CPU data hold time is satisfied.
From 1) and 2), 2-wait/4-cycle access is possible.
64
(2) SH7708 SRAM Read Timing
T1
33.3ns
Tw
33.3ns
T2
33.3ns
CKIO
tAD
15ns
A25:0
tCSD1
14ns
tRDH1
0ns
_CS2
(c) CPU data
hold time
CPU
tRWD
14ns
RD/_WR
tRSD
14ns
tRDH1
0ns
_RD
tRDS1
12ns
D31:0
(a) Time until CPU data read setup
71.25ns
tOE 6ns (max)
tACS 12ns (max)
tLB, tUB 6ns(max)
_LB,
_UB
I/O
(d) SRAM data
hold time
TTL circuit
delayviewed
from _RD: 6 ns
(b) Time until SRAM
outputs data
SRAM
tAA 12ns (max)
tOH 3ns
42.65 [ns] (worst case)
65
In case of 1-wait/3-cycle read access to SRAM:
1) Data setup time:
(a) Time until CPU data read setup
T1 + Tw + (T2/2) – tRDS1 = 33.3 + 33.3 + (33.3/2) – 12 = 71.25 [ns]
(b) Time until SRAM outputs data
Viewed from address: t AD + tAA = 15 + 12 = 27 [ns]
Viewed from _CS2: tCSD1 + tACS = 14 + 12 = 26 [ns]
Viewed from _RD: (T1/2) + t RSD + tOE = (33.3/2) + 14 + 6 = 36.65 [ns]
Viewed from _LB, _UB: (T1/2) + tRSD + TTL circuit delay + t LB , tUB = (33.3/2) + 14 + 6 + 6
= 42.65 [ns] ← Worst case
Thus, (b) < (a), and the CPU setup time is satisfied.
2) Data hold time:
(c) CPU data hold time tRDH1 = 0 [ns]
(d) SRAM data hold time (viewed from address) tOH = 3 [ns]
Thus, (d) ≥ (c), and the CPU data hold time is satisfied.
From 1) and 2), 1-wait/3-cycle read access is possible.
66
(3) SH7708 SRAM Write Timing
T1
33.3ns
Tw
33.3ns
T2
33.3ns
CKIO
tAD
15ns
A25:0
tCSD1
14ns
CPU
_CS2
tRWD
14ns
RD/_WR
tWDH3
0ns
tWED
14ns
_WEn
(c) CPU data
hold time
(a) Time until
CPU data
write setup
D31:0
tWDD1
17ns
TTL circuit delay viewed
from _WEn: 6 ns
Delay: 6 ns
SRAM
tLBW,tUBW(min) 9ns
_LB, _UB
tDW 6ns
I/O
(b) Time until SRAM
inputs data
39.65 [ns] (worst case)
tOH 3ns
(d) SRAM data hold time
67
In case of 1-wait/3-cycle write access to SRAM:
1) Data setup time:
(a) Time until CPU data write setup
tWDD1 = 17 [ns]
(b) Time until SRAM inputs data
Viewed from _LB, _UB: (T1/2) + tWED + TTL circuit delay + t LBW, tUBW – tDW = (33.3/2) +
14 + 6 + 9 – 6 = 39.65 [ns] ← Worst case
Thus, (b) > (a), and the CPU setup time is satisfied.
2) Data hold time:
(c) CPU data hold time (viewed from _WEn) tWDH1 = 0 [ns]
(d) SRAM data hold time tDH = 0 [ns]
Thus, (d) ≤ (c), and the CPU data hold time is satisfied.
From 1) and 2), 1-wait/3-cycle write access is possible.
68
(4) SH7708 DRAM Normal Access Read Timing (EDO Mode)
_CAS
Read data
assert cycle latch cycle
Tc1
Tc2
33.3ns
33.3ns
_RAS assert cycle
Tr
Trw
33.3ns
33.3ns
_RAS precharge
interval
(Tpc)
(Tpc)
33.3ns
33.3ns
CKIO
tAD
tAD
15ns
15ns
A25–16
Row address
tAD
tAS
tAD
tAS
tAH
15ns
0ns
15ns
0ns
10ns
A15–0
Row address
tRWD
Column address
tRWH 0ns
tRWD 14ns
tAH
10ns
14ns
RD/_WR
tRASD1
CPU
tRASD2
15ns
15ns
_RAS
tCASD1
tCASD1
15ns
15ns
_CASxx
tRDS2 tRDH2
12ns 6ns
D31–0
(a) Time until CPU data read setup
In case of 2-wait/5-cycle
access to DRAM, (b) ≤ (a),
and the setup time is
satisfied.
Tr + Trw + Tc1 + Tc2 – tRDS2 = 121.2 ns
tRC 104ns
tRAS 60ns
tRP 40ns
_RAS
tCSH 48ns
tRCD 20ns
tRSH 15ns
tCAS 10ns
tRAD 15ns
tASR 0ns
tRAH 10ns
tASC 0ns
tRAL 30ns
tCAL 30ns
tCAH 10ns
DRAM
_UCAS,
_LCAS
A9:0
tCRP 5ns
C
R
tRCHR 60ns
tRCS 0ns
tRCH 0ns
_WE
tCAC 15ns
tAA 30ns
tOHR 3ns
tRAC 60ns
Dout
(b) Time until DRAM outputs data
Viewed from _RAS: Tr / 2 + tRASD1 + tRAC = 91.65 ns
Viewed from _CAS: Tr + Trw + Tc1 / 2 + tCASD1 + tCAC = 113.25 ns ← Worst case
Viewed from address: Tr + Trw + tAD + tAA = 111.6 ns
69
(5) SH7708 DRAM Normal Access Write Timing (EDO Mode)
_RAS assert cycle
Tr
Trw
33.3ns
33.3ns
_CAS
assert cycle
Tc1
33.3ns
Tc2
33.3ns
_RAS precharge
interval
(Tpc)
(Tpc)
33.3ns
33.3ns
CKIO
tAD
tAD
15ns
15ns
A25–16
Row address
tAD
15ns
tAS
0ns
A15–0
tAD
tAS
tAH
10ns
15ns 0ns
Row address
tRWD
Column address
tRWH 0ns
tAH
10ns
14ns
tRWD 14ns
CPU
RD/_WR
tRASD1
tRASD2
15ns
15ns
_RAS
tCASD1
tCASD1
15ns
_CASxx
D31–0
(a) Time until CPU
data write setup
15ns
tWDS
tWDD2 0ns
16ns
tWDH3 0ns
tWDH1 0ns
In case of 2-wait/5-cycle
access to DRAM,
(b) > (a), and the
setup time is satisfied.
Tr + Trw + tWDD2 = 33.3 + 33.3 + 16 = 82.6 ns
tRC 104ns
tRAS 60ns
tRP 40ns
_RAS
tCSH 48ns
tRCD 20ns
tCRP 5ns
tRSH 15ns
tCAS 10ns
tASR 0ns
A9:0
tRAH 10ns
tASC 0ns
tCAH 10ns
C
R
DRAM
_UCAS,
_LCAS
tWCH 10ns
tWCS 0ns
_WE
tDS 0ns tDH 10ns
(b) Time until DRAM inputs data
Dout
Tr + Trw + Tc1 / 2 + tCASD1 – tDS = 33.3 + 33.3 + (33.3/2) + 15 – 0 = 98.25 ns
70
(6) SH7708 DRAM Burst Access Read Timing (EDO Mode)
Burst cycle = 2 cycles
_CAS
Read data
_CAS
Read data
assert cycle latch cycle assert cycle latch cycle
_RAS assert cycle
Tr
33.3ns
Trw
33.3ns
Tc1
33.3ns
Tc2
33.3ns
Tc1
33.3ns
Tc2
33.3ns
_RAS precharge
interval
(Tpc)
33.3ns
(Tpc)
33.3ns
CKIO
tAD
tAD
15ns
15ns
A25–16
Row address
tAD tAS
15ns 0ns
tAD tAS
15ns 0ns
A15–0
Row address
tRWD
tAD
Column address
Column address
tAH
tAH
10ns
14ns
tAH
10ns
15ns
tRWH 0ns
10ns
tRWD 14ns
CPU
RD/_WR
tRASD2
tRASD1
15ns
15ns
_RAS
tCASD1
tCASD1
15ns
15ns
tCASD1
tCASD1
15ns
15ns
_CASxx
tRDS2 tRDH2
tRDS2 tRDH2
12ns 6ns
12ns 6ns
D31–0
tRASP 10000ns(max)
tRP 40ns
_RAS
tCSH 48ns
tCRP 5ns
_UCAS,
_LCAS
tCAL 30ns
tASC 0ns tCAH 10ns
tASR 0ns tRAH 10ns
A9:0
C
R
tCP 10ns
tRAL 30ns
tCAL 30ns
DRAM
tCAS 10ns
tRSH 15ns
tCAS 10ns
tASC 0ns tCAH 10ns
C
tRCH 0ns
tRCS 0ns
_WE
tCAC 15ns
tCAC 15ns
tRAC 60ns
tAA 30ns
tAA 30ns
tCPA 35ns
tOHR 3ns
Dout
71
(7) SH7708 DRAM Burst Access Write Timing (EDO Mode)
_RAS assert cycle
Tr
33.3ns
Burst cycle = 2 cycles
_CAS
assert cycle
_CAS
assert cycle
Trw
33.3ns
Tc1
33.3ns
Tc2
33.3ns
Tc1
33.3ns
Tc2
33.3ns
_RAS precharge
interval
(Tpc)
33.3ns
(Tpc)
33.3ns
CKIO
tAD
tAD
15ns
15ns
A25–16
Row address
tAD tAS
15ns 0ns
tAD tAS
15ns 0ns
A15–0
Row address
tRWD
tAD
Column address
Column address
tAH
tAH
10ns
14ns
tAH
10ns
15ns
tRWH 0ns
tRWD 14ns
10ns
tRASD1
CPU
RD/_WR
tRASD2
15ns
15ns
_RAS
tCASD1
tCASD1
15ns
15ns
_CASxx
tWDS
tWDD2
0ns
tCASD1
tCASD1
15ns
15ns
tWDD2
tWDH3 0ns
tWDH3 0ns
16ns
tWDH1 0ns
16ns
D31–0
tRASP 10000ns
tRP 40ns
_RAS
tCSH 48ns
tRCD 20ns
tRSH 15ns
tCAS 10ns
tCP 10ns
tCAS 5ns
tCRP 5ns
tASR 0ns tRAH 10ns
A9:0
tASC 0ns tCAH 10ns
C
R
tASC 0ns tCAH 10ns
C
tWCH 10ns
tWCS 0ns
_WE
tDS 0ns tDH 10ns
Dout
72
tDS 0ns tDH 10ns
DRAM
_UCAS,
_LCAS
(8) SH7708 Q2 Read Timing
33.3ns
T1
33.3ns
T2
33.3ns
T3
33.3ns
T4
33.3ns
Tw
33.3ns
Tw
33.3ns
T5
33.3ns
T1
33.3ns
33.3ns
CKI0
tAD
tAD
15ns
15ns
A25:0
tCSD1 14ns
tCSD2 14ns
10ns tAH
14ns tRSD
CPU
_CS4
tRSD 14ns
_RD
tRDS1 12ns
D15:0
Decode
circuit delay:
12 ns
_CS1, 0
_RD
tWAD 20ns
Q2
tWAD 20ns
_WAIT
tRDDWS 10ns
tRDDH 4ns
tRDDRS 66.6ns
D15:0
73
(9) SH7708 Q2 Write Timing
33.3ns
T1
33.3ns
T2
33.3ns
T3
33.3ns
T4
33.3ns
Tw
33.3ns
Tw
33.3ns
T5
33.3ns
T1
33.3ns
33.3ns
CKI0
tAD
tAD
15ns
15ns
A25:0
tCSD1 14ns
tCSD2 14ns
10ns tAH
14ns tRSD
CPU
_CS4
tWED 14ns
_WEn
tWDD1
17ns
D15:0
Decode
circuit delay:
12 ns
_CS1, 0
_WEn
tWAD 20ns
Q2
tWAD 20ns
_WAIT
tWRDWS 0ns
tWRDES 66.6ns
D15:0
74
tWRDH 0ns
SH Graphics/Speech Processing Demonstration System
NAV-DS4 Application Note
Publication Date: 1st Edition, January 1998
Published by:
Semiconductor and IC Div.
Hitachi, Ltd.
Edited by:
Technical Documentation Center
Hitachi Microcomputer System Ltd.
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.