ETC HD64F2623

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April 1, 2003
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H8S/2623F-ZTAT™
On-Chip HCAN
(Hitachi Controller Area Network)
Application Note
ADE-502-071
Rev. 1.0
1/28/2000
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
This Application Note gives examples of operation in cases where the H8S Series on-chip HCAN
(Hitachi Controller Area Network) is used.
(The program examples in the text refer to the H8S/2623 on-chip HCAN.)
The operation of programs, circuit examples, and so forth appearing in this Application Note has
been confirmed, but correct operation must be reconfirmed before any of these examples are
actually used.
Rev. 1.0, 1/00, page v of 8
Contents
Section 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Specifications ....................................................................................................................
Functions ..........................................................................................................................
Operation...........................................................................................................................
Software ............................................................................................................................
Transmission Flowchart ....................................................................................................
Transmission Program List................................................................................................
Reception Flowchart..........................................................................................................
Reception Program List.....................................................................................................
Notes..................................................................................................................................
Section 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
1
1
3
4
6
8
9
11
12
14
HCAN Transmission/Reception (Example 2): Standard Format,
8-Byte Data, Using DTC .............................................................................. 21
Specifications ....................................................................................................................
Functions ..........................................................................................................................
Operation...........................................................................................................................
Software ............................................................................................................................
Transmission Flowchart ....................................................................................................
Transmission Program List................................................................................................
Reception Flowcharts ........................................................................................................
Reception Program List.....................................................................................................
Notes..................................................................................................................................
Section 3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
HCAN Transmission/Reception (Example 1): Standard Format,
1-Byte Data.......................................................................................................
21
24
26
28
32
33
35
38
41
HCAN Transmission/Reception (Example 3): Extended Format,
1-Byte Data....................................................................................................... 47
Specifications ....................................................................................................................
Functions ...........................................................................................................................
Operation...........................................................................................................................
Software ............................................................................................................................
Transmission Flowchart ....................................................................................................
Transmission Program List................................................................................................
Reception Flowcharts ........................................................................................................
Reception Program List.....................................................................................................
Notes..................................................................................................................................
47
50
52
54
56
57
59
62
64
Rev. 1.0, 1/00, page vii of 8
Section 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Specifications ....................................................................................................................
Functions ...........................................................................................................................
Operation...........................................................................................................................
Software ............................................................................................................................
Transmission Flowchart ....................................................................................................
Transmission Program List................................................................................................
Reception Flowcharts ........................................................................................................
Reception Program List.....................................................................................................
Notes..................................................................................................................................
Section 5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
HCAN Transmission/Reception (Example 4): Standard Format,
8-Byte Data, Prioritized ................................................................................ 71
71
74
76
78
84
85
91
94
99
HCAN Transmission/Reception (Example 5): Remote Frame ......... 105
Specifications .................................................................................................................... 105
Functions ........................................................................................................................... 107
Operation........................................................................................................................... 108
Software ............................................................................................................................ 110
Transmission Flowchart .................................................................................................... 112
Transmission Program List................................................................................................ 113
Reception Flowchart.......................................................................................................... 115
Reception Program List..................................................................................................... 116
Notes.................................................................................................................................. 118
Rev. 1.0, 1/00, page viii of 8
Section 1 HCAN Transmission/Reception (Example 1):
Standard Format, 1-Byte Data
MCU: H8S/2623F-ZTAT
1.1
Function Used: HCAN
Specifications
1
1. Data frame* transmission/reception (using two H8S/2623F-ZTATs).
Data frame specifications are shown in figure 1.1.
a. SOF: Indicates start of data frame.
2
b. Arbitration field* : Set to 101010101010.
•
RTR = 0: Select data frame
3
c. Control field* : Set to 000001.
•
IDE = 0: Select standard format
•
R0 = 0: Reserved bit
•
DLC = 0001: Set data length of 1 byte
4
d. Data field* : Set to 10101010.
5
e. CRC field* : CRC is generated automatically within the HCAN.
6
f. ACK field* : 11 is output on the transmitting side, and 01 (in normal operation) on the
receiving side.
g. EOF: Indicates the end of a transmit/receive data frame.
2. A communication speed of 250 kbps (when operating at 20 MHz) is set.
3. The data length is set to 1 byte.
4. Message transmission uses mailbox 1.
5. Message reception uses mailbox 0. The message reception method is to mask the identifier and
receive the message in case of a match.
6. Receive data is stored in on-chip RAM.
7. Figure 1.2 shows an example of CAN bus connection.
Note: * See 1.9 Notes.
Rev. 1.0, 1/00, page 1 of 119
Data frame
Arbitration field
Control field
Data field
12 bits
1 bit
6 bits
8 bits
16 bits
2 bits
7 bits
EOF
SOF
ACK field
CRC field
(with CRC delimiter*5)
Identifier
RTR IDE R0
DLC
Note: * See 1.9 Notes.
Figure 1.1 Data Frame Specifications
Transmission side
H8S/2623F-ZTAT
Reception side
H8S/2623F-ZTAT
5V
5V
PCA82C250
NC
5
8
HRxD
HTxD
4
1
Vref
Rs
Vcc
GND
RxD
CANH
TxD
CANL
PCA82C250
3
0.1 µF
2
124 Ω
NC
5
8
7
7
6
6
Vref
Rs
Vcc
GND
CANH RxD
CANL
TxD
3
2
0.1 µF
4
1
HRxD
HTxD
124 Ω
CAN bus
Note: A bus transceiver IC is necessary to connect an H8S/2623F-ZTAT to the CAN bus. One compatible with the
Philips PCA82C50 is recommended.
Figure 1.2 CAN Interface Using H8S/2623F-ZTATs
Rev. 1.0, 1/00, page 2 of 119
1.2
Functions
Tables 1.1 and 1.2 show the function allocation of this sample task. This sample task allocates
H8S/2623F-ZTAT on-chip HCAN functions as shown in these tables, and carries out HCAN
transmission and reception.
Table 1.1
HCAN Function Allocation
HCAN Register
Pins
Function
HTxD
Transmits messages.
HRxD
Receives messages.
Transmission/ IRR
reception
BCR
registers
MBCR
Transmission
registers
Reception
registers
Table 1.2
Displays status of each interrupt source.
Sets CAN baud rate prescaler and bit timing parameters.
Sets mailbox transmission/reception.
MCR
Controls CAN interface.
MC0_1
to
MC15_8
Arbitration field and control field settings.
MD0_1
to
MD15_8
Data field settings.
TXPR
Sets transmission wait state after transmit messages are stored in
the mailbox.
TXACK
Indicates that the transmit message of the corresponding mailbox
was transmitted normally.
LAFMH
Sets filter mask for reception mailbox 0 identifier.
RXPR
Indicates that data has been received normally by the corresponding
mailbox.
MSTPCR Function Allocation
MSTPCR Register
Function
MSTPCRC
Controls module stop mode.
Rev. 1.0, 1/00, page 3 of 119
1.3
Operation
Operation (Transmission)
Figure 1.3 shows the principle of operation during transmission. HCAN transmission is carried out
by H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
Stuff bits*7
CRC delimiter
SOF
ACK field
Control
field
Arbitration field
Data field
CRC field
Transmit
data frame
EOF
Initial settings
Transmit data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. SOF output
2. Data frame
transmission
3. Automatic generation of stuff bits
1. Automatically
generates and
transmits CRC
calculated from all
bit data except stuff
bits in data field
from SOF (15 bits)
2. CRC delimiter
(1 bit) output
1. ACK reception
2. Sets transmission
completed flag
Software processing
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 1
for transmission
• Initializes
mailboxes (RAM)
• Sets transmission
format (order of
mailbox numbers)
2. Releases configuration mode
1. Transmit data
settings
• Arbitration field
setting
• Control field
setting
• Data field setting
2. Message
transmission
• Sets mailbox 1
to transmission
wait state
Software processing
None
Software processing
None
Note: * See 1.9 Notes.
Figure 1.3 Operation During HCAN Transmission
Rev. 1.0, 1/00, page 4 of 119
Software processing
1. Clears transmission
completed flag
Operation (Reception)
Figure 1.4 shows the principle of operation during reception. HCAN reception is carried out by
H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
Stuff bits*7
CRC delimiter
SOF
ACK field
Arbitration field
Control
field
Data field
CRC field
Identifier
Received
data frame
Initial settings
EOF
Receive data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. Compares received
identifier with filter
mask of mailbox 0
identifier, and if it
matches, stores it
in mailbox
2. Sets reception
completed flag
1. CRC check
2. ACK transmission
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 0
for reception
• Initializes
mailboxes (RAM)
2. Releases configuration mode
Software processing
1. Receive data
settings
• Arbitration field
setting
• Filter mask setting
for mailbox 0
identifier
Software processing
1. Confirms completion of reception
2. Stores receive data
in on-chip RAM
Software processing
None
Note: * See 1.9 Notes.
Figure 1.4 Operation During HCAN Reception
Rev. 1.0, 1/00, page 5 of 119
1.4
Software
1. Modules
Module Name
Label
Function
Main routine
main
HCAN initial settings and transmission/reception settings.
2. Variables Used
Label
Function
Data Length
Module
COUNT
Initializes HCAN_MC0_1 to MC15_8, and
HCAN_MD0_1 to MD15_8.
Unsigned short
Main routine
3. Internal Registers Used
Register Name
Function
Setting
Module
Main routine
Settings Common to Transmission/Reception
MSTPCRC
Releases HCAN module stop mode.
0xF7
HCAN_IRR
Initializes HCAN module reset flag.
0x0100
HCAN_BCR
Sets HCAN bit rate to 250 kbps.
0x0334
Settings for Transmission
HCAN_MBCR
Sets mailbox 1 for transmission.
0xFDFF
HCAN_MCR
Sets transmission in order of mailbox numbers,
and clears reset request bit.
0x04
HCAN_MC1_1
Sets 1-byte data length.
0x01
HCAN_MC1_5
Selects mailbox 1 data frame and standard
format, and sets identifier.
0xA0
HCAN_MC1_6
Sets mailbox 1 identifier.
0xAA
HCAN_MD1_1
Sets transmit data for mailbox 1.
0xAA
HCAN_TXPR
Sets mailbox 1 to transmission wait state.
0x0200
HCAN_TXACK
Clears data frame transmission completed flag.
0x0200
Main routine
Settings for Reception
HCAN_MBCR
Sets mailbox 0 for reception.
0x0100
HCAN_MCR
Clears reset request bit.
0xFE
HCAN_MC0_5
Selects mailbox 0 data frame and standard
format, and sets identifier.
0xA0
HCAN_MC0_6
Sets mailbox 0 identifier.
0xAA
HCAN_LAFMH
Sets filter mask for mailbox 0 identifier.
0x0000
Rev. 1.0, 1/00, page 6 of 119
Main routine
4. RAM Used
Symbol
Function
Address
Module
MAIL_BOX0
Stores HCAN_MD0_1 data.
H'FFC100
Main routine
Rev. 1.0, 1/00, page 7 of 119
1.5
Transmission Flowchart
Transmit operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate
• Set mailbox 1 for transmission
• Initialize mailboxes (RAM)
• Set transmission format (order of mailbox
numbers)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Transmit data settings
• Set arbitration field
• Set control field
• Set data field
Message transmission
• Set mailbox 1 to transmission wait state
No
End of transmission?
Yes
Transmission
completed flag set?
No
Yes
: Set by user
Clear transmission completed flag
: Processed by hardware
End of ransmission
Note: * See 1.9 Notes.
Figure 1.5 Transmission Flowchart
Rev. 1.0, 1/00, page 8 of 119
1.6
Transmission Program List
/********************************************************************************/
/*
HCAN Transmission Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file
*/
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT
(*(unsigned short *)0xFFC000)
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial Settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0334;
/* Bit rate: 250 kbps
*/
HCAN_MBCR = 0xFDFF;
/* Set mailbox 1 for transmission
*/
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM)
*/
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM) */
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR = 0x04;
/* Set transmission in order of mailbox numbers, and release configuration
mode*/
/* Transmit data settings */
HCAN_MC1_5 = 0xA0;
/* Select data frame and standard format, and set identifier */
HCAN_MC1_6 = 0xAA;
/* Set identifier
*/
Rev. 1.0, 1/00, page 9 of 119
HCAN_MC1_1 = 0x01;
/* Data length: 1 byte
*/
HCAN_MD1_1 = 0xAA;
/* Transmit data: 10101010
*/
/* Message transmission */
HCAN_TXPR = 0x0200;
/* Set mailbox 1 to transmission wait state */
while((HCAN_TXACK & 0x0200) != 0x0200);
/* Wait for completion of transmission
*/
/* Clear transmission completed flag */
HCAN_TXACK &= 0x0200;
while(1);
}
Rev. 1.0, 1/00, page 10 of 119
/* Clear transmission completed flag
*/
1.7
Reception Flowchart
Receive operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate
• Set mailbox 0 for reception
• Initialize mailboxes (RAM)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Receive data settings
• Set arbitration field
• Set filter mask for mailbox 0 identifier
No
Message received?
Yes
CRC check
ACK transmission
Compare filter mask for mailbox 0
identifier with received identifier
Store receive data
Reception
completed flag set?
No
Yes
: Set by user
Store receive data in on-chip RAM
: Processed by hardware
End of reception
Note: * See 1.9 Notes.
Figure 1.6 Reception Flowchart
Rev. 1.0, 1/00, page 11 of 119
1.8
Reception Program List
/********************************************************************************/
/*
HCAN Reception Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file
*/
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT
(*(unsigned short *)0xFFC000)
#define MAIL_BOX0
(*(unsigned char *) 0xFFC100)
/* Store receive data for mailbox 0
*/
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0334;
/* Bit rate: 250 kbps
*/
HCAN_MBCR = 0x0100;
/* Set mailbox 0 for reception
*/
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM)
*/
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM)
*/
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR &= 0xFE;
/* Release configuration mode
*/
/* Receive data settings */
HCAN_MC0_5 = 0xA0;
HCAN_MC0_6 = 0xAA;
Rev. 1.0, 1/00, page 12 of 119
/* Set data frame, standard format, and identifier */
/* Set identifier
*/
HCAN_LAFMH = 0x0000;
/* Set filter mask for mailbox 0 identifier */
while((HCAN_RXPR & 0x0100) != 0x0100);
/* Wait for completion of reception */
/* Store receive data in on-chip RAM */
MAIL_BOX0 = HCAN_MD0_1;
/* Store receive data
*/
while(1);
}
Rev. 1.0, 1/00, page 13 of 119
1.9
Notes
1. Data frame: Data to be transferred from the transmission source to the transmission
destination.
2. Arbitration field: Set unique ID for message and data frame or remote frame.
3. Control field: Set the data length to be transmitted, and standard format or extended format.
4. Data field: Set message contents (data to be transmitted).
5. CRC field: A CRC is generated automatically in the HCAN from all bit data except stuff bits
in the data field from SOF, and is used to detect transmit message errors.
The CRC field comprises a 15-bit CRC and a 1-bit delimiter.
The CRC delimiter is always output as a 1 after the CRC.
CRC field
CRC
CRC delimiter
Figure 1.7 CRC Field
About the CRC:
R
R
Transmit data polynomial P(X) is multiplied by X , then X · P(X) is divided by generating
polynomial G(X) to give a remainder, R(X). On the side transmitting information, R(X) found
R
from X · P(X) is added as check bits, and the result is sent as transmit data Tx(X).
On the side receiving the information, receive data Rx(X) is divided by generating polynomial
G(X) to give a remainder. If this remainder is zero, information transmission is regarded as
having been completed normally. If the remainder is nonzero, an error is judged to have
occurred in the information transmitted.
P(X) = {SOF through data field, excluding stuff bits}
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
R = 15
Note: G(X) is stipulated in the CAN protocol as the polynomial that generates the CRC.
Rev. 1.0, 1/00, page 14 of 119
As an example, the procedure is described below for a data frame transmitted using the
following settings.
Settings SOF: 0
Arbitration field: 101010101010
Control field: 000001
Data field: 10101010
The bit pattern from SOF through the data field in the transmitted data is as follows
( indicates the stuff bit):
0–1010101010100000–1–0110101010
Data field
SOF
Control field
Arbitration field
Excluding the stuff bit gives the following data subject to CRC computation:
010101010101000000110101010
Thus,
25
23
21
19
17
15
8
7
5
3
P(X) = X + X + X + X + X + X + X + X + X + X + X
1
15
P(X) is multiplied by X , giving:
15
40
38
36
34
32
30
23
22
20
18
X · P(X) = X + X + X + X + X + X + X + X + X + X + X
16
and this value is divided by
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
Rev. 1.0, 1/00, page 15 of 119
X15 . P(X) = X40 + X38 + X36 + X34 + X32 + X30 + X23 + X22 + X20 + X18 + X16
P[40:0] = 10101010101000000110101010000000000000000
G(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1
G[15:0] = 1100010110011001
Quotient
1100010110011001 10101010101000000110101010000000000000000
1100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1100010110011001
taken.
1101011000111101
1 1 0 0 0 1 0 1 1 0 0 1 1 0 01
1001110100100010
1100010110011001
1011000101110110
1100010110011001
1110100111011110
1100010110011001
1011000100011100
1100010110011001
1110100100001010
1100010110011001
1011001001001100
1100010110011001
1110111110101010
1100010110011001
1010100011001100
1100010110011001
1101101010101010
1100010110011001
1111100110011000
1100010110011001
111100000000010
Remainder:
R[14:0]
The following value is obtained from the calculation.
R [14:0] = 111100000000010
In other words, this is the CRC value, added after the data field to give transmit data Tx(X),
which is transmitted.
In practice, a stuff bit ( ) and CRC delimiter ( ) are added, so that 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1
is transmitted in the CRC field.
Rev. 1.0, 1/00, page 16 of 119
Next, the calculation is shown which determines whether there is an error in receive data
Rx(X).
Rx(X) is the value obtained by adding the remainder given by the previous calculation to
15
X · P(X). This value is divided by G(X).
P[40:0] = 1010101010100 0000110101010000000000000000
111100000000010
1 0101010101000000110101010111100000000010
+ R[14:0] =
This value is divided by G[15:0].
Quotient
1100010110011001 1 010101010100000 011010101011110 0000000010
1 100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1 100010110011001
taken.
1101011000111101
1100010110011001
1001110100100010
1100010110011001
1011000101110111
1100010110011001
1110100111011101
1100010110011001
1011000100010011
1100010110011001
1110100100010100
1100010110011001
1011001000110100
1100010110011001
1110111101011010
1100010110011001
1010101100001100
1100010110011001
1101110100101010
110 0010110011001
1100010110011001
1100010110011001
0
Remainder
The remainder from the above calculation is zero, so the transmission is considered to be errorfree.
Rev. 1.0, 1/00, page 17 of 119
6. ACK field: For confirmation of normal reception.
Comprises a 1-bit ACK slot and a 1-bit ACK delimiter.
ACK field
ACK slot
ACK delimiter
Figure 1.8 ACK Field
The receiving H8S/2623F-ZTAT outputs a high-level ACK slot if it finds an error in the CRC
check, and a low-level ACK slot if it finds no error.
7. Stuff bits: If there are five consecutive low bits in the data frame, the output is always high for
the next bit. Similarly, if there are five consecutive high bits, the output is always low for the
next bit.
When stuff bits are output in this way, the bit length of the data frame is increased by the
number of stuff bits.
As an example, consider the case where the following settings are made:
Arbitration field: 101010101010
Control field: 000001
The bit pattern in this case is thus 101010101010000001, and so a stuff bit ( ) is output as the
second-but-lowest bit (after the five consecutive 0s).
The value transmitted on the CAN bus is therefore 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 , and the data
frame length is increased by the one stuff bit.
Rev. 1.0, 1/00, page 18 of 119
Values set in arbitration field,
control field, data field
(A)
CRC field
0 1 0 1 0 10 1 0 1 0 1 0 0 0 0 0 0 1 1 01 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1
Stuff bit is
output here
(B)
0101 01 01 01 01000 00101101 0101 0 111 100 0001 00001 0 1
For the data frame to be transmitted, shown in (A), data frame (B), with stuff bits added, is actually
transmitted on the CAN bus. Data frame (B) is longer by the length of the stuff bits.
Figure 1.9 Stuff Bits
8. Configuration mode: In this mode, the HCAN module is in the reset state. This mode is
released by clearing the reset request bit (MCR0) in the master control register (MCR).
Rev. 1.0, 1/00, page 19 of 119
Section 2 HCAN Transmission/Reception (Example 2):
Standard Format, 8-Byte Data, Using DTC
MCU: H8S/2623F-ZTAT
2.1
Function Used: HCAN, DTC
Specifications
1
1. Data frame* transmission/reception (using two H8S/2623F-ZTATs).
Data frame specifications are shown in figure 2.1.
a. SOF: Indicates start of data frame.
2
b. Arbitration field* : Set to 101010101010.
•
RTR = 0: Select data frame
3
c. Control field* : Set to 001000.
•
IDE = 0: Select standard format
•
R0 = 0: Reserved bit
•
DLC = 1000: Set data length of 8 bytes
d. Data field*
4
st
•
1 byte: Set to 01010101 (H'55).
•
2 byte: Set to 01100110 (H'66).
•
3 byte: Set to 01110111 (H'77).
•
4 byte: Set to 10001000 (H'88).
•
5 byte: Set to 10011001 (H'99).
•
6 byte: Set to 10101010 (H'AA).
•
7 byte: Set to 10111011 (H'BB).
•
8 byte: Set to 11111111 (H'FF).
nd
rd
th
th
th
th
th
5
e. CRC field* : CRC is generated automatically within the HCAN.
6
f. ACK field* : 11 is output on the transmitting side, and 01 (in normal operation) on the
receiving side.
g. EOF: Indicates the end of a transmit/receive data frame.
2. A communication speed of 250 kbps (when operating at 20 MHz) is set.
3. The data length is set to 8 bytes.
4. Message transmission uses mailbox 1.
5. Message reception uses mailbox 0. The message reception method is to mask the identifier and
receive the message in case of a match.
Rev. 1.0, 1/00, page 21 of 119
6. Select interrupt control mode 2, and
a. Use bus operation interrupt (OVR0).
b. Use DTC interrupts by message reception and the message reception interrupt (RM0).
7. Receive messages are stored in on-chip RAM using the DTC.
a. The DTC is started up by a message being received.
b. DTC specifications are as follows.
•
Block transmission mode is used.
•
After transmission ends, the message reception interrupt (RM0) is used.
8. Use HCAN sleep mode.
a. After initial settings, transfer to HCAN sleep mode (released by a CAN bus operation).
b. After reception processing, transfer to HCAN sleep mode (released by a CAN bus
operation).
9. Figure 2.2 shows an example of CAN bus connection.
Note: * See 2.9 Notes.
Data frame
Arbitration field
Control field
Data field
1 bit
12 bits
6 bits
8 bits × 8
16 bits
2 bits
7 bits
EOF
SOF
ACK field
CRC field
(With CRC delimiter*5)
Identifier
RTR IDE R0
DLC
Note: * See 2.9 Notes.
Figure 2.1 Data Frame Specifications
Rev. 1.0, 1/00, page 22 of 119
Reception side
H8S/2623F-ZTAT
Transmission side
H8S/2623F-ZTAT
5V
5V
PCA82C250
NC
5
8
HRxD
HTxD
4
1
Vref
Rs
RxD
TxD
Vcc
GND
CANH
CANL
PCA82C250
3
0.1 µF
2
124 Ω
NC
5
8
7
7
6
6
Vref
Rs
Vcc
GND
CANH RxD
CANL
TxD
3
2
0.1 µF
4
1
HRxD
HTxD
124 Ω
CAN bus
Note: A bus transceiver IC is necessary to connect an H8S/2623F-ZTAT to the CAN bus. One compatible with the
Philips PCA82C50 is recommended.
Figure 2.2 CAN Interface Using H8S/2623F-ZTATs
Rev. 1.0, 1/00, page 23 of 119
2.2
Functions
Tables 2.1 to 2.4 show the function allocation of this sample task. This sample task allocates
H8S/2623F-ZTAT on-chip HCAN functions as shown in these tables, and carries out HCAN
transmission and reception.
Table 2.1
HCAN Function Allocation
HCAN Register
Pins
Function
HTxD
Transmits messages.
HRxD
Receives messages.
Transmission/ IRR
reception
BCR
registers
MBCR
Transmission
registers
Reception
registers
Table 2.2
Displays status of each interrupt source.
Sets CAN baud rate prescaler and bit timing parameters.
Sets mailbox transmission/reception.
MCR
Controls CAN interface.
MC0_1
to
MC15_8
Arbitration field and control field settings.
MD0_1
to
MD15_8
Data field settings.
TXPR
Sets transmission wait state after transmit messages are stored in
the mailbox.
TXACK
Indicates that the transmit message of the corresponding mailbox
was transmitted normally.
MBIMR
Enables/disables interrupt requests for each mailbox.
IMR
Enables/disables requests for each interrupt source.
LAFMH
Sets filter mask for reception mailbox 0 identifier.
MSTPCR Function Allocation
MSTPCR Register
Function
MSTPCRC
Control module stop mode.
MSTPCRA
Rev. 1.0, 1/00, page 24 of 119
Table 2.3
Interrupt Controller Allocation
IPR Register
Function
IPRM
Controls interrupt priority level.
SYSCR
Sets interrupt control mode.
exr
Specifies interrupt request mask level.
Table 2.4
DTC Function Allocation
DTC Register
Function
SAR (On-chip RAM)
Sets source address (where receive messages are stored from).
DAR (On-chip RAM)
Sets destination address (where receive messages are stored to).
MAR (On-chip RAM)
Sets block transfer mode, byte size transfer, etc.
MRB (On-chip RAM)
Sets interrupt to CPU after DTC data transfer.
CRA (On-chip RAM)
Sets number of DTC data transfers.
CRB (On-chip RAM)
Sets number of DTC block data transfers.
DTCERG (Register)
Sets DTC start by interrupt.
Rev. 1.0, 1/00, page 25 of 119
2.3
Operation
Operation (Transmission)
Figure 2.3 shows the principle of operation during transmission. HCAN transmission is carried out
by H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
Stuff bit*7
CRC delimiter
ACK field
SOF
Control
field
Arbitration field
Data field
CRC field
Transmit
data frame
EOF
H'55 H'66 H'77 H'88 H'99 H'AA H'BB H'FF
Stuff bit*7
Data field
Initial settings
Transmit data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. SOF output
2. Data frame
transmission
3. Automatic generation of stuff bits
1. Automatically
generate and
transmits CRC
calculated from all
bit data except stuff
bits in data field
from SOF(15 bits)
2. CRC delimiter
(1 bit) output
1. ACK reception
2. Sets transmission
completed flag
Software processing
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 1
for transmission
• Initializes
mailboxes (RAM)
• Sets transmission
format (order of
mailbox numbers)
2. Releases configuration mode
1. Transmit data
settings
• Arbitration field
setting
• Control field
setting
• Data field setting
2. Message
transmission
• Sets mailbox 1
to transmission
wait state
Software processing
None
Software processing
None
Note: * See 2.9 Notes.
Figure 2.3 Operation During HCAN Transmission
Rev. 1.0, 1/00, page 26 of 119
Software processing
1. Clears transmission
completed flag
Operation (Reception)
Figure 2.4 shows the principle of operation during reception. HCAN reception is carried out by
H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
Recessive bits
(recovery from
bus off to
bus idle)
CRC delimiter
SOF
ACK field
Arbitration
field
Bus idle
Control
field
Data
field
CRC field
Identifier
Received data
frame
EOF
Stuff bit*7
H'55 H'66 H'77 H'88 H'99 H'AA H'BB H'FF
Initial settings
Data field
Interrupt settings
Stuff bit*7
Receive data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. Bus operation
interrupt
1. Compares received
identifier with filter
mask of mailbox 0
identifier, and if it
matches, stores it
in mailbox
2. DTC startup by
message reception
3. DTC data transfer
4. Sets DTC data
transfer end bit
5. DTC transfer end
interrupt
1. CRC check
2. ACK transmission
Software processing
Software processing
Software processing
1. DTC initial settings
• Releases DTC
module stop
mode
• Initializes DTC
2. HCAN initial
settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 0
for reception
• Initializes mailboxes (RAM)
3. Releases configuration mode
1. Interrupt settings
• Sets interrupt
request for
mailbox 0
• Enables message
reception and bus
operation interrupt
• Sets interrupt
control mode
• Sets HCAN
interrupt priority
level
• Specifies interrupt
request mask
level
2. Receive data
setting
• Arbitration field
setting
• Filter mask setting
for mailbox 0
identifier
3. HCAN sleep mode
settings
• Sets method of
transferring to and
releasing HCAN
sleep mode
1. Clears bus operation interrupt flag
Software processing
1. Clears DTC start
source (receive
message interrupt
flag)
2. HCAN sleep mode
setting
• Transfers to
HCAN sleep
mode
Software processing
None
Note: * See 2.9 Notes.
Figure 2.4 Operation During HCAN Reception
Rev. 1.0, 1/00, page 27 of 119
2.4
Software
1. Modules
Module Name
Label
Function
Main routine
main
HCAN initial settings and transmission/reception settings.
Bus operation
interrupt routine
OVR0_IRR12
Clears bus operation interrupt flag.
DTC transfer end
interrupt routine
DTCend_RM0
Clears DTC start source and transfers to HCAN sleep mode.
2. Variables Used
Label
Function
Data Length
Module
COUNT
Initializes HCAN_MC0_1 to MC15_8, and
HCAN_MD0_1 to MD15_8.
Unsigned short
Main routine
Rev. 1.0, 1/00, page 28 of 119
3. Internal Registers Used
Register Name
Function
Setting
Module
Main routine
Settings Common to Transmission/Reception
MSTPCRC
Release HCAN module stop mode.
0xF7
HCAN_BCR
Sets HCAN bit rate to 250 kbps.
0x0334
Settings for Transmission
HCAN_IRR
Initializes HCAN module reset flag.
0x0100
HCAN_MBCR
Sets mailbox 1 for transmission.
0xFDFF
HCAN_MCR
Sets transmission in order of mailbox numbers,
and clears reset request bit.
0x04
HCAN_MC1_1
Sets 8-byte data length.
0x08
HCAN_MC1_5
Selects mailbox 1 data frame and standard
format, and sets identifier
0xA0
HCAN_MC1_6
Sets mailbox 1 identifier.
HCAN_MD1_1
Sets transmit data for 1 byte of mailbox 1.
HCAN_MD1_2
Sets transmit data for 2 byte of mailbox 1.
HCAN_MD1_3
HCAN_MD1_4
HCAN_MD1_5
0xAA
st
0x55
nd
0x66
rd
0x77
th
0x88
th
0x99
th
0xAA
th
0xBB
th
Sets transmit data for 3 byte of mailbox 1.
Sets transmit data for 4 byte of mailbox 1.
Sets transmit data for 5 byte of mailbox 1.
HCAN_MD1_6
Sets transmit data for 6 byte of mailbox 1.
HCAN_MD1_7
Sets transmit data for 7 byte of mailbox 1.
Main routine
HCAN_MD1_8
Sets transmit data for 8 byte of mailbox 1.
0xFF
HCAN_TXPR
Sets mailbox 1 to transmission wait state.
0x0200
HCAN_TXACK
Clears data frame transmission completed flag.
0x0200
Rev. 1.0, 1/00, page 29 of 119
Register Name
Function
Setting
Module
Initializes HCAN module reset flag.
0x0100
Main routine
Clears bus operation interrupt flag.
0x0010
Bus operation
Clears reset request bit.
0xFE
Main routine
Sets transfer to HCAN sleep mode and release
by bus operation.
0xA0
Transfers to HCAN sleep mode.
0x20
Clears receive message interrupt.
0xFFFF
HCAN_MBCR
Sets mailbox 0 for reception.
0x0100
HCAN_MC0_5
Selects mailbox 0 data frame and standard
format, and sets identifier.
0xA0
HCAN_MC0_6
Sets identifier for mailbox 0.
0xAA
HCAN_LAFMH
Sets filter mask for mailbox 0 identifier.
0x0000
HCAN_MBIMR
Sets enabling of mailbox 0 interrupt requests.
0xFEFF
HCAN_IMR
Sets enabling of message reception and bus
operation interrupt requests.
0xFCEF
INTC. IPRM
Sets HCAN interrupt priority level to 7.
0x70
SYSCR
Sets interrupt control mode 2.
0x20
exr
Specifies interrupt request mask level.
0x00
MSTPCRA
Releases DTC module stop mode.
0x3F
DTC_DTCERG
Sets DTC start by HCAN receive message.
0x20
Settings for Reception
HCAN_IRR
HCAN_MCR
HCAN_RXPR
Note: Bus operation: Bus operation interrupt routine
DTC end: DTC transfer end interrupt routine
Rev. 1.0, 1/00, page 30 of 119
DTC end
Main routine
4. RAM Used
Symbol
Function
Address
Module
Message_Box1
to 8
Storage destination address for mailbox 0
data (8-byte)
0xFFC000 to 7
(Undefined)
Main routine
SAR
Sets source address (where receive
messages are stored from).
0xFFEC01 to 3
(0xFFF8B0)
MRA
Sets block transfer mode, byte size transfer,
etc.
0xFFEC00
(0xA8)
DAR
Sets destination address (where receive
message are stored to).
0xFFEC05 to 7
(0xFFC000)
MRB
Enables message reception interrupt (RM0)
after DTC data transfer ends.
0xFFEC04
(0x00)
CRA
Sets transfer block size retained value for
DTC data transfer (upper byte) and transfer
block size counter (lower byte).
0xFFEC08, 9
(0x0808)
CRB
Sets transfer number of DTC block transfers. 0xFFEC0A, B
(0x0001)
Figures in parentheses are settings.
Rev. 1.0, 1/00, page 31 of 119
2.5
Transmission Flowchart
Transmit operation: Main routine
Initial Settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (250 kbps)
• Set mailbox 1 for transmission
• Initialize mailboxes (RAM)
• Set transmission format (order of mailbox
numbers)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Transmit data settings
• Set arbitration field
• Set control field
• Set data field
Message transmission
• Set mailbox 1 to transmission wait state
No
End of transmission?
Yes
Transmission
completed flag set?
No
Yes
: Set by user
Clear transmission completed flag
: Processed by hardware
End of transmission
Note: * See 2.9 Notes.
Figure 2.5 Transmission Flowchart
Rev. 1.0, 1/00, page 32 of 119
2.6
Transmission Program List
/********************************************************************************/
/*
HCAN Transmission Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT (*(unsigned long *)0xFFC000)
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial Settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0334;
/* Bit rate: 250 kbps
*/
HCAN_MBCR = 0xFDFF;
/* Set mailbox 1 for transmission
*/
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM)
*/
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM)
*/
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR = 0x04;
/* Set transmission in order of mailbox numbers, and release configuration
mode */
/* Transmit data settings */
HCAN_MC1_5 = 0xA0;
/* Select data frame and standard format, and set identifier */
HCAN_MC1_6 = 0xAA;
/* Set identifier
*/
Rev. 1.0, 1/00, page 33 of 119
HCAN_MC1_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD1_1 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD1_2 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD1_3 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD1_4 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD1_5 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD1_6 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD1_7 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD1_8 = 0xFF;
/* Message contents: 11111111
*/
/* Set mailbox 1 to transmission wait state
*/
/* Message transmission */
HCAN_TXPR = 0x0200;
while((HCAN_TXACK & 0x0200) != 0x0200);
/* Clear transmission completed flag */
HCAN_TXACK &= 0x0200;
while(1);
}
Rev. 1.0, 1/00, page 34 of 119
/* Clear transmission completed flag
*/
2.7
Reception Flowcharts
Receive operation: Main routine
DTC initial settings
• Release DTC module stop mode
• Set transfer source and destination
addresses
• Set block transfer mode, etc.
• Enable interrupt after end of transfer
• Set block size and number of transfers
HCAN initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (250 kbps)
• Set mailbox 0 for reception
• Initialize mailbox (RAM)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Interrupt settings
• Set mailbox 0 interrupt request
• Enable message reception and bus
operation interrupt
• Set interrupt control mode 2
• Set HCAN interrupt priority level
• Set interrupt request mask level
Receive data settings
• Set arbitration field
• Set filter mask for mailbox 0 identifier
HCAN sleep mode settings
• Set method of transferring to and
releasing HCAN sleep mode
No
Is there a bus operation?
Yes
No
11-bit recessive reception?
Yes
: Set by user
CAN bus communication enabled
: Processed by hardware
EXIT
Note: * See 2.9 Notes.
Figure 2.6 Reception Flowchart (1)
Rev. 1.0, 1/00, page 35 of 119
EXIT
Message received?
No
Yes
CRC check
ACK transmission
Compare filter mask for mailbox 0 identifier
with received identifier
Store receive data
Set reception completed flag
DTC start
Transfer receive data to on-chip RAM
No
End of DTC transfer?
Yes
Clear DTC start enable bit
End of reception
Figure 2.6 Reception Flowchart (2)
Rev. 1.0, 1/00, page 36 of 119
: Processed by hardware
Bus operation interrupt routine
Clear bus operation interrupt flag
RTE
: Set by user
Figure 2.7 Bus Operation Interrupt Flowchart
DTC transfer end interrupt routine
Release DTC start source
• Clear receive message interrupt flag
Set HCAN sleep mode
• Transfer to HCAN sleep mode
: Set by user
RTE
Figure 2.8 DTC Transfer End Interrupt Flowchart
Rev. 1.0, 1/00, page 37 of 119
2.8
Reception Program List
/********************************************************************************/
/*
HCAN Reception Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file
*/
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT
(*(unsigned short *)0xFFC100)
#define Message_Box1 (*(volatile unsigned char
*)0xFFC000)
/* Store receive data 1 */
#define Message_Box2 (*(volatile unsigned char
*)0xFFC001)
/* Store receive data 2 */
#define Message_Box3 (*(volatile unsigned char
*)0xFFC002)
/* Store receive data 3 */
#define Message_Box4 (*(volatile unsigned char
*)0xFFC003)
/* Store receive data 4 */
#define Message_Box5 (*(volatile unsigned char
*)0xFFC004)
/* Store receive data 5 */
#define Message_Box6 (*(volatile unsigned char
*)0xFFC005)
/* Store receive data 6 */
#define Message_Box7 (*(volatile unsigned char
*)0xFFC006)
/* Store receive data 7 */
#define Message_Box8 (*(volatile unsigned char
*)0xFFC007)
/* Store receive data 8 */
#define SAR
(*(volatile unsigned long
*)0xFFEC00)
/* Set DTC register information */
#define MRA
(*(volatile unsigned char
*)0xFFEC00)
/* Set DTC register information */
#define DAR
(*(volatile unsigned long
*)0xFFEC04)
/* Set DTC register information */
#define MRB
(*(volatile unsigned char
*)0xFFEC04)
/* Set DTC register information */
#define CRA
(*(volatile unsigned short *)0xFFEC08)
/* Set DTC register information */
#define CRB
(*(volatile unsigned short *)0xFFEC0A)
/* Set DTC register information */
Rev. 1.0, 1/00, page 38 of 119
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* DTC initial settings */
MSTPCRA = 0x3F;
/* Release DTC module stop mode
*/
SAR = (long)(&HCAN_MD0_1);
/* Set transfer source address
*/
MRA = 0xA8;
/* Set SAR and DAR incrementing after transfer, and block transfer mode */
DAR = (long)(&Message_Box1);
/* Set transfer destination address (on-chip RAM)
MRB = 0x00;
/* Enable interrupt after end of data transfer by DTC */
CRA = 0x0808;
CRB = 0x0001;
DTC_DTCERG |= 0x20;
*/
/* Set block transfer to 8-byte units
*/
/* Set number of block transfers to 1
*/
Enable DTC start by HCAN interrupt (RM0) */
/* HCAN initial settings */
MSTPCRC = 0xF7
/* Release HCAN module stop mode
*/
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag
*/
HCAN_BCR = 0x0334;
/* Bit rate: 250 kbps
*/
HCAN_MBCR = 0x0100;
/* Set mailbox 0 for reception
*/
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM) */
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM) */
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR &= 0xFE;
/* Release configuration mode
*/
/* Enable mailbox 0 interrupt request
*/
/* Interrupt settings */
HCAN_MBIMR = 0xFEFF;
HCAN_IMR = 0xFCEF; /* Enable message reception and bus operation interrupt */
SYSCR |= 0x20;
/* Set interrupt control mode 2
*/
INTC.IPRM = 0x70;
/* Set HCAN interrupt priority level to 7 */
set_imask_exr(0);
/* Specify interrupt request mask level
*/
/* Receive data settings */
HCAN_MC0_5 = 0xA0;
/* Set standard format, data frame, and identifier */
HCAN_MC0_6 = 0xAA;
HCAN_LAFMH = 0x0000;
/* Set identifier
*/
/* Mailbox 0 stores data in case of bit match
*/
/* HCAN sleep mode setting */
Rev. 1.0, 1/00, page 39 of 119
HCAN_MCR |= 0xA0;
/* Enable transfer to HCAN mode and release by bus operation */
while(1);
}
/********************************************************************************/
/*
Bus Operation Interrupt Routine
*/
/********************************************************************************/
#pragma interrupt(OVR0_IRR12)
void OVR0_IRR12(void)
{
HCAN_IRR &= 0x0010;
/* Clear IRR12 (bus operation interrupt flag)
*/
}
/********************************************************************************/
/*
DTC Transfer End Interrupt Routine
*/
/********************************************************************************/
#pragma interrupt(DTCend_RM0)
void DTCend_RM0(void)
{
HCAN_RXPR &= 0xFFFF;
/* Clear IRR1 (receive message interrupt flag) */
/* HCAN sleep mode setting */
HCAN_MCR |= 0x20;
}
Rev. 1.0, 1/00, page 40 of 119
/* Transfer to HCAN sleep mode
*/
2.9
Notes
1. Data frame: Data to be transferred from the transmission source to the transmission
destination.
2. Arbitration field: Set unique ID for message and data frame or remote frame.
3. Control field: Set the data length to be transmitted, and standard format or extended format.
4. Data field: Set message contents (data to be transmitted).
5. CRC field: A CRC is generated automatically in the HCAN from all bit data except stuff bits
in the data field from SOF, and is used to detect transmit message errors.
The CRC field comprises a 15-bit CRC and a 1-bit delimiter.
The CRC delimiter is always output as a 1 after the CRC.
CRC field
CRC
CRC delimiter
Figure 2.9 CRC Field
About the CRC:
R
R
Transmit data polynomial P(X) is multiplied by X , then X · P(X) is divided by generating
polynomial G(X) to give a remainder, R(X). On the side transmitting information, R(X) found
R
from X · P(X) is added as check bits, and the result is sent as transmit data Tx(X).
On the side receiving the information, receive data Rx(X) is divided by generating polynomial
G(X) to give a remainder. If this remainder is zero, information transmission is regarded as
having been completed normally. If the remainder is nonzero, an error is judged to have
occurred in the information transmitted.
P(X) = {SOF through data field, excluding stuff bits}
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
R = 15
Note: G(X) is stipulated in the CAN protocol as the polynomial that generates the CRC.
Rev. 1.0, 1/00, page 41 of 119
As an example, the procedure is described below for a data frame transmitted using the
following settings.
Settings SOF: 0
Arbitration field: 101010101010
Control field: 000001
Data field: 10101010
The bit pattern from SOF through the data field in the transmitted data is as follows
( indicates the stuff bit):
0–1010101010100000–1–0110101010
Data field
SOF
Control field
Arbitration field
Excluding the stuff bit gives the following data subject to CRC computation:
010101010101000000110101010
Thus,
25
23
21
19
17
15
8
7
5
3
P(X) = X + X + X + X + X + X + X + X + X + X + X
1
15
P(X) is multiplied by X , giving:
15
40
38
36
34
32
30
23
22
20
18
X · P(X) = X + X + X + X + X + X + X + X + X + X + X
and this value is divided by
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
Rev. 1.0, 1/00, page 42 of 119
16
X15 . P(X) = X40 + X38 + X36 + X34 + X32 + X30 + X23 + X22 + X20 + X18 + X16
P[40:0] = 10101010101000000110101010000000000000000
G(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1
G[15:0] = 1100010110011001
Quotient
1100010110011001 10101010101000000110101010000000000000000
1100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1100010110011001
taken.
1101011000111101
1 1 0 0 0 1 0 1 1 0 0 1 1 0 01
1001110100100010
1100010110011001
1011000101110110
1100010110011001
1110100111011110
1100010110011001
1011000100011100
1100010110011001
1110100100001010
1100010110011001
1011001001001100
1100010110011001
1110111110101010
1100010110011001
1010100011001100
1100010110011001
1101101010101010
1100010110011001
1111100110011000
1100010110011001
111100000000010
Remainder:
R[14:0]
The following value is obtained from the calculation.
R [14:0] = 111100000000010
In other words, this is the CRC value, added after the data field to give transmit data Tx(X),
which is transmitted.
In practice, a stuff bit ( ) and CRC delimiter ( ) are added, so that 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1
is transmitted in the CRC field.
Rev. 1.0, 1/00, page 43 of 119
Next, the calculation is shown which determines whether there is an error in receive data
Rx(X).
Rx(X) is the value obtained by adding the remainder given by the previous calculation to
15
X · P(X). This value is divided by G(X).
P[40:0] = 1010101010100 0000110101010000000000000000
111100000000010
1 0101010101000000110101010111100000000010
+ R[14:0] =
This value is divided by G[15:0].
Quotient
1100010110011001 1 010101010100000 011010101011110 0000000010
1 100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1 100010110011001
taken.
1101011000111101
1100010110011001
1001110100100010
1100010110011001
1011000101110111
1100010110011001
1110100111011101
1100010110011001
1011000100010011
1100010110011001
1110100100010100
1100010110011001
1011001000110100
1100010110011001
1110111101011010
1100010110011001
1010101100001100
1100010110011001
1101110100101010
110 0010110011001
1100010110011001
1100010110011001
0
Remainder
The remainder from the above calculation is zero, so the transmission is considered to be errorfree.
Rev. 1.0, 1/00, page 44 of 119
6. ACK field: For confirmation of normal reception.
Comprises a 1-bit ACK slot and a 1-bit ACK delimiter.
ACK field
ACK slot
ACK delimiter
Figure 2.10 ACK Field
The receiving H8S/2623F-ZTAT outputs a high-level ACK slot if it finds an error in the CRC
check, and a low-level ACK slot if it finds no error.
7. Stuff bits: If there are five consecutive low bits in the data frame, the output is always high for
the next bit. Similarly, if there are five consecutive high bits, the output is always low for the
next bit.
When stuff bits are output in this way, the bit length of the data frame is increased by the
number of stuff bits.
As an example, consider the case where the following settings are made:
Arbitration field: 101010101010
Control field: 000001
The bit pattern in this case is thus 101010101010000001, and so a stuff bit ( ) is output as the
second-but-lowest bit (after the five consecutive 0s).
The value transmitted on the CAN bus is therefore 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 , and the data
frame length is increased by the one stuff bit.
Rev. 1.0, 1/00, page 45 of 119
Values set in arbitration field,
control field, data field
(A)
CRC field
0 1 0 1 0 10 1 0 1 0 1 0 0 0 0 0 0 1 1 01 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1
Stuff bit is
output here
(B)
0101 01 01 01 01000 00101101 0101 0 111 100 0001 00001 0 1
For the data frame to be transmitted, shown in (A), data frame (B), with stuff bits added, is actually
transmitted on the CAN bus. Data frame (B) is longer by the length of the stuff bits.
Figure 2.11 Stuff Bits
8. Configuration mode: In this mode, the HCAN module is in the reset state. This mode is
released by clearing the reset request bit (MCR0) in the master control register (MCR).
Rev. 1.0, 1/00, page 46 of 119
Section 3 HCAN Transmission/Reception (Example 3):
Extended Format, 1-Byte Data
MCU: H8S/2623F-ZTAT
3.1
Function Used: HCAN
Specifications
1
1. Data frame* transmission/reception (using two H8S/2623F-ZTATs).
Data frame specifications are shown in figure 3.1.
a. SOF: Indicates start of data frame.
2
b. Arbitration field*
•
11-bit identifier = 10101010101
•
SRR (Substitute Remote Request) = 1: Select extended format
•
IDE (ID Extension) = 1: Select extended format
•
18-bit identifier = 101010101010101010
•
RTR = 0: Select data frame
3
c. Control field* : Set to 000001.
•
R0 = 0: Reserved bit
•
R1 = 0: Reserved bit
•
DLC = 0001: Set data length of 1 byte
4
d. Data field* : Set to 10101010.
5
e. CRC field* : CRC is generated automatically within the HCAN.
6
f. ACK field* : 11 is output on the transmitting side, and 01 (in normal operation) on the
receiving side.
g. EOF: Indicates the end of a transmit/receive data frame.
2. A communication speed of 1 Mbps (when operating at 20 MHz) is set.
3. The data length is set to 1 byte.
4. Message transmission uses mailbox 1.
5. Message reception uses mailbox 0. The message reception method is to mask the identifier and
receive the message in case of a match.
6. Select interrupt control mode 2, and
a. Use bus operation interrupt (OVR0).
b. Use message reception interrupt (RM0).
Rev. 1.0, 1/00, page 47 of 119
7. Receive messages are stored in on-chip RAM.
8. Use HCAN sleep mode.
a. After initial settings, transfer to HCAN sleep mode (released by CAN bus operation).
b. After reception processing, transfer to HCAN sleep mode (released by CAN bus
operation).
9. Figure 3.2 shows an example of CAN bus connection.
Note: * See 3.9 Notes.
Data frame
Arbitration field
Control field
Data field
1 bit
32 bits
6 bits
8 bits
16 bits
2 bits
7 bits
EOF
SOF
ACK field
CRC field
(With CRC delimiter*5)
11-bit identifier
SRR IDE
18-bit identifier
RTR R1 R0
Note: * See 3.9 Notes.
Figure 3.1 Data Frame Specifications
Rev. 1.0, 1/00, page 48 of 119
DLC
Reception side
H8S/2623F-ZTAT
Transmission side
H8S/2623F-ZTAT
5V
5V
PCA82C250
NC
5
8
HRxD
HTxD
4
1
Vref
Rs
RxD
TxD
Vcc
GND
CANH
CANL
PCA82C250
3
0.1 µF
2
124 Ω
NC
5
8
7
7
6
6
Vref
Rs
Vcc
GND
CANH RxD
CANL
TxD
3
2
0.1 µF
4
1
HRxD
HTxD
124 Ω
CAN bus
Note: A bus transceiver IC is necessary to connect an H8S/2623F-ZTAT to the CAN bus. One compatible with the
Philips PCA82C50 is recommended.
Figure 3.2 CAN Interface Using H8S/2623F-ZTATs
Rev. 1.0, 1/00, page 49 of 119
3.2
Functions
Tables 3.1 to 3.3 show the function allocation of this sample task. This sample task allocates
H8S/2623F-ZTAT on-chip HCAN functions as shown in these tables, and carries out HCAN
transmission and reception.
Table 3.1
HCAN Function Allocation
HCAN Register
Pins
Function
HTxD
Transmits messages.
HRxD
Receives messages.
Transmission/ IRR
reception
BCR
registers
MBCR
Transmission
registers
Reception
registers
Table 3.2
Displays status of each interrupt source.
Sets CAN baud rate prescaler and bit timing parameters.
Sets mailbox transmission/reception.
MCR
Controls CAN interface.
MC0_1
to
MC15_8
Arbitration field and control field settings.
MD0_1
to
MD15_8
Data field settings.
TXPR
Sets transmission wait state after transmit messages are stored in
the mailbox.
TXACK
Indicates that the transmit message of the corresponding mailbox
was transmitted normally.
MBIMR
Sets enabling of mailbox 0 interrupt requests.
IMR
Sets enabling of receive message and bus operation interrupts.
LAFMH, L
Sets filter mask for reception mailbox 0 identifier.
RXPR
Clears receive message interrupt flag.
MSTPCR Function Allocation
MSTPCR Register
Function
MSTPCRC
Controls module stop mode.
Rev. 1.0, 1/00, page 50 of 119
Table 3.3
Interrupt Controller Allocation
IPR Register
Function
IPRM
Controls interrupt priority level.
SYSCR
Sets interrupt control mode.
exr
Specifies interrupt request mask level.
Rev. 1.0, 1/00, page 51 of 119
3.3
Operation
Operation (Transmission)
Figure 3.3 shows the principle of operation during transmission. HCAN transmission is carried out
by H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
Stuff bit*7
ACK field
SOF
Arbitration field
Control
field
Data
field
CRC field
Transmit
data frame
CRC delimiter
EOF
Initial settings
Transmit data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. SOF output
2. Data frame
transmission
3. Automatic generation of stuff bits
1. Automatically
generates and
transmits CRC
calculated from all
bit data except
stuff bits in data
field from SOF
(15 bits)
2. CRC delimiter
(1 bit) output
1. ACK reception
2. Sets transmission
completed flag
Software processing
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 1
for transmission
• Initializes
mailboxes (RAM)
• Sets transmission
format (order of
mailbox numbers)
2. Releases configuration mode
1. Transmit data
settings
• Arbitration field
setting
• Control field
setting
• Data field setting
2. Message
transmission
• Sets mailbox 1
to transmission
wait state
Software processing
None
Software processing
None
Note: * See 3.9 Notes.
Figure 3.3 Operation During HCAN Transmission
Rev. 1.0, 1/00, page 52 of 119
Software processing
1. Clears transmission
completed flag
Operation (Reception)
Figure 3.4 shows the principle of operation during reception. HCAN reception is carried out by
H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
Recessive bits
(recovery from
bus off
to bus idle)
Stuff bit*7
ACK field
Bus idle
Control
field
SOF
Data
field
CRC field
CRC delimiter
Arbitration field
Received
data frame
EOF
Initial settings
Interrupt settings
Receive data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. Bus operation
interrupt
1. Compares received
identifier with filter
mask of mailbox 0
identifier, and if it
matches, stores it
in mailbox
2. Sets reception
completed flag,
receive message
interrupt flag
1. CRC check
2. ACK transmission
Software processing
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
reset flag
• Sets bit rate
• Sets mailbox 0
for reception
• Initializes mailboxes (RAM)
2. Releases configuration mode
1. Interrupt settings
• Sets interrupt
request for
mailbox 0
• Enables message
reception and bus
operation interrupt
• Sets interrupt
control mode
• Sets HCAN
interrupt priority
level
• Sets interrupt
request mask
level
2. Receive data
settings
• Arbitration field
setting
• Filter mask setting
for mailbox 0
identifier
3. HCAN sleep mode
settings
• Sets method of
transferring to and
releasing HCAN
sleep mode
Software processing
1. Clears bus operation interrupt flag
Software processing
None
Software processing
1. Clears receive
message interrupt
flag
2. Stores receive data
3. HCAN sleep mode
setting
• Transfers to
HCAN sleep
mode
Note: * See 3.9 Notes.
Figure 3.4 Operation During HCAN Reception
Rev. 1.0, 1/00, page 53 of 119
3.4
Software
1. Modules
Module Name
Label
Function
Main routine
main
HCAN initial settings and transmission/reception settings.
Bus operation
interrupt routine
OVR0_IRR12
Clears bus operation interrupt flag.
Message
RM0
reception interrupt
routine
Transfers messages stored in mailbox 0 to on-chip RAM.
2. Variables Used
Label
Function
Data Length
Module
COUNT
Initializes HCAN_MC0_1 to MC15_8, and
HCAN_MD0_1 to MD15_8.
Unsigned short
Main routine
3. Internal Registers Used
Register Name
Function
Setting
Module
Main routine
Settings Common to Transmission/Reception
MSTPCRC
Releases HCAN module stop mode.
0xF7
HCAN_BCR
Sets HCAN bit rate to 1 Mbps.
0x0025
Settings for Transmission
HCAN_IRR
Initializes HCAN module reset flag.
0x0100
HCAN_MBCR
Sets mailbox 1 for transmission.
0xFDFF
HCAN_MCR
Sets transmission in order of mailbox numbers,
and clears reset request bit.
0x04
HCAN_MC1_1
Sets 1-byte data length.
0x01
HCAN_MC1_5
Selects mailbox 1 data frame and extended
format, and sets identifier
0xAA
HCAN_MC1_6
Sets mailbox 1 identifier.
0xAA
HCAN_MC1_7
Sets mailbox 1 identifier.
0xAA
HCAN_MC1_8
Sets mailbox 1 identifier.
0xAA
HCAN_MD1_1
Sets transmit data for mailbox 1.
0xAA
HCAN_TXPR
Sets mailbox 1 to transmission wait state.
0x0200
HCAN_TXACK
Clears data frame transmission completed flag.
0x0200
Rev. 1.0, 1/00, page 54 of 119
Main routine
Register Name
Function
Setting
Module
Initializes HCAN module reset flag.
0x0100
Main routine
Clears bus operation interrupt flag.
0x0010
Bus operation
interrupt
Clears reset request bit.
0xFE
Main routine
Sets transfer to HCAN sleep mode and release
by bus operation.
0xA0
Sets transfer to HCAN sleep mode.
0x20
Reception
interrupt
HCAN_MBCR
Sets mailbox 0 for reception.
0x0100
Main routine
HCAN_MC0_5
Selects mailbox 0 data frame and extended
format, and sets identifier.
0xAA
HCAN_MC0_6
Sets mailbox 0 identifier.
0xAA
HCAN_MC0_7
Sets mailbox 0 identifier.
0xAA
HCAN_MC0_8
Sets mailbox 0 identifier.
0xAA
HCAN_LAFMH
Sets filter mask for mailbox 0 identifier.
0x0000
HCAN_LAFML
Sets filter mask for mailbox 0 identifier.
0x0000
HCAN_MBIMR
Sets enabling of mailbox 0 interrupt requests.
0xFEFF
HCAN_IMR
Sets enabling of message reception and bus
operation interrupt requests.
0xFCEF
INTC.IPRM
Sets HCAN interrupt priority level to 7.
0x70
SYSCR
Sets interrupt control mode 2.
0x20
exr
Specifies interrupt request mask level.
0x00
HCAN_RXPR
Clears receive message interrupt flag.
0xFFFF
Settings for Reception
HCAN_IRR
HCAN_MCR
Reception
interrupt
Note: Reception interrupt: Message reception interrupt routine
Bus operation: Bus operation interrupt routine
4. RAM Used
Symbol
Function
Address
Module
0xFFC100
Main routine
Settings for Reception
Message_DATA
Storage destination address for mailbox 0
data.
Rev. 1.0, 1/00, page 55 of 119
3.5
Transmission Flowchart
Transmit operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (1 Mbps)
• Set mailbox 1 for transmission
• Initialize mailbox (RAM)
• Set transmission format (order of mailbox
numbers)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Transmit data settings
• Set arbitration field
• Set control field
• Set data field
Message transmission
• Set mailbox 1 to transmission wait state
No
End of transmission?
Yes
Transmission
completed flag set?
No
Yes
: Set by user
Clear transmission completed flag
: Processed by hardware
End of transmission
Note: * See 3.9 Notes.
Figure 3.5 Transmission Flowchart
Rev. 1.0, 1/00, page 56 of 119
3.6
Transmission Program List
/********************************************************************************/
/*
HCAN Transmission Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT (*(unsigned short *)0xFFC000)
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial Settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0025;
/* Bit rate: 1 Mbps
*/
HCAN_MBCR = 0xFDFF;
/* Set mailbox 1 for transmission
*/
for( COUNT = 0; COUNT < 128; COUNT++ )
*/
/* Initialize mailbox (RAM)
*/
/* Initialize mailbox (RAM)
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR = 0x04;
/* Set transmission in order of mailbox numbers, and release configuration
mode */
/* Transmit data settings */
HCAN_MC1_5 = 0xAA;
/* Select data frame and extended format, and set identifier */
HCAN_MC1_6 = 0xAA;
/* Set identifier
*/
Rev. 1.0, 1/00, page 57 of 119
HCAN_MC1_7 = 0xAA;
/* Set identifier
*/
HCAN_MC1_8 = 0xAA;
/* Set identifier
*/
HCAN_MC1_1 = 0x01;
/* Data length: 1 byte
*/
HCAN_MD1_1 = 0xAA;
/* Message contents: 10101010
*/
/* Message transmission */
HCAN_TXPR = 0x0200;
/* Set mailbox 1 to transmission wait state */
while((HCAN_TXACK & 0x0200) != 0x0200);
/* Clear transmission completed flag */
HCAN_TXACK &= 0x0200;
while(1);
}
Rev. 1.0, 1/00, page 58 of 119
/* Clear transmission completed flag */
3.7
Reception Flowcharts
Receive operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (1 Mbps)
• Set mailbox 0 for reception
• Initialize mailboxes (RAM)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Interrupt settings
• Set mailbox 0 interrupt request
• Enable message reception and bus
operation interrupt
• Set interrupt control mode 2
• Set HCAN interrupt priority level
• Specify interrupt request mask level
Receive data settings
• Set arbitration field
• Set filter mask for mailbox 0 identifier
HCAN sleep mode settings
• Set method of transferring to and
releasing HCAN sleep mode
Is there a bus operation?
No
Yes
No
11-bit recessive reception?
Yes
: Set by user
CAN bus communication enabled
: Processed by hardware
EXIT
Note: * See 3.9 Notes.
Figure 3.6 Reception Flowchart (1)
Rev. 1.0, 1/00, page 59 of 119
EXIT
Message received?
No
Yes
CRC check
ACK transmission
Compare filter mask for mailbox 0 identifier
with received identifier
Store receive data
Set reception completed flag and receive
message interrupt flag
End of reception
Figure 3.6 Reception Flowchart (2)
Rev. 1.0, 1/00, page 60 of 119
: Processed by hardware
Bus operation interrupt routine
Clear bus operation interrupt flag
RTE
: Set by user
Figure 3.7 Bus Operation Interrupt Flowchart
Message reception interrupt routine
Clear receive message interrupt flag
Store receive data in on-chip RAM
Set HCAN sleep mode
• Transfer to HCAN sleep mode
RTE
: Set by user
Figure 3.8 Message Reception Interrupt Flowchart
Rev. 1.0, 1/00, page 61 of 119
3.8
Reception Program List
/********************************************************************************/
/*
HCAN Reception Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT
(*(unsigned short *)0xFFC000)
#define Message_DATA (*(unsigned char
*)0xFFC100)
/* Store receive data */
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0025;
/* Bit rate: 1 Mbps
*/
HCAN_MBCR = 0x0100;
/* Set mailbox 0 for reception
*/
for( COUNT = 0; COUNT < 128; COUNT++ )
*/
/* Initialize mailbox (RAM) */
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM) */
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR &= 0xFE;
/* Release configuration mode
*/
/* Enable mailbox 0 interrupt request
*/
/* Interrupt settings */
HCAN_MBIMR = 0xFEFF;
HCAN_IMR = 0xFCEF;
/* Enable message reception and bus operation interrupt */
SYSCR |= 0x20;
Rev. 1.0, 1/00, page 62 of 119
/* Set interrupt control mode 2
*/
INTC.IPRM = 0x70;
/* Set HCAN interrupt priority level to 7 */
set_imask_exr(0);
/* Specify interrupt request mask level
*/
/* Reception data settings */
HCAN_MC0_5 = 0xAA;
/* Set extended format, data frame, and identifier */
HCAN_MC0_6 = 0xAA;
/* Set identifier
*/
HCAN_MC0_7 = 0xAA;
/* Set identifier
*/
/* Set identifier
*/
HCAN_MC0_8 = 0xAA;
HCAN_LAFMH = 0x0000;
/* Mailbox 0 stores data in case of bit match */
HCAN_LAFML = 0x0000;
/* Mailbox 0 stores data in case of bit match */
/* HCAN sleep mode setting */
HCAN_MCR |= 0xA0;
/* Enable transfer to HCAN mode and release by bus operation */
while(1);
}
/********************************************************************************/
/*
Bus Operation Interrupt Routine
*/
/********************************************************************************/
#pragma interrupt(OVR0_IRR12)
void OVR0_IRR12(void)
{
HCAN_IRR &= 0x0010;
/* Clear IRR12 (bus operation interrupt flag)
*/
}
/********************************************************************************/
/*
Message Reception Interrupt Routine
*/
/********************************************************************************/
#pragma interrupt(RM0)
void RM0(void)
{
HCAN_RXPR &= 0xFFFF;
Message_DATA = HCAN_MD0_1;
/* Clear IRR1 (receive message interrupt flag) */
/* Store receive data
*/
/* HCAN sleep mode setting */
HCAN_MCR |= 0x20;
/* Transfer to HCAN sleep mode */
}
Rev. 1.0, 1/00, page 63 of 119
3.9
Notes
1. Data frame: Data to be transferred from the transmission source to the transmission
destination.
2. Arbitration field: Set unique ID for message and data frame or remote frame.
3. Control field: Set the data length to be transmitted, and standard format or extended format.
4. Data field: Set message contents (data to be transmitted).
5. CRC field: A CRC is generated automatically in the HCAN from all bit data except stuff bits
in the data field from SOF, and is used to detect transmit message errors.
The CRC field comprises a 15-bit CRC and a 1-bit delimiter.
The CRC delimiter is always output as a 1 after the CRC.
CRC field
CRC
CRC delimiter
Figure 3.9 CRC Field
About the CRC:
R
R
Transmit data polynomial P(X) is multiplied by X , then X · P(X) is divided by generating
polynomial G(X) to give a remainder, R(X). On the side transmitting information, R(X) found
R
from X · P(X) is added as check bits, and the result is sent as transmit data Tx(X).
On the side receiving the information, receive data Rx(X) is divided by generating polynomial
G(X) to give a remainder. If this remainder is zero, information transmission is regarded as
having been completed normally. If the remainder is nonzero, an error is judged to have
occurred in the information transmitted.
P(X) = {SOF through data field, excluding stuff bits}
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
R = 15
Note: G(X) is stipulated in the CAN protocol as the polynomial that generates the CRC.
Rev. 1.0, 1/00, page 64 of 119
As an example, the procedure is described below for a data frame transmitted using the
following settings.
Settings SOF: 0
Arbitration field: 101010101010
Control field: 000001
Data field: 10101010
The bit pattern from SOF through the data field in the transmitted data is as follows
( indicates the stuff bit):
0–1010101010100000–1–0110101010
Data field
SOF
Control field
Arbitration field
Excluding the stuff bit gives the following data subject to CRC computation:
010101010101000000110101010
Thus,
25
23
21
19
17
15
8
7
5
3
P(X) = X + X + X + X + X + X + X + X + X + X + X
1
15
P(X) is multiplied by X , giving:
15
40
38
36
34
32
30
23
22
20
18
X · P(X) = X + X + X + X + X + X + X + X + X + X + X
16
and this value is divided by
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
Rev. 1.0, 1/00, page 65 of 119
X15 . P(X) = X40 + X38 + X36 + X34 + X32 + X30 + X23 + X22 + X20 + X18 + X16
P[40:0] = 10101010101000000110101010000000000000000
G(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1
G[15:0] = 1100010110011001
Quotient
1100010110011001 10101010101000000110101010000000000000000
1100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1100010110011001
taken.
1101011000111101
1 1 0 0 0 1 0 1 1 0 0 1 1 0 01
1001110100100010
1100010110011001
1011000101110110
1100010110011001
1110100111011110
1100010110011001
1011000100011100
1100010110011001
1110100100001010
1100010110011001
1011001001001100
1100010110011001
1110111110101010
1100010110011001
1010100011001100
1100010110011001
1101101010101010
1100010110011001
1111100110011000
1100010110011001
111100000000010
Remainder:
R[14:0]
The following value is obtained from the calculation.
R [14:0] = 111100000000010
In other words, this is the CRC value, added after the data field to give transmit data Tx(X),
which is transmitted.
In practice, a stuff bit ( ) and CRC delimiter ( ) are added, so that 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1
is transmitted in the CRC field.
Rev. 1.0, 1/00, page 66 of 119
Next, the calculation is shown which determines whether there is an error in receive data
Rx(X).
Rx(X) is the value obtained by adding the remainder given by the previous calculation to
15
X · P(X). This value is divided by G(X).
P[40:0] = 1010101010100 0000110101010000000000000000
111100000000010
1 0101010101000000110101010111100000000010
+ R[14:0] =
This value is divided by G[15:0].
Quotient
1100010110011001 1 010101010100000 011010101011110 0000000010
1 100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1 100010110011001
taken.
1101011000111101
1100010110011001
1001110100100010
1100010110011001
1011000101110111
1100010110011001
1110100111011101
1100010110011001
1011000100010011
1100010110011001
1110100100010100
1100010110011001
1011001000110100
1100010110011001
1110111101011010
1100010110011001
1010101100001100
1100010110011001
1101110100101010
110 0010110011001
1100010110011001
1100010110011001
0
Remainder
The remainder from the above calculation is zero, so the transmission is considered to be errorfree.
Rev. 1.0, 1/00, page 67 of 119
6. ACK field: For confirmation of normal reception.
Comprises a 1-bit ACK slot and a 1-bit ACK delimiter.
ACK field
ACK slot
ACK delimiter
Figure 3.10 ACK Field
The receiving H8S/2623F-ZTAT outputs a high-level ACK slot if it finds an error in the CRC
check, and a low-level ACK slot if it finds no error.
7. Stuff bits: If there are five consecutive low bits in the data frame, the output is always high for
the next bit. Similarly, if there are five consecutive high bits, the output is always low for the
next bit.
When stuff bits are output in this way, the bit length of the data frame is increased by the
number of stuff bits.
As an example, consider the case where the following settings are made:
Arbitration field: 101010101010
Control field: 000001
The bit pattern in this case is thus 101010101010000001, and so a stuff bit ( ) is output as the
second-but-lowest bit (after the five consecutive 0s).
The value transmitted on the CAN bus is therefore 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 , and the data
frame length is increased by the one stuff bit.
Rev. 1.0, 1/00, page 68 of 119
Values set in arbitration field,
control field, data field
(A)
CRC field
0 1 0 1 0 10 1 0 1 0 1 0 0 0 0 0 0 1 1 01 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1
Stuff bit is
output here
(B)
0101 01 01 01 01000 00101101 0101 0 111 100 0001 00001 0 1
For the data frame to be transmitted, shown in (A), data frame (B), with stuff bits added, is actually
transmitted on the CAN bus. Data frame (B) is longer by the length of the stuff bits.
Figure 3.11 Stuff Bits
8. Configuration mode: In this mode, the HCAN module is in the reset state. This mode is
released by clearing the reset request bit (MCR0) in the master control register (MCR).
Rev. 1.0, 1/00, page 69 of 119
Section 4 HCAN Transmission/Reception (Example 4):
Standard Format, 8-Byte Data, Prioritized
MCU: H8S/2623F-ZTAT
4.1
Function Used: HCAN, DTC
Specifications
1
1. Data frame* transmission/reception (using two H8S/2623F-ZTATs).
Data frame specifications are shown in figure 4.1.
a. SOF: Indicates start of data frame.
2
b. Arbitration field*
•
Mailbox 1:
110011001100 (H'CCC) → Priority is 12 highest.
•
Mailbox 2:
010101010100 (H'554) → Priority is 5 highest.
•
Mailbox 3:
111011101110 (H'EEE) → Priority is 14 highest.
•
Mailbox 4:
011001100110 (H'666) → Priority is 6 highest.
•
Mailbox 5:
000100010000 (H'110) → Priority is highest.
•
Mailbox 6:
100110011000 (H'998) → Priority is 9 highest.
•
Mailbox 7:
001100110010 (H'332) → Priority is 3 highest.
•
Mailbox 8:
111111111110 (H'FFE) → Priority is lowest.
•
Mailbox 9:
001000100010 (H'222) → Priority is 2 highest.
•
Mailbox 10: 100010001000 (H'888) → Priority is 8 highest.
•
Mailbox 11: 101010101010 (H'AAA)→ Priority is 10 highest.
•
Mailbox 12: 110111011100 (H'DDC)→ Priority is 13 highest.
•
Mailbox 13: 011101110110 (H'776) → Priority is 7 highest.
•
Mailbox 14: 010001000100 (H'444) → Priority is 4 highest.
•
Mailbox 15: 101110111010 (H'BBA) → Priority is 11 highest.
th
th
th
th
th
rd
nd
th
th
th
th
th
th
3
c. Control field* : Set to 00100. (Mailboxes 1 to 15)
•
IDE = 0: Select standard format
•
RO = 0: Reserved bit
•
DLC = 1000: Set data length of 8 bytes
4
d. Data field* : Set to 10101010.
•
Mailbox 1:
H'1111111111111111
•
Mailbox 2:
H'2222222222222222
•
Mailbox 3:
H'3333333333333333
•
Mailbox 4:
H'4444444444444444
•
Mailbox 5:
H'5555555555555555
•
Mailbox 6:
H'6666666666666666
Rev. 1.0, 1/00, page 71 of 119
•
Mailbox 7:
H'7777777777777777
•
Mailbox 8:
H'8888888888888888
•
Mailbox 9:
H'9999999999999999
•
Mailbox 10: H'AAAAAAAAAAAAAAAA
•
Mailbox 11: H'BBBBBBBBBBBBBBBB
•
Mailbox 12: H'CCCCCCCCCCCCCCCC
•
Mailbox 13: H'DDDDDDDDDDDDDDDD
•
Mailbox 14: H'EEEEEEEEEEEEEEEE
•
Mailbox 15: H'FFFFFFFFFFFFFFFF
5
e. CRC field* : CRC is generated automatically within the HCAN. (Mailboxes 1 to 15)
6
f. ACK field* : 11 is output on the transmitting side, and 01 (in normal operation) on the
receiving side. (Mailboxes 1 to 15)
g. EOF: Indicates the end of a transmit/receive data frame. (Mailboxes 1 to 15)
2. A communication speed of 1 Mbps (when operating at 20 MHz) is set.
3. The data length is set to 8 bytes. (Mailboxes 1 to 15)
4. Message transmission uses mailboxes 1 to 15.
5. Message reception uses mailboxes 0 to 15. The message reception method for mailbox 0 is to
mask the identifier and receive the message in case of a match.
6. Messages are transmitted in message identifier priority order.
7. Receive messages are stored in on-chip RAM using the DTC.
a. After all messages have been received, the DTC is started by software.
b. Use block transfer mode.
8. After a DTC transfer end interrupt, transfer to HCAN sleep mode.
9. Figure 4.2 shows an example of CAN bus connection.
Note: * See 4.9 Notes.
Rev. 1.0, 1/00, page 72 of 119
Data frame
Arbitration field
Control field
Data field
CRC field
(With CRC delimiter*5)
ACK field
EOF
SOF
1 bit
12 bits
8 bits × 8
6 bits
16 bits
2 bits
7 bits
15 transmissions/
receptions
Identifier
RTR IDE
R0
DLC
Note: * See 4.9 Notes.
Figure 4.1 Data Frame Specifications
Transmission side
H8S/2623F-ZTAT
Reception side
H8S/2623F-ZTAT
5V
5V
PCA82C250
NC
5
8
HRxD
HTxD
4
1
Vref
Rs
Vcc
GND
RxD
CANH
TxD
CANL
PCA82C250
3
0.1 µF
2
124 Ω
NC
5
8
7
7
6
6
Vref
Rs
Vcc
GND
CANH RxD
CANL
TxD
3
2
0.1 µF
4
1
HRxD
HTxD
124 Ω
CAN bus
Note: A bus transceiver IC is necessary to connect an H8S/2623F-ZTAT to the CAN bus. One compatible with the
Philips PCA82C50 is recommended.
Figure 4.2 CAN Interface Using H8S/2623F-ZTATs
Rev. 1.0, 1/00, page 73 of 119
4.2
Functions
Tables 4.1 to 4.4 show the function allocation of this sample task. This sample task allocates
H8S/2623F-ZTAT on-chip HCAN functions as shown in these tables, and carries out HCAN
transmission and reception.
Table 4.1
HCAN Function Allocation
HCAN Register
Pins
Function
HTxD
Transmits messages.
HRxD
Receives messages.
Transmission/ IRR
reception
BCR
registers
MBCR
Transmission
registers
Reception
registers
Table 4.2
Displays status of each interrupt source.
Sets CAN baud rate prescaler and bit timing parameters.
Sets mailbox transmission/reception.
MCR
Controls CAN interface.
MC0_1 to
MC15_8
Arbitration field and control field settings.
MD0_1 to
MD15_8
Data field settings.
TXPR
Sets transmission wait state after transmit messages are stored in
the mailbox.
TXACK
Indicates that the transmit message of the corresponding mailbox
was transmitted normally.
LAFMH
Sets filter mask for reception mailbox 0 identifier.
RXPR
Indicates that data has been received normally by the corresponding
mailbox.
MSTPCR Function Allocation
MSTPCR Register
Function
MSTPCRC
Controls module stop mode.
MSTPCRA
Table 4.3
Interrupt Controller Allocation
IPR Register
Function
IPRC
Controls interrupt priority level.
SYSCR
Sets interrupt control mode.
exr
Specifies interrupt request mask level.
Rev. 1.0, 1/00, page 74 of 119
Table 4.4
DTC Function Allocation
DTC Register
Function
SAR (On-chip RAM)
Sets source address (where receive messages are stored from).
DAR (On-chip RAM)
Sets destination address (where receive messages are stored to).
MAR (On-chip RAM)
Sets block transfer mode, byte size transfer, etc.
MRB (On-chip RAM)
Sets interrupt to CPU after DTC data transfer.
CRA (On-chip RAM)
Sets number of DTC data transfers.
CRB (On-chip RAM)
Sets number of DTC block data transfers.
DTVECR (Register)
Sets DTC start by software, and vector number.
Rev. 1.0, 1/00, page 75 of 119
4.3
Operation
Operation (Transmission)
Figure 4.3 shows the principle of operation during transmission. HCAN transmission is carried out
by H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
14 asserts
Response of
receiving side
CRC delimiter
ACK field
SOF
Arbitration field
Control
field
Data field
CRC field
14 transfers
Stuff bits*7
Transmit
data frame
EOF
H'55 H'55 H'55 H'55 H'55 H'55 H'55 H'55
Data field (1st time)
Initial settings
Transmit data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. SOF output
2. Data frame
transmission
3. Automatic generation of stuff bits
1. Automatically
generates and
transmits CRC
calculated from all
bit data except stuff
bits in data field
from SOF (15 bits)
2. CRC delimiter
(1 bit) output
1. ACK reception
2. Sets transmission
completed flag
Software processing
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 1
for transmission
• Initializes
mailboxes (RAM)
• Sets transmission
format (message
identifier priority
order)
2. Releases configuration mode
1. Transmit data
settings
• Arbitration field
setting
• Control field
setting
• Data field setting
2. Message
transmission
• Sets mailboxes 1
to 15 to transmission wait state
Software processing
None
Software processing
None
15 transmissions
Note: * See 4.9 Notes.
Figure 4.3 Operation During HCAN Transmission
Rev. 1.0, 1/00, page 76 of 119
Software processing
1. Clears transmission
completed flag
Operation (Reception)
Figure 4.4 shows the principle of operation during reception. HCAN reception is carried out by
H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
14 asserts
Response of
receiving side
CRC delimiter
ACK field
SOF
Arbitration field
Control
field
Data field
CRC field
14 transmissions
Stuff bits*7
Received data
frame
EOF
H'55 H'55 H'55 H'55 H'55 H'55 H'55 H'55
Data field (1st time)
Initial settings
Receive data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to configuration mode
1. Sets normal
operation state
1. Compares received
identifier with filter
mask of mailbox 0
identifier, and if it
matches, stores it
in mailbox
2. Compares received
identifier with identifier of mailboxes 1
to 15, and if it
matches, stores it
in that mailbox
3. Sets reception
completed flag
1. CRC check
2. ACK transmission
1. Generates DTC
transfer end
interrupt
Software processing
Software processing
1. DTC initial settings
• Releases DTC
module stop
mode
• Initializes DTC
2. HCAN initial
settings
• Release HCAN
module stop
mode
• Initializes HCAN
reset flag
• Sets bit rate
• Sets mailboxes 0
to 15 for reception
• Initializes mailboxes (RAM)
3. Releases configuration mode
1. Receive data
settings
• Arbitration field
setting
• Filter mask setting
for mailbox 0
identifier
Software processing
None
Note: * See 4.9 Notes.
Software processing
1. Confirms completion of reception
2. Interrupt settings
• Sets interrupt
control mode 2
• Sets DTC interrupt priority level
• Specifies interrupt
request mask
level
3. DTC software start
• Sets vector
number
• Confirms vector
number
• Enables DTC
software start
Software processing
1. Disables DTC
software start
2. HCAN sleep mode
setting
• Transfers to
HCAN sleep
mode
15 transmissions
Figure 4.4 Operation During HCAN Reception
Rev. 1.0, 1/00, page 77 of 119
4.4
Software
1. Modules
Module Name
Label
Function
Main routine
main
HCAN initial settings and transmission/reception settings.
DTC transfer end
interrupt routine
SWDTEND
Disables DTC software startup and transfers to HCAN sleep
mode.
2. Variables Used
Label
Function
Data Length
Module
COUNT
Initializes HCAN_MCO_1 to MC15_8, and
HCAN_MDO_1 to MD15_8.
Unsigned short
Main routine
3. Internal Registers Used
Register Name
Function
Setting
Module
Main routine
Settings Common to Transmission/Reception
MSTPCRC
Releases HCAN module stop mode.
0xF7
HCAN_BCR
Sets HCAN bit rate to 1 Mbps.
0x0025
HCAN_IRR
Initializes HCAN module reset flag.
0x0100
Settings for Transmission
HCAN_MBCR
Sets mailboxes 1 to 15 for transmission.
0x0100
HCAN_MCR
Sets transmission in order of priority of
message identifier, and clears reset request bit.
0x00
HCAN_MC1 to
15_1
Sets 8-byte data length.
All 0x08
HCAN_MC1_5
Select mailbox 1 data frame and standard
format, and set identifier.
0xC0
HCAN_MC1_6
HCAN_MC2_5
HCAN_MC2_6
HCAN_MC3_5
HCAN_MC3_6
Select mailbox 2 data frame and standard
format, and set identifier.
Select mailbox 3 data frame and standard
format, and set identifier.
Rev. 1.0, 1/00, page 78 of 119
0xCC
0x40
0x55
0xE0
0xEE
Main routine
Register Name
Function
Setting
Module
0x60
Main routine
Settings for Transmission
HCAN_MC4_5
HCAN_MC4_6
HCAN_MC5_5
HCAN_MC5_6
HCAN_MC6_5
HCAN_MC6_6
HCAN_MC7_5
HCAN_MC7_6
HCAN_MC8_5
HCAN_MC8_6
HCAN_MC9_5
HCAN_MC9_6
HCAN_MC10_5
HCAN_MC10_6
HCAN_MC11_5
HCAN_MC11_6
HCAN_MC12_5
HCAN_MC12_6
HCAN_MC13_5
HCAN_MC13_6
HCAN_MC14_5
HCAN_MC14_6
HCAN_MC15_5
HCAN_MC15_6
Select mailbox 4 data frame and standard
format, and set identifier.
Select mailbox 5 data frame and standard
format, and set identifier.
Select mailbox 6 data frame and standard
format, and set identifier.
0x66
0x00
0x11
0x80
0x99
0x20
Select mailbox 7 data frame and standard
format, and set identifier.
0x33
Select mailbox 8 data frame and standard
format, and set identifier.
0xFF
Select mailbox 9 data frame and standard
format, and set identifier.
Select mailbox 10 data frame and standard
format, and set identifier.
0xE0
0x20
0x22
0x80
0x88
Select mailbox 11 data frame and standard
format, and set identifier.
0xA0
Select mailbox 12 data frame and standard
format, and set identifier.
0xC0
0xDD
Select mailbox 13 data frame and standard
format, and set identifier.
0x77
Select mailbox 14 data frame and standard
format, and set identifier.
Select mailbox 15 data frame and standard
format, and set identifier.
0xAA
0x60
0x40
0x44
0xA0
0xBB
st
th
All 0x11
st
th
All 0x22
st
th
All 0x33
st
th
All 0x44
st
th
All 0x55
HCAN_MD1_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
1.
HCAN_MD2_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
2.
HCAN_MD3_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
3.
HCAN_MD4_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
4.
HCAN_MD5_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
5.
Rev. 1.0, 1/00, page 79 of 119
Register Name
Function
Setting
Module
Main routine
Settings for Transmission
st
th
All 0x66
st
th
All 0x77
st
th
All 0x88
st
th
All 0x99
st
th
All 0xAA
st
th
All 0xBB
st
th
All 0xCC
st
th
All 0xDD
st
th
All 0xEE
Sets transmit data for 1 to 8 bytes of mailbox
15.
st
th
All 0xFF
HCAN_TXPR
Sets mailboxes 1 to 15 to transmission wait
state.
0xFEFF
HCAN_TXACK
Clears data frame transmission completed flag.
0xFEFF
HCAN_MD6_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
6.
HCAN_MD7_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
7.
HCAN_MD8_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
8.
HCAN_MD9_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
9.
HCAN_MD10_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
10.
HCAN_MD11_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
11.
HCAN_MD12_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
12.
HCAN_MD13_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
13.
HCAN_MD14_1
to 8
Sets transmit data for 1 to 8 bytes of mailbox
14.
HCAN_MD15_1
to 8
Settings for Reception
MSTPCRA
HCANMCR
Releases DTC module stop mode.
0x3F
Clears reset request bit.
0xFE
Transfers to HCAN sleep mode.
0x20
HCAN_MBCR
Sets mailboxes 0 to 15 for reception.
0xFFFF
HCAN_LAFMH
Sets filter mask for mailbox 0 identifier.
0x0000
HCAN_RXPR
Clears message reception completed flag.
0xFFFF
SYSCR
Sets interrupt control mode 2.
0x20
INTC. IPRC
Sets DTC interrupt priority level to 7.
0x07
exr
Specifies interrupt request mask level.
0x00
Rev. 1.0, 1/00, page 80 of 119
Main routine
Register Name
Function
Setting
Module
Sets vector number.
0x60
Main routine
Enables DTC software startup.
0x80
Settings for Reception
DTC_DTVECR
HCAN_MC0_5
HCAN_MC0_6
HCAN_MC1_5
HCAN_MC1_6
HCAN_MC2_5
HCAN_MC2_6
HCAN_MC3_5
HCAN_MC3_6
HCAN_MC4_5
HCAN_MC4_6
HCAN_MC5_5
HCAN_MC5_6
HCAN_MC6_5
HCAN_MC6_6
HCAN_MC7_5
HCAN_MC7_6
HCAN_MC8_5
HCAN_MC8_6
HCAN_MC9_5
HCAN_MC9_6
HCAN_MC10_5
HCAN_MC10_6
HCAN_MC11_5
HCAN_MC11_6
HCAN_MC12_5
HCAN_MC12_6
HCAN_MC13_5
HCAN_MC13_6
Disables DTC software startup.
0x7F
End interrupt
Select mailbox 0 data frame and standard
format, and set identifier.
0xA0
Main routine
Select mailbox 1 data frame and standard
format, and set identifier.
0x00
0x11
Select mailbox 2 data frame and standard
format, and set identifier.
0x22
Select mailbox 3 data frame and standard
format, and set identifier.
Select mailbox 4 data frame and standard
format, and set identifier.
Select mailbox 5 data frame and standard
format, and set identifier.
Select mailbox 6 data frame and standard
format, and set identifier.
Select mailbox 7 data frame and standard
format, and set identifier.
Select mailbox 8 data frame and standard
format, and set identifier.
Select mailbox 9 data frame and standard
format, and set identifier.
0xAA
0x20
0x20
0x33
0x40
0x44
0x40
0x55
0x60
0x66
0x60
0x77
0x80
0x88
0x80
0x99
Select mailbox 10 data frame and standard
format, and set identifier.
0xA0
Select mailbox 11 data frame and standard
format, and set identifier.
0xA0
Select mailbox 12 data frame and standard
format, and set identifier.
0xC0
Select mailbox 13 data frame and standard
format, and set identifier.
0xAA
0xBB
0xCC
0xC0
0xDD
Note: End interrupt: DTC transfer end interrupt routine
Rev. 1.0, 1/00, page 81 of 119
Register Name
Function
Setting
Module
Select mailbox 14 data frame and standard
format, and set identifier.
0xE0
Main routine
Select mailbox 15 data frame and standard
format, and set identifier.
0xE0
Settings for Reception
HCAN_MC14_5
HCAN_MC14_6
HCAN_MC15_5
HCAN_MC15_6
0xEE
0xFF
4. RAM Used
Symbol
Function
Address
Module
MAILBOX0.
Message_DATA1 to 8
Store data for HCAN_MD0_1 to 8.
0xFFC100 to 7
Main routine
MAILBOX1.
Message_DATA1 to 8
Store data for HCAN_MD1_1 to 8.
0xFFC108 to F
MAILBOX2.
Message_DATA1 to 8
Store data for HCAN_MD2_1 to 8.
0xFFC110 to 7
MAILBOX3.
Message_DATA1 to 8
Store data for HCAN_MD3_1 to 8.
0xFFC118 to F
MAILBOX4.
Message_DATA1 to 8
Store data for HCAN_MD4_1 to 8.
0xFFC120 to 7
MAILBOX5.
Message_DATA1 to 8
Store data for HCAN_MD5_1 to 8.
0xFFC128 to F
MAILBOX6.
Message_DATA1 to 8
Store data for HCAN_MD6_1 to 8.
0xFFC130 to 7
MAILBOX7.
Message_DATA1 to 8
Store data for HCAN_MD7_1 to 8.
0xFFC138 to F
MAILBOX8.
Message_DATA1 to 8
Store data for HCAN_MD8_1 to 8.
0xFFC140 to 7
MAILBOX9.
Message_DATA1 to 8
Store data for HCAN_MD9_1 to 8.
0xFFC148 to F
MAILBOX10.
Message_DATA1 to 8
Store data for HCAN_MD10_1 to 8.
0xFFC150 to 7
MAILBOX11.
Message_DATA1 to 8
Store data for HCAN_MD11_1 to 8.
0xFFC158 to F
MAILBOX12.
Message_DATA1 to 8
Store data for HCAN_MD12_1 to 8.
0xFFC160 to 7
Settings for Reception
Rev. 1.0, 1/00, page 82 of 119
Symbol Name
Function
Address
Module
MAILBOX13.
Message_DATA1 to 8
Store data for HCAN_MD13_1 to 8.
0xFFC168 to F
Main routine
MAILBOX14.
Message_DATA1 to 8
Store data for HCAN_MD14_1 to 8.
0xFFC170 to 7
MAILBOX15.
Message_DATA1 to 8
Store data for HCAN_MD15_1 to 8.
0xFFC178 to F
SAR
Sets source address (where receive
messages are stored from).
0xFFEC01 to 3
(0xFFF8B0)
MRA
Sets block transfer mode, byte size
transfer, etc.
0xFFEC00
(0xA8)
DAR
Sets destination address (where receive
messages are stored to).
0xFFEC05 to 7
(0xFFC100)
MRB
Enables interrupt to CPU after DTC
data transfer ends.
0xFFEC04
(0x00)
CRA
Sets transfer block size retained value
for DTC data transfer (upper byte) and
transfer block size counter (lower byte).
0xFFEC08, 9
(0x8080)
CRB
Sets number of DTC block transfers.
0xFFEC0A, B
(0x0001)
Settings for Reception
Figures in parentheses are settings.
Rev. 1.0, 1/00, page 83 of 119
4.5
Transmission Flowchart
Transmit operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (1 Mbps)
• Set mailboxes 1 to 15 for transmission
• Initialize mailboxes (RAM)
• Set transmission format (message
identifier priority order)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Transmit data settings
• Set arbitration field
• Set control field
• Set data field
Message transmission
• Set mailboxes 1 to 15 to transmission
wait state
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Mailbox 5 message transmission
Mailbox 9 message transmission
Mailbox 7 message transmission
Mailbox 14 message transmission
Mailbox 2 message transmission
Mailbox 4 message transmission
Mailbox 13 message transmission
Mailbox 10 message transmission
Mailbox 6 message transmission
Mailbox 11 message transmission
Mailbox 15 message transmission
Mailbox 12 message transmission
Mailbox 3 message transmission
Mailbox 8 message transmission
No
End of transmission?
Yes
Transmission
completed flag set?
No
: Set by user
Yes
Clear transmission completed flag
End of transmission
: Processed by hardware
Note: * See 4.9 Notes.
Figure 4.5 Transmission Flowchart
Rev. 1.0, 1/00, page 84 of 119
4.6
Transmission Program List
/********************************************************************************/
/*
HCAN Transmission Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT (*(unsigned short *)0xFFC000)
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial Settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0025;
/* Bit rate: 1 Mbps
HCAN_MBCR = 0x0100;
*/
*/
/* Set mailboxes 1 to 15 for transmission */
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailboxes (RAM)
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailboxes (RAM)
*/
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR = 0x00;
/* Set transmission in message identifier priority order */
/* Transmit data settings */
/*******
Mail Box 1
*******/
HCAN_MC1_5 = 0xC0;
/* Set standard format, data frame, and identifier */
Rev. 1.0, 1/00, page 85 of 119
HCAN_MC1_6 = 0xCC;
/* Set identifier
*/
HCAN_MC1_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD1_1 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_2 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_3 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_4 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_5 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_6 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_7 = 0x11;
/* Message contents: 00010001
*/
HCAN_MD1_8 = 0x11;
/* Message contents: 00010001
*/
/*******
Mail Box 2
*******/
HCAN_MC2_5 = 0x40;
/* Set standard format, data frame, and identifier */
HCAN_MC2_6 = 0x55;
/* Set identifier
*/
HCAN_MC2_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD2_1 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_2 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_3 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_4 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_5 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_6 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_7 = 0x22;
/* Message contents: 00100010
*/
HCAN_MD2_8 = 0x22;
/* Message contents: 00100010
*/
/*******
Mail Box 3
*******/
HCAN_MC3_5 = 0xE0;
/* Set standard format, data frame, and identifier */
HCAN_MC3_6 = 0xEE;
/* Set identifier
*/
HCAN_MC3_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD3_1 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_2 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_3 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_4 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_5 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_6 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_7 = 0x33;
/* Message contents: 00110011
*/
HCAN_MD3_8 = 0x33;
/* Message contents: 00110011
*/
/*******
Mail Box 4
*******/
HCAN_MC4_5 = 0x60;
/* Set standard format, data frame, and identifier */
HCAN_MC4_6 = 0x66;
/* Set identifier
*/
HCAN_MC4_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD4_1 = 0x44;
/* Message contents: 01000100
*/
HCAN_MD4_2 = 0x44;
/* Message contents: 01000100
*/
Rev. 1.0, 1/00, page 86 of 119
HCAN_MD4_3 = 0x44;
/* Message contents: 01000100
*/
HCAN_MD4_4 = 0x44;
/* Message contents: 01000100
*/
HCAN_MD4_5 = 0x44;
/* Message contents: 01000100
*/
HCAN_MD4_6 = 0x44;
/* Message contents: 01000100
*/
HCAN_MD4_7 = 0x44;
/* Message contents: 01000100
*/
HCAN_MD4_8 = 0x44;
/* Message contents: 01000100
*/
/*******
Mail Box 5
*******/
HCAN_MC5_5 = 0x00;
/* Set standard format, data frame, and identifier */
HCAN_MC5_6 = 0x11;
/* Set identifier
*/
HCAN_MC5_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD5_1 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_2 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_3 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_4 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_5 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_6 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_7 = 0x55;
/* Message contents: 01010101
*/
HCAN_MD5_8 = 0x55;
/* Message contents: 01010101
*/
/*******
Mail Box 6
*******/
HCAN_MC6_5 = 0x80;
/* Set standard format, data frame, and identifier */
HCAN_MC6_6 = 0x99;
/* Set identifier
*/
HCAN_MC6_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD6_1 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_2 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_3 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_4 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_5 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_6 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_7 = 0x66;
/* Message contents: 01100110
*/
HCAN_MD6_8 = 0x66;
/* Message contents: 01100110
*/
/*******
Mail Box 7
*******/
HCAN_MC7_5 = 0x20;
/* Set standard format, data frame, and identifier */
HCAN_MC7_6 = 0x33;
/* Set identifier
*/
HCAN_MC7_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD7_1 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD7_2 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD7_3 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD7_4 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD7_5 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD7_6 = 0x77;
/* Message contents: 01110111
*/
Rev. 1.0, 1/00, page 87 of 119
HCAN_MD7_7 = 0x77;
/* Message contents: 01110111
*/
HCAN_MD7_8 = 0x77;
/* Message contents: 01110111
*/
/*******
Mail Box 8
*******/
HCAN_MC8_5 = 0xE0;
/* Set standard format, data frame, and identifier */
HCAN_MC8_6 = 0xFF;
/* Set identifier
*/
HCAN_MC8_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD8_1 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_2 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_3 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_4 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_5 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_6 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_7 = 0x88;
/* Message contents: 10001000
*/
HCAN_MD8_8 = 0x88;
/* Message contents: 10001000
*/
/*******
Mail Box 9
*******/
HCAN_MC9_5 = 0x20;
/* Set standard format, data frame, and identifier */
HCAN_MC9_6 = 0x22;
/* Set identifier
*/
HCAN_MC9_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD9_1 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_2 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_3 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_4 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_5 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_6 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_7 = 0x99;
/* Message contents: 10011001
*/
HCAN_MD9_8 = 0x99;
/* Message contents: 10011001
*/
/*******
Mail Box 10
*******/
HCAN_MC10_5 = 0x80;
/* Set standard format, data frame, and identifier */
HCAN_MC10_6 = 0x88;
/* Set identifier
*/
HCAN_MC10_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD10_1 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_2 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_3 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_4 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_5 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_6 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_7 = 0xAA;
/* Message contents: 10101010
*/
HCAN_MD10_8 = 0xAA;
/* Message contents: 10101010
*/
/*******
Mail Box 11
*******/
HCAN_MC11_5 = 0xA0;
Rev. 1.0, 1/00, page 88 of 119
/* Set standard format, data frame, and identifier */
HCAN_MC11_6 = 0xAA;
/* Set identifier
*/
HCAN_MC11_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD11_1 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_2 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_3 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_4 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_5 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_6 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_7 = 0xBB;
/* Message contents: 10111011
*/
HCAN_MD11_8 = 0xBB;
/* Message contents: 10111011
*/
/*******
Mail Box 12
*******/
HCAN_MC12_5 = 0xC0;
/* Set standard format, data frame, and identifier */
HCAN_MC12_6 = 0xDD;
/* Set identifier
*/
HCAN_MC12_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD12_1 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_2 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_3 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_4 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_5 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_6 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_7 = 0xCC;
/* Message contents: 11001100
*/
HCAN_MD12_8 = 0xCC;
/* Message contents: 11001100
*/
/*******
Mail Box 13
*******/
HCAN_MC13_5 = 0x60;
/* Set standard format, data frame, and identifier */
HCAN_MC13_6 = 0x77;
/* Set identifier
*/
HCAN_MC13_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD13_1 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_2 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_3 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_4 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_5 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_6 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_7 = 0xDD;
/* Message contents: 11011101
*/
HCAN_MD13_8 = 0xDD;
/* Message contents: 11011101
*/
/*******
Mail Box 14
*******/
HCAN_MC14_5 = 0x40;
/* Set standard format, data frame, and identifier */
HCAN_MC14_6 = 0x44;
/* Set identifier
*/
HCAN_MC14_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD14_1 = 0xEE;
/* Message contents: 11101110
*/
HCAN_MD14_2 = 0xEE;
/* Message contents: 11101110
*/
Rev. 1.0, 1/00, page 89 of 119
HCAN_MD14_3 = 0xEE;
/* Message contents: 11101110
*/
HCAN_MD14_4 = 0xEE;
/* Message contents: 11101110
*/
HCAN_MD14_5 = 0xEE;
/* Message contents: 11101110
*/
HCAN_MD14_6 = 0xEE;
/* Message contents: 11101110
*/
HCAN_MD14_7 = 0xEE;
/* Message contents: 11101110
*/
HCAN_MD14_8 = 0xEE;
/* Message contents: 11101110
*/
/*******
Mail Box 15
*******/
HCAN_MC15_5 = 0xA0;
/* Set standard format, data frame, and identifier */
HCAN_MC15_6 = 0xBB;
/* Set identifier
*/
HCAN_MC15_1 = 0x08;
/* Data length: 8 bytes
*/
HCAN_MD15_1 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_2 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_3 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_4 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_5 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_6 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_7 = 0xFF;
/* Message contents: 11111111
*/
HCAN_MD15_8 = 0xFF;
/* Message contents: 11111111
*/
/* Message transmission */
HCAN_TXPR = 0xFEFF;
/* Set mailboxes 1 to 15 to transmission wait state */
while((HCAN_TXACK & 0xFEFF) != 0xFEFF);
/* Wait for completion of transmission */
/* Clear transmission completed flag */
HCAN_TXACK &= 0xFEFF;
while(1);
}
Rev. 1.0, 1/00, page 90 of 119
/* Clear transmission completed flag
*/
4.7
Reception Flowcharts
Receive operation: Main routine
DTC initial settings
• Release DTC module stop mode
• Initialize DTC
— Set transfer source and destination
addresses
— Set block transfer mode
— Enable interrupt after end of data
transfer
— Set block size and number of transfers
HCAN initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (1 Mbps)
• Set mailboxes 0 to 15 for reception
• Initialize mailboxes (RAM)
• Release configuration mode
Initial settings must always
be made in configuration
mode*8.
Receive data settings
• Set arbitration field
• Set filter mask for mailbox 0 identifier
No
Message received?
Yes
CRC check
ACK transmission
Compare filter mask for mailbox 1 to 15
identifier with received identifier
Compare identifier for mailbox 1 to 15
with received identifier
Store receive data in corresponding
mailbox
No
: Set by user
Messages of mailboxes
0 to 15 received?
: Processed by hardware
Yes
EXIT
Note: * See 4.9 Notes.
Figure 4.6 Reception Flowchart (1)
Rev. 1.0, 1/00, page 91 of 119
EXIT
Reception
completed flag set?
No
Yes
Clear reception completed flag
Interrupt settings
• Set interrupt control mode 2
• Set DTC interrupt priority level
• Specify interrupt request mask level
Transfer by DTC
software start in progress?
Yes
No
Set vector number
Set vector number again
Vector
number written correctly?
No
Yes
Enable DTC software start
End of reception
Figure 4.6 Reception Flowchart (2)
Rev. 1.0, 1/00, page 92 of 119
: Set by user
DTC transfer end interrupt routine
Disable DTC software start
Set HCAN sleep mode
• Transfer to HCAN sleep mode
RTE
: Set by user
Figure 4.7 DTC Transfer End Interrupt Routine Flowchart
Rev. 1.0, 1/00, page 93 of 119
4.8
Reception Program List
/********************************************************************************/
/*
HCAN Reception Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT
(*(unsigned short *)0xFFC000)
volatile struct MB
/* struct MAILBOX0-15
*/
{
unsigned char Message_DATA1;
/* Store receive data 1 */
unsigned char Message_DATA2;
/* Store receive data 2 */
unsigned char Message_DATA3;
/* Store receive data 3 */
unsigned char Message_DATA4;
/* Store receive data 4 */
unsigned char Message_DATA5;
/* Store receive data 5 */
unsigned char Message_DATA6;
/* Store receive data 6 */
unsigned char Message_DATA7;
/* Store receive data 7 */
unsigned char Message_DATA8;
/* Store receive data 8 */
};
#define MAILBOX0
(*(volatile struct MB *)0xFFC100)
/* Mailbox 0 address
*/
#define MAILBOX1
(*(volatile struct MB *)0xFFC108)
/* Mailbox 1 address
*/
#define MAILBOX2
(*(volatile struct MB *)0xFFC110)
/* Mailbox 2 address
*/
#define MAILBOX3
(*(volatile struct MB *)0xFFC118)
/* Mailbox 3 address
*/
#define MAILBOX4
(*(volatile struct MB *)0xFFC120)
/* Mailbox 4 address
*/
#define MAILBOX5
(*(volatile struct MB *)0xFFC128)
/* Mailbox 5 address
*/
#define MAILBOX6
(*(volatile struct MB *)0xFFC130)
/* Mailbox 6 address
*/
#define MAILBOX7
(*(volatile struct MB *)0xFFC138)
/* Mailbox 7 address
*/
#define MAILBOX8
(*(volatile struct MB *)0xFFC140)
/* Mailbox 8 address
*/
#define MAILBOX9
(*(volatile struct MB *)0xFFC148)
/* Mailbox 9 address
*/
#define MAILBOX10 (*(volatile struct MB *)0xFFC150)
/* Mailbox 10 address
*/
#define MAILBOX11 (*(volatile struct MB *)0xFFC158)
/* Mailbox 11 address
*/
#define MAILBOX12 (*(volatile struct MB *)0xFFC160)
/* Mailbox 12 address
*/
Rev. 1.0, 1/00, page 94 of 119
#define MAILBOX13 (*(volatile struct MB *)0xFFC168)
/* Mailbox 13 address
*/
#define MAILBOX14 (*(volatile struct MB *)0xFFC170)
/* Mailbox 14 address
*/
#define MAILBOX15 (*(volatile struct MB *)0xFFC178)
/* Mailbox 15 address
*/
#define SAR
(*(volatile unsigned long
*)0xFFEC00)
/* Set register information */
#define MRA
(*(volatile unsigned char
*)0xFFEC00)
/* Set register information */
#define DAR
(*(volatile unsigned long
*)0xFFEC04)
/* Set register information */
#define MRB
(*(volatile unsigned char
*)0xFFEC04)
/* Set register information */
#define CRA
(*(volatile unsigned short *)0xFFEC08)
/* Set register information */
#define CRB
(*(volatile unsigned short *)0xFFEC0A)
/* Set register information */
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* DTC initial settings */
MSTPCRA = 0x3F;
/* Release DTC module stop mode */
SAR = (long)(&HCAN_MD0_1);
/* Set transfer source address
*/
MRA = 0xA8;
/* Set SAR and DAR set incrementing after transfer, and block transfer
mode */
DAR = (long)(&MAILBOX0.Message_DATA1);
/* Set transfer destination address (on-chip RAM)
MRB = 0x00;
*/
/* Enable interrupt after end of data transfer by DTC */
CRA = 0x8080;
/* Set block transfer to 128-byte units */
CRB = 0x0001;
/* Set number of block transfers to 1
*/
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
*/
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag
*/
HCAN_BCR = 0x0025;
/* Bit rate: 1 Mbps
*/
HCAN_MBCR = 0xFFFF;
/* Set mailboxes 0 to 15 for reception
*/
/* HCAN initial settings */
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailboxes (RAM)
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailboxes (RAM)
*/
Rev. 1.0, 1/00, page 95 of 119
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR &= 0xFE;
/* Release configuration mode
*/
/* Receive data settings*/
/* Mail Box 0 */
HCAN_MC0_5 = 0xA0;
/* Set standard format, data frame, and identifier */
HCAN_MC0_6 = 0xAA;
/* Set identifier
*/
/* Mail Box 1 */
HCAN_MC1_5 = 0x00;
/* Set standard format, data frame, and identifier */
HCAN_MC1_6 = 0x11;
/* Set identifier
*/
/* Mail Box 2 */
HCAN_MC2_5 = 0x20;
/* Set standard format, data frame, and identifier */
HCAN_MC2_6 = 0x22;
/* Set identifier
*/
/* Mail Box 3 */
HCAN_MC3_5 = 0x20;
/* Set standard format, data frame, and identifier */
HCAN_MC3_6 = 0x33;
/* Set identifier
*/
/* Mail Box 4 */
HCAN_MC4_5 = 0x40;
/* Set standard format, data frame, and identifier */
HCAN_MC4_6 = 0x44;
/* Set identifier
*/
/* Mail Box 5 */
HCAN_MC5_5 = 0x40;
/* Set standard format, data frame, and identifier */
HCAN_MC5_6 = 0x55;
/* Set identifier
*/
/* Mail Box 6 */
HCAN_MC6_5 = 0x60;
/* Set standard format, data frame, and identifier */
HCAN_MC6_6 = 0x66;
/* Set identifier
*/
/* Mail Box 7 */
HCAN_MC7_5 = 0x60;
/* Set standard format, data frame, and identifier */
HCAN_MC7_6 = 0x77;
/* Set identifier
*/
/* Mail Box 8 */
HCAN_MC8_5 = 0x80;
/* Set standard format, data frame, and identifier */
HCAN_MC8_6 = 0x88;
/* Set identifier
*/
/* Mail Box 9 */
HCAN_MC9_5 = 0x80;
/* Set standard format, data frame, and identifier */
HCAN_MC9_6 = 0x99;
/* Set identifier
*/
/* Mail Box 10 */
HCAN_MC10_5 = 0xA0;
/* Set standard format, data frame, and identifier */
HCAN_MC10_6 = 0xAA;
/* Set identifier
*/
/* Mail Box 11 */
HCAN_MC11_5 = 0xA0;
Rev. 1.0, 1/00, page 96 of 119
/* Set standard format, data frame, and identifier */
HCAN_MC11_6 = 0xBB;
/* Set identifier
*/
/* Mail Box 12 */
HCAN_MC12_5 = 0xC0;
/* Set standard format, data frame, and identifier */
HCAN_MC12_6 = 0xCC;
/* Set identifier
*/
/* Mail Box 13 */
HCAN_MC13_5 = 0xC0;
/* Set standard format, data frame, and identifier */
HCAN_MC13_6 = 0xDD;
/* Set identifier
*/
/* Mail Box 14 */
HCAN_MC14_5 = 0xE0;
/* Set standard format, data frame, and identifier */
HCAN_MC14_6 = 0xEE;
/* Set identifier
*/
/* Mail Box 15 */
HCAN_MC15_5 = 0xE0;
/* Set standard format, data frame, and identifier */
HCAN_MC15_6 = 0xFF;
/* Set identifier
*/
/* Mailbox 0 stores data in case of bit match
*/
HCAN_LAFMH = 0x0000;
/* Wait for completion of reception */
while((HCAN_RXPR & 0xFFFF) != 0xFFFF);
/* Wait for completion of reception */
HCAN_RXPR &= 0xFFFF;
/* Clear reception completed flag
*/
/* Interrupt settings */
SYSCR |= 0x20;
/* Set interrupt control mode 2
INTC.IPRC = 0x07;
/* Set DTC interrupt priority level to 7 */
*/
set_imask_exr(0);
/* Specify interrupt request mask level
*/
/* DTC software start */
while(DTC_DTVECR & 0x80);
/* Confirm whether transfer by DTC software start is in progress */
DTC_DTVECR |= 0x60;
/* Set vector number (H'4C0)
*/
while((DTC_DTVECR & 0x7F) != 0x60){
/* Confirm vector number written to DTVECR */
DTC_DTVECR |= 0x60;
/* Set vector number (H'4C0) again */
}
DTC_DTVECR |= 0x80;
/* Enable DTC software start
*/
while(1);
}
/********************************************************************************/
/*
DTC Transfer End Interrupt Routine
*/
/********************************************************************************/
#pragma interrupt(SWDTEND)
void SWDTEND(void)
{
DTC_DTVECR &= 0x7F;
/* Disable DTC software start
*/
Rev. 1.0, 1/00, page 97 of 119
/* HCAN sleep mode setting */
HCAN_MCR |= 0x20;
}
Rev. 1.0, 1/00, page 98 of 119
/* Transfer to HCAN sleep mode
*/
4.9
Notes
1. Data frame: Data to be transferred from the transmission source to the transmission
destination.
2. Arbitration field: Set unique ID for message and data frame or remote frame.
3. Control field: Set the data length to be transmitted, and standard format or extended format.
4. Data field: Set message contents (data to be transmitted).
5. CRC field: A CRC is generated automatically in the HCAN from all bit data except stuff bits
in the data field from SOF, and is used to detect transmit message errors.
The CRC field comprises a 15-bit CRC and a 1-bit delimiter.
The CRC delimiter is always output as a 1 after the CRC.
CRC field
CRC
CRC delimiter
Figure 4.8 CRC Field
About the CRC:
R
R
Transmit data polynomial P(X) is multiplied by X , then X · P(X) is divided by generating
polynomial G(X) to give a remainder, R(X). On the side transmitting information, R(X) found
R
from X · P(X) is added as check bits, and the result is sent as transmit data Tx(X).
On the side receiving the information, receive data Rx(X) is divided by generating polynomial
G(X) to give a remainder. If this remainder is zero, information transmission is regarded as
having been completed normally. If the remainder is nonzero, an error is judged to have
occurred in the information transmitted.
P(X) = {SOF through data field, excluding stuff bits}
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
R = 15
Note: G(X) is stipulated in the CAN protocol as the polynomial that generates the CRC.
Rev. 1.0, 1/00, page 99 of 119
As an example, the procedure is described below for a data frame transmitted using the
following settings.
Settings SOF: 0
Arbitration field: 101010101010
Control field: 000001
Data field: 10101010
The bit pattern from SOF through the data field in the transmitted data is as follows
( indicates the stuff bit):
0–1010101010100000–1–0110101010
Data field
SOF
Control field
Arbitration field
Excluding the stuff bit gives the following data subject to CRC computation:
010101010101000000110101010
Thus,
25
23
21
19
17
15
8
7
5
3
P(X) = X + X + X + X + X + X + X + X + X + X + X
1
15
P(X) is multiplied by X , giving:
15
40
38
36
34
32
30
23
22
20
18
X · P(X) = X + X + X + X + X + X + X + X + X + X + X
and this value is divided by
15
14
10
8
7
4
3
G(X) = X + X + X + X + X + X + X + 1
Rev. 1.0, 1/00, page 100 of 119
16
X15 . P(X) = X40 + X38 + X36 + X34 + X32 + X30 + X23 + X22 + X20 + X18 + X16
P[40:0] = 10101010101000000110101010000000000000000
G(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1
G[15:0] = 1100010110011001
Quotient
1100010110011001 10101010101000000110101010000000000000000
1100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1100010110011001
taken.
1101011000111101
1 1 0 0 0 1 0 1 1 0 0 1 1 0 01
1001110100100010
1100010110011001
1011000101110110
1100010110011001
1110100111011110
1100010110011001
1011000100011100
1100010110011001
1110100100001010
1100010110011001
1011001001001100
1100010110011001
1110111110101010
1100010110011001
1010100011001100
1100010110011001
1101101010101010
1100010110011001
1111100110011000
1100010110011001
111100000000010
Remainder:
R[14:0]
The following value is obtained from the calculation.
R [14:0] = 111100000000010
In other words, this is the CRC value, added after the data field to give transmit data Tx(X),
which is transmitted.
In practice, a stuff bit ( ) and CRC delimiter ( ) are added, so that 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1
is transmitted in the CRC field.
Rev. 1.0, 1/00, page 101 of 119
Next, the calculation is shown which determines whether there is an error in receive data
Rx(X).
Rx(X) is the value obtained by adding the remainder given by the previous calculation to
15
X · P(X). This value is divided by G(X).
P[40:0] = 1010101010100 0000110101010000000000000000
111100000000010
1 0101010101000000110101010111100000000010
+ R[14:0] =
This value is divided by G[15:0].
Quotient
1100010110011001 1 010101010100000 011010101011110 0000000010
1 100010110011001
1101111001110010
1100010110011001
EOR of divisor
1101111101011110
and dividend is
1 100010110011001
taken.
1101011000111101
1100010110011001
1001110100100010
1100010110011001
1011000101110111
1100010110011001
1110100111011101
1100010110011001
1011000100010011
1100010110011001
1110100100010100
1100010110011001
1011001000110100
1100010110011001
1110111101011010
1100010110011001
1010101100001100
1100010110011001
1101110100101010
110 0010110011001
1100010110011001
1100010110011001
0
Remainder
The remainder from the above calculation is zero, so the transmission is considered to be errorfree.
Rev. 1.0, 1/00, page 102 of 119
6. ACK field: For confirmation of normal reception.
Comprises a 1-bit ACK slot and a 1-bit ACK delimiter.
ACK field
ACK slot
ACK delimiter
Figure 4.9 ACK Field
The receiving H8S/2623F-ZTAT outputs a high-level ACK slot if it finds an error in the CRC
check, and a low-level ACK slot if it finds no error.
7. Stuff bits: If there are five consecutive low bits in the data frame, the output is always high for
the next bit. Similarly, if there are five consecutive high bits, the output is always low for the
next bit.
When stuff bits are output in this way, the bit length of the data frame is increased by the
number of stuff bits.
As an example, consider the case where the following settings are made:
Arbitration field: 101010101010
Control field: 000001
The bit pattern in this case is thus 101010101010000001, and so a stuff bit ( ) is output as the
second-but-lowest bit (after the five consecutive 0s).
The value transmitted on the CAN bus is therefore 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 , and the data
frame length is increased by the one stuff bit.
Rev. 1.0, 1/00, page 103 of 119
Values set in arbitration field,
control field, data field
(A)
CRC field
0 1 0 1 0 10 1 0 1 0 1 0 0 0 0 0 0 1 1 01 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1
Stuff bit is
output here
(B)
0101 01 01 01 01000 00101101 0101 0 111 100 0001 00001 0 1
For the data frame to be transmitted, shown in (A), data frame (B), with stuff bits added, is actually
transmitted on the CAN bus. Data frame (B) is longer by the length of the stuff bits.
Figure 4.10 Stuff Bits
8. Configuration mode: In this mode, the HCAN module is in the reset state. This mode is
released by clearing the reset request bit (MCR0) in the master control register (MCR).
Rev. 1.0, 1/00, page 104 of 119
Section 5 HCAN Transmission/Reception (Example 5):
Remote Frame
MCU: H8S/2623F-ZTAT
5.1
Function Used: HCAN
Specifications
1
1. Remote frame* transmission/reception (using two H8S/2623F-ZTATs).
Remote frame specifications are shown in figure 5.1.
a. SOF: Indicates start of remote frame.
2
b. Arbitration field* : Set to 101010101011.
•
RTR = 1: Select remote frame
3
c. Control field* : Set to 00001.
•
IDE = 0: Select standard format
•
R0 = 0: Reserved bit
•
DLC = 0001: Data length setting (Because it is a remote frame, transfer of data from
4
the transmission side (there is no data field* ) is not carried out.)
5
d. CRC field* : CRC is generated automatically within the HCAN.
6
e. ACK field* : 11 is output on the transmitting side, and 01 (in normal operation) on the
receiving side. (Mailboxes 1 to 15)
f. EOF: Indicates the end of a transmit/receive data frame.
2. A communication speed of 250 kbps (when operating at 20 MHz) is set.
3. Message transmission uses mailbox 1.
4. Message reception uses mailbox 0. The message reception method is to mask the identifier and
receive the message in case of a match.
5. Figure 5.2 shows an example of CAN bus connection.
Note: * See 5.9 Notes.
Rev. 1.0, 1/00, page 105 of 119
Remote frame
Arbitration field
Control field
1 bit
12 bits
6 bits
16 bits
2 bits
7 bits
EOF
SOF
ACK field
CRC field
(with CRC delimiter*5)
Identifier
RTR IDE R0
DLC
Note: * See 5.9 Notes.
Figure 5.1 Remote Frame Specifications
Transmission side
H8S/2623F-ZTAT
Reception side
H8S/2623F-ZTAT
5V
5V
PCA82C250
NC
5
8
HRxD
HTxD
4
1
Vref
Rs
Vcc
GND
RxD
CANH
TxD
CANL
PCA82C250
3
0.1 µF
2
124 Ω
NC
5
8
7
7
6
6
Vref
Rs
Vcc
GND
CANH RxD
CANL
TxD
3
2
0.1 µF
4
1
HRxD
HTxD
124 Ω
CAN bus
Note: A bus transceiver IC is necessary to connect an H8S/2623F-ZTAT to the CAN bus. One compatible with the
Philips PCA82C50 is recommended.
Figure 5.2 CAN Interface Using H8S/2623F-ZTATs
Rev. 1.0, 1/00, page 106 of 119
5.2
Functions
Tables 5.1 and 5.2 show the function allocation of this sample task. This sample task allocates
H8S/2623F-ZTAT on-chip HCAN functions as shown in these tables, and carries out HCAN
transmission and reception.
Table 5.1
HCAN Function Allocation
HCAN Register
Pins
Function
HTxD
Transmits messages.
HRxD
Receives messages.
Transmission/ IRR
reception
BCR
registers
MBCR
Transmission
registers
Reception
registers
Table 5.2
Displays status of each interrupt source.
Sets CAN baud rate prescaler and bit timing parameters.
Sets mailbox transmission/reception.
MCR
Controls CAN interface.
MC0_1
to
MC15_8
Arbitration field and control field settings.
MD0_1
to
MD15_8
Data field settings.
TXPR
Sets transmission wait state after transmit messages are stored in
the mailbox.
TXACK
Indicates that the transmit message of the corresponding mailbox
was transmitted normally.
LAFMH
Sets filter mask for reception mailbox 0 identifier.
RXPR
Indicates that data has been received normally by the corresponding
mailbox.
RFPR
Indicates that remote frame has been received normally by the
corresponding mailbox.
MSTPCR Function Allocation
MSTPCR Register
Function
MSTPCRC
Controls module stop mode.
Rev. 1.0, 1/00, page 107 of 119
5.3
Operation
Operation (Transmission)
Figure 5.3 shows the principle of operation during transmission. HCAN transmission is carried out
by H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
CRC delimiter
SOF
ACK field
Arbitration field
Control field
CRC field
Transmit
data frame
EOF
Stuff bit
*7
Initial settings
Transmit data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfers to con-
1. Sets normal
1. SOF output
2. Remote frame
transmission
3. Automatic generation of stuff bits
1. Automatically
1. ACK reception
2. Sets transmission
completed flag
figuration mode
operation state
Software processing
Software processing
1. Initial settings
• Release HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 1
for transmission
• Initializes
mailboxes (RAM)
• Sets transmission
format (order of
mailbox numbers)
2. Releases configuration mode
1. Transmit data
settings
• Arbitration field
setting
• Control field
setting
2. Message
transmission
• Sets mailbox 1
to transmission
wait state
Software processing
None
generates and
transmits CRC
calculated from all
bit data except stuff
bits in data field
from SOF (15 bits)
2. CRC delimiter
(1 bit) output
Software processing
None
Note: * See 5.9 Notes.
Figure 5.3 Operation During HCAN Transmission
Rev. 1.0, 1/00, page 108 of 119
Software processing
1. Clears transmission
completed flag
Operation (Reception)
Figure 5.4 shows the principle of operation during transmission. HCAN reception is carried out by
H8S/2623F-ZTAT hardware processing and software processing as shown in the figure.
Response of
receiving side
CRC delimiter
SOF
ACK field
Arbitration field
Identifier
Control field
CRC field
Received
data frame
EOF
Stuff bit*7
Initial settings
Receive data settings
Hardware processing
Hardware processing
Hardware processing
Hardware processing
1. Transfer to con-
1. Sets normal
1. Compares received
identifier with filter
mask of mailbox 0
identifier, and if it
matches, stores it
in mailbox
2. Sets reception
completed flag
1. CRC check
2. ACK transmission
figuration mode
operation state
Software processing
Software processing
1. Initial settings
• Releases HCAN
module stop
mode
• Initializes HCAN
module reset flag
• Sets bit rate
• Sets mailbox 0
for reception
• Initializes
mailboxes (RAM)
2. Releases configuration mode
1. Receive data
settings
• Arbitration field
setting
• Filter mask setting
for mailbox 0
identifier
Software processing
Software processing
1. Confirms completion of reception
2. Clears reception
completed flag
3. Clears remote
request flag
None
Note: * See 5.9 Notes.
Figure 5.4 Operation During HCAN Reception
Rev. 1.0, 1/00, page 109 of 119
5.4
Software
1. Modules
Module Name
Label
Function
Main routine
main
HCAN initial settings and transmission/reception settings.
2. Variables Used
Label
Function
Data Length
Module
COUNT
Initializes HCAN_MCO_1 to MC15_8 and
HCAN_MDO_1 to MD15_8.
Unsigned short
Main routine
Rev. 1.0, 1/00, page 110 of 119
3. Internal Registers Used
Register Name
Function
Setting
Module
Main routine
Settings Common to Transmission/Reception
MSTPCRC
Releases HCAN module stop mode.
0xF7
HCAN_IRR
Initializes HCAN module reset flag.
0x0100
HCAN_BCR
Sets HCAN bit rate to 250 kbps.
0x0334
Settings for Transmission
HCAN_MBCR
Sets mailbox 1 for transmission.
0xFDFF
HCAN_MCR
Sets transmission in order of mailbox numbers,
and clears reset request bit.
0x04
HCAN_MC1_1
Sets 1-byte data length.
0x01
HCAN_MC1_5
Selects mailbox 1 remote frame and standard
format, and sets identifier.
0xB0
HCAN_MC1_6
Sets mailbox 1 identifier.
0xAA
HCAN_TXPR
Sets mailbox 1 to transmission wait state.
0x0200
HCAN_TXACK
Clears remote frame transmission completed
flag.
0x0200
Main routine
Settings for Reception
HCAN_MBCR
Sets mailbox 0 for reception.
0x0100
HCAN_MCR
Clears reset request bit.
0xFE
HCAN_MC0_5
Selects mailbox 0 remote frame and standard
format, and sets identifier.
0xB0
HCAN_MC0_6
Sets mailbox 0 identifier.
0xAA
HCAN_LAFMH
Sets filter mask for mailbox 0 identifier.
0x0000
HCAN_RXPR
Clears message reception completed flag.
0x0100
HCAN_RFPR
Clears remote frame reception completed flag.
0x0100
Main routine
Rev. 1.0, 1/00, page 111 of 119
5.5
Transmission Flowchart
Transmit operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (250 kbps)
• Set mailbox 1 for transmission
• Initialize mailboxes (RAM)
• Set transmission format (order of mailbox
numbers)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Transmit data settings
• Set arbitration field
• Set control field
Message transmission
• Set mailbox 1 to transmission wait state
No
End of transmission?
Yes
Transmission
completed flag set?
No
Yes
: Set by user
Clear transmission completed flag
: Processed by hardware
End of transmission
Note: * See 5.9 Notes.
Figure 5.5 Transmission Flowchart
Rev. 1.0, 1/00, page 112 of 119
5.6
Transmission Program List
/********************************************************************************/
/*
HCAN Transmission Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file
*/
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT (*(unsigned short *)0xFFC000)
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial Settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0334;
/* Bit rate: 250 kbps
*/
HCAN_MBCR = 0xFDFF;
/* Set mailbox 1 for transmission
*/
for( COUNT = 0; COUNT < 128; COUNT++ ) /* Initialize mailbox (RAM)
*/
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM) */
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR = 0x04;
/* Set transmission in order of mailbox numbers, and release configuration
mode */
/* Transmit data settings */
HCAN_MC1_5 = 0xB0;
/* Set standard format, remote frame, and identifier */
HCAN_MC1_6 = 0xAA;
/* Set identifier
*/
Rev. 1.0, 1/00, page 113 of 119
HCAN_MC1_1 = 0x01;
/* Data length: 1 byte
*/
/* Message transmission */
HCAN_TXPR = 0x0200;
/* Set mailbox 1 to transmission wait state */
while((HCAN_TXACK & 0x0200) != 0x0200);
/* Wait for completion of transmission */
/* Clear transmission completed flag */
HCAN_TXACK &= 0x0200;
while(1);
}
Rev. 1.0, 1/00, page 114 of 119
/* Clear transmission completed flag */
5.7
Reception Flowchart
Receive operation: Main routine
Initial settings
• Release HCAN module stop mode
• Initialize HCAN module reset flag
• Set bit rate (250 kbps)
• Set mailbox 0 for reception
• Initialize mailboxes (RAM)
• Release configuration mode
Initial settings must always
be made while HCAN is
in configuration mode*8.
Receive data settings
• Set arbitration field
• Set filter mask for mailbox 0 identifier
No
Message received?
Yes
CRC check
ACK transmission
Compare filter mask for mailbox 0 identifier
with received identifier
Store receive data
Reception
completed flag and remote
request flag set?
No
Yes
Clear reception completed flag
: Set by user
Clear remote request flag
End of reception
: Processed by hardware
Note: * See 5.9 Notes.
Figure 5.6 Reception Flowchart
Rev. 1.0, 1/00, page 115 of 119
5.8
Reception Program List
/********************************************************************************/
/*
HCAN Reception Program
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file
*/
#include <machine.h>
/* Library function header file
*/
#include "2623.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function Protocol Declaration
*/
/********************************************************************************/
void main( void );
/********************************************************************************/
/*
Definition of Constants
*/
/********************************************************************************/
#define COUNT (*(unsigned short *)0xFFC000)
/********************************************************************************/
/*
Main Routine
*/
/********************************************************************************/
void main(void)
{
/* Initial settings */
MSTPCRC = 0xF7;
/* Release HCAN module stop mode
HCAN_IRR = 0x0100;
/* Initialize HCAN module reset flag */
HCAN_BCR = 0x0334;
/* Bit rate: 250 kbps
*/
HCAN_MBCR = 0x0100;
/* Set mailbox 0 for reception
*/
for( COUNT = 0; COUNT < 128; COUNT++ ) /* Initialize mailbox (RAM)
*/
*/
{
*(char*)(&HCAN_MC0_1 + COUNT) = 0x00;
}
for( COUNT = 0; COUNT < 128; COUNT++ )
/* Initialize mailbox (RAM)
*/
{
*(char*)(&HCAN_MD0_1 + COUNT) = 0x00;
}
HCAN_MCR &= 0xFE;
/* Release configuration mode */
/* Receive data settings */
HCAN_MC0_5 = 0xB0;
HCAN_MC0_6 = 0xAA;
HCAN_LAFMH = 0x0000;
/* Reception wait */
Rev. 1.0, 1/00, page 116 of 119
/* Set standard format, remote frame, and identifier */
/* Set identifier
*/
/* Mailbox 0 stores data in case of bit match */
while(((HCAN_RXPR & 0x0100) != 0x0100)
/* Wait for completion of remote frame reception */
&&((HCAN_RFPR & 0x0100) != 0x0100));
HCAN_RXPR &= 0x0100;
/* Clear reception completed flag
*/
HCAN_RFPR &= 0x0100;
/* Clear remote request flag
*/
while(1);
}
Rev. 1.0, 1/00, page 117 of 119
5.9
Notes
1. Remote frame: Data frame request is made to the transmission source.
2. Arbitration field: Set unique ID for message and data frame or remote frame.
3. Control field: Set the data length to be transmitted, and standard format or extended format.
4. Data field: Data fields do not exist in remote frames. However, the data length code (DLC) of
the control field on the transmission side must have stored in it the data length that should be
returned by the data frame.
5. CRC field: A CRC is generated automatically in the HCAN from all bit data except stuff bits
in the data field from SOF, and is used to detect transmit message errors.
The CRC field comprises a 15-bit CRC and a 1-bit delimiter.
The CRC delimiter is always output as a 1 after the CRC.
CRC field
CRC
CRC delimiter
Figure 5.7 CRC Field
6. ACK field: For confirmation of normal reception.
Comprises a 1-bit ACK slot and a 1-bit ACK delimiter.
ACK field
ACK slot
ACK delimiter
Figure 5.8 ACK Field
The receiving H8S/2623F-ZTAT outputs a high-level ACK slot if it finds an error in the CRC
check, and a low-level ACK slot if it finds no error.
Rev. 1.0, 1/00, page 118 of 119
7. Stuff bits: If there are five consecutive low bits in the data frame, the output is always high for
the next bit. Similarly, if there are five consecutive high bits, the output is always low for the
next bit.
When stuff bits are output in this way, the bit length of the data frame is increased by the
number of stuff bits.
As an example, consider the case where the following settings are made:
Arbitration field: 101010101010
Control field: 000001
The bit pattern in this case is thus 101010101010000001, and so a stuff bit ( ) is output as the
second-but-lowest bit (after the five consecutive 0s).
The value transmitted on the CAN bus is therefore 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 , and the data
frame length is increased by the one stuff bit.
8. Configuration mode: In this mode, the HCAN module is in the reset state. This mode is
released by clearing the reset request bit (MCR0) in the master control register (MCR).
Rev. 1.0, 1/00, page 119 of 119
H8S/2623F-ZTAT™ On-Chip HCAN
(Hitachi Controller Area Network)
Application Note
Publication Date: 1st Edition, January 2000
Published by:
Electronic Devices Sales & Marketing Group
Semiconductor & Integrated Circuits
Hitachi, Ltd.
Edited by:
Technical Documentation Group
Hitachi Kodaira Semiconductor Co., Ltd.
Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.