RENESAS SH7047F

32
SH7047F HCAN2
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7047 Series
Rev.1.00
2003.8.18
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/
SH7047 Series
SH7047F HCAN2
Application Note
REJ05B0144-0100O
Cautions
Keep safety first in your circuit designs!
1.
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there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire
or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or
mishap.
Notes regarding these materials
1.
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product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any
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2.
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originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in
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Rev. 1.00, 08/03, page iv of viii
Preface
Outline
The HCAN-2 control area network is a module designed to control a CAN (controller area
network) for implementing real-time communications in an automobile, industrial machinery
system, or the like.
This Application Note consists of communications operation examples using the HCAN-2, which
incorporates the SH7047F. It is hoped that these examples will produce useful to designers of
software and hardware systems.
The task examples and application examples contained in this Application Note have been tested
and verified to work properly. Nevertheless, their operation should be confirmed in actual use
before final implementation.
Device Used for Operation Verification
SH7047F
Rev. 1.00, 08/03, page v of viii
Rev. 1.00, 08/03, page vi of viii
Contents
Section 1 Example 1 (Standard Format, 1 Byte of Data) .........................................
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Transmission and Reception Specifications ......................................................................
Transmission and Reception Specifications, Function Description...................................
Transmission Flowchart ....................................................................................................
Software Description (Transmission) ................................................................................
Transmission Program Listing...........................................................................................
Reception Flowchart..........................................................................................................
Software Description (Reception) .....................................................................................
Reception Program Listing................................................................................................
Operation Waveforms (Transmission and Reception).......................................................
1
1
1
3
4
5
6
7
8
9
Section 2 Example 2 (Standard Format, 8 Bytes of Data, Using DTC) ............... 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Transmission and Reception Specifications ......................................................................
Transmission and Reception Specifications, Function Description...................................
Transmission Flowchart ....................................................................................................
Software Description (Transmission) ................................................................................
Transmission Program Listing...........................................................................................
Reception Flowchart..........................................................................................................
Software Description (Reception) .....................................................................................
Reception Program Listing................................................................................................
Operation Waveforms (Transmission and Reception).......................................................
10
10
13
14
16
18
19
21
23
Section 3 Example 3 (Extended Format, 1 Byte of Data) ........................................ 24
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Transmission and Reception Specifications ......................................................................
Transmission and Reception Specifications, Function Description...................................
Transmission Flowchart ....................................................................................................
Software Description (Transmission) ................................................................................
Transmission Program Listing...........................................................................................
Reception Flowchart..........................................................................................................
Software Description (Reception) .....................................................................................
Reception Program Listing................................................................................................
Operation Waveforms (Transmission and Reception).......................................................
24
24
26
28
29
31
33
34
36
Section 4 Example 4 (Standard Format, 8 Bytes of Data, Prioritized) ................. 37
4.1
4.2
4.3
4.4
4.5
Transmission and Reception Specifications ......................................................................
Transmission and Reception Specifications, Function Description...................................
Transmission Flowchart ....................................................................................................
Software Description (Transmission) ................................................................................
Transmission Program Listing...........................................................................................
37
38
41
43
44
Rev. 1.00, 08/03, page vii of viii
4.6
4.7
4.8
4.9
Reception Flowchart .........................................................................................................
Software Description (Reception).....................................................................................
Reception Program Listing ...............................................................................................
Operation Waveforms (Transmission and Reception) ......................................................
49
50
52
54
Section 5 Example 5 (Remote Frame) .......................................................................... 56
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Transmission and Reception Specifications......................................................................
Transmission and Reception Specifications, Function Description ..................................
Transmission Flowchart....................................................................................................
Software Description (Transmission) ...............................................................................
Transmission Program Listing ..........................................................................................
Reception Flowchart .........................................................................................................
Software Description (Reception).....................................................................................
Reception Program Listing ...............................................................................................
Operation Waveforms (Transmission and Reception) ......................................................
Rev. 1.00, 08/03, page viii of viii
56
57
59
61
63
66
67
70
72
Section 1 Example 1
(Standard Format, 1 Byte of Data)
1.1
Transmission and Reception Specifications
Transmission and reception of 1 byte of data in the standard format using two SH7047F devices.
Common Transmission and Reception Specifications
• The data transfer speed is 250 kbps (during 50 MHz operation).
• The identifier is H'555.
Transmission Specifications
• Mailbox 1 is used.
• The data length is 1 byte, and the data transmitted is H'AA.
• The transmission end flag is polled while transmission is in progress.
• After confirmation that the transmission end flag has been set, the transmission end flag is
cleared, completing the operation.
Reception Specifications
• Mailbox 0 is used.
• The identifier is masked and reception takes place when a match occurs.
• The received data is stored in on-chip RAM, completing the operation.
1.2
Transmission and Reception Specifications, Function Description
Table 1.1 lists the functions allocated to pins and registers.
Rev. 1.00, 08/03, page 1 of 74
Table 1.1
HCAN-2 Function Allocation
Pin
Pin
Function
HTxD1
Used to perform message transmission using the HCAN-2 (pin
57).
HRxD1
Used to perform message reception using the HCAN-2 (pin 56).
Register
Common
transmission
and reception
registers
Function
PBCR1
Port B control registers
PBCR2
Set to functions of pins HTxD1 and HRxD1.
MCR
Master control register
Controls operation of HCAN-2.
BCR0
Bit timing configuration registers
BCR1
Used to set baud rate prescaler and bit timing parameters of
CAN.
IRR
Interrupt request register
Shows status of interrupt sources.
MBx
MC0
Message control register
Used to set identifier and whether frames are data frames or
remote frames.
MC4
Message control register
Used to select transmission or reception.
MC5
Message control register
Used to set the data length.
MD7
Message data register
Stores transmitted and received CAN message data.
LAFM15 Local acceptance filter mask
Used to set filter mask for identifier of reception mailbox.
Transmission
registers
TXPR
Transmission wait register
Used to set transmission wait status after transmitted message
is stored in mailbox.
TXACK
Transmission acknowledge register
Indicates that the transmitted message has been properly
transmitted to the corresponding mailbox.
Reception
register
RXPR
Rev. 1.00, 08/03, page 2 of 74
Reception end register
Indicates that the data has been properly received by the
corresponding mailbox.
1.3
Transmission Flowchart
Transmission operation: main routine
Clear bit MCR0
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set transmission method
Set transmission data
Set to transmission wait status
Transmission complete?
No
Yes
Clear transmission end flag
End of transmission
Figure 1.1 Transmission Flowchart
Rev. 1.00, 08/03, page 3 of 74
1.4
Software Description (Transmission)
Module Description
Module
Label
Function
Main routine
t_main
Performs initial settings and transmission settings for HCAN-2.
Description of Registers Used
Register
Function
Initial Value
Module
PB.PBCR1
Sets pins PB1 and PB0 (pins 56 and 57) to
HRxD1 and HTxD1.
0x0000
Main routine
PB.PBCR2
0x000F
work
Work register used for mailbox initialization.
―
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt flags.
(To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is 50 MHz.
HCAN_BCR1
0x0009
0x4300
HCAN_MB1.MC0
Sets data frame and standard format for
mailbox 1. Also sets identifier (H'555).
0x5550
HCAN_MB1.MC4
Sets mailbox 1 as for transmission.
0x01
HCAN_MB1.MC5
Sets mailbox 1 transmission size to a data
length of 1 byte.
0x01
HCAN_MB1.MD7
Sets mailbox 1 transmission data (H'AA).
0xAA
HCAN_TXPR0
Sets mailbox 1 to transmission wait status.
0x0002
HCAN_TXACK0
Checks and clears mailbox 1 transmission
end flag. (To clear, write 1.)
0x0002
Rev. 1.00, 08/03, page 4 of 74
1.5
Transmission Program Listing
/********************************************************************************/
/*
HCAN-2 Transmission Program (Example 1)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void t_main(void );
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void t_main(void){
unsigned short *work;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *) 0xFFFFB4F4);
/* Set MBC */
HCAN_MB1.MC4 = 0x01;
/* Set mailbox 1 as for transmission */
/* Set transmission method */
HCAN_MB1.MC0 = 0x5550;
/* Select data frame and standard format,
set identifier */
HCAN_MB1.MC5 = 0x01;
/* Set data length: 1 byte */
/* Set transmission data */
HCAN_MB1.MD7 = 0xAA;
/* Set transmission data: 10101010 */
/* Set message transmission wait status */
HCAN_TXPR0 = 0x0002;
/* Set mailbox 1 to transmission wait status */
/* Wait for transmission end */
while((HCAN_TXACK0 & 0x0002) != 0x0002);
/* Clear transmission end flag */
HCAN_TXACK0 = 0x0002; /* Clear transmission end flag (to clear, write 1) */
while(1);
}
Rev. 1.00, 08/03, page 5 of 74
1.6
Reception Flowchart
Reception operation: main routine
Initialize reception data storage area
Clear bit MCR0
Set local acceptance filter
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set reception method
Reception complete?
No
Yes
Store received data
Clear reception end flag
End of reception
Figure 1.2 Reception Flowchart
Rev. 1.00, 08/03, page 6 of 74
1.7
Software Description (Reception)
Module Description
Module
Label
Function
Main routine
r_main
Performs initial settings and reception settings for HCAN-2.
Description of Registers Used
Register
Function
Initial Value
Module
MBbuff
Storage area for received data (address:
H'FFFFD100).
―
Main routine
work
Work register used for mailbox
initialization.
―
PB.PBCR1
0x0000
PB.PBCR2
Sets pins PB1 and PB0 (pins 56 and 57) to
HRxD1 and HTxD1.
0x000F
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is
50 MHz.
0x0009
HCAN_BCR1
0x4300
HCAN_MB0.MC0
Sets data frame and standard format for
mailbox 0. Also sets identifier (H'555).
0x5550
HCAN_MB0.MC4
Sets mailbox 0 as for reception.
0x03
HCAN_MB0.MC5
Sets mailbox 0 reception size to a data
length of 1 byte.
0x01
HCAN_MB0.LAFM15
Sets identifier filter mask for mailbox 0.
0x0000
HCAN_RXPR0
Checks and clears mailbox 0 reception end
flag. (To clear, write 1.)
0x0001
Rev. 1.00, 08/03, page 7 of 74
1.8
Reception Program Listing
/********************************************************************************/
/*
HCAN-2 Reception Program (Example 1)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void r_main(void );
/********************************************************************************/
/*
Define constants
*/
/********************************************************************************/
#define MBbuff (*(unsigned char *)0xFFFFD100) /* Storage for mailbox 0 reception
data */
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void r_main(void){
unsigned short *work;
/* Initialize storage area for received data */
MBbuff = 0x00;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Set local acceptance filter */
HCAN_MB0.LAFM15 = 0x0000;
/* Set identifier filter mask for mailbox 0 */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB0.MC4 = 0x03;
/* Set mailbox 0 as for reception */
/* Set reception method */
HCAN_MB0.MC0 = 0x5550;
/* Select data frame and standard
format, set identifier */
HCAN_MB0.MC5 = 0x01;
/* Set data length: 1 byte */
/* Wait for reception end */
while((HCAN_RXPR0 & 0x0001) != 0x0001); /* Wait for reception end */
Rev. 1.00, 08/03, page 8 of 74
/* Store received data */
MBbuff = HCAN_MB0.MD7;
/* Store received data in on-chip RAM */
/* Clear reception end flag */
HCAN_RXPR0 = 0x0001;
/* Clear reception end flag (to clear, write 1) */
while(1);
}
1.9
Operation Waveforms (Transmission and Reception)
Figure 1.3 shows the waveforms during the operation of this application.
Control field
CF = b’000001
ACK field
Data field
0xAA
Arbitration field
ID = 0x555 (11 bits)
RTR = 0 (1 bit)
CRC field
(16 bits: generated
automatically)
EOF (7 bits)
CRC delimiter
SOF
Transmission waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits (generated automatically)
Figure 1.3 Operation Waveforms
Rev. 1.00, 08/03, page 9 of 74
Section 2 Example 2
(Standard Format, 8 Bytes of Data, Using DTC)
2.1
Transmission and Reception Specifications
Transmission and reception of 8 bytes of data in the standard format using two SH7047F devices
and storage of received data using DTC.
Common Transmission and Reception Specifications
• The data transfer speed is 250 kbps (during 50 MHz operation).
• The identifier is H'555.
Transmission Specifications
• Mailbox 1 is used.
• The data length is 8 bytes, and the data transmitted is H'55, H'66, H'77, H'88, H'99, H'AA,
H'BB, H'FF.
• The mailbox empty interrupt (IRR8) is used. After message transmission wait status has been
set, the transmission end flag is cleared and mailbox empty interrupts are prohibited within the
mailbox empty interrupt routine, completing the operation.
Reception Specifications
• Mailbox 0 is used.
• The identifier is masked and reception takes place when a match occurs.
• The message reception interrupt (IRR1) is used.
(a) When the data is received DTC is triggered by the message reception interrupt, and the
received data is stored in on-chip RAM.
(b) Block transfer mode is used for the DTC transfer, and the 8 bytes of data are transferred as
a single block.
(c) After the DTC transfer is completed, the reception end flag is cleared and message
reception interrupts are prohibited within the message reception interrupt routine,
completing the operation.
2.2
Transmission and Reception Specifications, Function Description
Tables 2.1 and 2.2 list the functions allocated to registers. (See example 1 for information on pins
and port registers.)
Rev. 1.00, 08/03, page 10 of 74
Table 2.1
HCAN-2 Function Allocation
Register
Common
transmission
and reception
registers
Function
MCR
Master control register
Controls operation of HCAN-2.
BCR0
Bit timing configuration registers
BCR1
Used to set baud rate prescaler and bit timing parameters of
CAN.
IRR
Interrupt request register
Shows status of interrupt sources.
MBx
MC0
Message control register
Used to set identifier and whether frames are data frames or
remote frames.
MC4
Message control register
Used to select transmission or reception.
MC5
Message control register
Used to set the data length.
MD7 to
MD14
Message data registers
Store transmitted and received CAN message data.
LAFM15 Local acceptance filter mask
Used to set filter mask for identifier of reception mailbox.
Transmission
registers
TXPR
Transmission wait register
Used to set transmission wait status after transmitted message
is stored in mailbox.
TXACK
Transmission acknowledge register
Indicates that the transmitted message has been properly
transmitted to the corresponding mailbox.
Reception
register
RXPR
Interrupt
registers
MBIMR
Reception end register
Indicates that the data has been properly received by the
corresponding mailbox.
Mailbox interrupt mask register
Used to enable interrupt requests for mailboxes.
IMR
Interrupt mask register
Used to enable interrupt requests using IRR interrupt flag.
IPRK
Interrupt priority register
Used to set the priority of HCAN-2 interrupt requests.
Rev. 1.00, 08/03, page 11 of 74
Table 2.2
DTC Function Allocation
Register
Function
DTMR
DTC mode register
Controls the DTC operation mode.
DTSAR
DTC source address register
Specifies the source address for data to be transferred using DTC.
DTDAR
DTC destination address register
Specifies the destination address for data to be transferred using DTC.
DTCRA
DTC transfer count register A
Specifies the number of DTC transfers.
DTCRB
DTC transfer count register B
In the block transfer mode, specifies the block length.
DTBR
DTC database register
Specifies the top 16 bits of the memory address at which data transferred using
DTC is to be stored.
DTEF
DTC enable register
Selects the interrupt source (RM1 in HCAN-2) for starting DTC.
Rev. 1.00, 08/03, page 12 of 74
2.3
Transmission Flowchart
Transmission operation: main routine
Clear bit MCR0
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set mailbox empty interrupt
Set transmission method
Set transmission data
Set to transmission wait status
Figure 2.1 Transmission Flowchart (1)
Rev. 1.00, 08/03, page 13 of 74
Mailbox empty interrupt routine
Clear transmission end flag
Prohibit mailbox empty interrupts
RTE
Figure 2.2 Transmission Flowchart (2)
2.4
Software Description (Transmission)
Module Description
Module
Label
Function
Main routine
t_main
Performs initial settings and transmission settings for
HCAN-2.
Mailbox empty
interrupt routine
SLE1_IRR8
Clears transmission end flag and sets interrupt
prohibition.
Rev. 1.00, 08/03, page 14 of 74
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
Initial Value
Module
work
Work register used for mailbox initialization.
―
Main routine
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt flags.
(To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is 50 MHz.
0x0009
HCAN_BCR1
0x4300
HCAN_MB1.MC0
Sets data frame and standard format for
mailbox 1. Also sets identifier (H'555).
0x5550
HCAN_MB1.MC4
Sets mailbox 1 as for transmission.
0x01
HCAN_MB1.MC5
Sets mailbox 1 transmission size to a data
length of 8 bytes.
0x08
HCAN_MB1.MD7
Sets mailbox 1 byte 1 transmission data
(H'55).
0x55
HCAN_MB1.MD8
Sets mailbox 1 byte 2 transmission data
(H'66).
0x66
HCAN_MB1.MD9
Sets mailbox 1 byte 3 transmission data
(H'77).
0x77
HCAN_MB1.MD10
Sets mailbox 1 byte 4 transmission data
(H'88).
0x88
HCAN_MB1.MD11
Sets mailbox 1 byte 5 transmission data
(H'99).
0x99
HCAN_MB1.MD12
Sets mailbox 1 byte 6 transmission data
(H'AA).
0xAA
HCAN_MB1.MD13
Sets mailbox 1 byte 7 transmission data
(H'BB).
0xBB
HCAN_MB1.MD14
Sets mailbox 1 byte 8 transmission data
(H'FF).
0xFF
HCAN_IMR
Enables mailbox empty interrupts.
0xFEFF
HCAN_MBIMR0
Enables mailbox 1 interrupt requests.
0xFFFD
INTC.IPRK
Sets the priority of HCAN-2 interrupt requests. 0x00F0
HCAN_TXPR0
Sets mailbox 1 to transmission wait status.
0x0002
HCAN_TXACK0
Clears mailbox 1 transmission end flag.
(To clear, write 1.)
0x0002
HCAN_IMR
Prohibits mailbox empty interrupts.
0xFFFF
Mailbox
empty
interrupt
routine
Rev. 1.00, 08/03, page 15 of 74
2.5
Transmission Program Listing
/********************************************************************************/
/*
HCAN-2 Transmission Program (Example 2)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void t_main(void );
void SLE1_IRR8(void);
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void t_main(void){
unsigned short *work;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB1.MC4 = 0x01;
/* Set mailbox 1 as for transmission */
/* Set interrupts */
HCAN_IMR = 0xFEFF;
/* Enable interrupt IRR8 */
HCAN_MBIMR0 = 0xFFFD;
/* Enable mailbox 1 interrupt requests */
INTC.IPRK = 0x00F0;
/* Set SLE1 priority */
/* Set transmission method */
HCAN_MB1.MC0 = 0x5550;
/* Select data frame and standard format,
set identifier */
HCAN_MB1.MC5 = 0x08;
/* Set data length: 8 bytes */
/* Set transmission data */
HCAN_MB1.MD7 = 0x55;
/* Set transmission data: 01010101 */
HCAN_MB1.MD8 = 0x66;
/* Set transmission data: 01100110 */
HCAN_MB1.MD9 = 0x77;
/* Set transmission data: 01110111 */
HCAN_MB1.MD10 = 0x88;
/* Set transmission data: 10001000 */
Rev. 1.00, 08/03, page 16 of 74
HCAN_MB1.MD11 = 0x99;
HCAN_MB1.MD12 = 0xAA;
HCAN_MB1.MD13 = 0xBB;
HCAN_MB1.MD14 = 0xFF;
/* Set message transmission wait status
HCAN_TXPR0 = 0x0002;
/* Set
set_imask(0);
while(1);
}
/* Set
/* Set
/* Set
/* Set
*/
mailbox
transmission
transmission
transmission
transmission
data:
data:
data:
data:
10011001
10101010
10111011
11111111
*/
*/
*/
*/
1 to transmission wait status */
/********************************************************************************/
/*
Mailbox empty interrupt routine
*/
/********************************************************************************/
#pragma interrupt(SLE1_IRR8)
void SLE1_IRR8(void){
/* Clear transmission end flag */
HCAN_TXACK0 = 0x0002;
/*Clear transmission end flag (to clear, write 1) */
/* Prohibit mailbox empty interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit interrupt IRR8 */
}
Rev. 1.00, 08/03, page 17 of 74
2.6
Reception Flowchart
Reception operation: main routine
Initialize reception data storage area
Set DTC
Clear bit MCR0
Set local acceptance filter
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set reception interrupts
Set reception method
Figure 2.3 Reception Flowchart (1)
Rev. 1.00, 08/03, page 18 of 74
Reception interrupt routine
Clear reception end flag
Prohibit reception interrupts
RTE
Figure 2.4 Reception Flowchart (2)
2.7
Software Description (Reception)
Module Description
Module
Label
Function
Main routine
r_main
Performs initial settings and reception settings for
HCAN-2.
Reception interrupt
routine
RM1_IRR1
Clears reception end flag and sets interrupt prohibition.
Rev. 1.00, 08/03, page 19 of 74
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
MBbuff
Storage area for received data (address: ―
H'FFFFD100–H'FFFFD107).
work
Work register used for mailbox
initialization.
―
DTMR
Increments both DTSAR and DTDAR
after transfer completes, sets block
transfer mode and byte transfer.
0xA890
DTSAR
Sets transfer source address as mailbox
0 message data area.
0xFFFFB108
DTDAR
Sets transfer destination address as
received data storage area.
0xFFFFD100
DTCRA
Sets number of block transfers (1).
0x0001
DTCRB
Sets block length (8 bytes).
0x0008
DTC.DTBR
Sets top 16 bits of memory address at
which data transferred using DTC is
stored.
0xFFFF
DTC.DTEF
Selects the interrupt source (RM1 in
HCAN-2) for starting DTC.
0x04
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is
50 MHz.
0x0009
HCAN_BCR1
Initial Value
Module
Main routine
0x4300
HCAN_MB0.MC0
Sets data frame and standard format for
mailbox 0. Also sets identifier (H'555).
0x5550
HCAN_MB0.MC4
Sets mailbox 0 as for reception.
0x03
HCAN_MB0.MC5
Sets mailbox 0 reception size to a data
length of 8 bytes.
0x08
HCAN_MB0.LAFM15
Sets identifier filter mask for mailbox 0.
0x0000
HCAN_IMR
Enables message reception interrupts.
0xFFFD
HCAN_MBIMR0
Enables mailbox 0 interrupt requests.
0xFFFE
INTC.IPRK
Sets priority of HCAN-2 interrupt
requests.
0x00F0
HCAN_RXPR0
Clears mailbox 0 reception end flag.
(To clear, write 1.)
0x0001
HCAN_IMR
Prohibits message reception interrupts.
0xFFFF
Rev. 1.00, 08/03, page 20 of 74
Reception
interrupt
routine
2.8
Reception Program Listing
/********************************************************************************/
/*
HCAN-2 Reception Program (Example 2)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void r_main(void );
void RM1_IRR1(void);
/********************************************************************************/
/*
Define constants
*/
/********************************************************************************/
#define DTMR (*(unsigned short *)0xFFFFD080) /* DTC register data */
#define DTCRA (*(unsigned short *)0xFFFFD082) /* DTC register data */
#define DTCRB (*(unsigned short *)0xFFFFD086) /* DTC register data */
#define DTSAR (*(unsigned long *)0xFFFFD088) /* DTC register data */
#define DTDAR (*(unsigned long *)0xFFFFD08C) /* DTC register data */
#define MBbuff (*(unsigned char *)0xFFFFD100) /* Storage area for received data */
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void r_main(void){
unsigned short *work;
/* Initialize storage area for received data */
work = (unsigned short *)0xFFFFD100;
do {
*work = 0x0000;
work++;
} while(work < (unsigned short *)0xFFFFD108);
/* DTC settings */
DTMR = 0xA890;
/* Increment both DTSAR and DTDAR
after transfer completes, set block transfer mode and byte transfer */
DTSAR = (unsigned long)&HCAN_MB0.MD7; /* Set transfer source address */
DTDAR = (unsigned long)&MBbuff;
/* Set transfer destination address */
DTCRA = 0x0001;
/* Block transfer: 1 block */
DTCRB = 0x0008;
/* Block length: 8 bytes */
DTC.DTBR = 0xFFFF;
/* Register data base address */
DTC.DTEF |= 0x04;
/* HCAN-2 interrupt (RM1) */
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Set local acceptance filter */
HCAN_MB0.LAFM15 = 0x0000;
/* Set identifier filter mask for mailbox 0 */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
Rev. 1.00, 08/03, page 21 of 74
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB0.MC4 = 0x03;
/* Set mailbox 0 as for reception */
/* Set interrupts */
HCAN_IMR = 0xFFFD;
/* Enable message reception interrupts */
HCAN_MBIMR0 = 0xFFFE;
/* Enable mailbox 0 reception interrupt requests */
INTC.IPRK = 0x00F0;
/* Set RM1 priority */
/* Set reception method */
HCAN_MB0.MC0 = 0x5550;
/* Select data frame and standard format,
set identifier */
HCAN_MB0.MC5 = 0x08;
/* Set data length: 8 bytes */
set_imask(0);
while(1);
}
/********************************************************************************/
/*
Reception interrupt routine
*/
/********************************************************************************/
#pragma interrupt(RM1_IRR1)
void RM1_IRR1(void){
/* Clear reception end register */
HCAN_RXPR0 = 0x0001;
/* Clear reception end flag (to clear, write 1) */
/* Prohibit reception interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit message reception interrupts */
}
Rev. 1.00, 08/03, page 22 of 74
2.9
Operation Waveforms (Transmission and Reception)
Figure 2.5 shows the waveforms during the operation of this application.
Control field
CF = b’001000
Arbitration field
ID = 0x555 (11 bits)
RTR = 0 (1 bit)
Data field
0x55
SOF
0x66
0x77
0x88
Transmission waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
ACK field
CRC field
(16 bits: generated
automatically)
Data field
0x99
0xAA
0xBB
EOF (7 bits)
CRC delimiter
0xFF
Transmission waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits (generated automatically)
Figure 2.5 Operation Waveforms
Rev. 1.00, 08/03, page 23 of 74
Section 3 Example 3
(Extended Format, 1 Byte of Data)
3.1
Transmission and Reception Specifications
Transmission and reception of 1 byte of data in the extended format using two SH7047F devices.
Common Transmission and Reception Specifications
• The data transfer speed is 250 kbps (during 50 MHz operation).
• The standard identifier is H'555, and the extended identifier is H'2AAAA.
Transmission Specifications
• Mailbox 1 is used.
• The data length is 1 byte, and the data transmitted is H'AA.
• The mailbox empty interrupt (IRR8) is used. After message transmission wait status has been
set, the transmission end flag is cleared and mailbox empty interrupts are prohibited within the
mailbox empty interrupt routine, completing the operation.
Reception Specifications
• Mailbox 0 is used.
• The identifier is masked and reception takes place when a match occurs.
• The message reception interrupt (IRR1) is used. The received data is stored in on-chip RAM,
the reception end flag is cleared, and message reception interrupts are prohibited within the
message reception interrupt routine, completing the operation.
3.2
Transmission and Reception Specifications, Function Description
Table 3.1 lists the functions allocated to registers. (See example 1 for information on pins and
port registers.)
Rev. 1.00, 08/03, page 24 of 74
Table 3.1
HCAN-2 Function Allocation
Register
Common
transmission
and reception
registers
Function
MCR
Master control register
Controls operation of HCAN-2.
BCR0
Bit timing configuration registers
BCR1
Used to set baud rate prescaler and bit timing parameters of
CAN.
IRR
Interrupt request register
Shows status of interrupt sources.
MBx
MC0 to
MC2
Message control register
MC4
Message control register
Used to set identifier and whether frames are data frames or
remote frames.
Used to select transmission or reception.
MC5
Message control register
Used to set the data length.
MD7
Message data registers
Store transmitted and received CAN message data.
LAFM15 Local acceptance filter mask
LAFM17 Used to set filter mask for identifier of reception mailbox.
Transmission
registers
TXPR
Transmission wait register
Used to set transmission wait status after transmitted message
is stored in mailbox.
TXACK
Transmission acknowledge register
Indicates that the transmitted message has been properly
transmitted to the corresponding mailbox.
Reception
register
RXPR
Interrupt
registers
MBIMR
Reception end register
Indicates that the data has been properly received by the
corresponding mailbox.
Mailbox interrupt mask register
Used to enable interrupt requests for mailboxes.
IMR
Interrupt mask register
Used to enable interrupt requests using IRR interrupt flag.
IPRK
Interrupt priority register
Used to set the priority of HCAN-2 interrupt requests.
Rev. 1.00, 08/03, page 25 of 74
3.3
Transmission Flowchart
Transmission operation: main routine
Clear bit MCR0
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set mailbox empty interrupt
Set transmission method
Set transmission data
Set to transmission wait status
Figure 3.1 Transmission Flowchart (1)
Rev. 1.00, 08/03, page 26 of 74
Mailbox empty interrupt routine
Clear transmission end flag
Prohibit mailbox empty interrupts
RTE
Figure 3.1 Transmission Flowchart (2)
Rev. 1.00, 08/03, page 27 of 74
3.4
Software Description (Transmission)
Module Description
Module
Label
Function
Main routine
t_main
Performs initial settings and transmission settings for
HCAN-2.
Mailbox empty
interrupt routine
SLE1_IRR8
Clears transmission end flag and sets interrupt
prohibition.
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
Initial Value
Module
work
Work register used for mailbox initialization.
―
Main routine
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt flags.
(To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is 50 MHz.
0x0009
HCAN_BCR1
0x4300
HCAN_MB1.MC2
Sets data frame and extended format for
0x5556
mailbox 1. Also sets standard identifier (H'555)
0xAAAA
and extended identifier (H'2AAAA).
HCAN_MB1.MC4
Sets mailbox 1 as for transmission.
0x01
HCAN_MB1.MC5
Sets mailbox 1 transmission size to a data
length of 1 byte.
0x01
HCAN_MB1.MD7
Sets mailbox 1 transmission data (H'AA).
0xAA
HCAN_IMR
Enables mailbox empty interrupts.
0xFEFF
HCAN_MBIMR0
Enables mailbox 1 interrupt requests.
0xFFFD
INTC.IPRK
Sets the priority of HCAN-2 interrupt requests. 0x00F0
HCAN_TXPR0
Sets mailbox 1 to transmission wait status.
0x0002
HCAN_TXACK0
Clears mailbox 1 transmission end flag.
(To clear, write 1.)
0x0002
HCAN_IMR
Prohibits mailbox empty interrupts.
0xFFFF
HCAN_MB1.MC0
Rev. 1.00, 08/03, page 28 of 74
Mailbox
empty
interrupt
routine
3.5
Transmission Program Listing
/********************************************************************************/
/*
HCAN-2 Transmission Program (Example 3)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void t_main(void );
void SLE1_IRR8(void);
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void t_main(void){
unsigned short *work;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB1.MC4 = 0x01;
/* Set mailbox 1 as for transmission */
/* Set interrupts */
HCAN_IMR = 0xFEFF;
/* Enable interrupt IRR8 */
HCAN_MBIMR0 = 0xFFFD;
/* Enable mailbox 1 interrupt requests */
INTC.IPRK = 0x00F0;
/* Set SLE1 priority */
/* Set transmission method */
HCAN_MB1.MC0 = 0x5556;
/* Select data frame and extended format,
set identifier */
HCAN_MB1.MC2 = 0xAAAA;
/* Set (extended) identifier */
HCAN_MB1.MC5 = 0x01;
/* Set data length: 1 byte */
/* Set transmission data */
HCAN_MB1.MD7 = 0xAA;
/* Set transmission data: 10101010 */
/* Set message transmission wait status */
HCAN_TXPR0 = 0x0002;
/* Set mailbox 1 to transmission wait status */
set_imask(0);
Rev. 1.00, 08/03, page 29 of 74
while(1);
}
/********************************************************************************/
/*
Mailbox empty interrupt routine
*/
/********************************************************************************/
#pragma interrupt(SLE1_IRR8)
void SLE1_IRR8(void){
/* Clear transmission end flag */
HCAN_TXACK0 = 0x0002; /* Clear transmission end flag (to clear, write 1) */
/* Prohibit mailbox empty interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit interrupt IRR8 */
}
Rev. 1.00, 08/03, page 30 of 74
3.6
Reception Flowchart
Reception operation: main routine
Initialize reception data storage area
Clear bit MCR0
Set local acceptance filter
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set reception interrupts
Set reception method
Figure 3.3 Reception Flowchart (1)
Rev. 1.00, 08/03, page 31 of 74
Reception interrupt routine
Clear reception end flag
Store received data
Prohibit reception interrupts
RTE
Figure 3.4 Reception Flowchart (2)
Rev. 1.00, 08/03, page 32 of 74
3.7
Software Description (Reception)
Module
Label
Function
Main routine
r_main
Performs initial settings and reception settings for HCAN-2.
Reception interrupt
routine
RM1_IRR1
Clears reception end flag and sets interrupt prohibition.
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
Initial Value
Module
MBbuff
Storage area for received data (address:
H'FFFFD100).
―
Main routine
work
Work register used for mailbox initialization. ―
HCAN_MCR
Clears reset request bit.
HCAN_IRR
Clears reset, hold, and sleep interrupt flags. 0x0001
(To clear, write 1.)
HCAN_BCR0
Sets bit rate to 250 kbps when φ is 50 MHz. 0x0009
HCAN_BCR1
0x4300
HCAN_MB0.MC0
0x0000
HCAN_MB0.MC2
Sets data frame and extended format for
0x5556
mailbox 1. Also sets standard identifier
0xAAAA
(H'555) and extended identifier (H'2AAAA).
HCAN_MB0.MC4
Sets mailbox 0 as for reception.
0x03
HCAN_MB0.MC5
Sets mailbox 0 reception size to a data
length of 1 byte.
0x01
HCAN_MB0.LAFM15
Sets identifier filter mask for mailbox 0.
0x0000
HCAN_MB0.LAFM17
Sets identifier filter mask for mailbox 0.
0x0000
HCAN_IMR
Enables message reception interrupts.
0xFFFD
HCAN_MBIMR0
Enables mailbox 0 interrupt requests.
0xFFFE
INTC.IPRK
Sets priority of HCAN-2 interrupt requests.
0x00F0
HCAN_RXPR0
Clears mailbox 0 reception end flag.
(To clear, write 1.)
0x0001
HCAN_IMR
Prohibits message reception interrupts.
0xFFFF
Reception
interrupt
routine
Rev. 1.00, 08/03, page 33 of 74
3.8
Reception Program Listing
/********************************************************************************/
/*
HCAN-2 Reception Program (Example 3)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void r_main(void );
void RM1_IRR1(void);
/********************************************************************************/
/*
Define constants
*/
/********************************************************************************/
#define MBbuff (*(unsigned char *)0xFFFFD100) /* Storage area for received data */
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void r_main(void){
unsigned short *work;
/* Initialize storage area for received data */
MBbuff = 0x00;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Set local acceptance filter */
HCAN_MB0.LAFM15 = 0x0000;
/* Set identifier filter mask for mailbox 0
HCAN_MB0.LAFM17 = 0x0000;
/* Set identifier filter mask for mailbox 0
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1)
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB0.MC4 = 0x03;
/* Set mailbox 0 as for reception */
/* Set interrupts */
HCAN_IMR = 0xFFFD;
/* Enable message reception interrupts */
HCAN_MBIMR0 = 0xFFFE;
/* Enable mailbox 0 reception interrupt requests
INTC.IPRK = 0x00F0;
/* Set RM1 priority */
Rev. 1.00, 08/03, page 34 of 74
*/
*/
*/
*/
/* Set reception method */
HCAN_MB0.MC0 = 0x5556;
set identifier */
HCAN_MB0.MC2 = 0xAAAA;
HCAN_MB0.MC5 = 0x01;
/* Select data frame and extended format,
/* Set (extended) identifier */
/* Set data length: 1 byte */
set_imask(0);
while(1);
}
/********************************************************************************/
/*
Reception interrupt routine
*/
/********************************************************************************/
#pragma interrupt(RM1_IRR1)
void RM1_IRR1(void){
/* Clear reception end register */
HCAN_RXPR0 = 0x0001;
/* Clear reception end flag (to clear, write 1) */
/* Store received data */
MBbuff = HCAN_MB0.MD7;
/* Prohibit reception interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit interrupt IRR1 */
}
Rev. 1.00, 08/03, page 35 of 74
3.9
Operation Waveforms (Transmission and Reception)
Figure 3.5 shows the waveforms during the operation of this application.
Arbitration field
ST_ID = 0x555 (11 bits)
SRR = 1 (1 bit)
IDE = 1 (1 bit)
EXT_ID = 0x2AAAA (18 bits)
RTR = 0 (1 bit)
Data field
0xAA
Control
field
CF = b’000001
ACK field
CRC field
(16 bits: generated
automatically)
CRC delimiter
SOF
Transmission waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits (generated automatically)
Figure 3.5 Operation Waveforms
Rev. 1.00, 08/03, page 36 of 74
EOF
(7 bits)
Section 4 Example 4
(Standard Format, 8 Bytes of Data, Prioritized)
4.1
Transmission and Reception Specifications
Using two SH7047F devices, transmission of 8 bytes of data in the standard format from multiple
mailboxes using identifier priority settings and reception by mailbox 0 only .
Common Transmission and Reception Specifications
• The data transfer speed is 250 kbps (during 50 MHz operation).
Transmission Specifications
• Mailboxes 1 to 15 are used.
• Messages are transmitted based on identifier priority settings.
• The data length for each mailbox is 8 bytes. The identifier and data for each mailbox are listed
in table 4.1.
Table 4.1
Mailbox Settings
MBx
Identifier (11 Bits)
Data (8 Bytes)
Priority
1
0x666
0x1111 1111 1111 1111
12
2
0x2AA
0x2222 2222 2222 2222
5
3
0x777
0x3333 3333 3333 3333
14
4
0x333
0x4444 4444 4444 4444
6
5
0x088
0x5555 5555 5555 5555
1
6
0x4CC
0x6666 6666 6666 6666
9
7
0x199
0x7777 7777 7777 7777
3
8
0x7FF
0x8888 8888 8888 8888
15
9
0x111
0x9999 9999 9999 9999
2
10
0x444
0xAAAA AAAA AAAA AAAA
8
11
0x555
0xBBBB BBBB BBBB BBBB
10
12
0x6EE
0xCCCC CCCC CCCC CCCC
13
13
0x3BB
0xDDDD DDDD DDDD DDDD
7
14
0x222
0xEEEE EEEE EEEE EEEE
4
15
0x5DD
0xFFFF FFFF FFFF FFFF
11
Rev. 1.00, 08/03, page 37 of 74
• The data from mailboxes 1 to 15 is transmitted in a single batch.
• The transmission end flag is polled while transmission is in progress.
• After confirmation that the transmission end flag has been set, the transmission end flag is
cleared, completing the operation.
Reception Specifications
• Mailbox 0 is used.
• Identifiers are not masked and all transmissions are received.
• The message reception interrupt (IRR1) is used.
(a) When data is received DTC is triggered by the message reception interrupt, and the
received data is stored in on-chip RAM.
(b) Block transfer mode is used for DTC transfers. Fifteen blocks are transferred, with each
block containing 8 bytes of data.
(c) After the DTC transfers are completed, the reception end flag is cleared and message
reception interrupts are prohibited within the message reception interrupt routine,
completing the operation.
4.2
Transmission and Reception Specifications, Function Description
Tables 4.2 and 4.3 list the functions allocated to registers. (See example 1 for information on pins
and port registers.)
Rev. 1.00, 08/03, page 38 of 74
Table 4.2
HCAN-2 Function Allocation
Register
Common
transmission
and reception
registers
Function
MCR
Master control register
Controls operation of HCAN-2.
BCR0
Bit timing configuration registers
BCR1
Used to set baud rate prescaler and bit timing parameters of
CAN.
IRR
Interrupt request register
Shows status of interrupt sources.
MBx
MC0
Message control register
Used to set identifier and whether frames are data frames or
remote frames.
MC4
Message control register
Used to select transmission or reception.
MC5
Message control register
Used to set the data length.
MD7 to
MD14
Message data registers
Store transmitted and received CAN message data.
LAFM15 Local acceptance filter mask
Used to set filter mask for identifier of reception mailbox.
Transmission
registers
TXPR
Transmission wait register
Used to set transmission wait status after transmitted message
is stored in mailbox.
TXACK
Transmission acknowledge register
Indicates that the transmitted message has been properly
transmitted to the corresponding mailbox.
Reception
register
RXPR
Interrupt
registers
MBIMR
Reception end register
Indicates that the data has been properly received by the
corresponding mailbox.
Mailbox interrupt mask register
Used to enable interrupt requests for mailboxes.
IMR
Interrupt mask register
Used to enable interrupt requests using IRR interrupt flag.
IPRK
Interrupt priority register
Used to set the priority of HCAN-2 interrupt requests.
Rev. 1.00, 08/03, page 39 of 74
Table 4.3
DTC Function Allocation
Register
Function
DTMR
DTC mode register
Controls the DTC operation mode.
DTSAR
DTC source address register
Specifies the source address for data to be transferred using DTC.
DTDAR
DTC destination address register
Specifies the destination address for data to be transferred using DTC.
DTCRA
DTC transfer count register A
Specifies the number of DTC transfers.
DTCRB
DTC transfer count register B
In the block transfer mode, specifies the block length.
DTBR
DTC database register
Specifies the top 16 bits of the memory address at which data transferred using
DTC is to be stored.
DTEF
DTC enable register
Selects the interrupt source (RM1 in HCAN-2) for starting DTC.
Rev. 1.00, 08/03, page 40 of 74
4.3
Transmission Flowchart
Transmission operation: main routine
Clear bit MCR0
Clear bit IRR0
Set pins
Set bit rate
Initialize mailboxes
Mailbox 1
Set MBC
Set transmission method
Set transmission data
Mailbox 2
Set MBC
Set transmission method
Set transmission data
Mailbox 14
Set MBC
Set transmission method
Set transmission data
Mailbox 15
Set MBC
Set transmission method
Set transmission data
1
Figure 4.1 Transmission Flowchart (1)
Rev. 1.00, 08/03, page 41 of 74
1
Set to transmission wait status
Transmission complete?
No
Yes
Clear transmission end flag
End of transmission
Figure 4.2 Transmission Flowchart (2)
Rev. 1.00, 08/03, page 42 of 74
4.4
Software Description (Transmission)
Module Description
Module
Label
Function
Main routine
t_main
Performs initial settings and transmission settings for HCAN-2.
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
Initial Value
Module
work
Work register used for mailbox
initialization.
―
Main routine
HCAN_MCR
Clears reset request bit. Also sets
transmissions based on priority of
mailbox identifier.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is
50 MHz.
HCAN_BCR1
0x0009
0x4300
HCAN_MBx.MC0
Sets data frame and standard format
for mailboxes 1 to 15. Also sets
identifiers (see table 4.1 for setting
values).
―
HCAN_MBx.MC4
Sets mailboxes 1 to 15 as for
transmission.
0x01
HCAN_MBx.MC5
Sets transmission size for mailboxes 1
to 15 to a data length of 8 bytes.
0x08
HCAN_MBx.MD7 to 14
Sets transmission data for mailboxes 1
to 15. Also sets identifiers (see table
4.1 for setting values).
―
HCAN_TXPR0
Sets mailboxes 1 to 15 to transmission
wait status.
0xFFFE
HCAN_TXACK0
Checks and clears transmission end
flags for mailboxes 1 to 15. (To clear,
write 1.)
0xFFFE
Rev. 1.00, 08/03, page 43 of 74
4.5
Transmission Program Listing
/********************************************************************************/
/*
HCAN-2 Transmission Program (Example 4)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declaration
*/
/********************************************************************************/
void t_main(void );
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void t_main(void){
unsigned short *work;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit,
identifier priority-based transmission */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailboxes */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set transmission data */
/*** MB1 ***/
HCAN_MB1.MC4 = 0x01;
HCAN_MB1.MC0 = 0x6660;
set identifier */
HCAN_MB1.MC5 = 0x08;
HCAN_MB1.MD7 = 0x11;
HCAN_MB1.MD8 = 0x11;
HCAN_MB1.MD9 = 0x11;
HCAN_MB1.MD10 = 0x11;
HCAN_MB1.MD11 = 0x11;
HCAN_MB1.MD12 = 0x11;
HCAN_MB1.MD13 = 0x11;
HCAN_MB1.MD14 = 0x11;
Rev. 1.00, 08/03, page 44 of 74
/* Set mailbox 1 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 00010001
data: 00010001
data: 00010001
data: 00010001
data: 00010001
data: 00010001
data: 00010001
data: 00010001
*/
*/
*/
*/
*/
*/
*/
*/
/*** MB2 ***/
HCAN_MB2.MC4 = 0x01;
HCAN_MB2.MC0 = 0x2AA0;
set identifier */
HCAN_MB2.MC5 = 0x08;
HCAN_MB2.MD7 = 0x22;
HCAN_MB2.MD8 = 0x22;
HCAN_MB2.MD9 = 0x22;
HCAN_MB2.MD10 = 0x22;
HCAN_MB2.MD11 = 0x22;
HCAN_MB2.MD12 = 0x22;
HCAN_MB2.MD13 = 0x22;
HCAN_MB2.MD14 = 0x22;
/*** MB3 ***/
HCAN_MB3.MC4 = 0x01;
HCAN_MB3.MC0 = 0x7770;
set identifier */
HCAN_MB3.MC5 = 0x08;
HCAN_MB3.MD7 = 0x33;
HCAN_MB3.MD8 = 0x33;
HCAN_MB3.MD9 = 0x33;
HCAN_MB3.MD10 = 0x33;
HCAN_MB3.MD11 = 0x33;
HCAN_MB3.MD12 = 0x33;
HCAN_MB3.MD13 = 0x33;
HCAN_MB3.MD14 = 0x33;
/*** MB4 ***/
HCAN_MB4.MC4 = 0x01;
HCAN_MB4.MC0 = 0x3330;
set identifier */
HCAN_MB4.MC5 = 0x08;
HCAN_MB4.MD7 = 0x44;
HCAN_MB4.MD8 = 0x44;
HCAN_MB4.MD9 = 0x44;
HCAN_MB4.MD10 = 0x44;
HCAN_MB4.MD11 = 0x44;
HCAN_MB4.MD12 = 0x44;
HCAN_MB4.MD13 = 0x44;
HCAN_MB4.MD14 = 0x44;
/*** MB5 ***/
HCAN_MB5.MC4 = 0x01;
HCAN_MB5.MC0 = 0x0880;
set identifier */
HCAN_MB5.MC5 = 0x08;
HCAN_MB5.MD7 = 0x55;
HCAN_MB5.MD8 = 0x55;
HCAN_MB5.MD9 = 0x55;
HCAN_MB5.MD10 = 0x55;
/* Set mailbox 2 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 00100010
data: 00100010
data: 00100010
data: 00100010
data: 00100010
data: 00100010
data: 00100010
data: 00100010
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 3 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 00110011
data: 00110011
data: 00110011
data: 00110011
data: 00110011
data: 00110011
data: 00110011
data: 00110011
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 4 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 01000100
data: 01000100
data: 01000100
data: 01000100
data: 01000100
data: 01000100
data: 01000100
data: 01000100
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 5 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
8 bytes */
data: 01010101
data: 01010101
data: 01010101
data: 01010101
*/
*/
*/
*/
Rev. 1.00, 08/03, page 45 of 74
HCAN_MB5.MD11
HCAN_MB5.MD12
HCAN_MB5.MD13
HCAN_MB5.MD14
=
=
=
=
0x55;
0x55;
0x55;
0x55;
/*** MB6 ***/
HCAN_MB6.MC4 = 0x01;
HCAN_MB6.MC0 = 0x4CC0;
set identifier */
HCAN_MB6.MC5 = 0x08;
HCAN_MB6.MD7 = 0x66;
HCAN_MB6.MD8 = 0x66;
HCAN_MB6.MD9 = 0x66;
HCAN_MB6.MD10 = 0x66;
HCAN_MB6.MD11 = 0x66;
HCAN_MB6.MD12 = 0x66;
HCAN_MB6.MD13 = 0x66;
HCAN_MB6.MD14 = 0x66;
/*** MB7 ***/
HCAN_MB7.MC4 = 0x01;
HCAN_MB7.MC0 = 0x1990;
set identifier */
HCAN_MB7.MC5 = 0x08;
HCAN_MB7.MD7 = 0x77;
HCAN_MB7.MD8 = 0x77;
HCAN_MB7.MD9 = 0x77;
HCAN_MB7.MD10 = 0x77;
HCAN_MB7.MD11 = 0x77;
HCAN_MB7.MD12 = 0x77;
HCAN_MB7.MD13 = 0x77;
HCAN_MB7.MD14 = 0x77;
/*** MB8 ***/
HCAN_MB8.MC4 = 0x01;
HCAN_MB8.MC0 = 0x7FF0;
set identifier */
HCAN_MB8.MC5 = 0x08;
HCAN_MB8.MD7 = 0x88;
HCAN_MB8.MD8 = 0x88;
HCAN_MB8.MD9 = 0x88;
HCAN_MB8.MD10 = 0x88;
HCAN_MB8.MD11 = 0x88;
HCAN_MB8.MD12 = 0x88;
HCAN_MB8.MD13 = 0x88;
HCAN_MB8.MD14 = 0x88;
Rev. 1.00, 08/03, page 46 of 74
/*
/*
/*
/*
Set
Set
Set
Set
transmission
transmission
transmission
transmission
data:
data:
data:
data:
01010101
01010101
01010101
01010101
*/
*/
*/
*/
/* Set mailbox 6 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 01100110
data: 01100110
data: 01100110
data: 01100110
data: 01100110
data: 01100110
data: 01100110
data: 01100110
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 7 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 01110111
data: 01110111
data: 01110111
data: 01110111
data: 01110111
data: 01110111
data: 01110111
data: 01110111
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 8 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 10001000
data: 10001000
data: 10001000
data: 10001000
data: 10001000
data: 10001000
data: 10001000
data: 10001000
*/
*/
*/
*/
*/
*/
*/
*/
/*** MB9 ***/
HCAN_MB9.MC4 = 0x01;
HCAN_MB9.MC0 = 0x1110;
set identifier */
HCAN_MB9.MC5 = 0x08;
HCAN_MB9.MD7 = 0x99;
HCAN_MB9.MD8 = 0x99;
HCAN_MB9.MD9 = 0x99;
HCAN_MB9.MD10 = 0x99;
HCAN_MB9.MD11 = 0x99;
HCAN_MB9.MD12 = 0x99;
HCAN_MB9.MD13 = 0x99;
HCAN_MB9.MD14 = 0x99;
/*** MB10 ***/
HCAN_MB10.MC4 = 0x01;
HCAN_MB10.MC0 = 0x4440;
set identifier */
HCAN_MB10.MC5 = 0x08;
HCAN_MB10.MD7 = 0xAA;
HCAN_MB10.MD8 = 0xAA;
HCAN_MB10.MD9 = 0xAA;
HCAN_MB10.MD10 = 0xAA;
HCAN_MB10.MD11 = 0xAA;
HCAN_MB10.MD12 = 0xAA;
HCAN_MB10.MD13 = 0xAA;
HCAN_MB10.MD14 = 0xAA;
/*** MB11 ***/
HCAN_MB11.MC4 = 0x01;
HCAN_MB11.MC0 = 0x5550;
set identifier */
HCAN_MB11.MC5 = 0x08;
HCAN_MB11.MD7 = 0xBB;
HCAN_MB11.MD8 = 0xBB;
HCAN_MB11.MD9 = 0xBB;
HCAN_MB11.MD10 = 0xBB;
HCAN_MB11.MD11 = 0xBB;
HCAN_MB11.MD12 = 0xBB;
HCAN_MB11.MD13 = 0xBB;
HCAN_MB11.MD14 = 0xBB;
/*** MB12 ***/
HCAN_MB12.MC4 = 0x01;
HCAN_MB12.MC0 = 0x6EE0;
set identifier */
HCAN_MB12.MC5 = 0x08;
HCAN_MB12.MD7 = 0xCC;
HCAN_MB12.MD8 = 0xCC;
HCAN_MB12.MD9 = 0xCC;
HCAN_MB12.MD10 = 0xCC;
/* Set mailbox 9 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 10011001
data: 10011001
data: 10011001
data: 10011001
data: 10011001
data: 10011001
data: 10011001
data: 10011001
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 10 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 10101010
data: 10101010
data: 10101010
data: 10101010
data: 10101010
data: 10101010
data: 10101010
data: 10101010
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 11 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 10111011
data: 10111011
data: 10111011
data: 10111011
data: 10111011
data: 10111011
data: 10111011
data: 10111011
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 12 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
8 bytes */
data: 11001100
data: 11001100
data: 11001100
data: 11001100
*/
*/
*/
*/
Rev. 1.00, 08/03, page 47 of 74
HCAN_MB12.MD11
HCAN_MB12.MD12
HCAN_MB12.MD13
HCAN_MB12.MD14
=
=
=
=
0xCC;
0xCC;
0xCC;
0xCC;
/*** MB13 ***/
HCAN_MB13.MC4 = 0x01;
HCAN_MB13.MC0 = 0x3BB0;
set identifier */
HCAN_MB13.MC5 = 0x08;
HCAN_MB13.MD7 = 0xDD;
HCAN_MB13.MD8 = 0xDD;
HCAN_MB13.MD9 = 0xDD;
HCAN_MB13.MD10 = 0xDD;
HCAN_MB13.MD11 = 0xDD;
HCAN_MB13.MD12 = 0xDD;
HCAN_MB13.MD13 = 0xDD;
HCAN_MB13.MD14 = 0xDD;
/*** MB14 ***/
HCAN_MB14.MC4 = 0x01;
HCAN_MB14.MC0 = 0x2220;
set identifier */
HCAN_MB14.MC5 = 0x08;
HCAN_MB14.MD7 = 0xEE;
HCAN_MB14.MD8 = 0xEE;
HCAN_MB14.MD9 = 0xEE;
HCAN_MB14.MD10 = 0xEE;
HCAN_MB14.MD11 = 0xEE;
HCAN_MB14.MD12 = 0xEE;
HCAN_MB14.MD13 = 0xEE;
HCAN_MB14.MD14 = 0xEE;
/*** MB15 ***/
HCAN_MB15.MC4 = 0x01;
HCAN_MB15.MC0 = 0x5DD0;
set identifier */
HCAN_MB15.MC5 = 0x08;
HCAN_MB15.MD7 = 0xFF;
HCAN_MB15.MD8 = 0xFF;
HCAN_MB15.MD9 = 0xFF;
HCAN_MB15.MD10 = 0xFF;
HCAN_MB15.MD11 = 0xFF;
HCAN_MB15.MD12 = 0xFF;
HCAN_MB15.MD13 = 0xFF;
HCAN_MB15.MD14 = 0xFF;
/*
/*
/*
/*
Set
Set
Set
Set
transmission
transmission
transmission
transmission
data:
data:
data:
data:
11001100
11001100
11001100
11001100
*/
*/
*/
*/
/* Set mailbox 13 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 11011101
data: 11011101
data: 11011101
data: 11011101
data: 11011101
data: 11011101
data: 11011101
data: 11011101
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 14 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 11101110
data: 11101110
data: 11101110
data: 11101110
data: 11101110
data: 11101110
data: 11101110
data: 11101110
*/
*/
*/
*/
*/
*/
*/
*/
/* Set mailbox 15 as for transmission */
/* Select data frame and standard format,
/*
/*
/*
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
Set
Set
Set
data length:
transmission
transmission
transmission
transmission
transmission
transmission
transmission
transmission
8 bytes */
data: 11111111
data: 11111111
data: 11111111
data: 11111111
data: 11111111
data: 11111111
data: 11111111
data: 11111111
*/
*/
*/
*/
*/
*/
*/
*/
/* Set message transmission wait status */
HCAN_TXPR0 = 0xFFFE; /* Set mailboxes 1 to 15 to transmission wait status */
/* Wait for transmission end */
while((HCAN_TXACK0 & 0xFFFE) != 0xFFFE);
Rev. 1.00, 08/03, page 48 of 74
/* Clear transmission end flag */
HCAN_TXACK0 = 0xFFFE; /* Clear transmission end flag (to clear, write 1) */
while(1);
}
4.6
Reception Flowchart
Reception operation: main routine
Initialize reception data storage area
Set DTC
Clear bit MCR0
Set local acceptance filter
Clear bit IRR0
Set pins
Set bit rate
Initialize mailboxes
Set MBC
Set reception interrupts
Set reception method
Figure 4.3 Reception Flowchart (1)
Rev. 1.00, 08/03, page 49 of 74
Reception interrupt routine
Clear reception end flag
Prohibit reception interrupts
RTE
Figure 4.4 Reception Flowchart (2)
4.7
Software Description (Reception)
Module Description
Module
Label
Function
Main routine
r_main
Performs initial settings and reception settings for
HCAN-2.
Reception interrupt
routine
RM1_IRR1
Clears reception end flag and sets interrupt prohibition.
Rev. 1.00, 08/03, page 50 of 74
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
Initial Value
Module
MBbuff
Storage area for received data base
address (H'FFFFD100).
―
Main routine
work
Work register used for mailbox
initialization.
―
DTMR
Increments both DTSAR and DTDAR
after transfer completes, sets block
transfer mode and byte transfer.
0xA890
DTSAR
Sets transfer source address as mailbox
0 message data area.
0xFFFFB108
DTDAR
Sets transfer destination address as
received data storage area.
0xFFFFD100
DTCRA
Sets number of block transfers (15).
0x000F
DTCRB
Sets block length (8 bytes).
0x0008
DTC.DTBR
Sets top 16 bits of memory address at
which data transferred using DTC is
stored.
0xFFFF
DTC.DTEF
Selects the interrupt source (RM1 in
HCAN-2) for starting DTC.
0x04
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is
50 MHz.
0x0009
HCAN_BCR1
0x4300
HCAN_MB0.MC0
Sets data frame and standard format for
mailbox 0.
0x0000
HCAN_MB0.MC4
Sets mailbox 0 as for reception.
0x03
HCAN_MB0.MC5
Sets mailbox 0 reception size to a data
length of 8 bytes.
0x08
HCAN_MB0.LAFM15
Sets identifier filter mask for mailbox 0.
0x7FF0
HCAN_IMR
Enables message reception interrupts.
0xFFFD
HCAN_MBIMR0
Enables mailbox 0 interrupt requests.
0xFFFE
INTC.IPRK
Sets priority of HCAN-2 interrupt
requests.
0x00F0
HCAN_RXPR0
Clears mailbox 0 reception end flag.
(To clear, write 1.)
0x0001
HCAN_IMR
Prohibits message reception interrupts.
0xFFFF
Reception
interrupt
routine
Rev. 1.00, 08/03, page 51 of 74
4.8
Reception Program Listing
/********************************************************************************/
/*
HCAN-2 Reception Program (Example 4)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void r_main(void );
void RM1_IRR1(void);
/********************************************************************************/
/*
Define constants
*/
/********************************************************************************/
#define DTMR (*(unsigned short *)0xFFFFD080) /* DTC register data */
#define DTCRA (*(unsigned short *)0xFFFFD082) /* DTC register data */
#define DTCRB (*(unsigned short *)0xFFFFD086) /* DTC register data */
#define DTSAR (*(unsigned long *)0xFFFFD088) /* DTC register data */
#define DTDAR (*(unsigned long *)0xFFFFD08C) /* DTC register data */
#define MBbuff (*(unsigned char *)0xFFFFD100) /* Storage area for received data */
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void r_main(void){
unsigned short *work;
/* Initialize storage area for received data */
work = (unsigned short *)0xFFFFD100;
do {
*work = 0x0000;
work++;
} while(work < (unsigned short *)0xFFFFD180);
/* DTC settings */
DTMR = 0xA890;
/* Increment both DTSAR and DTDAR
after transfer completes, set block transfer mode and byte transfer */
DTSAR = (unsigned long)&HCAN_MB0.MD7; /* Set transfer source address */
DTDAR = (unsigned long)&MBbuff;
/* Set transfer destination address */
DTCRA = 0x000F;
/* Block transfer: 15 blocks */
DTCRB = 0x0008;
/* Block length: 8 bytes */
DTC.DTBR = 0xFFFF;
/* Register data base address */
DTC.DTEF |= 0x04;
/* HCAN-2 interrupt (RM1) */
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Set local acceptance filter */
HCAN_MB0.LAFM15 = 0x7FF0;
/* Set identifier filter mask for mailbox 0 */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
Rev. 1.00, 08/03, page 52 of 74
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB0.MC4 = 0x03;
/* Set mailbox 0 as for reception */
/* Set interrupts */
HCAN_IMR = 0xFFFD;
/* Enable message reception
interrupts */
HCAN_MBIMR0 = 0xFFFE;
/* Enable mailbox 0 reception interrupt requests */
INTC.IPRK = 0x00F0;
/* Set RM1 priority */
/* Set reception method */
HCAN_MB0.MC0 = 0x0000;
/* Select data frame and standard format,
set identifier */
HCAN_MB0.MC5 = 0x08;
/* Set data length: 8 bytes */
set_imask(0);
while(1);
}
/********************************************************************************/
/*
Reception interrupt routine
*/
/********************************************************************************/
#pragma interrupt(RM1_IRR1)
void RM1_IRR1(void){
/* Clear reception end register */
HCAN_RXPR0 = 0x0001;
/* Clear reception end flag (to clear, write 1) */
/* Prohibit reception interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit message reception interrupts */
}
Rev. 1.00, 08/03, page 53 of 74
4.9
Operation Waveforms (Transmission and Reception)
Figures 4.5 and 4.6 show the waveforms at the start and end of the operation of this application.
ACK field
Control field
CF = b’001000
Arbitration field
ID = 0x088 (11 bits)
RTR = 0 (1 bit)
Transmission
waveforms
SOF
CRC field
(16 bits: generated
automatically)
Data field
0x55 ´ 8
EOF (7 bits)
CRC delimiter
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception
waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits (generated automatically)
Figure 4.5 Operation Waveforms (Start of Operation)
Rev. 1.00, 08/03, page 54 of 74
Intermission
(3 bits)
SOF
Intermission
(3 bits)
ACK field
Control field
CF = b’001000
Arbitration field
ID = 0x7FF (11 bits)
RTR = 0 (1 bit)
Transmission
waveforms
SOF
CRC field
(16 bits: generated
automatically)
Data field
0x88 ´ 8
EOF (7 bits)
CRC delimiter
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception
waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits (generated automatically)
Figure 4.6 Operation Waveforms (End of Operation)
Rev. 1.00, 08/03, page 55 of 74
Section 5 Example 5
(Remote Frame)
5.1
Transmission and Reception Specifications
Remote frame transmission and reception in the standard format using two SH7047F devices.
Common Transmission and Reception Specifications
• The data transfer speed is 250 kbps (during 50 MHz operation).
• The identifier is H'555.
• The identifier is masked and reception takes place when a match occurs.
Remote Frame Transmission Specifications
• Mailbox 1 is used for remote frame transmission and data frame reception.
• Eight bytes of data are requested.
• The message reception interrupt (IRR1) is used.
(a) After remote frame transmission the system enters message reception interrupt wait status.
(b) The reception end flag is cleared and message reception interrupts are prohibited within the
message reception interrupt routine.
(c) When the data is received DTC settings are made and the software is triggered within the
message reception interrupt routine, and the received data is stored in on-chip RAM.
(d) Block transfer mode is used for the DTC transfer, and the 8 bytes of data are transferred as
a single block.
• The DTC transfer end interrupt is used.
Triggering of the DTC software is prohibited within the DTC transfer end interrupt routine,
completing the operation.
Remote Frame Reception Specifications
• Mailbox 1 is used for remote frame reception and data frame transmission.
• The data frame is prepared in advance, and the automatic transmission function (ATX) is used.
• The data transmitted is H'55, H'66, H'77, H'88, H'99, H'AA, H'BB, H'FF.
• The remote frame request interrupt (IRR2) is used.
(a) The remote frame reception end flag is cleared and reception interrupts are prohibited
within the remote frame request interrupt routine, and the data frame transmission end flag
is polled.
Rev. 1.00, 08/03, page 56 of 74
(b) Once it has been confirmed that the transmission end flag has been set, the transmission
end flag is cleared, completing the operation.
5.2
Transmission and Reception Specifications, Function Description
Tables 5.1 and 5.2 list the functions allocated to registers. (See example 1 for information on pins
and port registers.)
Table 5.1
HCAN-2 Function Allocation
Register
Common
transmission
and reception
registers
Function
MCR
Master control register
Controls operation of HCAN-2.
BCR0
Bit timing configuration registers
BCR1
Used to set baud rate prescaler and bit timing parameters of
CAN.
IRR
Interrupt request register
Shows status of interrupt sources.
MBx
MC0
Message control register
Used to set identifier and whether frames are data frames or
remote frames.
MC4
Message control register
Used to select transmission or reception.
MC5
Message control register
Used to set the data length.
MD7 to
MD14
Message data registers
Store transmitted and received CAN message data.
LAFM15 Local acceptance filter mask
Used to set filter mask for identifier of reception mailbox.
Transmission
registers
TXPR
Transmission wait register
Used to set transmission wait status after transmitted message
is stored in mailbox.
TXACK
Transmission acknowledge register
Indicates that the transmitted message has been properly
transmitted to the corresponding mailbox.
Rev. 1.00, 08/03, page 57 of 74
Register
Reception
register
Function
RXPR
Reception end register
Indicates that the data has been properly received by the
corresponding mailbox.
RFPR
Remote request register
Indicates reception of remote frames by the corresponding
mailbox.
Interrupt
registers
MBIMR
Mailbox interrupt mask register
Used to enable interrupt requests for mailboxes.
IMR
Interrupt mask register
Used to enable interrupt requests using IRR interrupt flag.
IPRK
Interrupt priority register
Used to set the priority of HCAN-2 interrupt requests.
Table 2.2
DTC Function Allocation
Register
Function
DTMR
DTC mode register
Controls the DTC operation mode.
DTSAR
DTC source address register
Specifies the source address for data to be transferred using DTC.
DTDAR
DTC destination address register
Specifies the destination address for data to be transferred using DTC.
DTCRA
DTC transfer count register A
Specifies the number of DTC transfers.
DTCRB
DTC transfer count register B
In the block transfer mode, specifies the block length.
DTBR
DTC database register
Specifies the top 16 bits of the memory address at which data transferred using
DTC is to be stored.
DTCSR
DTC control/status register
Used to enable or prohibit software triggering of DTC and to set the vector
address for software triggering of DTC.
IPRG
Interrupt priority register
Used to set the priority of DTC interrupt requests.
Rev. 1.00, 08/03, page 58 of 74
5.3
Transmission Flowchart
Transmission operation: main routine
(remote frame transmission)
Initialize reception data storage area
Clear bit MCR0
Set local acceptance filter
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set reception interrupt
Set remote frame transmission
Set to transmission wait status
Transmission complete?
No
Yes
Clear transmission end flag
Figure 5.1 Transmission Flowchart (1)
Rev. 1.00, 08/03, page 59 of 74
Reception interrupt routine
Clear reception end flag
Prohibit reception interrupts
Set and trigger DTC
RTE
Figure 5.2 Transmission Flowchart (2)
DTC transfer end interrupt routine
Prohibit DTC software triggering
RTE
Figure 5.3 Transmission Flowchart (3)
Rev. 1.00, 08/03, page 60 of 74
5.4
Software Description (Transmission)
Module Description
Module
Label
Function
Main routine
t_main
Performs initial settings and transmission settings for
HCAN-2.
Reception interrupt
routine
RM1_IRR1
Clears reception end flag, prohibits reception interrupts,
and stored received data by triggering DTC.
DTC transfer end
interrupt routine
DTC_SWDTEND
Prohibits DTC triggering by software.
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
MBbuff
Storage area for received data (address: ―
H'FFFFD100–H'FFFFD108).
work
Work register used for mailbox
initialization.
―
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is
50 MHz.
0x0009
HCAN_BCR1
Initial Value
Module
Main routine
0x4300
HCAN_MB1.MC0
Sets remote frame and standard format 0x5558
for mailbox 1. Also sets identifier (H'555).
HCAN_MB1.MC4
Sets mailbox 1 to allow remote frame
transmission and data frame reception.
0x05
HCAN_MB1.MC5
Sets mailbox 1 transmission size to a
data length of 8 bytes.
0x08
HCAN_MB1.LAFM15
Sets identifier filter mask for mailbox 1.
0x0000
HCAN_IMR
Enables message reception interrupts.
0xFFFD
HCAN_MBIMR0
Enables mailbox 1 interrupt requests.
0xFFFD
INTC.IPRK
Sets priority of HCAN-2 interrupt
requests.
0x00F0
INTC.IPRG
Sets priority of DTC interrupt requests.
0x0E00
HCAN_TXPR0
Sets mailbox 1 to transmission wait
status.
0x0002
HCAN_TXACK0
Checks and clears mailbox 1
0x0002
transmission end flag. (To clear, write 1.)
Rev. 1.00, 08/03, page 61 of 74
Register
Function
Initial Value
Module
HCAN_RXPR0
Checks and clears mailbox 1 reception
end flag. (To clear, write 1.)
0x0002
Reception
interrupt
routine
HCAN_IMR
Prohibits message reception interrupts.
0xFFFF
DTMR
Increments both DTSAR and DTDAR
after transfer completes, sets block
transfer mode and byte transfer.
0xA890
DTSAR
Sets transfer source address as mailbox
1 message data area.
H’FFFFB128
DTDAR
Sets transfer destination address as
received data storage area.
H’FFFFD100
DTCRA
Sets number of block transfers (1).
0x0001
DTCRB
Sets block length (8 bytes).
0x0008
DTC.DTBR
Sets top 16 bits of memory address at
which data transferred using DTC is
stored.
0xFFFF
DTC.DTCSR
Sets DTC software trigger and DTC
vector address (H'0000045A).
0x015A
DTC.DTCSR
Prohibits DTC software triggering.
0x06FF
Rev. 1.00, 08/03, page 62 of 74
DTC transfer
end interrupt
routine
5.5
Transmission Program Listing
/********************************************************************************/
/*
HCAN-2 Transmission Program (Example 5)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file */
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void t_main(void );
void RM1_IRR1(void);
void DTC_SWDTEND(void);
/********************************************************************************/
/*
Define constants
*/
/********************************************************************************/
#define DTMR (*(unsigned short *)0xFFFFD080) /* DTC register data */
#define DTCRA (*(unsigned short *)0xFFFFD082) /* DTC register data */
#define DTCRB (*(unsigned short *)0xFFFFD086) /* DTC register data */
#define DTSAR (*(unsigned long *)0xFFFFD088) /* DTC register data */
#define DTDAR (*(unsigned long *)0xFFFFD08C) /* DTC register data */
#define MBbuff (*(unsigned char *)0xFFFFD100) /* Storage area for received data */
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void t_main(void){
unsigned short *work;
/* Initialize storage area for received data */
work = (unsigned short *)0xFFFFD100;
do {
*work = 0x0000;
work++;
} while(work < (unsigned short *)0xFFFFD108);
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Set local acceptance filter */
HCAN_MB1.LAFM15 = 0x0000;
/* Set identifier filter mask for mailbox 1 */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
Rev. 1.00, 08/03, page 63 of 74
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB1.MC4 = 0x05;
/* Set mailbox 1 to enable remote frame
transmission and data frame reception */
/* Set reception interrupt */
HCAN_IMR = 0xFFFD;
/* Enable message reception interrupts */
HCAN_MBIMR0 = 0xFFFD;
/* Enable mailbox 1 interrupt requests */
INTC.IPRK = 0x00F0;
/* Set RM1 priority */
INTC.IPRG = 0x0E00;
/* Set DTC interrupt priority */
/* Set remote frame transmission */
HCAN_MB1.MC0 = 0x5558;
/* Select remote frame and standard
format, set identifier */
HCAN_MB1.MC5 = 0x08;
/* Set data length: 8 bytes */
/* Set message transmission wait status */
HCAN_TXPR0 = 0x0002;
/* Set mailbox 1 to transmission wait status */
/* Wait for transmission end */
while((HCAN_TXACK0 & 0x0002) != 0x0002);
/* Clear transmission end flag */
HCAN_TXACK0 = 0x0002; /* Clear transmission end flag (to clear, write 1) */
set_imask(0);
while(1);
}
/********************************************************************************/
/*
Reception interrupt routine
*/
/********************************************************************************/
#pragma interrupt(RM1_IRR1)
void RM1_IRR1(void){
/* Clear reception end flag */
HCAN_RXPR0 = 0x0002;
/* Clear reception end flag (to clear, write 1) */
/* Prohibit reception interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit message reception interrupts */
/* Set and trigger DTC */
DTMR = 0xA890;
/* Increment both DTSAR and DTDAR
after transfer completes, set block transfer mode and byte transfer */
DTSAR = (unsigned long)&HCAN_MB1.MD7; /* Set transfer source address */
DTDAR = (unsigned long)&MBbuff;
/* Set transfer destination address */
DTCRA = 0x0001;
/* Block transfer: 1 block */
DTCRB = 0x0008;
/* Block length: 8 bytes */
DTC.DTBR = 0xFFFF;
/* Register data base address */
while((DTC.DTCSR & 0x0100) != 0x0000); /* Confirm DTC software triggering is
prohibited */
DTC.DTCSR = 0x015A;
/* Enable DTC software triggering */
Rev. 1.00, 08/03, page 64 of 74
while((DTC.DTCSR & 0x00FF) != 0x005A); /* Confirm DTC trigger vector address
*/
}
/********************************************************************************/
/*
DTC transfer end interrupt routine
*/
/********************************************************************************/
#pragma interrupt(DTC_SWDTEND)
void DTC_SWDTEND(void){
DTC.DTCSR &= 0x06FF;
/* Prohibit DTC software triggering */
}
Rev. 1.00, 08/03, page 65 of 74
5.6
Reception Flowchart
Reception operation: main routine
(remote frame reception)
Clear bit MCR0
Set local acceptance filter
Clear bit IRR0
Set pins
Set bit rate
Initialize mailbox
Set MBC
Set remote request interrupt
Set transmission data
Figure 5.4 Reception Flowchart (1)
Rev. 1.00, 08/03, page 66 of 74
Remote request interrupt routine
Clear remote frame reception end flag
Prohibit remote frame reception interrupt
Data frame
transmission complete?
No
Yes
Clear transmission end flag
RTE
Figure 5.5 Reception Flowchart (2)
5.7
Software Description (Reception)
Module Description
Module
Label
Function
Main routine
r_main
Performs initial settings and reception settings for HCAN-2.
Remote request
interrupt routine
RM1_IRR2
Clears remote frame reception end flag, sets interrupt
prohibition, and checks and clears transmission end flag.
Rev. 1.00, 08/03, page 67 of 74
Description of Registers Used (See example 1 for information on pins and port registers.)
Register
Function
Initial Value
Module
work
Work register used for mailbox
initialization.
―
Main routine
HCAN_MCR
Clears reset request bit.
0x0000
HCAN_IRR
Clears reset, hold, and sleep interrupt
flags. (To clear, write 1.)
0x0001
HCAN_BCR0
Sets bit rate to 250 kbps when φ is
50 MHz.
0x0009
HCAN_BCR1
0x4300
HCAN_MB1.MC0
Sets data frame and standard format
for mailbox 1. Also sets identifier
(H'555).
0x5550
HCAN_MB1.MC4
Enables remote frame reception and
data frame transmission for mailbox 1.
Also sets ATX (automatic data frame
transmission).
0x11
HCAN_MB1.MC5
Sets mailbox 1 transmission size to a
data length of 8 bytes.
0x08
HCAN_MB1.MC7
Sets mailbox 1 byte 1 transmission
data (H'55).
0x55
HCAN_MB1.MC8
Sets mailbox 1 byte 2 transmission
data (H'66).
0x66
HCAN_MB1.MC9
Sets mailbox 1 byte 3 transmission
data (H'77).
0x77
HCAN_MB1.MC10
Sets mailbox 1 byte 4 transmission
data (H'88).
0x88
HCAN_MB1.MC11
Sets mailbox 1 byte 5 transmission
data (H'99).
0x99
HCAN_MB1.MC12
Sets mailbox 1 byte 6 transmission
data (H'AA).
0xAA
HCAN_MB1.MC13
Sets mailbox 1 byte 7 transmission
data (H'BB).
0xBB
HCAN_MB1.MC14
Sets mailbox 1 byte 8 transmission
data (H'FF).
0xFF
HCAN_MB1.LAFM15
Sets identifier filter mask for mailbox 1.
0x0000
HCAN_IMR
Enables remote request interrupts.
0xFFFB
HCAN_MBIMR0
Enables mailbox 1 interrupt requests.
0xFFFD
INTC.IPRK
Sets the priority of HCAN-2 interrupt
requests.
0x00F0
Rev. 1.00, 08/03, page 68 of 74
Register
Function
Initial Value
Module
HCAN_RFPR0
Clears mailbox 1 remote request
transmission end flag. (To clear, write
1.)
0x0002
HCAN_IMR
Prohibits remote request interrupts.
0xFFFF
Remote
request
interrupt
routine
HCAN_TXACK0
Checks and clears mailbox 1
transmission end flag. (To clear, write
1.)
0x0002
Rev. 1.00, 08/03, page 69 of 74
5.8
Reception Program Listing
/********************************************************************************/
/*
HCAN-2 Reception Program (Example 5)
*/
/********************************************************************************/
#include <stdio.h>
/* Library function header file */
#include <machine.h>
/* Library function header file */
#include "SH7047.h"
/* Peripheral register definition header file*/
/********************************************************************************/
/*
Function prototype declarations
*/
/********************************************************************************/
void r_main(void );
void RM1_IRR2(void);
/********************************************************************************/
/*
Main routine
*/
/********************************************************************************/
void r_main(void){
unsigned short *work;
/* Clear bit MCR0 */
HCAN_MCR = 0x0000;
/* Clear reset request bit */
/* Set local acceptance filter */
HCAN_MB1.LAFM15 = 0x0000;
/* Set identifier filter mask for mailbox 1 */
/* Clear bit IRR0 */
HCAN_IRR = 0x0001;
/* Clear reset interrupt flag (to clear, write 1) */
/* Set pins */
PB.PBCR1 = 0x0000;
/* Set PB HCAN-2 */
PB.PBCR2 = 0x000F;
/* Set PB HCAN-2 */
/* Set bit rate (BCR): bit rate is 250 kbps when φ = 50 MHz */
HCAN_BCR0 = 0x0009;
/* BRP=9(10 system clock) */
HCAN_BCR1 = 0x4300;
/* TSEG1=4(5tq),TSEG2=3(4tq) */
/* Initialize mailbox */
work = (unsigned short *)0xFFFFB100;
do {
*work = 0xFFFF;
work++;
} while(work < (unsigned short *)0xFFFFB4F4);
/* Set MBC */
HCAN_MB1.MC4 = 0x11;
/* Set mailbox 1 to use ATX, enable
remote frame reception, and enable data frame transmission */
/* Set remote request interrupt */
HCAN_IMR = 0xFFFB;
/* Enable remote request interrupts */
HCAN_MBIMR0 = 0xFFFD;
/* Enable mailbox 1 interrupt requests */
INTC.IPRK = 0x00F0;
/* Set RM1 priority */
/* Set transmission data */
HCAN_MB1.MC0 = 0x5550;
/* Select data frame and standard format,
set identifier */
HCAN_MB1.MC5 = 0x08;
/* Set data length: 8 bytes */
HCAN_MB1.MD7 = 0x55;
/* Set transmission data: 01010101 */
HCAN_MB1.MD8 = 0x66;
/* Set transmission data: 01100110 */
Rev. 1.00, 08/03, page 70 of 74
HCAN_MB1.MD9 = 0x77;
HCAN_MB1.MD10 = 0x88;
HCAN_MB1.MD11 = 0x99;
HCAN_MB1.MD12 = 0xAA;
HCAN_MB1.MD13 = 0xBB;
HCAN_MB1.MD14 = 0xFF;
/*
/*
/*
/*
/*
/*
Set
Set
Set
Set
Set
Set
transmission
transmission
transmission
transmission
transmission
transmission
data:
data:
data:
data:
data:
data:
01110111
10001000
10011001
10101010
10111011
11111111
*/
*/
*/
*/
*/
*/
set_imask(0);
while(1);
}
/********************************************************************************/
/*
Remote request interrupt routine
*/
/********************************************************************************/
#pragma interrupt(RM1_IRR2)
void RM1_IRR2(void){
/* Clear remote request register */
HCAN_RFPR0 = 0x0002;
/* Clear remote frame reception end flag (to clear,
write 1) */
/* Prohibit reception interrupts */
HCAN_IMR = 0xFFFF;
/* Prohibit remote frame reception interrupts */
/* Wait for transmission end */
while((HCAN_TXACK0 & 0x0002) != 0x0002);
/* Clear transmission end flag */
HCAN_TXACK0 = 0x0002; /* Clear transmission end flag (to clear, write 1) */
}
Rev. 1.00, 08/03, page 71 of 74
5.9
Operation Waveforms (Transmission and Reception)
Figure 5.6 shows the waveforms during the operation of this application.
Control field
CF = b’001000
Control field
CF = b’001000
Intermission (3 bits)
ACK field
Arbitration field
ID = 0x555 (11 bits)
RTR = 1 (1 bit)
CRC field
(16 bits: generated
automatically)
EOF
(7 bits)
Arbitration field
ID = 0x555 (11 bits)
RTR = 0 (1 bit)
CRC delimiter
SOF
Transmission
waveforms
HT x D1 (57 pin)
Data field
(8 bytes)
SOF
HR x D1 (56 pin)
Reception
waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits
(generated automatically)
ACK field
CRC field
(16 bits: generated
automatically)
Data field (8 bytes)
Transmission
waveforms
CRC delimiter
HT x D1 (57 pin)
HR x D1 (56 pin)
Reception
waveforms
HT x D1 (57 pin)
HR x D1 (56 pin)
Stuffed bits
(generated automatically)
Figure 5.6 Operation Waveforms
Rev. 1.00, 08/03, page 72 of 74
EOF (7 bits)
Reference Documents
(1) SH7047 Series Hardware Manual, Version 1.0 (Renesas Technology Corp.)
Rev. 1.00, 08/03, page 73 of 74
Rev. 1.00, 08/03, page 74 of 74
SH7047F HCAN2 Application Note
Publication Date: 1st Edition, August 18, 2003
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Technical Documentation & Information Department
Renesas Kodaira Semiconductor Co., Ltd.
©2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Colophon 0.0
SH7047F HCAN2
REJ05B0144-0100O