HYM532410C M-Series 4Mx32 bit FP DRAM MODULE based on 4Mx4 DRAM, 5V, 2K-Refresh GENERAL DESCRIPTION The HYM532410C M-Series is a 4Mx32-bit Fast Page mode CMOS DRAM module consisting of eight HY5117400C in 24/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.1µF and 0.01µF decoupling capacitors are mounted for each DRAM. The HYM532410CM is Tin plated and HYM532410CMG is Gold plated socket type Single In-line Memory Module suitable for easy interchange and addition of 16M byte memory. FEATURES • 72-Pin SIMM • Single power supply of 5.0V ± 10% • Fast Page Mode Operation • Low power dissipation Max. self-refresh : 13.2mW (SL-part) Max. battery back-up : 22.0mW (SL-part) Max. CMOS standby : 13.2mW (SL-part) 44.0mW Max. TTL standby : 88.0mW Max. operating • /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability • 2048 refresh cycles / 256ms (SL-part) 2048 refresh cycles / 32ms • Fast access time and cycle time Speed tRAC tCAC tPC Speed Power 50 60 70 50ns 60ns 70ns 13ns 15ns 18ns 35ns 40ns 45ns 50 60 70 6.38W 5.28W 4.40W • TTL compatible inputs and outputs • JEDEC standard pinout ORDERING INFORMATION PART NUMBER SPEED FEATURES PACKAGE PLATING HYM532410CM HYM532410CMG 50/60/70 50/60/70 FP, 2K, 5V, SOJ FP, 2K, 5V, SOJ SIMM SIMM Tin Gold This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.01 / Dec.97 1997 Hyundai Semiconductor HYM532410C M-Series PIN CONNECTION PIN DISCRIPTION /RAS0, /RAS2 /CAS0~/CAS3 /WE A0~A10 DQ0~DQ31 PD1~PD4 VCC VSS Rev.01 / Dec.97 Row Address Strobe Column Address Strobe Write Enable Address Input Data Input/Output Presence Detect Power (+5V) Ground 2 HYM532410C M-Series PIN ASSIGNMENTS # NAME # NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 NC /RAS2 NC NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC NC VSS /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 NC NC /WE NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS Rev.01 / Dec.97 3 HYM532410C M-Series PRESENCE DETECT PINS Speed PD1 PD2 PD3 PD4 50 60 70 VSS VSS VSS NC NC NC VSS NC VSS VSS NC NC BLOCK DIAGRAM Rev.01 / Dec.97 4 HYM532410C M-Series ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V VCC Voltage on VCC relative to VSS -1.0 to 7.0 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 8 W NOTE : Operation at or above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0°C to 70°C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC Power Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - VCC+1.0 V VIL Input Low Voltage -1.0 - 0.8 V NOTE : All voltages are referenced to VSS. Rev.01 / Dec.97 5 HYM532410C M-Series DC CHARACTERISTICS (TA=0°C to 70°C, VCC=5.0V ± 10% and VSS=0V, unless otherwise noted.) Symbol Parameter Test Condition ICC1 Operating Current /RAS and /CAS cycling tRC=tRC (min.) ICC2 TTL Standby Current ICC3 /RAS-only Refresh Current /RAS=/CAS ≥ VIH other inputs ≥ VSS /CAS=VIH, /RAS cycling tRC=tRC (min.) ICC4 Fast Page Mode Current /RAS=VIL, /CAS, Address cycling tPC=tPC (min.) ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC-0.2V ICC6 /CAS-before/RAS Refresh Current /RAS and /CAS cycling tRC=tRC (min.) ICC7 Battery Back-up Current (SL-part) tRC = 125µs /CAS = CBR cycling or 0.2V /OE & /WE = VCC - 0.2V Address = VCC-0.2V or 0.2V DQ = VCC-0.2V, 0.2V or open /RAS & /CAS = 0.2V Other pins are same as ICC7 ICC8 Self Refresh Current (SL-part) Symbol Speed/ Max. Current Power 2K Ref 50 60 70 1160 960 800 16 50 60 70 50 60 70 SL-part Parameter 50 60 70 tRAS ≤ 300ns tRAS ≤ 1µs Test condition UNIT mA mA 1160 960 800 720 640 560 8 2.4 1160 960 800 2.4 mA 4 mA 2.4 mA mA mA mA mA mA Min. Max. UNIT ILI Input Leakage current (Any Input) VSS ≤ VIN ≤ VCC + 1.0 All other pins not under test = VSS -80 80 µA ILO Output Leakage current (Any Input) -10 10 µA VOL VOH Output Low Voltage Output High Voltage VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH IOL = 4.2mA IOH = -5.0mA 2.4 0.4 - V V NOTE 1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC). 2. Specified values are obtained with outputs unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one Fast Page mode cycle time tPC. 4. Only /RAS(max.) = 1µs is applied to refresh of battery backup but tRAS(max.) = 10µs is applied to normal functional operation. 5. ICC5(max.) = 2.4mA, ICC7 and ICC8 are applied to SL-part only. Rev.01 / Dec.97 6 HYM532410C M-Series AC CHARACTERISTICS (TA=0°C to 70°C, VCC=5.0V ± 10% and VSS=0V, unless otherwise noted.) HYM532410C M-Series # SYMBOL PARAMETER -50 MIN. -60 -70 UNIT NOTE MAX. MIN. MAX. MIN. MAX. 1 tRC Random Read or Write Cycle Time 90 - 110 - 130 - ns 2 tRWC Read-Modify-Write Cycle Time 140 - 160 - 180 - ns 3 tPC Fast Page Mode Cycle Time 35 - 40 - 45 - ns 4 tPRWC FP Mode Read-Modify-Write Cycle Time 61 - 70 - 78 - ns 5 tRAC Access Time from /RAS - 50 - 60 - 70 ns 4,5,6 6 tCAC Access Time from /CAS - 13 - 15 - 18 ns 4,5 7 tAA Access Time from Column Address - 25 - 30 - 35 ns 4,6 8 tCPA Access Time from Column Precharge - 30 - 35 - 40 ns 4 9 tCLZ /CAS to Output Low Impedance 0 - 0 - 0 - ns 4 10 tOFF Out Buffer Turn-Off Delay Time from /CAS 0 10 0 13 0 15 ns 7 11 tT Transition Time (Rise and Fall) 3 50 3 50 3 50 ns 2 12 tRP /RAS Precharge Time 30 - 40 - 50 - ns 13 tRAS /RAS Pulse Width 50 10K 60 10K 70 10K ns 14 tRASP /RAS Pulse Width (Fast Page Mode) 50 200K 60 200K 70 200K ns 15 tRSH /RAS Hold Time 13 - 15 - 18 - ns 16 tCSH /CAS Hold Time 50 - 60 - 70 - ns 17 tCAS /CAS Pulse Width 13 10K 15 10K 18 10K ns 18 tRCD /RAS to /CAS Delay Time 18 37 20 45 20 52 ns 5 19 tRAD /RAS to Column Address Delay Time 10 25 15 30 15 35 ns 6 20 tCRP /CAS to /RAS Precharge Time 5 - 5 - 5 - ns 10 21 tCP /CAS Precharge Time 8 - 10 - 10 - ns 22 tASR Row Address Set-up Time 0 - 0 - 0 - ns 23 tRAH Row Address Hold Time 8 - 10 - 10 - ns 24 tASC Column Address Set-up Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 10 - 10 - 10 - ns 26 tRAL Column Address to /RAS Lead Time 25 - 30 - 35 - ns 27 tRCS Read Command Set-up Time 0 - 0 - 0 - ns 28 tRCH Read Command Hold Time Referenced to /CAS 0 - 0 - 0 - ns 8 29 tRRH Read Command Hold Time Referenced to /RAS 0 - 0 - 0 - ns 8 30 tWCH Write Command Hold Time 8 - 10 - 10 - ns 31 tWP Write Command Pulse Width 8 - 10 - 10 - ns 32 tRWL Write Command to /RAS Lead Time 13 - 15 - 18 - ns 33 tCWL Write Command to /CAS Lead Time 13 - 15 - 18 - ns Rev.01 / Dec.97 7 HYM532410C M-Series AC CHARACTERISTICS (Continued) HYM532410C M-Series # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 34 tDS Data-In Set-up Time 0 - 0 - 0 35 tDH Data-In Hold Time 36 tREF Refresh Period (2048 cycles) 10 - - 32 Refresh Period (SL-part) - 37 tWCS Write Command Set-up Time 38 tCWD 10 - 10 - 32 - 256 - 256 - 256 ms 0 - 0 - 0 - ns 9,10 /CAS to /WE Delay Time 33 - 38 - 43 - ns 10 39 tRWD /RAS to /WE Delay Time 70 - 83 - 95 - ns 10 40 tAWD Column Address to /WE Delay Time 45 - 53 - 60 - ns 10 41 tCSR /CAS Set-up Time (CBR Cycle) 5 - 5 - 5 - ns 9 42 tCHR /CAS Hold Time (CBR Cycle) 10 - 10 - 10 - ns 9 43 tRPC /RAS to /CAS Precharge Time 5 - 5 - 5 - ns 9 44 tCPT /CAS Precharge Time (CBR Counter Test) 15 - 20 - 25 - ns 45 tROH /RAS Hold Time Reference to /OE 10 - 10 - 10 - ns 46 tOEA /OE Access Time - 13 - 15 - 18 ns 47 tOED /OE to Data Delay Time 13 - 15 - 15 - ns 48 tOEZ Output Buffer Turn Off Delay Time from /OE 0 10 0 13 0 15 ns 49 tOEH /OE Command Hold Time 10 - 10 - 10 - ns 50 tCPWD /WE Delay Time from /CAS Precharge 47 - 54 - 62 - ns 51 tRHCP /RAS Hold Time from /CAS Precharge 30 - 35 - 40 - ns 52 tWRP /WE to /RAS Precharge Time(CBR cycle) 10 - 10 - 10 - ns 53 tWRH /WE to /RAS Hold Time (CBR cycle) 10 - 10 - 10 - ns 54 tRASS /RAS Pulse Width (Self Refresh) 100 - 100 - 100 - µs 55 tRPS /RAS Precharge Time (Self Refresh) 90 - 110 - 130 - ns 56 tCHS /CAS Hold Time (Self Refresh) -50 - -50 - -50 - ns Rev.01 / Dec.97 - ns 9 - ns 9 32 ms 7 10 8 HYM532410C M-Series NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS only refresh cycles are required. 2. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.) 3. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (TA = 0 to 70°C) is assured. 4. Measured at VOH=2.4V and VOL=0.4V with a load equivalent to 2 TTL loads and 100pF. 5. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC 6. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA 7. tOFF(max.), tOEZ(max.) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 8. Either tRCH or tRRH must be satisfied for a read cycle.. 9. These parameters are referred to /CAS leading edge in early write cycles and to /WE leading edge in Read-ModifyWrite cycles. 10. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS¡ Ã tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tCWD ≥ tCWD(min.), tRWD ≥ tRWD(min.) and tCPWD ≥ tCPWD(min.), then the cycle is a Read-Modify-Write cycle and data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. CAPACITANCE (TA=25°C, VCC=5.0V ± 10%, VSS=0V and f = 1MHz, unless otherwise noted.) SYMBOL CIN1 CIN2 CIN3 CIN4 CDQ Rev.01 / Dec.97 PARAMETER Input Capacitance (A0~A10) Input Capacitance (/RAS0, /RAS2) Input Capacitance (/CAS0~/CAS3) Input Capacitance (/WE) Data Input /Output Capacitance (DQ0~DQ31) TYP. MAX. UNIT - 56 38 24 72 14 pF pF pF pF pF 9 HYM532410C M-Series PACKAGE INFORMATION 72 pin Single In-line Memory Module (SOJ Mounted) Rev.01 / Dec.97 10