HYM5V72A804A H-Series Buffered 8Mx72 bit CMOS DRAM MODULE based on 8Mx8 DRAM, EDO, ECC, 3.3V, 4K/8K-Refresh DESCRIPTION The HYM5V72A804A H-Series is a 8Mx72-bit EDO mode CMOS DRAM module consisting of nine 8Mx8 TSOP and 16-bit BiCMOS line driver in TSSOP on a 168 pin glass-epoxy printed circuit board. 0.1µF and 0.01µF decoupling capacitors are mounted for each DRAM. The HYM5V72A804AH G-series is gold plated socket type Dual In-line Memory Module suitable for easy interchange and addition of 64M byte memory. FEATURES • Max. Active Power Dissipation • Single power supply of 3.3V ± 10% Speed 8K 4K 50 60 3.60W 2.95W 4.57W 3.92W • Read-Modify-Write Capability • LVTTL compatible inputs and outputs • /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability • Refresh cycles • Fast access time and cycle time Speed tRAC tCAC tHPC Part No. Ref. 50 50ns 18ns 25ns HYM5V72A804A H-Series 4K 60 60ns 20ns 30ns HYM5V72A834A H-Series 8K£ ª • 168-Pin Buffered DIMM • Buffered inputs (except /RAS and DQ) £ /ªCAS-before-/RAS refresh, Hidden refresh mode : 4K cycles / 64ms • Parallel Presence Detect with PD/ID pin Matrix • Extended Data Out Operation PIN DISCRIPTION /RAS0, /RAS2 /CAS0, /CAS4, /WE0, /WE2 /OE0, /OE2 A0, B0, A1-A12 A0, B0, A1-A11 DQ0-DQ71 PD1-PD8 /PDE ID0, ID1 VCC VSS Row Address Strobe Column Address Strobe Write Enable Output Enable Address Input(8K Product) Address Input(4K Product) Data Input / Output Presence Detect Presence Detect Enable ID Bit Power (+3.3V) Ground This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.03 / Jun.98 1998 Hyundai Semiconductor HYM5V72A804A H-Series PIN NAME # NAME # NAME # NAME # NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss NC NC Vcc /WE0 /CAS0 NC /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 *A12 Vcc NC NC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Vss /OE2 /RAS2 /CAS4 NC /WE2 Vcc NC NC DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 NC NC NC NC DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss PD1 PD3 PD5 PD7 ID0 Vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss NC NC Vcc NC NC NC NC NC Vss A1 A3 A5 A7 A9 A11 NC Vcc NC B0 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Vss NC NC NC NC /PDE Vcc NC NC DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 NC NC NC NC DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss PD2 PD4 PD6 PD8 ID1 Vcc NOTE : 1.A12 is used for 8K-Refresh Product (HYM5V72A834A H-Series) 2 HYM5V72A804A H-Series PRESENCE DETECT PINS PIN PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 -50 -60 NC NC Vss Vss NC NC NC NC NC NC Vss NC Vss NC Vss Vss Vss Vss Vss/NC Vss/NC NOTE : 1.PDs are either open NC or driven to Vss via on-board buffer circuit. 2.IDs are connected directly to NC or Vss without a buffer. 3.ID1 will be either open NC for Self-Refresh or driven to Vss for standard. BLOCK DIAGRAM NOTE : 1.A12 is used for 8K-Refresh Product (HYM5V72A834A H-Series) 2. All resistors are 25Ohm±5% 3 HYM5V72A804A H-Series ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -0.5 to 4.6 V VCC Voltage on VCC relative to VSS -0.5 to 4.6 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 11.4 W TSOLDER Soldering Temperature•Time 260•10 °C•sec Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0°C to 70°C ) SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC Power Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - VCC+0.3 V VIL Input Low Voltage -0.3 - 0.8 V Note: All voltages are referenced to VSS. 4 HYM5V72A804A H-Series DC CHARACTERISTICS (TA=0°C to 70°C , VCC=3.3V ± 10%, VSS=0V, unless otherwise noted.) Symbol Parameter Test Conditions Speed Max. Current Unit 8K Product 4K Product 1000 820 1270 1090 mA 9.18 9.18 mA ICC1 Operating Current /RAS, /CAS Cycling tRC=tRC (min.) ICC2 LVTTL Standby Current /RAS = /CAS ≥ VIH other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS cycling /CAS = VIH tRC = tRC (min.) 50 60 1000 820 1270 1090 mA ICC4 EDO Mode Current /CAS cycling /RAS = VIL tHPC = tHPC (min.) 50 60 1090 910 1180 1000 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V 4.68 2.88 4.68 2.88 mA SL-part ICC6 /CAS-before-/RAS Refresh Current tRC=tRC (min.) 50 60 1000 820 1270 1090 mA ICC7 Battery Back-up Current (SL-part) VIH = VCC - 0.2V, VIL = 0.2V /CAS = CBR cycling or 0.2V /OE & /WE = VIH = VCC - 0.2V Address = Don`t care DQ0-DQ71 = Open 5.13 5.13 mA Self Refresh Current (SL-part) /RAS & /CAS = 0.2V Other pins are same as ICC7 4.23 4.23 mA ICC8 Symbol Parameter Test Condition Input Leakage current(Any Input) VSS ≤ VIN ≤ VCC + 0.3, All other pins not under test=VSS ILO Output Leakage current(Any Input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH VOL Output Low Voltage VOH Output High Voltage ILI 50 60 Min. Max Unit µA All but /RAS -10 10 /RAS -22.5 22.5 -5 5 µA IOL = 2.0mA - 0.4 V IOH = -2.0mA 2.4 - V NOTE 1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle rates(tRC and tHPC). 2. Specified values are obtained with outputs unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one EDO mode cycle time tHPC. 4. Only /RAS(max.) = 1µs is applied to refresh of battery backup but tRAS(max.) = 10µs is applied to normal functional operation. 5. ICC5(max.) = 2.88mA, ICC7 and ICC8 are applied to SL-part only. 6. VOH = 2.0V, VOL = 0.8V at AC Functional Test. 5 HYM5V72A804A H-Series AC CHARACTERISTICS (TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, unless otherwise noted.) # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 1 tRC Random Read or Write Cycle Time 90 - 110 - ns 2 tRWC Read-Modify-Write Cycle Time 128 - 153 - ns 3 tHPC EDO Mode Cycle Time 4 tHPRWC EDO Mode Read-Modify-Write Cycle Time 14 25 - 30 - ns 70 - 77 - ns 14 5 tRAC Access Time from /RAS - 50 - 60 ns 4,5,10,11 6 tCAC Access Time from /CAS - 18 - 20 ns 4,5,10,14 7 tAA Access Time from Column Address - 30 - 35 ns 4,5,11,14 8 tCPA Access Time from /CAS Precharge - 35 - 40 ns 4,14 9 tCLZ /CAS to Output Low Impedance 8 - 8 - ns 3,14 10 tCEZ Out Buffer Turn-off delay from /CAS 8 18 8 18 ns 14 11 tT Transition Time (Rise and Fall) 2 50 2 50 ns 4 12 tRP /RAS Precharge Time 30 - 40 - ns 13 tRAS /RAS Pulse Width 50 10K 60 10K ns 14 tRASP /RAS Pulse Width (EDO Mode) 50 100K 60 100K ns 15 tRSH /RAS Hold Time 18 - 20 - ns 14 16 tCSH /CAS Hold Time 38 - 43 - ns 14 17 tCAS /CAS Pulse Width 8 10K 10 10K ns 18 tRCD /RAS to /CAS Delay 15 32 18 40 ns 10,14 19 tRAD /RAS to Column Address Delay Time 11 20 13 25 ns 11,14 20 tCRP /CAS to /RAS Precharge Time 10 - 10 - ns 14 21 tCP /CAS Precharge Time 8 - 10 - ns 22 tASR Row Address Set-up Time 5 - 5 - ns 14 23 tRAH Row Address Hold Time 6 - 8 - ns 14 24 tASC Column Address Set-up Time 0 - 0 - ns 25 tCAH Column Address Hold Time 8 - 10 - ns 26 tAR Column Address Hold Time from /RAS 43 - 48 - ns 14 27 tRAL Column Address to /RAS Lead Time 30 - 35 - ns 14 28 tRCS Read Command Set-up Time 0 - 0 - ns 29 tRCH Read Command Hold Time Referenced to /CAS 0 - 0 - ns 7 30 tRRH Read Command Hold Time Referenced to /RAS -2 - -2 - ns 14 31 tWCH Write Command Hold Time 10 - 10 - ns 32 tWCR Write Command Hold Time from /RAS 38 - 43 - ns 33 tWP Write Command Pulse Width 8 - 10 - ns 34 tRWL Write Command to /RAS Lead Time 20 - 20 - ns 35 tCWL Write Command to /CAS Lead Time 8 - 10 - ns 14 14 6 HYM5V72A804A H-Series AC CHARACTERISTICS # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 36 tDS Data-In Set-up Time -2 - -2 - ns 8,14 37 tDH Data-In Hold Time 15 - 15 - ns 8,14 38 tDHR Data-In Hold Time Referenced to /RAS 40 - 45 - ns 39 tREF Refresh Period (8192 cycles) - 64 - 64 ms Refresh Period (4096 cycles) - 64 - 64 ms 12 Refresh Period (SL-part) - 128 - 128 ms 12,13 40 tWCS Write Command Set-up Time 0 - 0 - ns 9 41 tCWD /CAS to /WE Delay Time 33 - 38 - ns 9 42 tRWD /RAS to /WE Delay Time 68 - 82 - ns 9,14 43 tAWD Column Address to /WE Delay Time 45 - 53 - ns 9 44 tCSR /CAS Set-up Time (CBR Cycle) 10 - 10 - ns 14 45 tCHR /CAS Hold Time (CBR Cycle) 8 - 8 - ns 14 46 tRPC /RAS to /CAS Precharge Time 3 - 3 - ns 14 47 tCPT /CAS Precharge Time (CBR Counter Test) 25 - 30 - ns 48 tROH /RAS Hold Time Reference to /OE 10 - 10 - ns 14 49 tOEA /OE Access Time - 18 - 20 ns 14 50 tOED /OE to Data Delay 18 - 20 - ns 14 51 tOEZ Output Buffer Turn Off Delay Time from /OE 8 18 8 18 ns 6,14 52 tOEH /OE Command Hold Time 13 - 15 - ns 53 tCPWD /WE Delay Time from /CAS Precharge 47 - 58 - ns 9 54 tRHCP /RAS Hold Time from /CAS Precharge 35 - 40 - ns 14 55 tWRP /WE to /RAS Precharge Time(CBR cycle) 12 - 12 - ns 14 14 12,13 56 tWRH /WE to /RAS Hold Time (CBR cycle) 8 - 8 - ns 57 tWTS Write Command Set-up Time (Test Mode In) 10 - 10 - ns 58 tWTH Write Command Hold Time (Test Mode In) 10 - 10 - ns 59 tRASS /RAS Pulse Width (Self Refresh) 100K - 100K - us 60 tRPS /RAS Precharge Time (Self Refresh) 100 - 110 - ns 61 tCHS /CAS Hold Time (Self Refresh) -50 - -50 - ns 62 tDOH Output Data Hold Time 10 - 10 - ns 14 63 tREZ Output Buffer Turn- off Delay from /RAS 0 10 0 15 ns 6 64 tWEZ Output Buffer Turn- off Delay from /WE 0 15 0 20 ns 6,14 65 tWED /WE to Data Delay Time 20 - 20 - ns 66 tOEP /OE Precharge Time 5 - 5 - ns 67 tWPE /WE Pulse Width (EDO cycle) 5 - 5 - ns 68 tOCH /OE to /CAS Hold Time 5 - 5 - ns 69 tCHO /CAS Hold Time to /OE 5 - 5 - ns 70 tPD /PDE to Valid Presence Detect Data - 10 - 10 ns 2 7 2 7 ns 71 tPDOFF /PDE Inactive to Presence Detect Inactive 7 HYM5V72A804A H-Series NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS-before-/RAS initialization cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented from being entered into multi bit test mode during initialization. 2. If /RAS=Vss during power-up, the HYM5V72A804A / HYM5V72A834A could begin an active cycle. This condition results in higher current than necessary current which is demanded from the power supply during power-up. 3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize the power-up current. 4. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.), and are assumed to be 5ns for all inputs. 5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1 TTL loads and 100pF. 6. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in Read-Modify-Write cycles and late Write cycle. 9. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min.), and tCPWD ≥ tCPWD(min.), the cycle is a Read-Modify-Write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10.Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 11.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 12.tREF(max.)=256ms is applied to SL-parts. 13.A burst of 8192 /CAS-before-/RAS refresh cycles must be executed within 64ms (256ms for SL-parts) after exiting self refresh. (CBR refresh & Hidden refresh : 4K cycle/64ms) 14.The timing skew from the DRAM to the DIMM resulted from the addition of buffers. CAPACITANCE (TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, f = 1MHz, unless otherwise noted.) SYMBOL CIN1 CIN2 CIN3 CIN4 CDQ PARAMETER Input Capacitance (A0 - A12) Input Capacitance (/WE0, /WE2, /OE0, /OE2) Input Capacitance (/RAS0, /RAS2) Input Capacitance (/CAS0, /CAS4) Data Input /Output Capacitance (DQ0 - DQ71) TYP. - MAX. 18 18 45 18 14 UNIT pF pF pF pF pF 8 HYM5V72A804A H-Series PACKAGE INFORMATION 9 HYM5V72A804A H-Series ORDERING INFORMATION Part Number Ref. Power Package HYM5V72A804ATHG HYM5V72A804ASLTHG 4K 4K Normal SL-part TSOP TSOP HYM5V72A834ATHG HYM5V72A834ASLTHG 8K 8K Normal SL-part TSOP TSOP 10