32Mx72 bits PC100 SDRAM Registered DIMM with PLL, based on 32Mx4 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V32D755AT4 Series DESCRIPTION The Hynix HYM71V32D755AT4 Series are 32Mx72bits ECC Synchronous DRAM Modules. The modules are composed of eighteen 32Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 200pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V32D755AT4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hynix HYM71V32D755AT4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • PC100MHz support • SDRAM internal banks : four banks • 200pin SDRAM Registered DIMM • Module bank : one physical bank • Serial Presence Detect with EEPROM • Auto refresh and self refresh • 1.75” (44.45mm) Height PCB with double sided components • 4096 refresh cycles / 64ms • Programmable Burst Length and Burst Type • Single 3.3±0.3V power supply • All device pins are compatible with LVTTL interface • Data mask function by DQM - 1, 2, 4 or 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HYM71V32D755AT4-8 125MHz HYM71V32D755AT4-P 100MHz HYM71V32D755AT4-S 100MHz Internal Bank Ref. Power SDRAM Package Plating 4 Banks 4K Normal TSOP-II Gold This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Dec. 01 2 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series PIN DESCRIPTION PIN PIN NAME DESCRIPTION CK0 Clock Inputs The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE0 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh /S0 Chip Select Enables or disables all inputs except CK, CKE and DQM BA0, BA1 SDRAM Bank Address Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9, CA11 Auto-precharge flag : A10 /RAS, /CAS, /WE Row Address Strobe, Column Address Strobe, Write Enable /RAS, /CAS and /WE define the operation Refer function truth table for details REGE Register Enable Register Enable pin which permits the DIMM to operateion in Buffered Mode when REGE input is Low, in Registered Mode when REGE input is High DQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ71 Data Input/Output Multiplexed data input / output pin VCC Power Supply (3.3V) Power supply for internal circuits and input buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~2 SPD Address Input Serial Presence Detect Address Input WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM ID1~3 Identification Detect Commend Interval, Read Precharge Timing, Power Detect NC No Connection No connection Rev. 0.4/Dec. 01 3 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series PIN ASSIGNMENTS PIN NO. NAME PIN NO. NAME PIN NO. NAME PIN NO. 1 VDD 51 VSS 101 NC, VTT 151 NAME CK0 2 NC, VTT 52 RAS 102 NC, VTT 152 VSS 3 NC, VTT 53 VSS 103 VSS 153 NC 4 IN 54 A12 104 NC 154 S0 5 OUT 55 A11 105 RFU 155 VSS 6 ID1 56 VDD 106 RFU 156 BA1 7 ID2 57 A0 107 ID3 157 A10 8 VSS 58 A1 108 DQ71 158 VDD 9 DQ67 59 VSS 109 DQ70 159 A2 10 DQ66 60 DQ35 110 VSS 160 A3 11 VDD 61 DQ34 111 DQ69 161 VSS 12 DQ65 62 VDD 112 DQ68 162 DQ31 13 DQ64 63 DQ33 113 VDD 163 DQ30 14 VSS 64 DQ32 114 NC 164 VDD 15 DQ63 65 VSS 115 VSS 165 DQ29 16 DQ62 66 DQ27 116 NC 166 DQ28 17 NC, VTT 67 DQ26 117 DQ59 167 VSS 18 DQ61 68 VSS 118 DQ58 168 DQ23 19 DQ60 69 DQ25 119 VSS 169 DQ22 20 VDD 70 DQ24 120 DQ57 170 VDD 21 NC 71 VSS 121 DQ56 171 DQ21 22 NC 72 DQ19 122 VDD 172 DQ20 23 VSS 73 DQ18 123 DQ55 173 VSS 24 NC 74 VDD 124 DQ54 174 NC 25 NC 75 DQ17 125 VSS 175 NC 26 VDD 76 DQ16 126 DQ53 176 VDD 27 DQ51 77 VSS 127 DQ52 177 NC 28 DQ50 78 NC 128 VDD 178 VSS 29 VSS 79 NC, VTT 129 DQ47 179 VSS 30 DQ49 80 VDD 130 DQ46 180 NC 31 DQ48 81 DQ15 131 VSS 181 NC 32 VDD 82 DQ14 132 DQ45 182 VDD 33 DQ43 83 VSS 133 DQ44 183 DQ11 34 DQ42 84 DQ13 134 VDD 184 DQ10 35 VSS 85 DQ12 135 DQ39 185 VSS 36 DQ41 86 VDD 136 DQ38 186 DQ9 37 DQ40 87 DQ7 137 VSS 187 DQ8 38 VDD 88 DQ6 138 DQ37 188 VDD 39 A4 89 VSS 139 DQ36 189 DQ3 40 A5 90 DQ5 140 VDD 190 DQ2 41 GND 91 DQ4 141 A6 191 VSS 42 A8 92 VDD 142 A7 192 DQ1 43 A9 93 PDE# 143 VSS 193 DQ0 44 VDD 94 PD1 144 BA0(A13) 194 SDA 45 NC 95 PD2 145 NC 195 SA0 46 CKE0 96 PD3 146 VDD 196 SA1 47 VSS 97 PD4 147 DQM 197 SA2 48 CAS 98 SCL 148 WE 198 VDD 49 NC, VTT 99 NC 149 VSS 199 NC, VTT 50 VDD 100 VSS 150 NC 200 NC, VTT Rev. 0.4/Dec. 01 4 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series BLOCK DIAGRAM RS0 RDQM DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQM DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQM DQ8 DQ9 DQ10 DQ11 DQ0 DQ1 DQ2 DQ3 DQM DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQM DQ16 DQ17 DQ18 DQ19 DQ0 DQ1 DQ2 DQ3 DQM DQ20 DQ21 DQ22 DQ23 DQ0 DQ1 DQ2 DQ3 DQM DQ0 DQ1 DQ2 DQ3 DQM DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQM DQ64 DQ65 DQ66 DQ67 DQ0 DQ1 DQ2 DQ3 DQM DQ24 DQ25 DQ26 DQ27 S0 DQM A0 ~ A11 BA0,BA1 RAS CAS CKE0 WE CS U0 CS U1 CS U2 CS U3 CS U4 CS U5 CS DQ0 DQ1 DQ2 DQ3 DQM DQ36 DQ37 DQ38 DQ39 DQ0 DQ1 DQ2 DQ3 DQM DQ40 DQ41 DQ42 DQ43 DQ0 DQ1 DQ2 DQ3 DQM DQ44 DQ45 DQ46 DQ47 DQ0 DQ1 DQ2 DQ3 DQM DQ48 DQ49 DQ50 DQ51 DQ0 DQ1 DQ2 DQ3 DQM DQ52 DQ53 DQ54 DQ55 DQ0 DQ1 DQ2 DQ3 DQM DQ0 DQ1 DQ2 DQ3 DQM DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQM DQ68 DQ69 DQ70 DQ71 DQ0 DQ1 DQ2 DQ3 DQM DQ56 DQ57 DQ58 DQ59 U6 CS U7 CS U8 R E G I S T E R DQ32 DQ33 DQ34 DQ35 RS0 U9 3.3V U0~17 U0~17 U0~17 U0~17 U0~17 U0~17 VSS U10 CS U11 CS U12 CS U13 CS U14 CS U15 CS U16 CS U17 U0 ~ U35 U0 ~ U35 Bypass Capacitor two 0.0022uF and one 0.22uF per SDRAM SCL WP CK0 CS VCC RDQM REGE CS PLL Serial PD A0 A1 A2 SA0 SA1 PLL CLK * When necessary two couples of the signals are created by double loading the register inputs. SA2 +3.3V ID1 ID2 ID3 Rev. 0.4/Dec. 01 SDA ID1=Command, Interval 0=2clocks 1=1clocks ID2=Read Precharge Timing 0=No Early RAS 1=Early RAS ID3=Power Detect 0=Normal 1=Low power 5 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series SERIAL PRESENCE DETECT BYTE NUMBER FUNCTION DESCRIPTION FUNCTION -8 VALUE -P -S -8 -P BYTE0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type BYTE3 -S SDRAM 04h # of Row Addresses on This Assembly 12 0Ch BYTE4 # of Column Addresses on This Assembly 11 0Bh BYTE5 # of Module Banks on This Assembly 1 Bank 01h BYTE6 Data Width of This Assembly 72 Bits 48h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly BYTE9 SDRAM Cycle Time @/CAS Latency=3 8ns 10ns 10ns 80h A0h A0h BYTE10 Access Time from Clock @/CAS Latency=3 6ns 6ns 6ns 60h 60h 60h BYTE11 DIMM Configuration Type BYTE12 Refresh Rate/Type BYTE13 BYTE14 LVTTL 02h 15.625us / Self Refresh Supported 80h Primary SDRAM Width x4 04h Error Checking SDRAM Width x4 04h BYTE15 BYTE16 Burst Lenth Supported BYTE17 # of Banks on Each SDRAM Device BYTE18 SDRAM Device Attributes, /CAS Lataency BYTE19 1 01h ECC Minimum Clock Delay Back to Back Random Column Address tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 2 4 Banks 04h /CAS Latency=2,3 06h SDRAM Device Attributes, /CS Lataency /CS Latency=0 01h BYTE20 SDRAM Device Attributes, /WE Lataency /WE Latency=0 01h BYTE21 SDRAM Module Attributes Registered inputs, with PLL 16h BYTE22 SDRAM Device Attributes, General +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 0Eh BYTE23 SDRAM Cycle Time @/CAS Latency=2 8ns 10ns 12ns A0h A0h C0h BYTE24 Access Time from Clock @/CAS Latency=2 6ns 6ns 6ns 60h 60h 60h BYTE25 SDRAM Cycle Time @/CAS Latency=1 - - - 00h 00h 00h BYTE26 Access Time from Clock @/CAS Latency=1 - - - 00h 00h 00h BYTE27 Minimum Row Precharge Time (tRP) 20ns 20ns 20ns 14h 14h 14h BYTE28 Minimum Row Active to Row Active Delay (tRRD) 16ns 20ns 20ns 10h 14h 14h BYTE29 Minimum /RAS to /CAS Delay (tRCD) 20ns 20ns 20ns 14h 14h 14h BYTE30 Minimum /RAS Pulse Width (tRAS) 48ns 50ns 50ns 30h 32h 32h BYTE31 Module Bank Density BYTE32 Command and Address Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE33 Command and Address Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE34 Data Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE35 Data Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE36 ~61 Superset Information (may be used in future) BYTE62 SPD Revision BYTE63 Checksum for Byte 0~62 BYTE64 Manufacturer JEDEC ID Code BYTE65 ~71 ....Manufacturer JEDEC ID Code BYTE72 Manufacturing Location Rev. 0.4/Dec. 01 NOTE 256MB 40h - 00h Intel SPD 1.2B - 12h 31h 57h Hynix JEDED ID ADh Unused FFh HSI (Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) Singapore ASIA Area 0*h 1*h 2*h 3*h 4*h 5*h 3, 8 77h 9 6 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series Continued BYTE NUMBER FUNCTION DESCRIPTION BYTE73 Manufacturer’s Part Number (Component) BYTE74 Manufacturer’s Part Number (128Mb based) BYTE75 Manufacturer’s Part Number (Voltage Interface) BYTE76 BYTE77 FUNCTION -8 -P VALUE -S -8 -P -S NOTE 7 (SDRAM) 37h 4, 5 1 31h 4, 5 V (3.3V, LVTTL) 56h 4, 5 Manufacturer’s Part Number (Memory Width) 3 33h 4, 5 ....Manufacturer’s Part Number (Memory Width) 2 32h 4, 5 BYTE78 Manufacturer’s Part Number (Module Type) D 44h 4, 5 BYTE79 Manufacturer’s Part Number (Data Width) 7 37h 4, 5 BYTE80 ....Manufacturer’s Part Number (Data Width) 5 35h 4, 5 BYTE81 Manufacturer’s Part Number (Refresh, SDRAM Bank) 5 (4K Refresh, 4Banks) 35h 4, 5 BYTE82 Manufacturer’s Part Number (Generation) A 41h 4, 5 BYTE83 Manufacturer’s Part Number (Package Type) BYTE84 Manufacturer’s Part Number (Component Configuration) BYTE85 Manufacturer’s Part Number (Hyphent) BYTE86 Manufacturer’s Part Number (Min. Cycle Time) BYTE87 ~90 Manufacturer’s Part Number BYTE91 T 54h 4, 5 4 (x4 based) 34h 4, 5 - (Hyphen) 8 P 2Dh S 38h 50h 4, 5 53h 4, 5 Blanks 20h 4, 5 Revision Code (for Component) Process Code - 4, 6 BYTE92 ....Revision Code (for PCB) Process Code - 4, 6 BYTE93 Manufacturing Date Year - 3, 6 BYTE94 ....Manufacturing Date Work Week - 3, 6 Serial Number - 6 None 00h BYTE95 ~98 BYTE99 ~125 Assembly Serial Number Manufacturer Specific Data (may be used in future) BYTE126 System Frequency Support BYTE127 Intel Specification Details for 100MHz Support BYTE128 ~256 Unused Storage Locations 100MHz Refer to Note7 - 64h 8Fh 8Fh 7, 8 8Dh 7, 8 00h Note : 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. Not fixed but dependent 7. CK0 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. Refer to Intel SPD Specification 1.2B 9. Refer to HSI Web site. Rev. 0.4/Dec. 01 7 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 18 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1 Input High voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2 Input Low voltage VIL -0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration. AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V) Parameter Symbol Value Unit AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement 1 Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit Rev. 0.4/Dec. 01 8 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series CAPACITANCE (TA=25°C, f=1MHz) -8/P/S Parameter Pin Input Capacitance Data Input / Output Capacitance Symbol Unit Min Max CK0 CI1 - 44 pF CKE0 CI2 - 20 pF /S0, /S2 CI3 - 20 pF A0~11, BA0, BA1 CI4 - 20 pF /RAS, /CAS, /WE CI5 - 20 pF DQM0~DQM7 CI6 - 20 pF DQ0 ~ DQ63 CI/O - 20 pF OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF DC Output Load Circuit Rev. 0.4/Dec. 01 50pF AC Output Load Circuit 9 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -10 10 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6 DC CHARACTERISTICS II Parameter Operating Current Symbol IDD1 Speed Test Condition Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA -8 -P -S 2200 2200 2200 CKE ≤ VIL(max), tCK = 15ns 356 CKE ≤ VIL(max), tCK = ∞ 356 IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V 760 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 270 IDD3P CKE ≤ VIL(max), tCK = 15ns 446 IDD3PS CKE ≤ VIL(max), tCK = ∞ 216 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V 1120 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 810 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V IDD2P Precharge Standby Current in Power Down Mode IDD2PS Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Unit Note mA 1 mA mA mA mA CL=3 2600 2400 2400 CL=2 2400 2400 2160 mA 1 4800 mA 2 276 mA Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II Rev. 0.4/Dec. 01 10 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series AAC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -8 Parameter Min System Clock Cycle Time CAS Latency = 3 -P tCK3 Max 8 Min Max 10 1000 CAS Latency = 2 -S Symbol Min Unit Note 1000 ns 1 Max 10 1000 tCK2 10 Clock High Pulse Width tCHW 3 - 3 - 3 - ns 2 Clock Low Pulse Width tCLW 3 - 3 - 3 - ns 2 CAS Latency = 3 tAC3 - 6 - 6 - 6 ns CAS Latency = 2 tAC2 - 6 - 6 - 6 ns Data-Out Hold Time tOH 3 - 3 - 3 - ns Data-Input Setup Time tDS 2 - 2 - 2 - ns 2 Data-Input Hold Time tDH 1 - 1 - 1 - ns 2 Address Setup Time tAS 2 - 2 - 2 - ns 2 Address Hold Time tAH 1 - 1 - 1 - ns 2 CKE Setup Time tCKS 2 - 2 - 2 - ns 2 CKE Hold Time tCKH 1 - 1 - 1 - ns 2 Command Setup Time tCS 2 - 2 - 2 - ns 2 Command Hold Time tCH 1 - 1 - 1 - ns 2 CLK to Data Output in Low-Z Time tOLZ 1 - 1 - 1 - ns CAS Latency = 3 tOHZ3 3 6 3 6 3 6 ns CAS Latency = 2 tOHZ2 3 6 3 6 3 6 ns Access Time From Clock CLK to Data Output in High-Z Time 10 12 3 Note : 1. In Registered DIMM, data is delayed an additional clock cycle due to the register (this is, Device CL + 1 = DIMM CL) 2.Assume tR / tF (input rise and fall time ) is 1ns, If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 3.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 0.4/Dec. 01 11 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series AC CHARACTERISTICS II -8 Parameter -P -S Symbol Unit Min Max Min Max Min Max Note Operation tRC 68 - 70 - 70 - ns Auto Refresh tRRC 68 - 70 - 70 - ns RAS to CAS Delay tRCD 20 - 20 - 20 - ns RAS Active Time tRAS 48 100K 50 100K 50 100K ns RAS Precharge Time tRP 20 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 16 - 20 - 20 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 1 - 1 - 1 - CLK 1 Data-In to Precharge Command tDPL 0 - 0 - 0 - CLK 1 Data-In to Active Command tDAL 3 - 2 - 2 - CLK 1 DQM to Data-Out Hi-Z tDQZ 3 - 3 - 3 - CLK 1 DQM to Data-In Mask tDQM 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - CLK CAS Latency = 3 tPROZ3 4 - 4 - 4 - CAS Latency = 2 tPROZ2 3 - 3 - 3 - Power Down Exit Time tPDE 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 ms RAS Cycle Time Precharge to Data Output Hi-Z CLK 1 2 Note : 1. Timing delay due to the register is considered in a registered DIMM 2. A new command can be given tRRC after self refresh exit Rev. 0.4/Dec. 01 12 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series DEVICE OPERATING OPTION TABLE HYM71V32S755AT4-8 CAS Latency tRCD tRAS tRC tRP tAC tOH 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HYM71V32S755AT4-P CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns HYM71V32S755AT4-S CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns Note : DIMM/CAS Latency = Device CL + 1 (Registered Mode) Rev. 0.4/Dec. 01 13 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series COMMAND TRUTH TABLE A10/ AP BA CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 Pin High (Other Pins OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Command Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh1 X Precharge power down Clock Suspend Exit L H Entry H L Exit L H X X ADDR RA Note V L H L H V V H X L V MRS Mode X X X X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1. Rev. 0.4/Dec. 01 14 PC100 SDRAM Registered DIMM HYM71V32D755AT4 Series PACKAGE DEMENSION Unit: mm R 2.0 "A" R 3.0 x 2 10.00 28.12 44.45 153.67 83.82 147.67 4.00 max. 0.99±0.05 157.48(4.0) min. R 1.00 ±0.10 2.79 3.12 2.0±0.1 50(1.27) DETAIL ”A" NOTES : 1. ALL DIMENSIONS ARE IN MILIMETERS 2. TOLERANCES ON ALL DIMMENSIONS ±0.127 UNLESS OTHERWISE. Rev. 0.4/Dec. 01 15