8Mx72 bits PC100 SDRAM Registered DIMM with PLL, based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh HYM7V75AC801B H-Series DESCRIPTION The Hynix HYM7V75AS801B H-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine 8Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, two 18bits driver ICs in 56pin TSSOP package, one PLL clock driver in 24pin TSSOP package and one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. A 0.22uF and two 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM7V75AS801B H-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The HYM7V75AS801B H-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. The DIMM /CAS latency in registered mode is one clock later than the device /CAS latency because of the register. FEATURES • PC100MHz support • SDRAM internal banks : four banks • 168pin SDRAM Registered DIMM • Module bank : one physical bank • Serial Presence Detect with EEPROM • Auto refresh and self refresh • 1.50” (38.10mm) Height PCB with Double Sided components • 4096 refresh cycles / 64ms • Programmable Burst Length and Burst Type -. 1, 2, 4, 8, or Full Page for Sequential Burst -. 1, 2, 4 or 8 for Interleave Burst • Single 3.3 ± 0.3V power supply • All devices pins are compatible with LVTTL interface • Data mask function by DQM • Programmable /CAS Latency : 2, 3 Clocks -. 1, 2, 4, 8, or Full Page for Sequential Burst -. 1, 2, 4 or 8 for Interleave Burst ORDERING INFORMATION PART NO. MAX. FREQUENCY HYM7V75AC801BTHG-8 125MHz HYM7V75AC801BTHG-10P 100MHz HYM7V75AC801BTHG-10S 100MHz INTERNAL BANK REF. POWER SDRAM PACKAGE PLATING 4 Banks 4K Normal TSOP-II Gold This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Apr.01 1999 Hyundai Electronics PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series PIN DESCRIPTION PIN NAME DESCRIPTION CK0~CK3 Clock Inputs The System Clock Input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE0 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. /S0, /S2 Chip Select Enables or disables all inputs except CK, CKE and DQM. BA0, BA1 SDRAM Bank Address A0~A11 Address Inputs /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable REGE Register Enable Register Enable pin which permits the DIMM to operation in Buffered Mode when REGE input is Low, in Registered Mode when REGE input is High. DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode. DQ0~DQ63 Data Input/Output Multiplexed data input/output pins CB0~CB7 ECC Data Input/Output Error Checking and Correction Bits VCC Power Supply (3.3V) Power supply for internal circuits and input/output buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock Input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~SA2 SPD Address Input Serial Presence Detect Address input WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM NC No Connect No Connect or Don’t Use Rev. 0.1/Apr.01 Select bank to be activated during /RAS activity. Select bank to be read/written during /CAS activity Row address : RA0~RA11, Column address : CA0~CA8 Auto-precharge flag : A10 /RAS define the operation. Refer to the function truth table for details. /CAS define the operation. Refer to the function truth table for details. /WE define the operation. Refer to the function truth table for details. 2 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series PIN ASSIGNMENTS FRONT SIDE PIN NO. NAME 1 2 3 4 5 6 7 8 9 10 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 BACK SIDE PIN NO. NAME 85 86 87 88 89 90 91 92 93 94 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 Architecture Key 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC /WE DQM0 DQM1 /S0 NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Voltage Key DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC /CAS DQM4 DQM5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC FRONT SIDE PIN NO. NAME 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VCC CK0 VSS NC /S2 DQM2 DQM3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS *CK2 NC WP SDA SCL VCC BACK SIDE PIN NO. NAME 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 *CK1 NC VSS CKE0 NC DQM6 DQM7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC SA0 SA1 SA2 VCC Note : *. CK1~CK3 are connected with termination R/C. (Refer to the Block Diagram.) Rev. 0.1/Apr.01 3 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series BLOCK DIAGRAM Note : 1. The serial resistor values of DQs are 10 Ohms. 2. The padding capacitance of termination R/C for CK1~CK3 is 12pF. Rev. 0.1/Apr.01 4 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series SERIAL PRESENCE DETECT BYTE FUNCTION NUMBER DESCRIBED FUNCTION -8 -10P VALUE -10S -8 -10P BYTE0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type BYTE3 -10S SDRAM 04h # of Row Addresses on This Assembly 12 0Ch BYTE4 # of Column Addresses on This Assembly 9 09h BYTE5 # of Module Banks on This Assembly 1 Bank 01h BYTE6 Data Width of This Assembly 72 Bits 48h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly BYTE9 SDRAM Cycle Time @ /CAS Latency=3 8ns 10ns 10ns 80h A0h A0h BYTE10 Access Time from Clock @ /CAS Latency=3 6ns 6ns 6ns 60h 60h 60h BYTE11 DIMM Configuration Type LVTTL ECC 02h 15.625µs / Self Refresh Supported 80h Refresh Rate/Type BYTE13 Primary SDRAM Width x8 08h BYTE14 Error Checking SDRAM Width x8 08h BYTE15 Minimum Clock Delay Back to Back Random Column Address BYTE16 Burst Lengths Supported BYTE17 # of Banks on Each SDRAM Device BYTE18 SDRAM Device Attributes, CAS # Latency BYTE19 SDRAM Device Attributes, CS # Latency BYTE20 SDRAM Device Attributes, Write Latency BYTE21 SDRAM Module Attributes SDRAM Device Attributes, General BYTE23 SDRAM Cycle Time @ /CAS Latency=2 BYTE24 Access Time from Clock @ /CAS Latency=2 BYTE25 BYTE26 BYTE27 1 01h BYTE12 BYTE22 tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 4 Banks 04h /CAS Latency=2,3 06h /CS Latency=0 01h /WE Latency=0 01h Registered Inputs, with PLL 16h +/-10% voltage tolerance, Burst Read Single bit Write, Precharge All, Auto Precharge, Early RAS Precharge 0Eh 10ns 12ns A0h A0h C0h 6ns 6ns 6ns 60h 60h 60h SDRAM Cycle Time @ /CAS Latency=1 - - - 00h 00h 00h Access Time from Clock @ /CAS Latency=1 - - - 00h 00h 00h Minimum Row Precharge Time (tRP) 20ns 20ns 20ns 14h 14h 14h BYTE28 Minimum Row Active to Row Active Delay (tRRD) 16ns 20ns 20ns 10h 14h 14h BYTE29 Minimum /RAS to /CAS Delay (tRCD) 20ns 20ns 20ns 14h 14h 14h BYTE30 Minimum /RAS Pulse width (tRAS) 48ns 50ns 50ns 30h 32h 32h BYTE31 Module Bank Density BYTE32 Command and Address Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE33 Command and Address Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE34 Data Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE35 Data Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE36 –61 Superset Information (may be used in future) BYTE62 SPD Revision BYTE63 Checksum for Bytes 0~62 BYTE64 Manufacturer JEDEC ID Code BYTE65 ~71 ....Manufacturer JEDEC ID Code BYTE72 Manufacturing Location Rev. 0.1/Apr.01 64MB 9 2 10ns 9 10h - 00h Intel SPD 1.2A - NOTE 12h 07h 2Dh Hynix JEDEC ID ADh Unused FFh Hynix (Korea Area) 0*h HAS (United States Area) HSJ (Europe Area 1*h 2*h HSJ (Japan Area) Asia Area 3*h 4*h 3, 8 4Dh 10 5 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series Continued BYTE FUNCTION NUMBER DESCRIBED BYTE73 Manufacturer’s Part Number (Component) BYTE74 Manufacturer’s Part Number (Voltage Interface) BYTE75 FUNCTION -8 -10P VALUE -10S -8 -10P -10S NOTE 7 (SDRAM) 37h 4, 5 V (3.3V, LVTTL) 56h 4, 5 Manufacturer’s Part Number (Data Width) 7 37h 4, 5 BYTE76 ....Manufacturer’s Part Number (Data Width) 5 35h 4, 5 BYTE77 Manufacturer’s Part Number (ECC) A 41h 4, 5 BYTE78 Manufacturer’s Part Number (Reg. DIMM Type) S (Intel Registered with PLL) 53h 4, 5 BYTE79 Manufacturer’s Part Number (Memory Depth) 8 38h 4, 5 BYTE80 Manufacturer’s Part Number (Refresh) 0 (4K Refresh) 30h 4, 5 BYTE81 Manufacturer’s Part Number (Internal Banks) 1 (4 Banks) 31h 4, 5 BYTE82 Manufacturer’s Part Number (Generation) B 42h 4, 5 BYTE83 Manufacturer’s Part Number (Package Type) T (TSOPII) 54h 4, 5 BYTE84 Manufacturer’s Part Number (Module Type) H (x8 based Registered DIMM) 48h 4, 5 BYTE85 Manufacturer’s Part Number (Plating Type) G (Gold) 47h 4, 5 BYTE86 Manufacturer’s Part Number (Hyphen) - (Hyphen) 2Dh BYTE87 Manufacturer’s Part Number (Min. Cycle Time) BYTE88 4, 5 8 1 1 38h 31h 31h 4, 5 ....Manufacturer’s Part Number (Min. Cycle Time) Blank 0 0 20h 30h 30h 4, 5 BYTE89 ....Manufacturer’s Part Number (Min. Cycle Time) Blank P S 20h 50h 53h 4, 5 BYTE90 Manufacturer’s Part Number BYTE91 Blanks 20h 4, 5 Revision Code (for Component) Process Code - 4, 6 BYTE92 ....Revision Code (for PCB) Process Code - 4, 6 BYTE93 Manufacturing Date Work Week - 3, 6 BYTE94 ....Manufacturing Date Year - 3, 6 BYTE95 ~98 Assembly Serial Number Serial Number - 6 None 00h BYTE99 ~125 Manufacturer Specific Data (may be used in future) BYTE126 System Frequency Support BYTE127 Intel Specification Details for 100MHz Support BYTE128 ~256 Unused Storage Locations 100MHz Refer to Note7 - 64h 87h 87h 8 85h 7, 8 00h Note: 1. The bank address is excluded. 2. 1,2,4,8 for Interleave Burst Type 3. BCD adopted. 4. ASCII adopted. 5. Basically Hynix writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently. 6. Not fixed but dependent. 7. CLK0 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. Refer to Intel SPD Specification Rev.1.2A. 9. In a registered DIMM, data is delayed an additional clock cycle due to the register (that is, Device CL + 1 = DIMM CL) 10. Refer to Hynix Web Site. Rev. 0.1/Apr.01 6 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT 0 ~ 70 °C Ambient Temperature TA Storage Temperature TSTG -55 ~ 125 °C Voltage on any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 MA Power Dissipation PD 9 W Soldering Temperature · Time TSOLDER 260 · 10 °C · Sec Note : Operation at above absolute maximum can adversely affect device reliability. DC OPERATING CONDITION (TA = 0 to 70°C) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Power Supply Voltage VCC 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VCC + 2.0 V 1, 2 Input Low Voltage VIL VSS – 2.0 0 0.8 V 1, 3 Note : 1. All voltage are referenced to VSS = 0V. 2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration. 3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration. AC OPERATING CONDITION (TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V) PARAMETER SYMBOL VALUE UNIT 2.4 / o.4 V 1.4 V AC Input High / Low Level Voltage VIH / VIL Input Timing Measurement Reference Level Voltage Vtrip Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V Output Load Capacitance for Access Time Measurement CL *Note pF Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output circuit. Rev. 0.1/Apr.01 7 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series CAPACITANCE (TA = 25°C, f = 1MHz) PARAMETER Input Capacitance Data Input/Output Capacitance PIN SYMBOL MIN MAX TYP. UNIT CK0 CIN1 - 32 - pF CKE0 CIN2 - 16 - pF /S0, /S1 CIN3 - 16 - pF A0~A11, BA0, BA1 CIN4 - 16 - pF /RAS, /CAS, /WE CIN5 - 16 - pF DQM0~DQM7 CIN6 - 16 - pF DQ0~DQ63, CB0~CB7 CI/O - 17 - pF OUTPUT LOAD CIRCUIT Rev. 0.1/Apr.01 8 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series DC CHARACTERISTICS I (TA = 0 to 70°C, VDD = 3.3 ± 0.3V) PARAMETER SYMBOL MIN MAX UNIT NOTE Input Leakage Current ILI -10 10 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V. 2. DOUT is disabled. VOUT = 0 to 3.6V. DC CHARACTERISTICS II (TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V) SPEED P ARAMETER Operating Current Precharge Standby Current in Power Down Mode SYMBOL Operating -10P -10S 1040 950 950 UNIT NOTE mA 1 Burst Length = 1, One bank active tRC ≥ tRC(min), IOL = 0mA IDD2P CKE ≤ VIL(max), tCK = min 338 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 108 mA IDD2N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 535 mA IDD2NS CKE ≥ VIH(max), tCK = ∞ Input signals are stable. 225 mA IDD3P CKE ≤ VIL(max), tCK = min 365 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ 135 mA IDD3N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 670 mA IDD3NS CKE ≥ VIH(max), tCK = ∞ Input signals are stable. 360 mA Active Standby Current in Non Power Down Mode Burst Mode Current -8 IDD1 Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode TEST CONDITION IDD4 tCK ≥ tCK(min), IOL = 0mA CL = 3 1310 1130 1130 All banks active CL = 2 1130 1130 1130 2000 1820 1820 Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V 258 mA 1 mA 2 mA Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II. Rev. 0.1/Apr.01 9 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -8 P ARAMETER /CAS Latency = 3 tCK3 MAX 8 MIN MAX 10 1000 MIN UNIT NOTE 1000 ns 1 MAX 10 1000 tCK2 10 Clock High Pulse Width tCHW 3 - 3 - 3 - ns 2 Clock Low Pulse Width tCLW 3 - 3 - 3 - ns 2 /CAS Latency = 3 tAC3 - 6 - 6 - 6 ns 3 /CAS Latency = 2 tAC2 - 6 - 6 - 6 Data-Out Hold Time tOH 3 - 3 - 3 - ns Data-Input Setup Time tDS 2 - 2 - 2 - ns 2 Data-Input Hold Time tDH 1 - 1 - 1 - ns 2 Address Setup Time tDS 2 - 2 - 2 - ns 2 Address Hold Time tDH 1 - 1 - 1 - ns 2 CKE Setup Time tDS 2 - 2 - 2 - ns 2 CKE Hold Time tDH 1 - 1 - 1 - ns 2 Command Setup Time tDS 2 - 2 - 2 - ns 2 Command Hold Time tDH 1 - 1 - 1 - ns 2 CLK to Data Output in Low-Z time tOLZ 1 - 1 - 1 - ns CLK to Data Output in High-Z time /CAS Latency = 3 tOHZ3 3 6 3 6 3 6 /CAS Latency = 2 tOHZ2 3 6 3 6 3 6 Access Time from Clock /CAS Latency = 2 -10S SYMBOL MIN System Clock Cycle Time -10P 10 12 ns Note : 1. In a registered DIMM, data is delayed an additional clock cycle due to the register (that is, Device CL + 1 = DIMM CL). 2. Assume tR / tF (input rise and fall time) is 1ns. 3. Access times to be measured with input signals of 1v/ns edge rate. Rev. 0.1/Apr.01 10 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series AC CHARACTERISTICS II -8 P ARAMETER Cycle Operation -10S UNIT MIN /RAS Time -10P SYMBOL tRC MAX 68 MIN MAX 70 - MIN NOTE MAX 70 - ns 20 - ns 100K 50 100K ns 20 - 20 - ns 20 - 20 - ns - 1 - 1 - CLK 1 - 1 - 1 - CLK 1 0 - 0 - 0 - CLK 1 tDAL 3 - 2 - 2 - CLK 1 DQM to Data-out Hi-Z tDQZ 3 - 3 - 3 - CLK 1 DQM to Data-in Mask tDQM 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - CLK Precharge to Data Output Hi-Z /CAS Latency = 3 tPROZ3 4 - 4 - 4 - /CAS Latency = 2 tPROZ2 3 - 3 - 3 - Power Down Exit Time tPDE 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - CLK Refresh Time tREF 64 - 64 - 64 - ms Auto Refresh - tRRC 68 70 70 /RAS to /CAS Delay tRCD 20 - 20 - /RAS Active Time tRAS 48 100K 50 /RAS Precharge Time tRP 20 - /RAS to /RAS Bank Active Delay tRRD 16 - /CAS to /CAS Delay tCCD 1 Write Command to Data-in Delay tWTL Data-in to Precharge Command tDPL Data-in to Active Command CLK 1 2 Note : 1. Timing delay due to the register is considered in a registered DIMM. 2. A new command can be given tRRC after self refresh exit. Rev. 0.1/Apr.01 11 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series OPERATING OPTION TABLE HYM7V75AC801BTHG-8 /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 125MHz (8.0ns) 3CLKS 3CLKS 6CLKS 9CLKS 3CLKS 6ns 3ns 100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 83MHz (12.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 83MHz (12.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 66MHz (15.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 100MHz (10.0ns) 3CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 83MHz (12.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 66MHz (15.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns HYM7V75AC801BTHG-10P HYM7V75AC801BTHG-10S Note : DIMM /CAS Latency = Device CL + 1 (Registered mode) Rev. 0.1/Apr.01 12 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series COMMAND TRUTH TABLE ADDR A10/ AP CKEn-1 CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA RA BA NOTE V Read L Read with Autoprecharge H Write V L V Write with Autoprecharge H Precharge All Banks H X L L H L X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Entry H L L L L H X H X X X Exit L H Precharge Selected Bank X Self Refresh Entry H L Precharge Power Down Exit Entry L H H X L V X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V H L X 1 X X X X Clock Suspend X Exit L H X X Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X = Don’t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code, NOP = No operation Rev. 0.1/Apr.01 13 PC100 SDRAM Registered DIMM HYM7V75AC801B H-Series PACKAGE DIMENSIONS Rev. 0.1/Apr.01 14