256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock(CK) • Data I/O transactions on both edges of data strobe • Edge aligned data output, center aligned data input • LDM,UDM/DM for write masking only • Auto & Self refresh • 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8 • 60 Ball FBGA package ORDERING INFORMATION Part No. Org. K4H560438D-GC(L)B3 K4H560438D-GC(L)A2 Package A2(DDR266@CL=2) SSTL2 60 ball FBGA SSTL2 60 ball FBGA SSTL2 60 ball FBGA B0(DDR266@CL=2.5) K4H560838D-GC(L)B3 B3(DDR333@CL=2.5) 32M x 8 A2(DDR266@CL=2) K4H560838D-GC(L)B0 B0(DDR266@CL=2.5) K4H561638D-GC(L)B3 B3(DDR333@CL=2.5) K4H561638D-GC(L)A2 Interface B3(DDR333@CL=2.5) 64M x 4 K4H560438D-GC(L)B0 K4H560838D-GC(L)A2 Max Freq. 16M x 16 K4H561638D-GC(L)B0 A2(DDR266@CL=2) B0(DDR266@CL=2.5) Operating Frequencies - B3(DDR333) - A2(DDR266A) - B0(DDR266B) Speed @CL2 133MHz 133MHz 100MHz Speed @CL2.5 166MHz 133MHz 133MHz *CL : Cas Latency - 1 - Rev. 2.2 Mar. ’03 256Mb DDR SDRAM Package Dimension 0.10 Max 8.00 ± 0.10 0.80 x 8 = 6.40 ENCAPSULANT AREA 0.80 x 4 = 3.20 0.80 x 2 = 1.60 8.0 0± 0.10 9 8 7 6 0.80 x 2 = 1.60 5 4 3 2 1 0.80 1.00 A B 0.50 5.50 0.45 ± 0.05 H J 14.00 ± 0.10 F G 1.00 x 11 = 11.00 0.50 E 14.0 ± 0.10 14.00 ± 0.10 D 5.50 C K L M 0.35 ± 0.05 60 - 0.45 π (0.90) (0.90) ± 0.05 (1.80) TOP VIEW 1.10± 0.10 BOTTOM VIEW Organization Column Address 64Mx4 A0-A9, A11 32Mx8 A0-A9 16Mx16 A0-A8 DM is internally loaded to match DQ and DQS identically. Column address configuration - 2 - Rev. 2.2 Mar. ’03 K4H561638D DDR SDRAM Pin configuration 64M x 4 60Ball CSP A B C D E F 1 VSSQ NC NC NC NC VREF 2 NC VDDQ VSSQ VDDQ VSSQ VSS G H J K L M CK A12 A11 A8 A6 A4 3 VSS DQ3 NC DQ2 DQS DM CK CKE A9 A7 A5 VSS 7 VDD DQ0 NC DQ1 NC NC WE RAS BA1 A0 A2 VDD 8 NC VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10 A1 A3 9 VDDQ NC NC NC NC NC G H J K L M 32M x 8 60Ball CSP A B C D E F 1 VSSQ NC NC NC NC VREF 2 DQ7 VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4 3 VSS DQ6 DQ5 DQ4 DQS DM CK CKE A9 A7 A5 VSS 7 VDD DQ1 DQ2 DQ3 NC NC WE RAS BA1 A0 A2 VDD 8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10 A1 A3 9 VDDQ NC NC NC NC NC G H J K L M 16M x 16 60Ball CSP A B C D E F 1 VSSQ DQ14 DQ12 DQ10 DQ8 VREF 2 DQ15 VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4 3 VSS DQ13 DQ11 DQ9 UDQS UDM CK CKE A9 A7 A5 VSS 7 VDD DQ2 DQ4 DQ6 LDQS LDM WE RAS BA1 A0 A2 VDD 8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10 A1 A3 9 VDDQ DQ1 DQ3 DQ5 DQ7 NC Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A12 Address BA0 ~ BA1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQM Data Input/Output Mask DQ0 ~ 15 Data Input/Output VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground - 3 - Rev. 2.2 Mar. ’03 256Mb DDR SDRAM Block Diagram (16Mbit x 4 I/O x 4 Banks) CK, CK WE I/O Control 4 Data Input Register DM Serial to parallel Bank Select 8 8Mx8 4 Output Buffer 8Mx8 8 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADD Address Register CK, CK 8Mx8 x4 DQi 8Mx8 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe Gen. DLL Programming Register Data Strobe LCKE LRAS LCBR LWE LCAS LWCBR CK, CK Timing Register CK, CK CKE CS RAS CAS - 4 - WE Rev. 2.2 Mar. ’03 256Mb DDR SDRAM Block Diagram (8Mbit x 8 I/O x 4 Banks) CK, CK WE I/O Control 8 Data Input Register DM Serial to parallel Bank Select 16 4Mx16 8 Output Buffer 4Mx16 16 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADD Address Register CK, CK 4Mx16 x8 DQi 4Mx16 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe Gen. DLL Programming Register Data Strobe LCKE LRAS LCBR LWE LCAS LWCBR CK, CK Timing Register CK, CK CKE CS RAS CAS - 5 - WE Rev. 2.2 Mar. ’03 256Mb DDR SDRAM Block Diagram (4Mbit x 16 I/O x 4 Banks) CK, CK LWE I/O Control 16 Data Input Register LDM Serial to parallel Bank Select 32 2Mx32 16 Output Buffer 2Mx32 32 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer Address Register ADD 2Mx32 x16 DQi 2Mx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe Gen. DLL Programming Register Data Strobe LCKE LRAS LCBR LWE LCAS LWCBR CK, CK Timing Register CK, CK CKE CS RAS CAS - 6 - WE Rev. 2.2 Mar. ’03 256Mb DDR SDRAM Input/Output Function Description SYMBOL TYPE DESCRIPTION CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. LDM,(U)DM Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. BA0, BA1 Input Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. A [n : 0] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). DQ I/O Data Input/Output : Data bus LDQS,(U)DQS I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. NC - No Connect : No internal electrical connection is present. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VSSQ Supply DQ Ground. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply Ground. VREF Input SSTL_2 reference voltage. - 7 - Rev. 2.2 Mar. ’03 256Mb DDR SDRAM Command Truth Table (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A11,A12 A9 ~ A0 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X Auto Refresh Refresh Entry Self Refresh H H L L H H H H X X X X L L H H V H X L H L H V H X L H L L V H X L H H L H X L L H L Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H Exit L H H X X X L V V V L H Bank Active & Row Address H Read & Column Address Write & Column Address Exit Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Active Power Down Precharge Power Down Mode DM H No operation (NOP) : Not defined H X X 3 3 3 X 3 Row Address L Column Address H L Column Address H X V L X H X X X L H H H 4 4 4, 6 7 X 5 X X X H 4 X 8 9 9 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2.EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. - 8 - Rev. 2.2 Mar. ’03 K4H560438D DDR SDRAM 16M x 4Bit x 4 Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H560438D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 16,777,216 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Absolute Maximum Rating Parameter Symbol Value Unit V Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.5 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70°C) Parameter Symbol Min Max Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7 I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5 II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Input leakage current - 9 - Unit Note Rev. 2.2 Mar. ’03 K4H560438D DDR SDRAM Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. DDR SDRAM IDD spec table (VDD=2.7V, T = 10°C) 64Mx4 Symbol IDD6 K4H560438D-GC(L)B3 (DDR333) Unit K4H560438D-GC(L)A2,B0 (DDR266A/B) IDD0 90 80 mA IDD1 110 100 mA IDD2P 3 3 mA IDD2F 25 20 mA IDD2Q 20 18 mA IDD3P 35 30 mA mA IDD3N 55 45 IDD4R 150 120 mA IDD4W 160 135 mA IDD5 180 165 mA 3 3 mA 1.5 1.5 mA 290 250 mA Normal Low power IDD7A Notes Optional AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Symbol Min VIH(AC) VREF + 0.31 Max Unit Note V 3 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V 3 Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Overshoot/Undershoot specification Specification Parameter Address & Control pins Data pins Maximum peak amplitude allowed for overshoot 1.6 V 1.2V Maximum peak amplitude allowed for undershoot 1.6 V 1.2V The area between the overshoot signal and VDD must be less than or equal to 4.5 V-ns 2.5 V-ns The area between the undershoot signal and GND must be less than or equal to 4.5 V-ns 2.5 V-ns - 10 - Rev. 2.2 Mar. ’03 K4H560438D DDR SDRAM AC Timming Parameters & Specifications Parameter B3 (DDR333) Symbol Min Row cycle time Max A2 (DDR266A) Min Max B0 (DDR266B) Min Unit tRC 60 65 65 ns tRFC 72 75 75 ns Row active time tRAS 42 RAS to CAS delay tRCD 18 20 20 ns tRP 18 20 20 ns Row active to Row active delay tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns tWTR 1 1 1 tCK Refresh row cycle time Row precharge time Last data in to Read command Col. address to Col. address delay Clock cycle time tCCD CL=2.0 CL=2.5 Clock high level width Clock low level width 70K 1 45 120K 1 45 120K 1 ns tCK 7.5 12 7.5 12 10 12 ns 5 6 12 7.5 12 7.5 12 ns 5 tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK tCK tCL 0.45 0.55 0.45 0.55 0.45 0.55 tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS-out access time from CK/CK Note Max 5 2 DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 tDSC 0.9 Address and Control Input setup time(fast) tIS 0.75 Address and Control Input hold time(fast) tIH 0.75 0.9 0.9 ns 6 Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns 6 Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns 6 Data-out high impedence time from CK/CK tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 Data-out low impedence time from CK/CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 tSL(I) 0.5 Input Slew Rate(for I/O pins) tSL(IO) 0.5 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 DQS-in cycle time Input Slew Rate(for input only pins) 0.35 1.1 0.9 0.35 1.1 0.9 tCK 1.1 0.9 0.5 tCK ns 0.5 0.5 - 11 - 0.9 ns ns V/ns 0.5 6 6 V/ns 7 V/ns 10 Rev. 2.2 Mar. ’03 K4H560438D Parameter DDR SDRAM Symbol -GC(L)B3 (DDR333) Min -GC(L)A2 (DDR266A) Max Min Max -GC(L)B0 (DDR266B) Min Unit Note Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns 7,8,9 DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns 7,8,9 Control & Address input pulse width tIPW 2.2 2.2 2.2 ns DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tQHS 0.5 0.6 0.75 tWPST 0.4 0.4 0.6 0.4 tRAP 18 20 20 tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) 4 0.75 ns 0.6 tCK 3 tCK 11 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate ∆tDS ∆tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. - 12 - Rev. 2.2 Mar. ’03 K4H560438D DDR SDRAM 8. I/O Setup/Hold Plateau Derating I/O Input Level ∆tDS ∆tDH (mV) (ps) (ps) ± 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate ∆tDS ∆tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. <Reference> The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) ∆tIH/tIS (ps) ∆tDSS/tDSH (ps) ∆tAC/tDQSCK (ps) ∆tLZ(min) (ps) ∆tHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 - 13 - Rev. 2.2 Mar. ’03 K4H560438D DDR SDRAM (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C) AC Operating Test Conditions Parameter Value Unit Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate (for imput only) 0.5 V/ns Input slew rate (I/O pins) 0.5 V/ns VREF+0.31/VREF-0.31 V VREF V Vtt V Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Load Circuit Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output Capacitance (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz) Symbol Min Max Delta Cap(max) Unit Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Parameter CIN1 1.5 3.5 0.5 pF Input capacitance( CK, CK ) CIN2 1.5 3.5 0.25 pF Data & DQS input/output capacitance COUT 3.5 5.5 pF 0.5 Input capacitance(DM) CIN3 - 14 - 3.5 5.5 pF Rev. 2.2 Mar. ’03 K4H560838D DDR SDRAM 8M x 8Bit x 4 Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H560838D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 8,388,608 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.5 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70°C) Parameter Symbol Min Max Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7 I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5 II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Input leakage current - 15 - Unit Note Rev. 2.2 Mar. ’03 K4H560838D DDR SDRAM Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. (VDD=2.7V, T = 10°C) DDR SDRAM IDD spec table 32Mx8 Symbol IDD6 K4H560838D-GC(L)B3 (DDR333) Unit K4H560838D-GC(L)A2, B0 (DDR266A/B) IDD0 90 80 mA IDD1 120 110 mA IDD2P 3 3 mA IDD2F 25 20 mA IDD2Q 20 18 mA IDD3P 35 30 mA IDD3N 55 45 mA IDD4R 170 140 mA IDD4W 170 140 mA IDD5 180 165 mA 3 3 mA 1.5 1.5 mA 325 280 mA Normal Low power IDD7A Notes Optional AC Operating Conditions Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Max Unit Note V 3 VREF - 0.31 V 3 0.7 VDDQ+0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Overshoot/Undershoot specification Specification Parameter Address & Control pins Data pins Maximum peak amplitude allowed for overshoot 1.6 V 1.2V Maximum peak amplitude allowed for undershoot 1.6 V 1.2V The area between the overshoot signal and VDD must be less than or equal to 4.5 V-ns 2.5 V-ns The area between the undershoot signal and GND must be less than or equal to 4.5 V-ns 2.5 V-ns - 16 - Rev. 2.2 Mar. ’03 K4H560838D DDR SDRAM AC Timming Parameters & Specifications Parameter Symbol B3 (DDR333) Min Row cycle time Max A2 (DDR266A) Min Max B0 (DDR266B) Min Unit tRC 60 65 65 ns tRFC 72 75 75 ns Row active time tRAS 42 RAS to CAS delay tRCD 18 20 20 ns tRP 18 20 20 ns Row active to Row active delay tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns tWTR 1 1 1 tCK Refresh row cycle time Row precharge time Last data in to Read command Col. address to Col. address delay Clock cycle time tCCD CL=2.0 CL=2.5 Clock high level width Clock low level width 70K 1 45 120K 1 45 120K 1 ns tCK 7.5 12 7.5 12 10 12 ns 5 6 12 7.5 12 7.5 12 ns 5 tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS-out access time from CK/CK Note Max 5 2 DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 tDSC 0.9 Address and Control Input setup time(fast) tIS 0.75 Address and Control Input hold time(fast) tIH 0.75 0.9 0.9 ns 6 Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns 6 Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns 6 Data-out high impedence time from CK/CK tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data-out low impedence time from CK/CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns tSL(I) 0.5 DQS-in cycle time Input Slew Rate(for input only pins) 0.35 1.1 0.9 0.35 1.1 0.9 0.9 tCK 1.1 0.9 0.5 ns 0.5 V/ns Input Slew Rate(for I/O pins) tSL(IO) 0.5 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 - 17 - 0.5 tCK 0.5 6 6 V/ns 7 V/ns 10 Rev. 2.2 Mar. ’03 K4H560838D Parameter DDR SDRAM B3 (DDR333) Symbol Min A2 (DDR266A) Max Min Max B0 (DDR266B) Min Unit Note Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns 7,8,9 DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns 7,8,9 Control & Address input pulse width tIPW 2.2 2.2 2.2 ns DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tQHS 0.5 0.6 0.75 tWPST 0.4 0.4 0.6 0.4 tRAP 18 20 20 tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) 4 0.75 ns 0.6 tCK 3 tCK 11 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate ∆tDS ∆tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. - 18 - Rev. 2.2 Mar. ’03 K4H560838D DDR SDRAM 8. I/O Setup/Hold Plateau Derating I/O Input Level ∆tDS ∆tDH (mV) (ps) (ps) ± 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate ∆tDS ∆tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. <Reference> The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) ∆tIH/tIS (ps) ∆tDSS/tDSH (ps) ∆tAC/tDQSCK (ps) ∆tLZ(min) (ps) ∆tHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 - 19 - Rev. 2.2 Mar. ’03 K4H560838D DDR SDRAM AC Operating Test Conditions (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C) Parameter Value Unit Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate (for imput only) 0.5 V/ns Input slew rate (I/O pins) 0.5 V/ns VREF+0.31/VREF-0.31 V VREF V Vtt V Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Load Circuit Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output Capacitance (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz) Symbol Min Max Delta Cap(max) Unit Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Parameter CIN1 1.5 3.5 0.5 pF Input capacitance( CK, CK ) CIN2 1.5 3.5 0.25 pF Data & DQS input/output capacitance COUT 3.5 5.5 pF 0.5 Input capacitance(DM) CIN3 - 20 - 3.5 5.5 pF Rev. 2.2 Mar. ’03 K4H561638D DDR SDRAM 4M x 16Bit x 4 Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H561638D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 4,194,304 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.5 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70°C) Parameter Symbol Min Max Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7 I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5 II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Input leakage current - 21 - Unit Note Rev. 2.2 Mar. ’03 K4H561638D DDR SDRAM Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. DDR SDRAM IDD spec table (VDD=2.7V, T = 10°C) 16Mx16 Symbol IDD6 K4H560838D-GC(L)B3 (DDR333) Unit K4H560838D-GC(L)A2, B0 (DDR266A/B) IDD0 90 80 mA IDD1 125 115 mA IDD2P 3 3 mA IDD2F 25 20 mA IDD2Q 20 18 mA IDD3P 35 30 mA IDD3N 55 45 mA IDD4R 200 170 mA IDD4W 190 155 mA IDD5 180 165 mA 3 3 mA 1.5 1.5 mA 350 300 mA Normal Low power IDD7A Notes Optional AC Operating Conditions Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Max Unit Note V 3 VREF - 0.31 V 3 0.7 VDDQ+0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Overshoot/Undershoot specification Specification Parameter Address & Control pins Data pins Maximum peak amplitude allowed for overshoot 1.6 V 1.2V Maximum peak amplitude allowed for undershoot 1.6 V 1.2V The area between the overshoot signal and VDD must be less than or equal to 4.5 V-ns 2.5 V-ns The area between the undershoot signal and GND must be less than or equal to 4.5 V-ns 2.5 V-ns - 22 - Rev. 2.2 Mar. ’03 K4H561638D DDR SDRAM AC Timming Parameters & Specifications Parameter Symbol B3 (DDR333) Min Row cycle time Max A2 (DDR266A) Min Max B0 (DDR266B) Min Unit tRC 60 65 65 ns tRFC 72 75 75 ns Row active time tRAS 42 RAS to CAS delay tRCD 18 20 20 ns tRP 18 20 20 ns Row active to Row active delay tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns tWTR 1 1 1 tCK Refresh row cycle time Row precharge time Last data in to Read command Col. address to Col. address delay Clock cycle time tCCD CL=2.0 CL=2.5 Clock high level width Clock low level width 70K 1 45 120K 1 45 120K 1 ns tCK 7.5 12 7.5 12 10 12 ns 5 6 12 7.5 12 7.5 12 ns 5 tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK tCK tCL 0.45 0.55 0.45 0.55 0.45 0.55 tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS-out access time from CK/CK Note Max 5 2 DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 tDSC 0.9 Address and Control Input setup time(fast) tIS 0.75 Address and Control Input hold time(fast) tIH 0.75 0.9 0.9 ns 6 Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns 6 Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns 6 Data-out high impedence time from CK/CK tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data-out low impedence time from CK/CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns tSL(I) 0.5 DQS-in cycle time Input Slew Rate(for input only pins) 0.35 1.1 0.9 0.35 1.1 0.9 0.9 tCK 1.1 0.9 0.5 ns 0.5 V/ns Input Slew Rate(for I/O pins) tSL(IO) 0.5 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 - 23 - 0.5 tCK 0.5 6 6 V/ns 7 V/ns 10 Rev. 2.2 Mar. ’03 K4H561638D Parameter DDR SDRAM Symbol B3 (DDR333) Min A2 (DDR266A) Max Min Max B0 (DDR266B) Min Unit Note Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns 7,8,9 DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns 7,8,9 Control & Address input pulse width tIPW 2.2 2.2 2.2 ns DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns tWPST 0.4 0.6 tRAP 18 20 20 tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tQHS 0.5 0.75 0.4 0.6 0.4 4 0.75 ns 0.6 tCK 3 tCK 11 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate ∆tDS ∆tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. - 24 - Rev. 2.2 Mar. ’03 K4H561638D DDR SDRAM 8. I/O Setup/Hold Plateau Derating I/O Input Level ∆tDS ∆tDH (mV) (ps) (ps) ± 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate ∆tDS ∆tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. <Reference> The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) ∆tIH/tIS (ps) ∆tDSS/tDSH (ps) ∆tAC/tDQSCK (ps) ∆tLZ(min) (ps) ∆tHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 - 25 - Rev. 2.2 Mar. ’03 K4H561638D DDR SDRAM AC Operating Test Conditions (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C) Parameter Value Unit Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate (for imput only) 0.5 V/ns Input slew rate (I/O pins) 0.5 V/ns VREF+0.31/VREF-0.31 V VREF V Vtt V Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Load Circuit Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output Capacitance (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz) Symbol Min Max Delta Cap(max) Unit Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Parameter CIN1 1.5 3.5 0.5 pF Input capacitance( CK, CK ) CIN2 1.5 3.5 0.25 pF Data & DQS input/output capacitance COUT 3.5 5.5 pF 0.5 Input capacitance(DM) CIN3 - 26 - 3.5 5.5 pF Rev. 2.2 Mar. ’03