IDT74ALVC00 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE FEATURES: – – DESCRIPTION: This quadruple 2-input positive-NAND gate is built using advanced dual metal CMOS technology. The ALVC00 performs the Boolean function Y = A • B or Y = A + B in positive logic. 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SOIC, SSOP and TSSOP packages – – – – – – IDT74ALVC00 The ALVC00 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: • 3.3V High Speed Systems • 3.3V and lower voltage computing systems Drive Features for ALVC00: – High Output Drivers: ±24mA – Suitable for heavy loads FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION 1A 1 14 V CC 1B 2 13 4B 1Y 3 4A 2A 4 12 SO14-1 SO14-2 11 SO14-3 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y A Y B 4Y SOIC/ SSOP/ TSSOP TOP VIEW (each gate)(1) FUNCTION TABLE PIN DESCRIPTION Inputs Description Output xY Pin Names xA, xB Data Inputs xA xB xY Data Outputs H H L L X H X L H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2000 1 c 1999 Integrated Device Technology, Inc. DSC-4632/- IDT74ALVC00 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max. CAPACITANCE Unit VTERM(2) Terminal Voltage with Respect to GND – 0.5 to + 4.6 V VTERM(3) Terminal Voltage with Respect to GND – 0.5 to VCC + 0.5 V TSTG Storage Temperature – 65 to + 150 °C IOUT DC Output Current – 50 to + 50 mA IIK ± 50 mA IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 – 50 mA ICC Continuous Current through each ±100 mA ISS VCC or GND (TA = +25°C, f = 1.0MHz) Parameter(1) Symbol CIN Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF ALVC QUAD Link NOTE: 1. As applicable to the device type. ALVC QUAD Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: T A = −40°C to +85°C Symbol VIH Parameter Input HIGH Voltage Level Typ.(1) VCC = 2.3V to 2.7V Min. 1.7 — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 Test Conditions Unit V VIL Input LOW Voltage Level — — 0.8 IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ∆ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC One input at VCC − 0.6V, other inputs at VCC or GND — 0.1 10 µA — — 750 µA VCC = 2.7V to 3.6V Quiescent Power Supply Current Variation µA ALVC QUAD Link NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. c V 2 IDT74ALVC00 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V ALVC QUAD Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD Parameter Power Dissipation Capacitance per gate SWITCHING CHARACTERISTICS Parameter Propagation Delay xA or xB to xY VCC = 3.3V ± 0.3V Typical 21 Typical 23 Test Conditions CL = 0pF, f = 10Mhz Unit pF (1) VCC = 2.5V ± 0.2V Symbol tPLH tPHL VCC = 2.5V ± 0.2V Min. 1 Max. 3.8 NOTE: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 3 VCC = 2.7V Min. 1 Max. 3.4 VCC = 3.3V ± 0.3V Min. 1 Max. 3.2 Unit ns IDT74ALVC00 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ± 0.3V VCC(1) = 2.7V 6 6 VIH 2.7 2.7 Vcc V SAM E PHASE INPUT TRANSITION VT 1.5 1.5 Vcc / 2 V OUTPUT VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 VCC(2)= 2.5V ± 0.2V Unit 2 x Vcc V 50 30 tPLH tPH L tPLH tPH L V IH VT 0V V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF ALVC QUAD Link ALVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LO AD V CC 500 Ω (1, 2) V IN GND tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT CL ALVC Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. V LO AD/2 V LO AD/2 VT V LZ V OL tPH Z V OH V HZ VT 0V 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SET-UP, HOLD, AND RELEASE TIMES DATA INPUT Switch VLOAD tS U tH tR EM ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL Open tS U tH ALVC QUAD Link INPUT TSK ALVC Link (x) V IH VT 0V tPH L1 tPLH1 PULSE WIDTH V OH OUTPUT 1 tSK (x) V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V TIM ING INPUT GND OUTPUT SKEW - 0V tPLZ ALVC Link SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests V IH VT CONTROL INPUT V OUT Pulse Generator DISABLE ENABLE Open LOW -HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT ALVC Link tPLH2 tPH L2 tSK (x) = tPL H2 - tP LH 1 or tPH L2 - tP HL1 ALV C Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 4 IDT74ALVC00 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Temp. R ange ALVC XXX XX Device Type Package DC PY PG Sm all Outline IC (SO14-1) Shrink Small Outline Package (SO14-2) Thin Shrink Small Outline Package (SO14-3) 00 Quadruple 2-Input Positive-NAND Gate, ±24mA 74 – 40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 5