IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O IDT74LVC08A FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • All inputs, outputs, and I/Os are 5V tolerant • Supports hot insertion • Available in SOIC, SSOP, and TSSOP packages This quadruple 2-input positive-AND gate is built using advanced dual metal CMOS technology. The LVC08A device performs the Boolean function Y = A • B or Y = A + B in positive logic. The LVC08A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. DRIVE FEATURES: APPLICATIONS: • High Output Drivers: ±24mA • Reduced system switching noise • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A Y B 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y SOIC/ SSOP/ TSSOP TOP VIEW PIN DESCRIPTION Pin Names FUNCTION TABLE (EACH GATE)(1) Inputs Description Output xA, xB Data Inputs xA xB xY xY Data Outputs H H H L X L X L L NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4585/1 IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHz) ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit Conditions Typ. Max. Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V CIN Input Capacitance VIN = 0V 4.5 6 pF TSTG Storage Temperature –65 to +150 °C COUT Output Capacitance VOUT = 0V 5.5 8 pF IOUT DC Output Current –50 to +50 mA CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA Symbol Parameter(1) NOTE: 1. As applicable to the device type. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V, VIN = GND or VCC — — 100 — — 10 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 500 µA IIH IIL NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2 IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per Gate VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz — 10 pF SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter tPLH Propagation Delay tPHL xA or xB to xY tSK(o) Output Skew(2) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 3 VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit — 4.8 1 4.1 ns — — — 1 ns IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 2.5V±0.2V VLOAD VIH VCC(2)= 3.3V±0.3V & 2.7V Unit 2 x Vcc 6 V Vcc 2.7 V VT Vcc / 2 1.5 V VLZ 150 300 mV VHZ 150 300 mV CL 30 50 pF tPHL tPLH tPHL VIH VT 0V OPPOSITE PHASE INPUT TRANSITION LVC QUAD Link Propagation Delay VIN tPZL VOUT D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω RT CL LVC QUAD Link Test Circuit for All Outputs VIH VT 0V CONTROL INPUT GND 500Ω DISABLE ENABLE Open (1, 2) tPLH OUTPUT VLOAD VCC Pulse Generator VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC QUAD Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. Enable and Disable Times SWITCH POSITION Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other Tests Open INPUT OUTPUT 1 tPLH1 tSK (x) tPLH2 tH tREM SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL tSU tH LVC QUAD Link Set-up, Hold, and Release Times VOH VT VOL LOW-HIGH-LOW PULSE VOH VT VOL OUTPUT 2 tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V TIMING INPUT VIH VT 0V tPHL1 tSK (x) DATA INPUT VT tW HIGH-LOW-HIGH PULSE tPHL2 VT LVC QUAD Link tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Pulse Width LVC QUAD Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 4 IDT74LVC08A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX LVC XXX XX IDT Temp. Range Device Type Package DC PY PG Small Outline IC Shrink Small Outline Package Thin Shrink Small Outline Package 08A Quadruple 2-Input Positive-AND Gate, ±24mA 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 – 40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 5 for Tech Support: [email protected] (408) 654-6459