IP113 10/100 Base-Tx / Fx Converter Feature Utilize single clock source only (25Mhz) 2 port 10/100 Ethernet switch with built in transceivers Utilize single power (2.5v) and memory 0.25um technology Build in SSRAM for frame buffer Packaged in 128 pin PQFP Built in storage of 1K MAC address Support flow control General Description - Support IEEE802.3x for flow control on full duplex IP113 is a 2 port 10/100 Ethernet integrated switch. It mode operation consists of a 2-port switch controller and two Fast - Support back pressure for flow control in half duplex Ethernet transceivers. Each of the transceivers complies mode operation with the IEEE802.3, IEEE802.3u, and IEEE802.3x A 2 port switching fabric specifications. The transceivers in IP113 are designed in - Support two-level hashing algorithm to solve address DSP approach with advance 0.25um technology; this collision results in high noise immunity and robust performance. - Support address aging - Store and forward mode The IP113 operates in store and forward mode. It stores - Broadcast storm protection the incoming packet to the internal SSRAM and learns - Full line speed capability of 148800 (14880) the SA (source address) automatically if the packet is packets/sec for 100M (10M) error free. The SA is stored in the internal address table. Integrate two transceivers IP113 forwards a packet according to DA destination - TP port with auto negotiation address and address table. When the segments of - Fully digital adaptive equalizer and timing recovery destination ports are free, it reads the packet from the module internal SSRAM and forwards it to the appropriate ports - Base line Wander correction according to the address table. The incoming packets - 10BaseTX, 100BaseTX, and 100BaseFX operation with errors are dropped. IP113 supports IEEE802.3x, Support link fault pass through optional backpressure, and various LED functions, etc. TP port forced 10M/100M, full/half These functions can be configured to fit the different Support all pass function - hashing disabled requirements by feeding operation parameters via LED status of Link, activity, Full/half duplex, and speed EEPROM interface or pull up/down resistors on specified Initial parameter setting by pin configuration or pins. EEPROM Preliminary, Specification subject to change without notice IP113-DS-P07 Jul.19, 2002 1 IP113 Block Diagram Address Table RxMAC Rx Buffer Mgnt Hashing Unit 10/100BASE-T Transceiver with N-WAY (x2) SSRAM Packet Buffer Memory I/F Unit (x2) TxMAC Empty Buffer Mgnt Tx Buffer Mgnt Queue Mgnt (x2) EEPROM Interface Application of IP113 FX Fiber Module IP113 TX Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 2 LED Controller IP113 OP[1] LED_SPEED[1] OP[0] VCC 109 103 GND 110 104 X2 111 LED_LINK[1] OSCI (X1) 112 TWOPART VCC 113 105 GND 114 106 GND 115 LED_FULL[1] VCC 116 LED_ACT[1] / FORCE_FULL VCC 117 107 GND 118 NC 1 102 FORCE_100 NC 2 101 GND_IO_1 NC 3 100 GND 4 99 LED_SPEED[0] VCC_IO_1 VCC 5 98 LED_FULL[0] / MODE GND 6 97 LED_ACT[0] NC 7 96 LED_LINK[0] NC 8 95 GND_SRAM NC 9 94 VCC_SRAM VCC 10 93 MODBCK NC 11 92 BK_EN NC 12 91 ALLPASS GND 13 90 AGING VCC 14 89 UTPDET BGRES 15 88 R4_EN GND 16 87 NC GND 17 86 X_EN RXIP 18 85 RESETB RXIM 19 84 TSE IP113 65 NC 3 64 38 63 NC GND NC 66 NC 37 62 NC VCC 61 67 NC 36 NC NC FXRDM NC 68 60 35 59 NC FXRDP GND TP_FORCE 69 58 70 34 VCC 33 GND 57 GND 56 NC TEST_ISRAM[1] 71 TEST_ISRAM[0] / LFP 32 55 NC NC 54 72 TEST2 31 TEST1 VCC_IO_2 NC VCC 73 53 30 52 GND_IO_2 VCC GND 74 51 29 GND NC NC 50 75 49 28 VCC NC NC VCC 76 48 27 47 BP_KIND[1] NC GND 77 FXSD 26 46 BP_KIND[0] GND GND VCC 78 45 79 25 44 24 VCC GND GND GND GND 43 80 42 23 VCC LED_SEL[1] TXOM GND 81 FXTDM 22 41 LED_SEL[0] TXOP 40 TSM 82 39 83 21 NC 20 NC FXTDP VCC Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 108 NC 119 NC 123 120 GND 124 GND NC 125 NC NC 126 121 VCC 127 122 GND 128 PIN Assignments IP113 PIN Description Type I O IPH IPL Pin no. MLT3 Signals 22 23 15 Description Used as Input pin Used as Output pin Input pin with pull-hi resistor Input pin with pull-low resistor Label Type Description TXOP TXOM BGRES O TP transmit O 47 FXSD I 18 19 35 36 40 41 RXIP RXIM FXRDP FXRDM FXTDP FXTDM I Band gap resister It is connected to GND through a 6.19k (1%) resistor in application circuit. 100Base-FX signal detect Fiber signal detect. It is an input signal from fiber MAU. Fiber signal detect is active if the voltage of FXSD is higher than 1.2v. TP receive I Fiber receiver data pair I Fiber transmit data pair Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 4 IP113 PIN Description (continued) Pin no. Label LED Normal Output Mode 81,82 LED_SEL[1:0] 106, 96 LED_LINK[1:0] Type Description IPH O LED output mode selection They are latched at the end of reset to select the LED output mode LED_SEL[1:0]=2’b00: LED mode 0, LED_SEL[1:0]=2’b01: LED mode 1, LED_SEL[1:0]=2’b10: LED mode 2, LED_SEL[1:0]=2’b11: LED mode 3 (default) After reset, IP113 reads EEPROM with LED_SEL[1:0], which works as EECS and EESK. These two pins are output signals during reading EEPROM. After finishing reading EEPROM, these two pins becomes input signal to isolate IP113 from EEPROM Link, Activity (output after reset) LED mode0: Link+Activity (off: Link fail, on:Link ok and no activity, flash: Link ok and TX/RX activity) LED mode1: Receive activity (off: not receiving, flash: receiving) LED mode2: Tx/Rx Activity (off: no activity, flash: TX or RX activity) 107,97 LED_ACT[1:0] O LED mode3: Link+Activity (off: Link fail, on:Link ok and no activity, flash: Link ok and TX/RX activity) Full/half, Collision, Tx Activity (output after reset) LED mode0: Collision (off: no collision, flash: when collision happens) LED mode1: Tx activity (1: no TX activity, flash: when TX activity happens) LED mode2, 3: Full+collision (1: half without collision, 0: full, flash: collision) 108, 98 LED_FULL[1:0] O Full/half, Link (output after reset) LED mode0, Full/half: (off: half, on: full) LED mode1, Link: (off: Link fail, on: Link ok) LED mode2, Link: (off: Link fail, on: Link ok) LED mode3: same as mode 0 109, 99 LED_SPEED[1:0] O Speed (output after reset) LED mode0: (off: speed=10M, on: speed=100M) LED mode1: (off: speed=10M, on: speed=100M) LED mode2: (off: speed=10M, on: speed=100M) LED mode3: (off: speed=10M, on: speed=100M) Note: Please refer to the paragraph of “LED display” for information about Flash and ON Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 5 IP113 PIN Description (continued) Pin no. Label Type Description LED pins used as initial setting mode during reset Note: Please refer to the paragraph of Initial Value Set Via Pins for detail information about pull high/ low setting. 86 X_EN IPH IEEE 802.3X enable (X_en) on all ports 1: enable (default), 0: disable 92 BK_EN IPH It is internally pulled high. Backpressure enable (BK_EN) 1: enable (default), 0: disable 90 AGING IPH 88 R4_EN IPL 98 103 104 MODE OP[1] OP[0] IPL It is internally pulled high. Address aging enable 1: enable, aging time 300s (default), 0: disable It is internally pulled high. Change capability enable (Update_r4_en) A full duplex port will change its capability to half duplex, if the remote full duplex port does not support IEEE802.3x and this function is enabled. 1: enable, 0: disable (default) It is internally pulled low. Operation mode setting It is used to enable TP port and fiber port. OP[1:0] should be connected to VCC through resistors. MODE should be connected to GND through resistors. 77,78 BP_KIND[1:0] IPL Backpressure type selection Bp_kind[1:0] are valid only if Bk_en is set to high. 00: carrier base backpressure (default) 01: collision base backpressure with hashing 10: collision base backpressure without hashing After reset, IP113 reads EEPROM with BP_KIND[1:0], which works as EEDO and EEDI. BP_KIND[1] is an input signal and BP_KIND[0] is an output signal during reading EEPROM. After finishing reading EEPROM, these two pins becomes input signal to isolate IP113 from EEPROM. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 6 IP113 PIN Description (continued) Pin no. Label Type Description LED pins used as initial setting mode during reset (continued) 105 TWOPART IPH Turn on twopartD (Twopart) IP113 examine the carrier for 64 bits only during its back off period if this function is enabled. It makes IP113 have higher priority in a collision event. 93 106 MODBCK LED_LINK[1] IPH 1: enable (default), 0: disable It is internally pulled high. Aggressive back off enable (MODBCK) IP113 uses modified (aggressive) back off algorithm if this function is enabled. The maximum back off period is limited to 8-slot time. It makes IP113 have higher priority in a collision event. 1: aggressive mode enable (default), 0: standard back off It is internally pulled high. Bypass scrambler (BPSCR_MODE) 1: bypass, 0: not bypass (default) IPL 96 LED_LINK[0] IPH 97 LED_ACT[0] IPL 108 LED_FULL[1] IPL 89 UTPDET IPH The default value must be adopted for normal operation. It is internally pulled low. Nodrop16 (Drop16*) 1: do not drop after 16 collisions, (default) 0: drop after 16 collision It is internally pulled high. Broadcast storm protection enable (BF_STM_EN) 1: enable, 0: disable (default) It is internally pulled low. FIBER_HALF 1: all fiber port works at half duplex, 0: all fiber port works at full duplex (default) It is internally pulled low. UTPdet It is a power saving mode for TP port. TP port will be power down when the cable is unplugged and the function is enabled. 1: enable (default), 0: disable It is internally pulled high. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 7 IP113 PIN Description (continued) Pin no. Label TP port force mode function TP_FORCE 70 Type IPL Description TP_FORCE 1: TP port is forced limited capability with NWAY, 0: TP port with all capability with NWAY (default). It is internally pulled low 102 FORCE_100 IPL See the note. FORCE _100, to select TP port with 100M or 10M capability 1: TP port can be linked at 100M only, 0: TP port can be linked at 10M only (default). IPL See the note. FORCE _FULL, to select TP port with full or half duplex capability 1: TP port can be linked full or half duplex, 0: TP port can be linked at half duplex only (default). It is internally pulled low 107 FORCE _FULL It is internally pulled low See the note. Note: IP113 TP port force mode function can be active, only if the following conditions exist: Pin 98 MODE = 1’b0, Pin 103, 104 OP[1:0] = 2’b11, Pin 70 TP_FORCE = 1’b1 Please see page 16 for detail information. ALLPASS 91 IPL ALLPASS 1: IP113 forwards all packets without hashing. 0: IP113 forwards packets depending on hashing table (default). This pin should be connected to VCC through resistor for normal operation 57 LFP IPL Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Link fault pass through (LFP) 1: enable Link status of one port is forwarded to the other port. It uses the same pin as Test_isram[0]. 0: disable (default) It is internally pulled low 8 IP113 PIN Description (continued) Pin no. Testing Pins 54,55 56,57 Label Type TEST1, TEST2 IPL TEST_ISRAM[1:0] IPL 83 TSM I 84 TSE I 1-3,7-9,11,12, 27-29,31,32, 60-72,75,76,87, 120,121, 123,125,126 Misc. 85 112 113 Power 5,25,43 10,20,30,37,127 14 49,50,53,58,79, 110,117,118 114 73 94 100 4,6,24,26,42 13,17,33,34,38, 124,128 16 44,46,48,51,52, 59,80,115, 116,119,122 111 74 95 101 NC Test mode selection They are internally pulled low. They are recommended to be connected to GND for normal operation Test internal SRAM It is valid to test internal SRAM only if both TEST1 and TEST0 are set to logic high. They are internally pulled low. Scan mode It is connected to GND in application circuit. Scan enable It is connected to GND in application circuit. No connection They should be left open for normal operation. RESETB X2 OSCI(X1) I O I Reset, low active Crystal pin 25M system clock input VCC VCC VCC VCC I I I I Tx VCC of analog circuit Rx VCC of analog circuit Band gap VCC of analog circuit VCC of digital core VCC VCC_IO_2 VCC_SRAM VCC_IO_1 GND GND I I I I I I VCC of crystal VCC of digital I/O buffer VCC of SRAM VCC of digital I/O buffer Tx GND of analog circuit Rx GND of analog circuit GND GND I I Band gap GND of analog circuit GND of digital core GND GND_IO_2 GND_SRAM GND_IO_1 I I I I GND of crystal GND of digital I/O buffer GND of SRAM GND of digital I/O buffer Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Description 9 IP113 PIN Description (continued) Functional Description Basic Operation internal memory through memory interface unit. Transmit IP113 consists of two switching ports. Full/half duplex MAC and receive MAC interface to transceivers and and speed of TP port depends on the result of auto implement Ethernet protocol. negotiation. It is not necessary to use an external Receive MAC receives the incoming data from memory to buffer packets. transceiver and converts nibble data into double word Each port in IP113 has its own receive buffer data. As a 32 bit data is ready, it feeds the data into management, transmit buffer management, transmit receive FIFO and requests receive buffer management queue management, transmit MAC and receive MAC. All ports share a hashing unit, a memory interface unit, an for data transfer. When receive buffer management receives the request, it gets a empty block from empty empty buffer management, and an address table. buffer management and writes the double word data to the buffer, which is located in the internal SSRAM, An incoming packet is stored in the internal memory if through memory interface unit. The incoming packet is the packet is error free. A packet is error free if its CRC fed to hashing unit at the same time. Hashing unit field is correct and its length is between 64 and 1536 byte. At the same time, IP113 examines the address field extracts the source address of incoming packet to set up an address table. An incoming packet is dropped or of the packet. By the way, switch learns the locations of forwarded according to the table. The address table is every station (source address) and records them on the built in the SSRAM of IP113. address table. IP113 then reads the packet from the internal memory and sends it to the other ports according to the address table. Eventually, IP113 supports the All ports share an empty buffer management. After reset, the empty buffer management provides 2 addresses of switching function by dropping or forwarding the empty blocks. When a packet comes in, it searches for a incoming packets. new empty block. After a packet is forwarded, the corresponding blocks are released. Empty buffer Block Description The basic function of each block in the block diagram is management treats the block as an empty block and illustrated in the following context. Hashing unit is provides its address to desired receive buffer responsible to learn and to recognize address. Transmit management. Two addresses are always ready for buffer management and receive buffer management are receive buffer management. responsible to store data to or to read data from the Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 10 IP113 Back off Algorithm Backpressure IP113 provides three parameters to modify its back off The backpressure is used for flow control in half duplex algorithm. They are Modbck, Twopart and NoDrop16. mode if Bk_en is turned on. When the buffer of a port is IP113 implements the IEEE802.3 standard binary full, it will start to send jam signals. The remote station exponential back off algorithm (Modbck=0) and modified will defer transmission after detecting the jam signals. back off algorithm (Modbck=1) when it works at half IP113 support two types of backpresure, collision base duplex mode. If Modbck is set, the maximum back off (Bp_kind =2’b10) and carrier base (Bp_kind=2’b00). time is limited to eight-slot time. The minimum defer time is separated into the two periods. The first period Collision based backpressure is sent by IP113, only nd consists of the first 64-bit time and the 2 period when the buffer of a port is full and it receives a packet. consists of the rest 32 bit-time. In the case of minimum IP113 stops sending backpressure packet when the defer time IP113 transmits a packet after 96-bit time remote station is idle. The definition of buffer full for nd immediately in spite of the status of cable on the 2 collision base backpressure is there is no empty buffer period if Twopart is set. After 16 consecutive collisions, for incoming packets. the transmitting packet is dropped if NoDrop16 is reset. Carrier based backpressure is sent by IP113, when the Operation Parameter buffer of a port is full. IP113 sends jam packets IP113 supports many optional functions. They can be continuously to defer the remote station. The length of configured to fit different requirements by setting jam packet is 1518 byte and the IPG is equal to 96-bit appropriate parameters. These parameters can be fed time. If the port has packets to transmit during this period, into IP113 through EEPROM interface or through pins. it transmits the queuing packet instead of the jam packets. After the queuing packets are transmitted, IP113 Flow Control resumes to jam the segment by sending jam packets if IP113 provides two mode of flow control. Backpressure the buffer of a port is full. If a collision occurs, the back is for half duplex mode and IEEE802.3x flow control is off algorithm is skipped and the jam packets are for full duplex. generated immediately. The definition of buffer full for carrier base backpressure is there is only one empty buffer for a port. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 11 IP113 IEEE 802.3x The IEEE 802.3x is used for flow control in full duplex with maximum delay to ensure the pause timer of the mode if both IP113 (X_en=1) and the remote station remote station does not expire and begins transmission. have IEEE802.3x capability. When the level of occupied The IPG between PAUSE frames is 42ms(100M) or buffer of a port is over set threshold, it will send a 420ms(10M). PAUSE frame with maximum delay FFFF. The remote station will stop to transmit the next packet after When an incoming PAUSE frame with non-zero delay is receiving the PAUSE frame. After level of the occupied received, the port stops the next frame transmission and buffer is below release threshold, the port sends out a starts its pause timer. It is re-enabled transmission PAUSE frame with zero delay to resume receiving the function either the pause timer is expired or a PAUSE incoming packets. The remote station is re-enable to frame with zero delay is received. If another pause frame transmit packets after receiving the PAUSE frame with is received before the timer expires, the timer will be zero delay. While level of the occupied buffer of a port is updated with the new value. During this period, only over set threshold, IP113 re-transmits the PAUSE frame PAUSE frame from IP113 will be transmitted. PAUSE Frame Format Destination 01-80-C2-00-00-01 6 bytes Source SA 6 bytes Type 8808 2 bytes Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Opcode 0001 2bytes 12 Pause Timer Pad FFFF(0000) PAD with zero 2 bytes 42 bytes CRC CRC 4 bytes IP113 Capability Changing If the remote station does not support IEEE802.3x and To do this, the port keeps silence to force the remote has full duplex capability, IP113 supports a private node link failure and changes its capability to half duplex mechanism to handle flow control to prevent packet loss. then restarts Nway. Both side of the segment will be link It is called capability changing and is controlled by the at half duplex. parameter Update_r4_en. When the remote station does not support IEEE802.3x When the remote station does not support IEEE802.3x and has full duplex capability and Update_r4_en is and has full duplex capability and Update_r4_en is turned off, the port turns off its IEEE802.3x capability and turned on, the port changes its ability to half duplex to is link at full duplex after Nway. There is no flow control make the remote station link at half duplex after Nway. between these two nodes in this application. The detail IP113 handles the data flow of segment by backpressure. operation is illustrated in the following table. X_EN x x 1 0 1 0 1 0 1 0 REMOTE_IEEE 802.3X x x 1 1 0 0 1 1 0 0 Conditions UPDATE_ R4_E x x 0 0 0 0 1 1 1 1 Result BK_EN Remote site My site Remote site My site My My back 802.3x pressure 0 half X half half off off 1 half X half half off on x full/half full/half full full on off x full/half full/half full full off off x full/half full/half full full off off x full/half full/half full full off off x full/half full/half full full on off x full/half full/half half half off on x full/half full/half half half off on x full/half full/half half half off on Aging Broadcast Storm Protection IP113 support address aging and buffer aging. If the IP113 is able to prevent receiving too many broadcast address aging is enabled, the learned SA will be cleared packets to waste the switch resource. IP113 discards the if it is not refreshed within the specified aging time (300 incoming broadcast packets depending on the setting of seconds). Bf_stm_en if the number of broadcast packets from a port exceeds threshold. The threshold can be set by writing Bq_hwm_0_sel[1:0]. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 13 IP113 Link Fault Pass Through Initial Value Set Via Pins IP113 supports link fault pass through in TX/FX converter To set the parameter via pins, connect them to vcc or application. This function is enabled if pin 57(LFP) is tied ground through resistors. IP113 reads initial value via to VCC. When IP113 works at this mode, port 0 is a TP pins during the period of reset. An initial value is set to port with auto-negotiation capability and port 1 is a fiber 1’b1 (1’b0) by connecting a pin to vcc (gnd) through a port. Link status on one port is propagated to the other 10kΩ (1kΩ) resistor as shown on the following figure. port to notice the remote nodes. The function begins after the internal PLL clock active. To make sure the proper operation of PLL, the duration of If TP port is unplugged, IP113 stops transmission on fiber reset must be no less than 1 ms. When there is no port. This causes the remote fiber node link fails. LED setting resistor, IP113 uses the default value. shows link failure on both TP port and fiber port. If fiber link fails, IP113 restarts auto-negotiation on TP port but IP113 reads initial setting via pins during the period of always stays in the link failure state. This causes the reset. At reset, these pins are input signals and IP113 remote TP node link fails. LED shows link failure on both reads the initial value. After reset, LED pins become TP port and fiber port. output signals and show LED functions at normal mode. The application circuit is shown below. LED and Initial Value Setting 2.5V 2.5V IP113 supports two ways to modify its initial values of operation parameters to fit different applications. It read LED PIN 220 10K LED PIN 220 the initial value via pins or EPROM interface. 1K To set initial value = 1 with pull up 10K ohm resister 2.5V LED PIN 220 To use default value (use no resistor to leave it open) Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 14 To set initial value = 0 with pull down 1K ohm resister IP113 EEPROM Interface During reset, IP113 sets the default value for each bit. IP113 will stop reading the content of an EEPROM if After reset, IP113 latches the setting on pins at the end there is no specific pattern 55AA read in the register 0. of reset and begins to read the content in the EEPROM. After IP113 read the EEPROM, the EEPROM pins The data in EEPROM is valid only if there is a specific (BP_KIND and LED_SEL) are kept in input mode. pattern 55AA read in the register 0. If there is no EEPROM, IP113 keeps the value read from resistors All fields in EEPROM corresponding to the registers of setting. IP113 is still in reset state before finishing IP113 should be filled with correct value if an EEPROM EEPROM reading. is used. Because the default value in IP113 will be replaced with the content in EEPROM if it is valid. IP113 uses a 93C46 EEPROM device. The detail operation is illustrated in the following figure. RESETB Internal Reset Internal PLL clock >10us Power On Latch setting on pins Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 15 Update setting with the content of EEPROM (Finish reading EEPROM) IP113 TP port force limited capability mode TP port of IP113 can be forced to be limited capability with Note: auto-negotiation by programming pin 70, 102 and 107. This IP113 TP port force mode function is enabled only if the makes IP113 link at limited speed or duplex. The force mode following conditions exist: can be enabled only if the op mode setting is correct (see Note). Pin 98 MODE = 1’b0, Otherwise, TP port performs auto-negotiation with all capability. Pin 103, 104 OP[1:0] = 2’b11, The detail behavior is illustrated in the following table. Pin 70 TP_FORCE = 1’b When force mode is enabled, users have to check the setting All pass function to make sure the traffic ok. IP113 disables its hashing mechanism and forwards all good packets, if pin 91 ALLPASS is pulled up. This function should be turned on for normal operation. A summary of TP port force mode Remote node’s capability TP_force TP_force_100 TP_force_full IP113 TP’s capability (pin 102) (pin 107) Speed Duplex Nway (pin 70) Speed Duplex Nway X X Yes 0 X X 100M/ Full/ Yes 10M Half 100M Full Yes 1 1 1 100M Full/ Half Yes 100M Half Yes 1 1 1 100M Full/ Half Yes 100M Full No 1 1 1 100M Full/ Half Yes 100M Half No 1 1 1 100M Full/ Half Yes 100M Full Yes 1 1 0 100M Half Yes 100M Half Yes 1 1 0 100M Half Yes 100M Full No 1 1 0 100M Half Yes 100M Half No 1 1 0 100M Half Yes 10M Full Yes 1 0 1 10M Full/ Half Yes 10M Half Yes 1 0 1 10M Full/ Half Yes 10M Full No 1 0 1 10M Full/ Half Yes 10M Half No 1 0 1 10M Full/ Half Yes 10M Full Yes 1 0 0 10M Half Yes 10M Half Yes 1 0 0 10M Half Yes 10M Full No 1 0 0 10M Half Yes 10M Half No 1 0 0 10M Half Yes X means “don’t care”. Fail means “packet loss”. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 16 Link result IP113 Remote The remote node’s capability 100M/ Full 100M/ Full 100M/ Full 100M/ Half 100M/ Full 100M/ Full 100M/ Full 100M/ Half Link fails 100M/ Half 100M/ Half 100M/ Half 100M/ Full 100M/ Half 100M/ Half 10M/ Full 10M/ Full 10M/ Full 10M/ Half 10M/ Full 10M/ Full 10M/ Full 10M/ Half Link fails 10M/ Half 10M/ Half 10M/ Half 10M/ Full 10M/ Half 10M/ Half Traffic Ok Ok Fail Ok Fail Fail Ok Fail Ok Ok Fail Ok Fail Fail Ok Fail Ok IP113 EEPROM Register Description Offset 00H[15:0] Default Value 55AA Corresponding Pin - LED output selection register 01H[15:2] 14’b0 01H[1:0] 11 LED_SEL[1:0] Description EEEPROM enable register This register should be filled with 55AA. IP113 will check the specified pattern to confirm a valid EEPROM exists. The initial setting is updated after power on reset only if the specified pattern 55AA is found. Reserved LED_SEL, LED mode selection LED_SEL[1:0]=2’b00: LED mode 0, LED_SEL[1:0]=2’b01: LED mode 1, LED_SEL[1:0]=2’b10: LED mode 2, LED_SEL[1:0]=2’b11: LED mode 3 Please refer to pin description for detail LED definition. Switch control register 1 02H[15:13] 3’b0 02H[12:11] 00 BP_KIND[1:0] 02H[10] 02H[8] 02H[7] 0 0 1 X_EN 02H[6:5] 02H[4] 2’b0 1 BK_EN 0 0 BF_STM_EN (LED_ACT[0]) 2’b0 - 02H[3] 02H[2] 02H[1:0] Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Reserved BP_KIND, Backpressure type selection It is valid only if Bk_en (02H[4]) is set to 1’b1. 00: carrier base backpressure 01: collision base backpressure with hashing 10: collision base backpressure without hashing Reserved Reserved X_EN, IEEE 802.3x flow control enable 1: enable 0:disable Reserved BK_EN, Backpressure enable 1: enable, 0: disable Reserved Broadcast storm enable 1: enable Drop the incoming packet if the number of queued broadcast packet is over the threshold. The threshold is defined in register 0AH[14:13]. 0: disable Reserved 17 IP113 EEPROM Register Description (continued) Offset Default Value Switch control register 2 03H[15:10] 6’b0 03H[8] 0 03H[7] 1 Corresponding Pin Description Nodrop16 (LED_LINK[0]) Reserved Reserved No drop16, A port will drop the transmitting packet after 16 consecutive collisions if this function is turned on. 1: do not drop 0: drop AGING, enable address aging timer An address tag in hashing table will be dropped if this function is turned on and its aging timer (300 seconds) expires. TWOPART, Turn on twopartD IP113 examine the carrier for 64 bits only during its back off period if this function is enabled. It makes IP113 have higher priority in a collision event. 1: turn on 0: turn off MODBCK, Turn on modified back off algorithm IP113 uses modified (aggressive) back off algorithm if this function is enabled. The maximum back off period is limited to 8-slot time. It makes IP113 have higher priority in a collision event. 1: turn on 0: turn off Reserved 03H[4] 1 AGING (LED_LINK[0]) 03H[2] 1 TWOPART 03H[1] 1 MODBCK 03H[0] 0 - Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 18 IP113 EEPROM Register Description (continued) Offset Default Value Corresponding Pin Transceiver control register 04H[15:14] 00 04H[13:11] 110 OP[1:0], MODE Description Reserved OP and MODE, Bit[13:11] are corresponding to op[1:0] and mode. The default value must be adopted for normal operation. 04H[9] 04H[8] 04H[7:0] 1 0 0000 0000 - Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. 19 IP113 EEPROM Register Description (continued) Offset Default Value Corresponding Pin Transceiver verification register 05H[15:14] 2’b0 05H[13] 0 05H[12] 0 UPDATE_R4_EN 05H[11] 05H[10] 05H[9] 05H[8] 05H[7:6] 05H[5] 05H[4] 05H[3] 05H[2] 05H[1] 0 0 0 0 00 0 0 0 0 0 05H[0] 0 Testing & verify mode register 06H[15:7] 9’b0 06H[6] 0 06H[5:0] 6’b0 07H[15:14] 2’b0 07H[13:10] 4’b0 07H[7:0] 8’h77 08H[15] 08H[14:8] 08H[7] 08H[6:0] 09H[15] 09H[14:8] 09H[7] 09H[6:0] 0 7’h30 0 7’h60 0 7’h30 0 7’h50 BPSCR (LED_LINK[1]) - - Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Description Reserved The default value must be adopted for normal operation. UPDATE_R4_EN, Change capability enable A full duplex port will change its capability to half duplex, if the remote full duplex port does not support 802.3x and this function is enable. 1: enable 0: disable The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. BYSCR_MODE, Bypass scrambler 1: bypass 0: not bypass The default value must be adopted for normal operation. The default value must be adopted for normal operation. Reserved The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. Reserved MAX_USE_THR, Input queue threshold An incoming packet will be dropped if the number of packet queued in a port is over the input queue threshold. This function is always active in spite of if there is flow control or not. It is usually higher than the threshold for flow control. It is recommended to adopt the default value. Reserved BCKP_THR_RLS, Backpressure off threshold Reserved BCKP_THR, Backpressure on threshold Reserved X802_3_THR_RLS, 802.3x off threshold Reserved X802_3_THR, 802.3x on threshold 20 IP113 EEPROM Register Description (continued) Offset Default Value Corresponding Pin Testing & verify mode register (continued) 0AH[15] 0 0AH[14:13] 11 - 0AH[12:11] 0AH[10:0] 2’b0 11’d128 - 0BH[14:10] 0BH[9:5] 0BH[4:0] NA NA 5’b0 5’b0 5’b0 0 0 - Description Reserved BQ_HWM_0_SEL, BQ_HWM_0_SEL, Broadcast Queue high water mark threshold selection. IP113 will drop the incoming broadcast packet if the broadcast packet count exceeds the threshold. If (register 02H[2]: bf_stm_en==1), its corresponding threshold is 00:1024, 01:256, 10:128, 11:48, If (register 02H[2]: bf_stm_en==0), the function is disabled. Reserved OQ_THR, Output Queue threshold An incoming packet will be dropped if the number of packet queued in destination port is over the output queue threshold. IP113 enables this function automatically only if there is no flow control. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 21 IP113 A summary of EEPROM Registers and Their Corresponding Pins Offset 00H[15:0] 01H[1:0] 02H[12:11] 02H[7] 02H[4] 02H[3] 02H[2] 03H[7] 03H[4] 03H[2] 03H[1] 04H[15] 04H[14] 04H[13] 04H[12] 04H[11] 04H[10] 04H[9] 04H[8] 04H[7:0] 05H[13] 05H[12] 05H[11] 05H[10] 05H[9] 05H[8] 05H[7:6] 05H[5] 05H[4] 05H[3] 05H[2] 05H[1] 05H[0] 06H[6] 06H[5] 06H[4] 06H[3] 06H[2] 06H[1] 06H[0] Default Value 55AA 11 00 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 8’b0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 Corresponding Pin LED_SEL BP_KIND X_EN BK_EN LED_ACT[0] LED_LINK[0] AGING TWOPART MODBCK OP[1] OP[0] LED_FULL[0] LED_FULL[1] BP_KIND[1] R4_EN BP_KIND[0] LED_LINK[1] LED_ACT[1] - Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 22 Normal X_EN BK_EN BF_STM_EN NODROP16 AGING TWOPART MODBCK OP[1] OP[0] MODE FIBER_HALF UPDATE_R4_EN BPSCR - Register Content LED_SEL BP_KINK X_EN BK_EN BF_STM_EN NO DROP16 AGING TWOPART MODBCK OP[1] OP[0] MODE FIBER_HALF UPDATE_R4_EN BYSCR_MODE - IP113 A summary of EEPROM Registers and Their Corresponding Pins (continued) Offset 07H[15:14] 07H[7:0] 08H[14:8] 08H[6:0] 09H[14:8] 09H[6:0] 0AH[14:13] 0AH[10:0] 0BH[14:10] 0BH[9:5] 0BH[4:0] 0CH[15] 0CH[14] 0CH[11:10] 0DH[15] 0DH[14] 0DH[13] 0DH[12] 0DH[11] 0DH[10] 0DH[7] 0DH[6] 0DH[5] 0DH[4] 0DH[3] 0DH[2] 0DH[1] 0DH[0] NA NA Default Value 2’b0 8’h77 7’h30 7’h60 7’h30 7’h50 11 11’d128 5’b0 5’b0 5’b0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Corresponding Pin - Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 23 Normal - Register Content MAX_USE_THR BCKP_THR_RLS BCKP_THR X802_3_THR_RLS X802_3_THR BQ_HWM_0_SEL OQ_THR - IP113 AC Characteristic Read EEPROM EESK tCS tSK EECS tDI EEDI 1 1 0 A5 A4 A0 tOD EEDO Parameter TSK TCS TDI TOD 0 Description Clock period Chip select delay Data input delay Output delay Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Min - 24 D15 D14 D0 Typical 5.12 - Max 2 2 2000 Units us ns ns ns IP113 Absolute Maximum Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage –0.3V to 4.0V Input Voltage –0.3V to 5.0V Output Voltage –0.3V to 5.0V Storage Temperature -65°C to 150°C Ambient Operating Temperature (Ta) 0°C to 70°C DC Characteristic Operating Conditions Parameter Supply Voltage Power Consumption Sym. VCC2.5 TXVCC - Min. 2.375 2.375 - Typ. 2.5 2.5 1.3 Max. 2.625 2.625 - Unit V V W Conditions Sym. - Min. -50 Typ. 25 - Max. +50 Unit MHz PPM Conditions Sym. VIL VIH VOL VOH VIH VIL Min. 2.0 2.4 1.35 - Typ. - Max. 0.8 0.4 1.2 Unit V V V V V V Conditions Input Clock Parameter Frequency Frequency Tolerance I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High voltage FXSD0~1 signal detect IOH=4mA, VCC=3.3V IOL=4mA, VCC=3.3V TX Transceiver Electrical Characteristics Parameter Peak Differential Output Voltage Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot Sym. VP TRF TRFS VO Min. 0.95 98 3 - Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 Typ. 1.0 100 4 - 25 Max. 1.05 102 5 0.5 0.5 5 Unit V % ns ns ns % Conditions IP113 Thermal Data Parameter Thermal resistance: junction to ambient 0 m/sec air flow Thermal resistance: junction to ambient 0 m/sec air flow Symbol θja Conditions 4 layer PCB, ambient temperature 70℃ θjc 4 layer PCB, ambient temperature 70℃ Min 9.0 Order Information Part No. IP113 PIN 128 PIN PQFP Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 26 Typical 20.8 Notice - Max Units °C/W °C/W IP113 Package Detail QFP 128L Outline Dimensions Unit: Inches/mm HD D 103 128 E HE 102 1 65 38 39 64 e b L A1 c A2 GAGE PLANE D L1 Symbol y Dimensions In Inches Dimensions In mm Min. Nom. Max. Min. Nom. Max. A1 0.010 0.014 0.018 0.25 0.35 0.45 A2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c HD 0.004 0.006 0.008 0.09 0.15 0.20 0.669 0.677 0.685 17.00 17.20 17.40 D 0.547 0.551 0.555 13.90 14.00 14.10 HE 0.906 0.913 0.921 23.00 23.20 23.40 E 0.783 0.787 0.791 19.90 20.00 20.10 e - 0.020 - - 0.50 - L 0.025 0.035 0.041 0.65 0.88 1.03 L1 - 0.063 - - 1.60 - y - - 0.004 - - 0.10 θ 0° - 12° 0° - 12° Note: 1. Dimension D & E do not include mold protrusion. 2. Dimension B does not include dambar protrusion. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Preliminary, Specification subject to change without notice IP113-DS-P07 Jul. 19, 2002 27