IP175
5 Port 10/100 Ethernet Integrated Switch
Feature
Utilize single clock source only (25Mhz)
5 port 10/100 Ethernet switch with built in transceivers
Utilize single power (2.5v)
and memory
0.25um technology
Build in SSRAM for frame buffer
Packaged in 128 pin PQFP
Built in storage of 1K MAC address
Support flow control
General Description
- Support IEEE802.3x for flow control on full duplex
IP175 is a 5 port 10/100 Ethernet integrated switch. It
mode operation
consists of a 5-port switch controller and five Fast
- Support back pressure for flow control in half duplex
Ethernet transceivers. Each of the transceivers complies
mode operation
with the IEEE802.3, IEEE802.3u, and IEEE802.3x
A 5 port switching fabric
specifications. The transceivers in IP175 are designed in
- Support two-level hashing algorithm to solve address
DSP approach with advance 0.25um technology; this
collision
results in high noise immunity and robust performance.
- Support address aging
- Store and forward mode
The IP175 operates in store and forward mode. It stores
- Broadcast storm protection
the incoming packet to the internal SSRAM and learns
- Full line speed capability of 148800 (14880)
the SA (source address) automatically if the packet is
packets/sec for 100M (10M)
error free. The SA is stored in the internal address table.
- Support 1536 byte data transfer for VLAN traffic
IP175 forwards a packet according to DA destination
Integrate 5 ports transceiver
address and address table. When the segments of
- Auto negotiation
destination ports are free, it reads the packet from the
- Fully digital adaptive equalizer and timing recovery
internal SSRAM and forwards it to the appropriate ports
module
according to the address table. The incoming packets
- Base line Wander correction
with errors are dropped. IP175 supports IEEE802.3x,
- 10BaseTX, 100BaseTX, and 100BaseFX operation
optional backpressure, and various LED functions, etc.
Support one MII port for router application
These functions can be configured to fit the different
LED status of Link, activity, Full/half duplex, and speed
requirements by feeding operation parameters via
LED with power on diagnostic function
EEPROM interface or pull up/down resistors on specified
Initial parameter setting by pin configuration or
pins.
EEPROM
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
1
IP175
Block Diagram
Address
Table
RxMAC
Rx Buffer Mgnt
10/100BASE-T
Transceiver
with N-WAY
Hashing
Unit
(x5)
Memory
I/F Unit
TxMAC
(x5)
Empty
Buffer
Mgnt
Tx Buffer Mgnt
Queue Mgnt
(x5)
EEPROM
Interface
LED
Controller
Two Applications of IP175
WAN
ARM
( MII )
IP175
IP175
5X Transformer
4X Transformer
A 5 port SOHO Ethernet Switch port
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
A 4 port Ethernet Switch + One WAN
2
SSRAM
Packet
Buffer
IP175
AOUT_MCLK
FXSD0
P4EXT_FULL
P4EXT_SPEED
GND
VCC
VCC
GND
GND
VCC
OSCI (X1)
X2
GND
VCC
LED_SPEED[4]
LED_FULL[4]
LED_ACT[4]
LED_LINK[4]
LED_SPEED[3]
LED_FULL[3]
LED_ACT[3]
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
RXIP0
GND
RXIM0
126
124
VCC
127
125
GND
128
PIN Assignments
VREF0
1
102
LED_LINK[3]
TXOP0
2
101
GND_IO_1
TXOM0
3
100
VCC_IO_1
GND
4
99
LED_SPEED[2]
VCC
5
98
LED_FULL[2]
GND
6
97
LED_ACT[2]
TXOP1
7
96
LED_LINK[2]
95
GND_SRAM
TXOM1
8
VREF1
9
94
VCC_SRAM
VCC
10
93
LED_SPEED[1]
RXIP1
11
92
LED_FULL[1]
RXIM1
12
91
LED_ACT[1]
GND
13
90
LED_LINK[1]
VCC
14
89
LED_SPEED[0]
BGRES
15
88
LED_FULL[0]
GND
16
87
LED_ACT[0]
86
LED_LINK[0]
GND
17
RXIP2
18
85
RESETB
RXIM2
19
84
TSE
IP175
65
MTXER
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
64
38
MTXD0
MII_CLK
GND
63
66
MTXD1
37
62
MRXDV
VCC
MTXD2
67
MTXD3
36
61
MRXD3
RXIM4
60
RXIP4
68
MTXEN
MRXD2
35
59
69
GND
34
58
MRXD1
GND
VCC
70
57
33
TEST_ISRAM[0]
MRXD0
GND
56
71
TEST_ISRAM[1]
32
55
MCOL
RXIM3
TEST2
72
54
31
TEST1
VCC_IO_2
RXIP3
53
73
VCC
30
GND
GND_IO_2
VCC
52
74
51
29
GND
P4EXT
VREF3
50
75
49
28
VCC
NC
TXOM3
VCC
76
48
27
GND
BP_KIND[1]
TXOP3
47
77
46
26
FXSD3
BP_KIND[0]
GND
FXSD4
VCC
78
45
79
25
44
24
VCC
FXSD1
GND
FXSD2
GND
VCC
80
43
23
42
LED_SEL[1]
TXOM2
GND
81
41
22
TXOM4
LED_SEL[0]
TXOP2
40
TSM
82
39
83
VREF4
20
21
TXOP4
VCC
VREF2
3
IP175
PIN Description
Type
I
O
O
IPL
Pin no.
MLT3 Signals
1,9,21,29,39
2,7,22,27,40,
3,8,23,28,41
15
122,44-47
Description
Used as Input pin
Used as Output pin
Used as Output with Open Drain
Input pin with pull-low resistor
Label
Type
Description
VREF0~4
TXOP0~4
TXOM0~4
BGRES
O
O
Reference voltage for transmit transformer center tap
TP transmit
O
FXSD0~4
I
Band gap resister
It is connected to GND through a 6.19k (1%) resistor in
application circuit
100Base-FX signal detect
It must be connected to ground to select TX mode.
TP receive
125,11,18,31,35, RXIP0~4
126,12,19,32,36 RXIM0~4
LED Normal Output Mode
81,82
LED_SEL[1:0]
I
IPH
LED output mode selection
They are latched at the end of reset to select the LED output
mode
LED_SEL[1:0]=2’b00: LED mode 0,
LED_SEL[1:0]=2’b01: LED mode 1,
LED_SEL[1:0]=2’b10: LED mode 2,
LED_SEL[1:0]=2’b11: LED mode 3 (default)
After reset, IP175 reads EEPROM with LED_SEL[1:0], which
works as EECS and EESK. These two pins are output signals
during reading EEPROM. After finishing reading EEPROM,
these two pins becomes input signal to isolate IP175 from
EEPROM
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
4
IP175
PIN Description (continued)
Pin no.
Label
LED Normal Output Mode (continued)
106,102, 96
LED_LINK[4:0]
90,86
Type
Description
O
Link, Activity (output after reset)
LED mode0: Link+Activity
(off: Link fail, on:Link ok and no activity,
flash: Link ok and TX/RX activity)
LED mode1: Receive activity
(off: not receiving, flash: receiving)
LED mode2: Tx/Rx Activity
(off: no activity, flash: TX or RX activity)
107,103,97,91,87 LED_ACT[4:0]
LED mode3: Link+Activity
(off: Link fail, on:Link ok and no activity,
flash: Link ok and TX/RX activity)
Full/half, Collision, Tx activity (output after reset)
LED mode0: Collision
(off: no collision, flash: when collision happens)
O
LED mode1: Tx activity
(1: no TX activity, flash: when TX activity happens)
LED mode2, 3: Full+collision
(1: half without collision, 0: full, flash: collision)
108,104,98,92,88 LED_FULL[4:0]
O
Full/half, Link (output after reset)
LED mode0, Full/half: (off: half, on: full)
LED mode1, Link: (off: Link fail, on: Link ok)
LED mode2, Link: (off: Link fail, on: Link ok)
LED mode3: same as mode 0
109,105,99,93,89 LED_SPEED[4:0]
O
Speed (output after reset)
LED mode0: (off: speed=10M, on: speed=100M)
LED mode1: (off: speed=10M, on: speed=100M)
LED mode2: (off: speed=10M, on: speed=100M)
LED mode3: (off: speed=10M, on: speed=100M)
Note: Please refer to the paragraph of “LED display” for information about Flash and ON
LED pins used as initial setting mode during reset
Note: Please refer to the paragraph of Initial Value Set Via Pins for detail information about pull high/ low setting.
86
LED_LINK[0]
IPH IEEE 802.3X enable (X_en) on all ports
1: enable (default),
0: disable
92
LED_FULL[1]
IPH
It is internally pulled high.
Backpressure enable (BK_EN)
1: enable (default),
0: disable
This pin doesn’t set the flow control of external MII port
It is internally pulled high.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
5
IP175
PIN Description (continued)
Pin no.
Label
Type
Description
LED pins used as initial setting mode during reset (continued)
90
LED_LINK[1]
IPH
88
LED_FULL[0]
IPL
98
99
102
103
104
LED_FULL[2]
LED_SPEED[2]
LED_LINK[3]
LED_ACT[3]
LED_FULL[3]
IPL
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Address aging enable
1: enable, aging time 300s (default),
0: disable
It is internally pulled high.
Change capability enable (Update_r4_en)
A full duplex port will change its capability to half duplex, if the
remote full duplex port does not support IEEE802.3x and this
function is enabled.
1: enable, 0: disable (default)
This pin doesn’t control the flow control of external MII port.
It is internally pulled low.
OP mode setting
It decides a port to work with nway or in force mode
force_mode = LED_FULL[2],
op1[1:0] = { LED_SPEED[2], LED_LINK[3] },
op0[1:0] = {LED_ACT [3], LED_FULL[3]}
The default value is 5’b0
They are internally pulled low.
Summary
op1 op0 force_
Description
[1:0] [1:0] mode
0 0 x
0
Port1,3 nway with all capability
0 1 x
0
Port1,3 half duplex only
1 0 x
0
Port1,3 nway with all capability
1 1 x
0
Port1,3 nway with all capability
0 0 x
1
Port1,3 force 100M full duplex
0 1 x
1
Port1,3 force 100M half duplex
1 0 x
1
Port1,3 force 10M full duplex
1 1 x
1
Port1,3 force 10M half duplex
x 0 0
0
Port0,2,4 nway with all capability
x 0 1
0
Port0,2,4 half duplex only
x 1 0
0
Port0,2,4 nway with all capability
x 1 1
0
Port0, 2 nway, Port 4 FX
x 0 0
1
Port0,2,4 force 100M full duplex
x 0 1
1
Port0,2,4 force 100M half duplex
x 1 0
1
Port0,2,4 force 10M full duplex
x 1 1
1
Port0,2,4 force 10M half duplex
6
IP175
PIN Description (continued)
Pin no.
Label
Type
Description
LED pins used as initial setting mode during reset (continued)
77,78
BP_KIND[1:0]
IPL
Backpressure type selection
Bp_kind[1:0] are valid only if Bk_en is set to high.
00: carrier base backpressure (default)
01: collision base backpressure with hashing
10: collision base backpressure without hashing
After reset, IP175 reads EEPROM with BP_KIND[1:0], which
works as EEDO and EEDI. BP_KIND[1] is an input signal and
BP_KIND[0] is an output signal during reading EEPROM. After
finishing reading EEPROM, these two pins becomes input
signal to isolate IP175 from EEPROM
105
93
LED_SPEED[3]
LED_SPEED[1]
IPH
IPH
They are internally pulled low.
Turn on twopartD (Twopart)
IP175 examine the carrier for 64 bits only during its back off
period if this function is enabled. It makes IP175 have higher
priority in a collision event.
1: enable (default), 0: disable
It is internally pulled high.
Aggressive back off enable (MODBCK)
IP175 uses modified (aggressive) back off algorithm if this
function is enabled. The maximum back off period is limited to
8-slot time. It makes IP175 have higher priority in a collision
event.
1: aggressive mode enable (default),
0: standard back off
106
96
LED_LINK[4]
LED_LINK[2]
IPL
IPH
This pin doesn’t affect the external MII port. It is internally
pulled high.
Bypass scrambler (BPSCR_MODE)
1: bypass, 0: not bypass (default)
The default value must be adopted for normal operation.
It is internally pulled low.
Nodrop16 (Drop16*)
1: do not drop after 16 collisions, (default)
0: drop after 16 collision
This pin doesn’t affect the external MII port. It is internally
pulled high.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
7
IP175
PIN Description (continued)
Pin no.
Label
Type
Description
LED pins used as initial setting mode during reset (continued)
97
LED_ACT[2]
IPL
108
LED_FULL[4]
IPL
Broadcast storm protection enable (BF_STM_EN)
1: enable,
0: disable (default)
It is internally pulled low.
FIBER_HALF
1: all fiber port works at half duplex,
0: all fiber port works at full duplex (default)
It is internally pulled low.
External MII control signals
75
P4EXT
I
Port4 external MII enable
1: IP175 works as a 4-TP + 1 MII port switch
MII interface is enabled and is connected to external MAC
device. The MAC data is fed to port4 MII interface of switch
core directly and bypass the internal port4 transceiver
0: IP175 works as a 5-TP port switch
120
P4EXT_SPEED
IPL
121
P4EXT_FULL
IPL
87
LED_ACT[0]
IPL
89
LED_SPEED[0]
IPH
If external MII is enabled, IP175 generates MCOL to external
MAC device when both MRXDV and MTXEN are active and
P4EXT_FULL is set to logic low.
Port4 external MII interface speed selection
1: 10M
0: 100M (default)
It is valid only if P4EXT is set to logic high.
Port4 external MII interface full/half duplex selection
0: half (default)
1: full
It is valid only if P4EXT is set to logic high.
MII_FC_EN, Flow control enable for MII port
1: enable,
0: disable (default)
UTPdet
It is a power saving mode for TP port. TP port will be power
down when the cable is unplugged and the function is enabled.
1: enable (default),
0: disable
It is internally pulled high.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
8
IP175
PIN Description (continued)
Pin no.
Label
Type
Description
Test Pin
54,55
TEST1, TEST2
IPL
56,57
TEST_ISRAM[1:0]
IPL
83
TSM
I
84
TSE
I
123
AOUT_MCLK
85
112
113
RESETB
X2
OSCI(X1)
IPL
Test mode selection
They are internally pulled low. They are recommended to be
connected to GND for normal operation
Test internal SRAM
It is valid to test internal SRAM only if both TEST1 and TEST0
are set to logic high. They are internally pulled low.
Scan mode
It is connected to GND in application circuit.
Scan enable
It is connected to GND in application circuit.
It is used as scan clock.
It is left open in application circuit.
Misc.
I
O
I
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Reset, low active
Crystal pin
25M system clock input
9
IP175
PIN Description (continued)
Pin no.
Label
External MII interface
60
MTXEN
61-64
MTXD[3:0]
65
MTXER
66
MII_CLK
67
Type
I
I
I
O
Description
MTXEN is used to frame NRZ data from external MII device
MTXD is NRZ data from external MAC controller
MTXER is transmit error
MII_CLK is MII interface clock
It is the MIITxclk of switch core and is used as MIITxclk and
MIIRxclk for the external MAC device
MRXDV is used to frame MRXD, which is sent to external
MAC device
MRXD is NRZ data to external MAC device
MCOL is active, only if both MRXDV and MTXEN are both
active and the MII interface is set to be half-duplex
MRXDV
O
MRXD[3:0]
MCOL
O
O
Power
5,25,43
VCC
I
10,20,30,37,127
VCC
I
14
VCC
I
49,50,53,58,79,
110,117,118
114
VCC
I
VCC
I
73
VCC_IO_2
I
94
VCC_SRAM
I
100
VCC_IO_1
I
GND
GND
I
I
Tx VCC of Analog circuit
It is connected to 2.5v.
Rx VCC of Analog circuit
It is connected to 2.5v.
Band gap VCC of Analog circuit
It is connected to 2.5v.
VCC of digital core
It is connected to 2.5v.
VCC of crystal
It is connected to 2.5v.
VCC of digital I/O buffer
It is connected to 2.5v for a dumb switch. It should be
connected to 3.3v if external MII interface is active.
VCC of SRAM
It is connected to 2.5v.
VCC of digital I/O buffer
It is connected to 2.5v for a dumb switch. It should be
connected to 3.3v if external MII interface is active.
Tx GND of Analog circuit
Rx GND of Analog circuit
GND
GND
I
I
Band gap GND of Analog circuit
GND of digital core
GND
GND_IO_2
GND_SRAM
GND_IO_1
I
I
I
I
GND of crystal
GND of digital I/O buffer
GND of SRAM
GND of digital I/O buffer
68-71
72
4,6,24,26,42
13,17,33,34,38,12
4,128
16
48,51,52,59,80,11
5, 116,119
111
74
95
101
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
10
IP175
PIN Description (continued)
A Summary of Multi-Function Pins
Pin no.
121
120
77
78
81
82
89
88
87
86
93
92
91
90
99
98
97
96
105
104
103
102
109
108
107
106
72
71
70
69
68
67
123
65
64
63
62
61
60
75
76
56
Label
P4EXT_FULL
P4EXT_SPEED
BP_KIND[1]
BP_KIND[0]
LED_SEL[1]
LED_SEL[0]
LED_SPEED[0]
LED_FULL [0]
LED_ACT[0]
LED_LINK[0]
LED_SPEED[1]
LED_FULL[1]
LED_ACT[1]
LED_LINK[1]
LED_SPEED[2]
LED_FULL[2]
LED_ACT[2]
LED_LINK[2]
LED_SPEED[3]
LED_FULL[3]
LED_ACT[3]
LED_LINK[3]
LED_SPEED[4]
LED_FULL[4]
LED_ACT [4]
LED_LINK[4]
MCOL
MRXD0
MRXD1
MRXD2
MRXD3
MRXDV
AOUT_MCLK
MTXER
MTXD0
MTXD1
MTXD2
MTXD3
MTXEN
P4EXT
NC
TSET_ISRAM1
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Default
0
0
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
0
0
0
0
0
0
0
-
11
PCB
R1/0
R1/0
0
0
R0
R0
R1
R1
R1
R1
Normal
P4EXT_FULL
P4EXT_SPEED
EEDO
EEDI
EECS
EESK
UTPDET
UPDATE_R4_EN
MII_FC_EN
X_EN
MODBCK
BK_EN
AGING
OP1[1]
FORCE_MODE
BF_STM_EN
NODROP16
TWOPART
OP0[0]
OP0[1]
OP1[0]
NA
FIBER_HALF
BPSCR
0
0
0
0
0
0
0
0
R0
IP175
Functional Description
Basic Operation
internal memory through memory interface unit. Transmit
IP175 consists of five switching ports. Full/half duplex
MAC and receive MAC interface to transceivers and
and speed of each port depends on the result of auto
implement Ethernet protocol.
negotiation of its corresponding transceiver. It is not
Receive MAC receives the incoming data from
necessary to use an external memory to buffer packets.
transceiver and converts nibble data into double word
Each port of IP175 has its own receive buffer
data. As a 32 bit data is ready, it feeds the data into
management, transmit buffer management, transmit
receive FIFO and requests receive buffer management
queue management, transmit MAC and receive MAC. All
ports share a hashing unit, a memory interface unit, an
for data transfer. When receive buffer management
receives the request, it gets a empty block from empty
empty buffer management, and an address table.
buffer management and writes the double word data to
An incoming packet is stored in the internal memory if
the buffer, which is located in the internal SSRAM,
the packet is error free. A packet is error free if its CRC
through memory interface unit. The incoming packet is
field is correct and its length is between 64 and 1536
fed to hashing unit at the same time. Hashing unit
byte. At the same time, IP175 examines the address field
extracts the source address of incoming packet to set up
of the packet. By the way, switch learns the locations of
an address table. An incoming packet is dropped or
every station (source address) and records them on the
forwarded according to the table. The address table is
address table. IP175 then reads the packet from the
built in the SSRAM of IP175.
internal memory and sends it to the appropriate ports
All ports share an empty buffer management. After reset,
according to the address table. Eventually, IP175
the empty buffer management provides 5 addresses of
supports the switching function by dropping or forwarding
the incoming packets.
empty blocks. When a packet comes in, it searches for a
new empty block. After a packet is forwarded, the
corresponding blocks are released. Empty buffer
Block Description
The basic function of each block in the block diagram is
management treats the block as an empty block and
illustrated in the following context. Hashing unit is
provides its address to desired receive buffer
responsible to learn and to recognize address. Transmit
management. Five addresses are always ready for
buffer management and receive buffer management are
receive buffer management.
responsible to store data to or to read data from the
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
12
IP175
Back off Algorithm
Backpressure
IP175 provides three parameters to modify its back off
The backpressure is used for flow control in half duplex
algorithm. They are Modbck, Twopart and NoDrop16.
mode if Bk_en is turned on. When the buffer of a port is
IP175 implements the IEEE802.3 standard binary
full, it will start to send jam signals. The remote station
exponential back off algorithm (Modbck=0) and modified
will defer transmission after detecting the jam signals.
back off algorithm (Modbck=1) when it works at half
IP175 support two types of backpresure, collision base
duplex mode. If Modbck is set, the maximum back off
(Bp_kind =2’b10) and carrier base (Bp_kind=2’b00).
time is limited to eight-slot time. The minimum defer time
is separated into the two periods. The first period
Collision based backpressure is sent by IP175, only
nd
consists of the first 64-bit time and the 2 period
when the buffer of a port is full and it receives a packet.
consists of the rest 32 bit-time. In the case of minimum
IP175 stops sending backpressure packet when the
defer time IP175 transmits a packet after 96-bit time
remote station is idle. The definition of buffer full for
nd
immediately in spite of the status of cable on the 2
collision base backpressure is there is no empty buffer
period if Twopart is set. After 16 consecutive collisions,
for incoming packets.
the transmitting packet is dropped if NoDrop16 is reset.
Carrier based backpressure is sent by IP175, when the
Operation Parameter
buffer of a port is full. IP175 sends jam packets
IP175 supports many optional functions. They can be
continuously to defer the remote station. The length of
configured to fit different requirements by setting
jam packet is 1518 byte and the IPG is equal to 96-bit
appropriate parameters. These parameters can be fed
time. If the port has packets to transmit during this period,
into IP175 through EEPROM interface or through pins.
it transmits the queuing packet instead of the jam
packets. After the queuing packets are transmitted,
Flow Control
IP175 resumes to jam the segment by sending jam
IP175 provides two mode of flow control. Backpressure
packets if the buffer of a port is full. If a collision occurs,
is for half duplex mode and IEEE802.3x flow control is
the back off algorithm is skipped and the jam packets are
for full duplex.
generated immediately. The definition of buffer full for
carrier base backpressure is there is only one empty
buffer for a port.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
13
IP175
IEEE 802.3x
The IEEE 802.3x is used for flow control in full duplex
with maximum delay to ensure the pause timer of the
mode if both IP175 (X_en=1) and the remote station
remote station does not expire and begins transmission.
have IEEE802.3x capability. When the level of occupied
The IPG between PAUSE frames is 42ms(100M) or
buffer of a port is over set threshold, it will send a
420ms(10M).
PAUSE frame with maximum delay FFFF. The remote
station will stop to transmit the next packet after
When an incoming PAUSE frame with non-zero delay is
receiving the PAUSE frame. After level of the occupied
received, the port stops the next frame transmission and
buffer is below release threshold, the port sends out a
starts its pause timer. It is re-enabled transmission
PAUSE frame with zero delay to resume receiving the
function either the pause timer is expired or a PAUSE
incoming packets. The remote station is re-enable to
frame with zero delay is received. If another pause frame
transmit packets after receiving the PAUSE frame with
is received before the timer expires, the timer will be
zero delay. While level of the occupied buffer of a port is
updated with the new value. During this period, only
over set threshold, IP175 re-transmits the PAUSE frame
PAUSE frame from IP175 will be transmitted.
PAUSE Frame Format
Destination
01-80-C2-00-00-01
6 bytes
Source
SA
6 bytes
Type
8808
2 bytes
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Opcode
0001
2bytes
14
Pause Timer
Pad
FFFF(0000) PAD with zero
2 bytes
42 bytes
CRC
CRC
4 bytes
IP175
Capability Changing
If the remote station does not support IEEE802.3x and
To do this, the port keeps silence to force the remote
has full duplex capability, IP175 supports a private
node link failure and changes its capability to half duplex
mechanism to handle flow control to prevent packet loss.
then restarts Nway. Both side of the segment will be link
It is called capability changing and is controlled by the
at half duplex.
parameter Update_r4_en.
When the remote station does not support IEEE802.3x
When the remote station does not support IEEE802.3x
and has full duplex capability and Update_r4_en is
and has full duplex capability and Update_r4_en is
turned off, the port turns off its IEEE802.3x capability and
turned on, the port changes its ability to half duplex to
is link at full duplex after Nway. There is no flow control
make the remote station link at half duplex after Nway.
between these two nodes in this application. The detail
IP175 handles the data flow of segment by backpressure.
operation is illustrated in the following table.
X_EN
x
x
1
0
1
0
1
0
1
0
REMOTE_IEEE
802.3X
x
x
1
1
0
0
1
1
0
0
Conditions
UPDATE_
R4_E
x
x
0
0
0
0
1
1
1
1
Result
BK_EN Remote site My site Remote site My site My My back
802.3x pressure
0
half
X
half
half
off
off
1
half
X
half
half
off
on
x
full/half
full/half
full
full
on
off
x
full/half
full/half
full
full
off
off
x
full/half
full/half
full
full
off
off
x
full/half
full/half
full
full
off
off
x
full/half
full/half
full
full
on
off
x
full/half
full/half
half
half
off
on
x
full/half
full/half
half
half
off
on
x
full/half
full/half
half
half
off
on
Aging
Broadcast Storm Protection
IP175 support address aging and buffer aging. If the
IP175 is able to prevent receiving too many broadcast
address aging is enabled, the learned SA will be cleared
packets to waste the switch resource. IP175 discards the
if it is not refreshed within the aging time (300 seconds).
incoming broadcast packets depending on the setting of
The aging time is not adjustable in IP175.
Bf_stm_en if the number of broadcast packets from a
port exceeds threshold. The threshold can be set by
writing Bq_hwm_0_sel[1:0] in EEPROM register.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
15
IP175
MII port
IP175 supports one MII port. When the interface is active,
one clock and there is no RXER signal on the interface.
the transceiver of port4 is disabled and the switch core
For half duplex operation, MCOL is used as a collision
interfaces the MII interface directly. This makes IP175
during transmission. The following diagram shows the
can behave like a Fast Ethernet transceiver.
interface in the IP175.
The major difference between the IP175 MII and IEEE
Pin 73 (VCC_IO_2) and pin 100 (VCC_IO_1) should be
standard MII are clock and RXER signal. There is only
connected to 3.3v in this application.
MII_RXCLK
MII_TXD[3:0]
MII_TXEN
SWITCH
CONTROLLER
PORT4
PHY
MII_RXD[3:0]
MII_RXDV
MII_TXCLK
MRXD[3:0]
MRXDV
MTXD[3:0]
MTXEN
MII_CLK
MCOL = MII_TXEN & MII_RXDV
MCOL
MTXER
IP175
(MII INTERFACE)
A System Block of Mac Interface
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
16
IP175
Power on Diagnostic of LED
Initial Value Set Via Pins
(Link, Act, Fdx and Speed LED are all the same during
To set the parameter via pins, connect them to vcc or
this period)
ground through resistors. IP175 reads initial value via
pins during the period of reset. An initial value is set to
(0) T = 0 sec
1’b1 (1’b0) by connecting a pin to vcc (gnd) through a
(1) T = 0.25 sec
10kΩ (1kΩ) resistor as shown on the following figure.
The function begins after the internal PLL clock active. To
(2) T = 0.50 sec
make sure the proper operation of PLL, the duration of
(3) T = 0.75 sec
reset must be no less than 1 ms. If there is no setting
(4) T = 1.00 sec
resistor, IP175 uses the default value.
(5) T = 1.25 sec
IP175 reads initial setting via pins during the period of
(6) T = 1.50 sec
reset. At reset, these pins are input signals and IP175
(7) T = 1.75 sec
reads the initial value. After reset, LED pins become
(8) T = 2.00 sec
output signals and show LED functions at normal mode.
The application circuit is shown below.
(9) T = 2.25 sec
2.5V
(10) After T = 2.5 sec, LED becomes normal operation
LED_SPEED
LED_FULL
LED_ACT
LED_LINK
LED PIN
2.5V
220
To set initial value = 1
with pull up 10K ohm resister
IP175 supports two ways to modify its initial values of
2.5V
operation parameters to fit different applications. It read
the initial value via pins or EPROM interface.
LED PIN
220
To use default value
(use no resistor to leave it open)
IP175-DS-P05
Jul. 19, 2002
LED PIN
220
1K
LED and Initial Value Setting
Preliminary, Specification subject to change without notice
10K
17
To set initial value = 0
with pull down 1K ohm resister
IP175
EEPROM Interface
During reset, IP175 sets the default value for each bit.
IP175 will stop reading the content of an EEPROM if
After reset, IP175 latches the setting on pins at the end
there is no specific pattern 55AA read in the register 0.
of reset and begins to read the content in the EEPROM.
After IP175 read the EEPROM, the EEPROM pins
The data in EEPROM is valid only if there is a specific
(BP_KIND and LED_SEL) are kept in input mode.
pattern 55AA read in the register 0. If there is no
EEPROM, IP175 keeps the value read from resistors
All fields in EEPROM corresponding to the registers of
setting. IP175 is still in reset state before finishing
IP175 should be filled with correct value if an EEPROM
EEPROM reading.
is used. Because the default value in IP175 will be
replaced with the content in EEPROM if it is valid.
IP175 uses a 93C46 EEPROM device. The detail
operation is illustrated in the following figure.
RESETB
Internal Reset
Internal PLL clock
>10us
Latch setting
on pins
Power On
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
18
Update setting with the
content of EEPROM
(Finish reading EEPROM)
IP175
EEPROM Register Description
Offset
00H[15:0]
Default Value
55AA
Corresponding Pin
-
LED output selection register
01H[15:2]
14’b0
01H[1:0]
11
LED_SEL[1:0]
Description
EEEPROM enable register
This register should be filled with 55AA. IP175 will check the
specified pattern to confirm a valid EEPROM exists. The initial
setting is updated after power on reset only if the specified
pattern 55AA is found.
Reserved
LED_SEL, LED mode selection
LED_SEL[1:0]=2’b00: LED mode 0,
LED_SEL[1:0]=2’b01: LED mode 1,
LED_SEL[1:0]=2’b10: LED mode 2,
LED_SEL[1:0]=2’b11: LED mode 3
Please refer to pin description for detail LED definition.
Switch control register 1
02H[15:13]
3’b0
02H[12:11]
00
BP_KIND[1:0]
02H[10]
02H[8]
02H[7]
0
0
1
X_EN
(LED_LINK[0])
02H[6:5]
02H[4]
2’b0
1
BK_EN
(LED_FULL[1])
02H[3]
0
(LED_ACT[0])
02H[2]
0
BF_STM_EN
(LED_ACT[2])
2’b0
-
02H[1:0]
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Reserved
BP_KIND, Backpressure type selection
It is valid only if Bk_en (02H[4]) is set to 1’b1.
00: carrier base backpressure
01: collision base backpressure with hashing
10: collision base backpressure without hashing
Reserved
Reserved
X_EN, IEEE 802.3x flow control enable
1: enable
0:disable
Reserved
BK_EN, Backpressure enable
1: enable,
0: disable
MII_FC_EN, External MII port flow control enable
1: enable,
0:disable
Broadcast storm enable
1: enable
Drop the incoming packet if the number of queued broadcast
packet is over the threshold. The threshold is defined in register
0AH[14:13].
0: disable
Reserved
19
IP175
EEPROM Register Description (continued)
Offset
Default Value
Switch control register 2
03H[15:10]
6’b0
03H[8]
0
03H[7]
1
Corresponding Pin
Description
Nodrop16
(LED_LINK[2])
Reserved
Reserved
No drop16,
A port will drop the transmitting packet after 16 consecutive
collisions if this function is turned on.
1: do not drop
0: drop
AGETIME, enable aging of address table
An address tag in hashing table will be dropped if this function
is turned on and its aging timer expires (300 seconds).
TWOPART, Turn on twopartD
IP175 examine the carrier for 64 bits only during its back off
period if this function is enabled. It makes IP175 have higher
priority in a collision event.
1: turn on
0: turn off
MODBCK, Turn on modified back off algorithm
IP175 uses modified (aggressive) back off algorithm if this
function is enabled. The maximum back off period is limited to
8-slot time. It makes IP175 have higher priority in a collision
event.
03H[4]
1
AGETIME
(LED_LINK[2])
03H[2]
1
TWOPART
(LED_SPEED[3])
03H[1]
1
MODBCK
(LED_SPEED[1])
03H[0]
0
-
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
1: turn on
0: turn off
Reserved
20
IP175
EEPROM Register Description (continued)
Offset
Default Value Corresponding Pin
Transceiver control register
04H[15:14]
00
OP1[1:0]
(LED_SPEED[2])
(LED_LINK[3])
04H[13:11]
Summary
04H[15:11]
04H[9]
04H[8]
04H[7:0]
000
OP1[1:0]
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
x
x
x
x
x
x
x
x
1
0
0000
0000
OP0[1:0],
FORCE_ MODE
(LED_ACT[3])
(LED_FULL[3])
(LED_FULL[2])
OP1,
Bit[15:14] are corresponding to op1[1:0].
The default value must be adopted for normal operation.
OP0 and FORCE_MODE,
Bit[13:11] are corresponding to op0[1:0] and force_mode.
The default value must be adopted for normal operation.
OP0[1:0] FORCE_MODE
Description
x
0
Port1, 3 nway with all capability
x
0
Port1, 3 half duplex only
x
0
Port1, 3 nway with all capability
x
0
Port1, 3 nway with all capability
x
1
Port1, 3 force 100M full duplex
x
1
Port1, 3 force 100M half duplex
x
1
Port1, 3 force 10M full duplex
x
1
Port1, 3 force 10M half duplex
0 0
0
Port0, 2, 4 nway with all capability
0 1
0
Port0, 2, 4 half duplex only
1 0
0
Port0, 2, 4 nway with all capability
1 1
0
Port0, 2 nway with all capability, Port 4 FX
0 0
1
Port0, 2, 4 force 100M full duplex
0 1
1
Port0, 2, 4 force 100M half duplex
1 0
1
Port0, 2, 4 force 10M full duplex
1 1
1
Port0, 2, 4 force 10M half duplex
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Description
21
IP175
EEPROM Register Description (continued)
Offset
Default Value Corresponding Pin
Transceiver verification register
05H[15:14]
2’b0
05H[13]
0
05H[12]
0
UPDATE_R4_EN
(LED_FULL[0])
05H[11]
05H[10]
05H[9]
05H[8]
05H[7:6]
05H[5]
05H[4]
05H[3]
05H[2]
05H[1]
0
0
0
0
00
0
0
0
0
0
05H[0]
0
Testing & verify mode register
06H[15:7]
9’b0
06H[6]
0
06H[5:0]
6’b0
07H[15:14]
2’b0
07H[13:10]
4’b0
07H[7:0]
8’h77
08H[15]
08H[14:8]
08H[7]
08H[6:0]
09H[15]
09H[14:8]
09H[7]
09H[6:0]
0
7’h30
0
7’h60
0
7’h30
0
7’h50
BPSCR
(LED_LINK[4])
-
-
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Description
Reserved
The default value must be adopted for normal operation.
UPDATE_R4_EN, Change capability enable
A full duplex port will change its capability to half duplex, if the
remote full duplex port does not support 802.3x and this function
is enable.
1: enable
0: disable
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
BYSCR_MODE, Bypass scrambler
1: bypass
0: not bypass
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
Reserved
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
Reserved
MAX_USE_THR, Input queue threshold
An incoming packet will be dropped if the number of packet
queued in a port is over the input queue threshold. This function
is always active in spite of if there is flow control or not. It is
usually higher than the threshold for flow control.
It is recommended to adopt the default value.
Reserved
BCKP_THR_RLS, Backpressure off threshold
Reserved
BCKP_THR, Backpressure on threshold
Reserved
X802_3_THR_RLS, 802.3x off threshold
Reserved
X802_3_THR, 802.3x on threshold
22
IP175
EEPROM Register Description (continued)
Offset
Default Value Corresponding Pin
Testing & verify mode register (continued)
0AH[15]
0
0AH[14:13]
11
-
0AH[12:11]
0AH[10:0]
2’b0
11’d128
-
0BH[14:10]
0BH[9:5]
0BH[4:0]
NA
NA
5’b0
5’b0
5’b0
0
0
-
Description
Reserved
BQ_HWM_0_SEL,
Broadcast Queue high water mark threshold selection. IP175 will
drop the incoming broadcast packet if the broadcast packet
count exceeds the threshold.
If (register 02H[2]: bf_stm_en==1), its corresponding threshold is
00:1024, 01:256, 10:128, 11:48,
If (register 02H[2]: bf_stm_en==0), the function is disabled.
Reserved
OQ_THR, Output Queue threshold
An incoming packet will be dropped if the number of packet
queued in destination port is over the output queue threshold.
IP175 enables this function automatically only if there is no flow
control.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
The default value must be adopted for normal operation.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
23
IP175
A summary of EEPROM Registers and Their Corresponding Pins
Offset
00H[15:0]
01H[1:0]
02H[12:11]
02H[7]
02H[4]
02H[3]
02H[2]
03H[7]
03H[4]
03H[2]
03H[1]
04H[15]
04H[14]
04H[13]
04H[12]
04H[11]
04H[10]
04H[9]
04H[8]
04H[7:0]
05H[13]
05H[12]
05H[11]
05H[10]
05H[9]
05H[8]
05H[7:6]
05H[5]
05H[4]
05H[3]
05H[2]
05H[1]
05H[0]
06H[6]
06H[5]
06H[4]
06H[3]
06H[2]
06H[1]
06H[0]
Default Value
55AA
11
00
1
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
8’b0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
0
0
0
0
0
0
Corresponding Pin
LED_SEL
BP_KIND
LED_LINK[0]
LED_FULL[1]
LED_ACT[0]
LED_ACT[2]
LED_LINK[2]
LED_LINK[1]
LED_SPEED[3]
LED_SPEED[1]
LED_SPEED[2]
LED_LINK[3]
LED_ACT[3]
LED_FULL[3]
LED_FULL[2]
LED_FULL[4]
BP_KIND[1]
LED_FULL[0]
AOUT_MCLK
MTXER
MTXD0
BP_KIND[0]
LED_SEL
MTXD1
MRXDV
LED_SPEED[0]
LED_LINK[4]
LED_ACT[4]
LED_ACT[1]
MCOL
MRXD0
MTXD3
MTXEN
MRXD2
MTXD2
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
24
Normal
-
X_EN
BK_EN
MII_FC_EN
BF_STM_EN
NODROP16
AGING
TWOPART
MODBCK
OP1[1]
OP1[0]
OP0[1]
OP0[0]
FORCE_ MODE
FIBER_HALF
-
Register Content
PROM ENABLE
LED_SEL
BP_KINK
X_EN
BK_EN
MII_FC_EN
BF_STM_EN
NO DROP16
AGETIME
TWOPART
MODBCK
OP1[1]
OP1[0]
OP0[1]
OP0[0]
FORCE_ MODE
FIBER_HALF
UPDATE_R4_EN
UPDATE_R4_EN
BPSCR
BYSCR_MODE
IP175
A summary of EEPROM Registers and Their Corresponding Pins (continued)
Offset
07H[15:14]
07H[7:0]
08H[14:8]
08H[6:0]
09H[14:8]
09H[6:0]
0AH[14:13]
0AH[10:0]
0BH[14:10]
0BH[9:5]
0BH[4:0]
0CH[15]
0CH[14]
0CH[11:10]
0DH[15]
0DH[14]
0DH[13]
0DH[12]
0DH[11]
0DH[10]
0DH[7]
0DH[6]
0DH[5]
0DH[4]
0DH[3]
0DH[2]
0DH[1]
0DH[0]
NA
NA
Default Value
2’b0
8’h77
7’h30
7’h60
7’h30
7’h50
11
11’d128
5’b0
5’b0
5’b0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Corresponding Pin
MRXD3
MRXD1
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
25
Normal
-
Register Content
MAX_USE_THR
BCKP_THR_RLS
BCKP_THR
X802_3_THR_RLS
X802_3_THR
BQ_HWM_0_SEL
OQ_THR
IP175
AC Characteristic
Read EEPROM
EESK
tCS
tSK
EECS
tDI
EEDI
1
1
0
A5
A4
A0
tOD
EEDO
Parameter
TSK
TCS
TDI
TOD
0
Description
Clock period
Chip select delay
Data input delay
Output delay
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Min
D15
D14
D0
Typical
5.12
Max
2
2
2000
26
Units
us
ns
ns
ns
IP175
Absolute Maximum Rating
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional
performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to
GND.
Supply Voltage
–0.3V to 4.0V
Input Voltage
–0.3V to 5.0V
Output Voltage
–0.3V to 5.0V
Storage Temperature
-65°C to 150°C
Ambient Operating Temperature (Ta)
0°C to 70°C
DC Characteristic
Operating Conditions
Parameter
Supply Voltage
Junction Operation Temperature
Power Consumption
Sym.
VCC2.5
TXVCC
Tj
Min.
2.375
2.375
0
Typ.
2.5
2.5
25
2.0
Max.
2.625
2.625
125
Unit
V
V
℃
W
Conditions
Sym.
Min.
Typ.
25
Max.
Unit
MHz
PPM
Conditions
Unit
V
V
V
V
Conditions
Input Clock
Parameter
Frequency
Frequency Tolerance
-50
+50
I/O Electrical Characteristics
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Sym.
VIL
VIH
VOL
VOH
Min.
Typ.
Max.
0.8
2.0
0.4
2.4
IOH=4mA, VCC=3.3V
IOL=4mA, VCC=3.3V
TX Transceiver Electrical Characteristics
Parameter
Peak Differential Output Voltage
Signal Amplitude Symmetry
Signal Rise/Fall Time
Rise/Fall Time Symmetry
Duty Cycle Distortion
Overshoot
Sym.
VP
TRF
TRFS
VO
Min.
0.95
98
3
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
Typ.
1.0
100
4
27
Max.
1.05
102
5
0.5
0.5
5
Unit
V
%
ns
ns
ns
%
Conditions
IP175
Thermal Data
Parameter
Thermal resistance: junction to
ambient
0 m/sec air flow
Thermal resistance: junction to
ambient
0 m/sec air flow
Symbol
θja
Conditions
4 layer PCB, ambient
temperature 70℃
θjc
4 layer PCB, ambient
temperature 70℃
Min
Typical
20.8
Max
°C/W
9.0
Order Information
Part No.
IP175
PIN
128 PIN PQFP
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
28
Units
°C/W
Notice
-
IP175
Package Detail
QFP 128L Outline Dimensions
Unit: Inches/mm
HD
D
103
128
E
HE
102
1
65
38
39
64
e
b
L
A1
c
A2
GAGE
PLANE
D
L1
Symbol
y
Dimensions In Inches
Dimensions In mm
Min.
Nom.
Max.
Min.
Nom.
Max.
A1
0.010
0.014
0.018
0.25
0.35
0.45
A2
0.107
0.112
0.117
2.73
2.85
2.97
b
0.007
0.009
0.011
0.17
0.22
0.27
c
HD
0.004
0.006
0.008
0.09
0.15
0.20
0.669
0.677
0.685
17.00
17.20
17.40
D
0.547
0.551
0.555
13.90
14.00
14.10
HE
0.906
0.913
0.921
23.00
23.20
23.40
E
0.783
0.787
0.791
19.90
20.00
20.10
e
-
0.020
-
-
0.50
-
L
0.025
0.035
0.041
0.65
0.88
1.03
L1
-
0.063
-
-
1.60
-
y
-
-
0.004
-
-
0.10
θ
0°
-
12°
0°
-
12°
Note:
1. Dimension D & E do not include mold protrusion.
2. Dimension B does not include dambar protrusion.
Total in excess of the B dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
Preliminary, Specification subject to change without notice
IP175-DS-P05
Jul. 19, 2002
29