:31 PM S/UNI-ATLAS-1k800 Data Sheet Errata Released ay ,1 9S ep tem be r, 20 02 11 :23 PM7328 Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd S/UNI-ATLAS-1k800 Errata Released Issue No. 2: August 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 1 S/UNI-ATLAS-1k800 Data Sheet Errata Released :31 PM Legal Information :23 Copyright 11 Copyright 2002 PMC-Sierra, Inc. All rights reserved. r, 20 02 The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or redistributed in any form without the express written consent of PMC-Sierra, Inc. tem be PMC-2011076 (R2) ep Disclaimer nT hu rsd ay ,1 9S None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. fo liv ett io In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. ef uo Trademarks yV inv S/UNI and PMC-Sierra are registered trademarks of PMC-Sierra, Inc. Other product and company names mentioned herein may be the trademarks of their respective owners. Do wn loa de Granted db Patents The technology discussed in this document is protected by one or more of the following patent grants: U.S. Patent No. 6,108,303 Canadian Patent No. 2,209,887. Other relevant patent grants may also exist. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 2 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM Contacting PMC-Sierra 11 :23 :31 PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 20 02 Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S ep tem be r, Document Information: [email protected] Corporate Information: [email protected] Technical Support: [email protected] Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 3 S/UNI-ATLAS-1k800 Data Sheet Errata Released 2 August 2002 Added U.S. patent number (PREP 7085) Added Canadian patent number (PREP 7937) Added sections 2.11. 2.12 and 3.5 Converted document to new template. 1 September 2001 Document creation. :23 Details of Change 11 Issue Date Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S ep tem be r, 20 02 Issue No. :31 PM Revision History Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 4 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM Table of Contents :31 Legal Information........................................................................................................................... 2 :23 Copyright................................................................................................................................. 2 11 Disclaimer ............................................................................................................................... 2 02 Trademarks ............................................................................................................................. 2 20 Patents .................................................................................................................................... 2 r, Contacting PMC-Sierra.................................................................................................................. 3 tem be Revision History............................................................................................................................. 4 Table of Contents........................................................................................................................... 5 ay Data Sheet Discrepancies ...................................................................................................... 9 CMOS input high DC level ............................................................................................ 9 2.2 TFIFODP[1:0] additional register bit description ........................................................... 9 2.3 Clarification in the use of CLRONRD and WM register bits........................................ 10 2.4 COSDATA[25:0] Bit Descriptions ................................................................................ 10 2.5 ITU-I.610 Recommendation Version ........................................................................... 11 2.6 Device ID Revision Number ........................................................................................ 11 2.7 Quad UL1 Mode .......................................................................................................... 11 2.8 Maximum ISYSCLK Frequency .................................................................................. 11 2.9 Maximum ESYSCLK Frequency ................................................................................. 12 fo liv ett io nT hu rsd 2.1 uo 2 Device Identification ...................................................................................................... 8 ,1 1.1 9S Issue 2 Errata.......................................................................................................................... 8 ef 1 ep List of Figures ................................................................................................................................ 7 inv 2.10 Patent Information ....................................................................................................... 12 yV 2.11 Table 18: PM Configuration Field ................................................................................ 12 Functional Discrepancies ...................................................................................................... 14 Do wn loa de 3 db 2.12 Equation to Calculate L2 Parameter for Policing ........................................................ 12 3.1 3.2 Egress Header Translation Not Performed under Certain Conditions ........................ 14 3.1.1 Description .................................................................................................. 14 3.1.2 Software Workaround ................................................................................. 14 3.1.3 Performance with Workaround ................................................................... 15 Reserved Bit in the Status Field of the Egress VC Table Erroneously Set when COS FIFO is Full.................................................................................................................. 15 3.2.1 Description .................................................................................................. 15 3.2.2 Software Workaround ................................................................................. 15 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 5 S/UNI-ATLAS-1k800 Data Sheet Errata Released 3.3.2 Workaround................................................................................................. 20 3.3.3 Performance with Workaround ................................................................... 21 11 :23 :31 Description .................................................................................................. 16 02 Non-Optimal Ingress Throughput Observed Due to “Stuttering” Effect ...................... 22 Description .................................................................................................. 22 3.4.2 Workaround................................................................................................. 23 3.4.3 Performance with Workaround ................................................................... 25 r, 20 3.4.1 tem be 3.5 3.3.1 F4 OAM cells are discarded at NNI connections if they have an unexpected Payload Type Identifier (PTI)..................................................................................................... 26 ep 3.4 Non-Optimal Ingress Throughput Observed With Certain Combinations of Features 16 3.5.1 Description .................................................................................................. 26 3.5.2 Workaround................................................................................................. 26 9S 3.3 Performance with Workaround ................................................................... 16 PM 3.2.3 Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 Notes ........................................................................................................................................... 27 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 6 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM List of Figures Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S ep tem be r, 20 02 11 :23 :31 Figure 1 PM7328 S/UNI-ATLAS-1K800 Branding Format .......................................................... 8 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 7 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM Issue 2 Errata :31 1 Device Identification 02 1.1 11 :23 This document is the errata notice for Revision A of the S/UNI-ATLAS-1K800 (PM7328-BI) and Issue 2 S/UNI-ATLAS-1K800 datasheet. The Issue 2 S/UNI-ATLAS-1K800 datasheet (PMC-2010142) and Issue 2 errata supersede all prior editions and versions of the datasheet. tem be r, 20 The information contained in this document applies to the PM7328 S/UNI-ATLAS-1K800 Revision A device only. The device revision code is marked at the end of the Wafer Batch Code on the face of the device (as shown in Figure 1). PM7328 S/UNI-ATLAS-1K800 Revision A is packaged in a 432 pin Super BGA package. rsd Reference Mark nT hu Pin A1 ay ,1 9S ep Figure 1 PM7328 S/UNI-ATLAS-1K800 Branding Format ett io PMC Logo ef uo fo liv SUNI -ATLAS-1K800 Logo R Do wn loa de db yV inv ATLAS-1K800 PM7328-BI C A Myyww Part Number Wafer Batch Code Assembly Date Code TOP VIEW SCALE: 2:1 (Approx) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 8 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM Data Sheet Discrepancies :31 2 Legend :23 1. unaltered text is unchanged to add context to changes 11 2. new material is bold and Italicized 3. obsolete material is struck out 02 4. comments specific to this document are in italics CMOS input high DC level ep 2.1 tem be NOTE: All items in Section 2 are documentation changes only. r, 20 5. A vertical bar in left margin indicates that this is a new item which was not present in the previous issue of this document. 0.3Vdd 0.7Vdd Max ay Input High Voltage (CMOS Only) Typ Units Conditions Volts Guaranteed Input HIGH Voltage Notes 7 nT TFIFODP[1:0] additional register bit description io 2.2 Min hu VIH Parameter rsd Symbol ,1 9S In Table 37 – D.C. Characteristics, the Min value for Input High Voltage (CMOS Only) should read as follows: fo liv ett The TFIFODP[1:0] registers bits are found in Register 0x40 – Egress Output Cell Configuration #1. The register bits’ description with the additional text is shown below. uo TFIFODP[1:0] Do wn loa de db yV inv ef The TFIFODP[1:0] register field determines the apparent cell depth of all FIFOs for the Egress output interface. The FIFO depth control may be important in systems where the cell latency through the Egress portion of the ATLAS-1K800. The apparent FIFO cell depth is configured as shown below: TFIFODP[1] TFIFODP[0] APPARENT DEPTH 0 0 4 cells 0 1 3 cells 1 0 2 cells 1 1 1 cell In single PHY OC-12 mode, TFIFODP[1:0] must be set to 00B to guarantee full OC-12 throughput. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 9 S/UNI-ATLAS-1k800 Data Sheet Errata Released Clarification in the use of CLRONRD and WM register bits PM 2.3 11 :23 :31 The CLRONRD and WM register bits are found in Register 0x182 - Ingress VC Table External RAM Access Control and Register 0x184 - Ingress VC Table Write Mask respectively. The register bit description of CLRONRD with the additional text is shown below. 02 CLRONRD tem be r, 20 If CLRONRD is logic 1, then after a read access of Row 5 of the Ingress VC Table specified in Register 0x181, a write with data bits [47:0] set to all ‘0’ is automatically initiated. Other bits in the words Data bits [63:48] and data bits with WM from register 0x184 set to 1 are preserved in the write back. ,1 9S ep If CLRONRD is logic 1, then after a read access of Row 6 and Row 9 of the Ingress VC Table specified in Register 0x181, a write with data bits all ‘0’ is automatically initiated. Data bits with WM from register 0x184 set to 1 are preserved in the write back. rsd COSDATA[25:0] Bit Descriptions hu 2.4 ay If CLRONRD = ‘0’, no write back to clear the data bits is initiated. nT The following changes are made to the COSDATA[25:16] bit descriptions in Registers 0x23b: ett io COSDATA[25:16] db yV inv ef uo fo liv The COSDATA[25:16] field contains the End-point information and Status field of a connection whose address is identified by the COSDATA[9:0] register. COSDATA[25] is the Segment End-Point bit (if this bit is logic 1, the connection is configured as a segment end-point), COSDATA[24] is the End-to-End Point bit (if this bit is logic 1, the connection is configured as an end-to-end point), COSDATA[23:16] is the Status field (LSB justified with COSDATA[23][23:21] set to logic 0) of the connection. The presence of data in this register indicates that the connection has undergone a change in connection state. This is the most significant 8-bits of the Ingress Change of State FIFO. Do wn loa de The following changes are made to the COSDATA[25:16] bit descriptions in Registers 0x2d7: COSDATA[25:16] The COSDATA[25:16] field contains the Status field of a connection whose address is identified by the COSDATA[9:0] register. COSDATA[25] is the Segment End-Point bit (if this bit is logic 1, the connection is configured as a segment end-point), COSDATA[24][25] is the End-to-End point bit (if this bit is logic 1, the connection is configured as an end-toend point), COSDATA[23:16] is the Status field (LSB justified with COSDATA[23:22][23:15] set to logic 0) of the connection. The presence of data in this register indicates that the connection has undergone a change in connection state. This is the most significant 8-bits of the Egress Change of State FIFO. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 10 S/UNI-ATLAS-1k800 Data Sheet Errata Released ITU-I.610 Recommendation Version PM 2.5 02 Device ID Revision Number 20 2.6 ITU-T Recommendation I.610 – “B-ISDN Operation and Maintenance Principles and Functions”, February, 1999 June, 1997 (Rapporteur’s edition). 11 · :23 :31 The reference to ITU-T Recommendation I.610 in Section 3 of the datasheet is changed to reflect the most recent version as shown below: tem be r, ID[3:0] ep The ID bits can be read to provide a binary number indicating the S/UNI-ATLAS-1K800 feature version. 9S NOTE 1: ay Quad UL1 Mode rsd 2.7 ,1 Rev A ID[3:0] = 0011 io nT hu The RPOLL, IPOLL and TPOLL pin description notes found in section 7 of the datasheet states that “the 4-PHY configuration is not recommended.” This is changed to “the 4-PHY configuration should not be used” as shown below: uo Maximum ISYSCLK Frequency ef 2.8 fo liv ett Note: In direct addressing mode, the 4-PHY configuration is not recommended should not be used. Instead the 4-PHY address-polling mode should be used. This does not apply to the Single or Dual-PHY configurations. Description db Symbol yV inv In Table 44 – Ingress SRAM Interface, the Max value for ISYSCLK frequency (including the reference to note 1) are changed as follows: Do wn loa de ISYSCLK Frequency ISYSCLK Duty Cycle Min Max Units Notes 24.5 52 MHz 1 59.5 40 60 % Notes: 1. Over the ISYSCLK frequency range 25 MHz to 52 59.5 Mhz Tj = -40°C to +120°C. Over the ISYSCLK frequency range 24.5 to 25 MHz Tj = -20°C to +120°C. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 11 S/UNI-ATLAS-1k800 Data Sheet Errata Released Maximum ESYSCLK Frequency PM 2.9 Description Min Max Units Notes ESYSCLK Frequency 24.5 52 11 Symbol :23 :31 In Table 45 – Egress SRAM Interface, the Max value for ESYSCLK frequency (including the reference to note 1) are changed as follows: 1 MHz 40 % tem be r, Notes: 60 20 ESYSCLK Duty Cycle 02 57.0 ep 1. Over the ESYSCLK frequency range 25 MHz to 52 57.0 Mhz Tj = -40°C to +120°C. Over the ESYSCLK frequency range 24.5 to 25 MHz Tj = -20°C to +120°C. ,1 ay No patent information in the original data sheet. 9S 2.10 Patent Information rsd Note: Patents nT hu The technology discussed is protected by one or more of the following Patents: io U.S. Patent No. 6,108,303 Canadian Patent No. 2,209,887 liv ett Relevant patent applications and other patents may also exist. fo 2.11 Table 18: PM Configuration Field ef uo The following changes are made to the description for the Bwd_PM_Pending bit (bit2) of the PM Table Configuration Field (Table 18, Section 8.7) Name Description 2 Bwd_PM_Pending This bit is a logic 1 if a Bwd PM cell is to be generated. Normally, Bwd Reserved PM cells are generated immediately upon receipt of a Fwd PM cell (if Do wn loa de db yV inv Bit so configured), however, in the event that the Bwd OAM cell FIFO is full, the request must be left pending until such time as it can be sent. This bit is used for internal purposes, and must be programmed to logic 0 at startup, and must not be altered by the microprocessor thereafter, for proper operation. 2.12 Equation to Calculate L2 Parameter for Policing Location Section 8.11 “Cell Rate Policing” Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 12 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM Original Wording :23 11 02 20 BT = Dt 1 1 ö ÷ è SCR PCR ø Dt (MBS - 1)æç r, L= 1 SCR (Dt ) tem be I= :31 For a Sustained Cell Rate (SCR) conformance definition, the parameters relate as follows: where ep SCR = Sustained Cell Rate (cells/s) ay ,1 9S MBS = Maximum Burst Size at the Peak Cell Rate (cells) BT = Burst Tolerance (s) rsd Replacement Wording io nT 1 SCR (Dt ) ett I= hu For a Sustained Cell Rate (SCR) conformance definition, the parameters relate as follows: liv inv ef where fo BT + CDVT = Dt uo L= 1 1 ö ÷ + CDVT è SCR PCR ø Dt (MBS - 1)æç yV SCR = Sustained Cell Rate (cells/s) db MBS = Maximum Burst Size at the Peak Cell Rate (cells) Do wn loa de BT = Burst Tolerance (s) CDVT = Cell Delay Variation Tolerance (s) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 13 S/UNI-ATLAS-1k800 Data Sheet Errata Released Functional Discrepancies 3.1 Egress Header Translation Not Performed under Certain Conditions 3.1.1 Description 02 11 :23 :31 PM 3 tem be r, 20 In the Egress direction of the ATLAS-1K800, the Egress Cell Processor (ECP) does not perform header translation on the incoming egress traffic when cells are also being inserted to the ECP from the microprocessor without header translation (i.e. E_UPHDRX bit from Register 0x061 is set to 0). This phenomenon has been observed at microprocessor cell insertion rates of 1 cell every 20ms or higher. Software Workaround ,1 3.1.2 9S ep Note: Egress header translation is performed properly on the incoming egress traffic when cells that are inserted to the ECP from the microprocessor are header translated. io nT hu rsd ay The software workaround is implemented by creating a dummy Virtual Connection (VC) with header translation enabled. Before each microprocessor cell insertion, copy the inserting cell’s VPI/VCI address to the VPI/VCI address field in the dummy VC Table. Subsequently, copy the dummy VC index into the inserting cell. Finally, write the cell into the Egress insert FIFO with header translation enabled. ett The following steps describe the above procedure in more detail: fo liv 1. Select an Egress Search Key (SRAM address) to be assigned to the dummy VC. ef uo 2. Create and Initialize a dummy Egress VC Table at the SRAM address specified by the Egress Search Key from step 1. yV inv 3. Set EAD[15:0] from Register 0x2AB to the Egress Search Key (SRAM address) of the chosen dummy VC. Do wn loa de db 4. Set ROW[0] from Register 0x2AD to 1 to allow write access to row 0 of the Egress VC Table. 5. Set the VPI/VCI address field located at ESA[19:16] = 0x0000 of the dummy VC Table by configuring ROW0[15:0] from Register 0x2AE and ROW0[31:16] from Register 0X2AF to the VPI/VCI address of the inserting cell. 6. Program the cell to be inserted so that its Egress Search Key will resolve to the SRAM address of the dummy VC 7. Set the E_UPHDRX bit from Register 0x061 to 1 to enable header translation. 8. Insert the cell to the Egress insert FIFO through Register 0x062. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 14 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM 9. Repeat Steps 3 to 8 for each microprocessor cell insertion. Performance with Workaround :23 3.1.3 :31 Note: Only one dummy VC is needed for all connections. 02 11 The implementation of the software workaround requires the user to dedicate only one Virtual Connection for all microprocessor cell insertions. tem be r, 20 Also, the active bit for this connection will be set even though it is not really an active connection. This may present a problem in cases where the system needs to go through the records in sequence and then verify if the active bit is set before doing any action on that particular connection. Reserved Bit in the Status Field of the Egress VC Table Erroneously Set when COS FIFO is Full 3.2.1 Description ,1 9S ep 3.2 nT hu rsd ay When the COS FIFO is full and a change of state occurs for a VC, the Egress Cell Processor (ECP) is supposed to set the Reserved bit in the Status Field of the Egress VC table (bit 31 of ESA[19:16] = 0x0010) to 1. This indicates that once there is space in the COS FIFO, the status of this VC must be copied to the COS FIFO. uo fo liv ett io Instead, at the instance the COS FIFO becomes full, the ECP sets the Reserved bits of all connections that receive cells regardless of the change of state condition. This situation only occurs for connections with the Active and COS_Enable bits set to 1. As the Reserved bits are set erroneously, the COS FIFO will contain vectors to a mix of connections that have no change of state and those that have a change of state. Software Workaround yV 3.2.2 inv ef This phenomenon can be detected when an interrupt generated by the setting of the E_COSFULLI bit in Register 0x006 is received. Do wn loa de db When the COS FIFO is full, E_COSFULLI in Register 0x006 will be set to 1 and will generate an interrupt. The software should poll the interrupt and then implement the following routine: 1. Clear the COS bit in Register 0x280. (This will disable the COS FIFO) 2. Empty the COS FIFO by reading Registers 0x2D6 and 0x2D7. 3. Initiate a wait state routine set to 1.0s. (This will ensure that the background processor has cleared all the Reserved bits in the Status field of the Egress VC Table) 4. Set COS bit in Register 0x280. (This will enable the COS FIFO) 5. Read the Status field from ESA[19:16] = 0010 for all connections in the Egress VC Table. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 15 S/UNI-ATLAS-1k800 Data Sheet Errata Released :31 PM 6. Check the value of E_COSFULLI in Register 0x006. If E_COSFULLI = 1, then go back to step 1, else go to step 7. :23 7. Empty the COS FIFO. At this point, the size of the COS FIFO should be less than 256. Performance with Workaround 20 3.2.3 02 11 Note: Step 5 can be modified or ignored if the microprocessor has limited allocated time to read all the connections. tem be r, When the COS FIFO is not full, the performance is unaffected. When the COS FIFO overflows, it takes greater than 1s for the COS FIFO to stabilize. Furthermore, the entire VC context table must be read to ensure that the current state of the connections is in the microprocessor memory. 9S ep Note: Software convergence rates will vary according to the microprocessor speed and the number of active connections. Non-Optimal Ingress Throughput Observed With Certain Combinations of Features 3.3.1 Description hu rsd ay ,1 3.3 ett io nT The two major parameters that determine the ingress throughput performance of the device are the ISYSCLK (Ingress System Clock) frequency and the average number of clock cycles spent to process an ATM cell in each cell period. ef uo fo liv For a 1xOC-12 or 4xOC-3 system, the maximum cell throughput is 1.413x106 cells/s. Therefore, in order to process the maximum cell throughput at an ISYSCLK frequency of 50MHz (most OC-12 systems run the ISYSCLK at this rate), the maximum number of clock cycles spent per cell period must be: inv Max Number of Clock Cycles = ISYSCLK frequency / Max cell throughput db yV = 50MHz / 1.413x106 cells/s Do wn loa de = 35.39 clock cycles = 35 clock cycles Under certain conditions, which will be described below, the average number of clock cycles spent in each cell period exceeds 35 clock cycles. As a rule of thumb, the average number of clock cycles spent in each cell period is dependent on the rate at which the microprocessor accesses the SRAM, the binary search tree depth and the amount of cell processing required by each cell. These factors are now described in further detail. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 16 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM MICROPROCESSOR SRAM ACCESS :23 :31 The device permits one microprocessor SRAM access per cell period. In the worst-case, the microprocessor may request a clear-on-read or a byte-masked write access, which takes 4 clock cycles to complete. 11 CPU Access = 4 clock cycles 20 02 By comparison, read-only or write-only operations take only 1 clock cycle. r, BINARY SEARCH ALGORITHM tem be The searching algorithm consists of the following steps: ep 1. Primary Lookup 9S 2. Secondary Branch Lookups, and ay ,1 3. Verification hu rsd As specified in section 8.2.1 of the datasheet, the maximum number of secondary lookups that can be performed to guarantee full throughput is 16. Therefore, the maximum possible number of clock cycles used up for the search is: io nT Search = 1 (Primary Lookup) + 16 (Secondary Branches) + 1 (Verification) ett = 18 clock cycles fo liv CELL PROCESSING inv ef uo The number of clock cycles used by the cell processor is highly dependent upon the type of cell received and upon the configuration of the device. Accordingly, the cell processor performs the necessary reads and writes to the appropriate rows in the Ingress VC Table outlined in Table 1 of the datasheet. Three cases are presented below. yV Case A: User Cells with a Cell Length = 27 or 28 Words Do wn loa de db For the case of a user cell, in which policing, PM and header translation are enabled, and the user cell is part of an F4 termination, the cell processing is as follows (assume that the output cell length is either 27 or 28 words): 1. Read Row2 (status, configuration, VPC pointer) 2. Read Row4 (policing parameters) 3. Read Row3 (policing parameters) 4. Read Row5 (policing parameters) 5. Read F4 Row2 (assumes user cell is part of a VPC flow) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 17 (translated header, UDF, prepend, postpend) 7. Read Row6 (ingress cell count 1, 2) :31 6. Read Row7 PM S/UNI-ATLAS-1k800 Data Sheet Errata Released :23 8. Bus Turnaround 11 9. Bus Turnaround (ingress cell count 1, 2) 11. Write Row 3 (update TAT1, TAT2) 12. Write Row 5* (update non-compliant cell count or GFR state) 13. Write Row 2 (update status) ep tem be r, 20 02 10. Write Row 6* 9S *Not always required. ay ,1 Cell Processing = 13 ISYSCLK cycles nT hu rsd In the example above, if the associated F4 connection was in AIS alarm or CC alarm (or in any case once per half-second per F4), an additional write would be performed to Row 2 of that F4 Connection, and thus, the total number of processing cycles would be 14. ett io Therefore, the worst-case total number of clock cycles required for all processing (searching, microprocessor access and cell processing) in this scenario is: fo liv Total cycles = CPU Access + Worst-Case Search + Cell Processing uo = 4 + 18 + 14 ef = 36 cycles yV inv NOTE: Segment and End-to-End F4 Must be Set Up as a Single Connection Do wn loa de db In some applications, segment and end-to-end F4 OAM connections are configured as two separate connections. This should not be done, as it will cause one additional read to Row 2 of the second F4 OAM connection per cell access, thereby increasing the maximum processing cycle by 1. In the case where the additional F4 OAM connection is in AIS or CC alarm, or if the background process has just decremented its CC alarm counters (which occurs once per half second), an additional write to Row 2 of that OAM connection may also occur. It is possible that this additional write could coincide with a write to the first F4 OAM connection. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 18 S/UNI-ATLAS-1k800 Data Sheet Errata Released 02 11 :23 :31 PM Instead, a single connection should be used for both Segment and End-To-End F4 OAM, and cells from both VCI= 0003 and VCI = 0004 should resolve to this connection. This combined OAM connection handles both the End-to-End and Segment OAM simultaneously in much the same way that any other connection does. This avoids the additional read or write operations to Row 2 of the second F4 OAM connection. This is shown in the figure below VCC2 tem be r, 20 VPC VCC1 VCCn 9S ep Ingress VC Table VCC2 VCCn uo fo liv ett io nT hu rsd ay ,1 VPC Connection VCC1 ef Case B: User Cells with a Cell Length > 28 words db yV inv For output cell lengths greater than 28 words (GPREPO bit in Register 0x200 = 1), an additional read from Row 8 is performed thereby increasing the maximum cell processing cycle by 1. Do wn loa de Case C: AIS Cells For AIS cell processing with IAISCOPY in Register 0x238 set to 1, an additional read to Row A, and writes to Row A, B (or D) and C (or E) are performed thereby increasing the maximum cell processing cycle by 4. Please note, however, that these read and writes are only performed if IAISCOPY = 1. If all features are enabled for these AIS cells as outlined above, then the maximum worst-case cell processing cycles required is 19 ISYSCLK cycles. Therefore, the worst-case total number of clock cycles required for all processing in this scenario is: Total cycles = CPU Access + Worst-Case Search + Cell Processing Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 19 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM = 4 + 18 + 19 :31 = 41 cycles Workaround 02 3.3.2 11 :23 This is the worst-case average number of clock cycles that can be encountered in a given system. tem be r, 20 In general, the workaround involves either reducing the average number of clock cycles spent per cell period or increasing the ISYSCLK frequency. Most system configurations are different and therefore will require a different workaround. Examples for common configurations are provided for each workaround. ep Pace Microprocessor SRAM Access ,1 9S The microprocessor SRAM access can be paced appropriately to ensure that the maximum average number of clock cycles required to guarantee full throughput is not exceeded. nT hu rsd ay As an example, consider the case where GPREPO = 0 and IAISCOPY = 0, this results in a maximum average number of clock cycle per cell period of 36. With the clock at 50MHz, the maximum average number of clock cycle per cell period must not exceed 35.39. By pacing the microprocessor accesses to 1 every 2 cell period at most, the average number of clock cycles is reduced to 34. This guarantees that full throughput is achieved. uo fo = 34 cycles liv = 2 + 18 + 14 ett io Total cycles = Ave CPU Access + Search + Maximum Cell Processing ef Avoid the use of Clear-On-Read or Masked-Write operations yV inv If microprocessor accesses are limited to simple read and simple write operations, then each access requires only 1 cycle. Do wn loa de db As an example, consider the case where GPREPO = 0 and IAISCOPY = 0, this results in a maximum average number of clock cycle per cell period of 36. With the clock at 50MHz, the maximum average number of clock cycle per cell period must not exceed 35.39. By eliminating the use of Clear-On-Read or Masked-Write operations, the average number of clock cycles is reduced to 33. This guarantees that full throughput is achieved. Total cycles = 1 read or write + Search + Maximum Cell Processing = 1 + 18 + 14 = 33 cycles Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 20 S/UNI-ATLAS-1k800 Data Sheet Errata Released PM Reduce Search Tree Depth :23 :31 The search tree depth can be reduced appropriately to ensure that the maximum average number of clock cycles required to guarantee full throughput is not exceeded. tem be r, = 4 + 17 + 14 20 Total cycles = CPU Access + Search + Maximum Cell Processing 02 11 Using the same example as above, where GPREPO = 0 and IAISCOPY = 0, the search tree depth can be reduced to 15 (instead of 16) to get a maximum average number of clock cycles of 35. This guarantees that full throughput is achieved. = 35 cycles 9S ep Increase ISYSCLK Frequency ay ,1 The ISYSCLK frequency can be increased appropriately to ensure that the device can process the worst-case average number of clock cycles per cell period while guaranteeing full throughput. nT hu rsd Using the same example as above, where GPREPO = 0 and IAISCOPY = 0, the maximum average number of clock cycles is 36. In order to ensure full throughput the ISYSCLK frequency must be run at: ett io ISYSCLK frequency = 36 cycles x 1.413x106 cells/s liv = 50.87 MHz uo fo In this case, a clock of 52 MHz should be used, to permit the use of the internally-generated half-second clock. yV inv ef In the absolute worst-case scenario as in case C (section 3.3.1) above, the maximum average number of clock cycles is 41. In order to ensure full throughput the ISYSCLK frequency must be run at: Do wn loa de db ISYSCLK frequency = 41 cycles x 1.413x106 cells/s = 57.94 MHz = 58 MHz If a 58 MHz clock is used, then the internally-generated half-second clock (which supports ISYSCLK frequencies of 25, 50, or 52 MHz) will be slightly fast. As a result, an external halfsecond clock must be provided on the HALFSECCLK pin, to provide accurate timing to the background processes that implement the CC, AIS, and RDI functions. 3.3.3 Performance with Workaround The device is able to process a full OC-12 worth of traffic after the workaround is implemented. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 21 S/UNI-ATLAS-1k800 Data Sheet Errata Released Non-Optimal Ingress Throughput Observed Due to “Stuttering” Effect 3.4.1 Description :23 :31 PM 3.4 r, 20 02 11 The Ingress SRAM bus is shared between two main blocks, the Ingress Search Engine (ISE) and Ingress Cell Processor (ICP). Under certain conditions, the way these blocks share the bus can enter an inefficient state, resulting in an inability to process cells at full throughput. In this inefficient state, the bandwidth is limited by the depth of the search tree and the length of the output cell in the ingress direction. rsd ay ,1 9S ep tem be The ISE performs searching on 3 cells in parallel. As soon as the next cell finishes its search, and is ready for transfer into the ICP, the SRAM bus is handed over. When the ICP is done processing cells, the SRAM bus is returned to the control of ISE for searching. Thus, searching is interleaved between each cell-processing step. Meanwhile, as soon as policing is complete, and the data for header translation has been read from the SRAM, the ICP begins streaming the cell from the ISE into the OCIF, modifying it as needed. This cell streaming continues in parallel with searching once the bus is turned back over to the ISE. The diagram below shows a 32-word cell case where the interleaving is occurring correctly. Search Process 3 18 cycles 14 cycles nT 14 cycles Process Search io 18 cycles hu 105 cycles (includes provision for micro or bkgnd) 3 liv ett Stream Cell 14 cycles Search Process Stream Cell Stream Cell 32 cycles 32 cycles uo fo 7 32 cycles = Excess b/w for micro or background processing 18 cycles Do wn loa de db yV inv ef Under certain conditions, the device can enter a state where all the searching for three cells is done at once, followed by cell processing of all three cells, without interleaving. Under this condition, the cell processing is throttled by the length of time it takes to stream the previous cell. No searching is done while the cell processor is waiting for the previous cell to stream. The diagram below illustrates this condition. 125 cycles (without provision for micro or bkgnd) Null Search (1) Null Search (1) 54 cycles 14 cycles 14 cycles 10 cyc 14 cycles Search Process Process Process 7 Wait for Streaming 17 cycles Search Wait for Streaming Stream Cell Stream Cell Stream Cell 32 cycles 32 cycles 32 cycles The process of getting into the stuttering state is probabilistic. The mechanism for entering this state is a combination of disturbing factors such as uneven search-tree depths, reception of unprovisioned cells, background processing, and other events. While it is unlikely that the worst version of this state will be entered, it cannot be ruled out. Once in this state, the throughput equation is as follows: Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 22 :23 Out_Cell_Len is the length of cells sent through the Ingress OCIF Sec_Search_Depth is the worst-case depth of the secondary search Fixed_Latency is 6 for cell lengths of 27 or 28, and 7 for greater cell lengths. :31 Time for 3 cells = 2(Out_Cell_Len) + 3(Sec_Search_Depth + 2) + Fixed_Latency PM S/UNI-ATLAS-1k800 Data Sheet Errata Released tem be r, 20 02 11 In the worst-case scenario, the microprocessor accesses can be additive to the total clock cycles consumed per 3 cell period. This occurs when the microprocessor access to SRAM is requested during the cell processing time before the long search in the stuttering case. This occurs less than 1/3 of the time, but could happen many times in succession resulting in cell loss. For a clear-on-read or a byte-masked write operation an additional of 4 clock cycles is added to the throughput equation as follows: ep Time for 3 cells = 2(Out_Cell_Len) + 3(Sec_Search_Depth + 2) + Fixed_Latency + 4 9S For a 1xOC-12 or 4xOC-3 system, the maximum cell throughput is 1.413x106 cells/s. Therefore the frequency at which ISYSCLK must be run is: ay ,1 Min ISYSCLK Freq = (1.413 x106) (Time for 3 cells)/3. hu rsd As long as the throughput is sufficient to temporarily handle the worst-case stuttering condition, the Input Cell Interface will be emptied, and the device will exit the stuttering condition. ett Workaround liv 3.4.2 io nT NOTE: Background processes have no impact, as they are automatically paused while bandwidth needs are high, and resumed once the inefficiency has passed. ef uo fo In general, the workaround involves a combination of reducing the maximum number of clock cycles spent during the worst-case stuttering condition, or increasing the ISYSCLK frequency. Most system configurations are different and therefore will require a different workaround. Examples for common configurations are provided for each workaround. yV inv Decrease the Output Cell Length Do wn loa de db Reducing the output cell length will reduce the length of time spent waiting for cells to stream into the OCIF. As per the equation, 2 cycles are saved from the 3-cell repeating pattern for every reduction of 1 word in the cell length. The following are some examples of the required throughput: Output Cell Length 30, Search Depth 16: (30x2 + 18x3 + 7 + 4)(1/3)(1.413) = 58.88 MHz Output Cell Length 29, Search Depth 16: (29x2 + 18x3 + 7 + 4)(1/3)(1.413) = 57.93 MHz Output Cell Length 28, Search Depth 16: (28x2 + 18x3 + 6 + 4)(1/3)(1.413) = 56.52 MHz Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 23 S/UNI-ATLAS-1k800 Data Sheet Errata Released :31 PM Output Cell Length 27, Search Depth 16: (27x2 + 18x3 + 6 + 4)(1/3)(1.413) = 55.58 MHz :23 Reduce Search Tree Depth 11 Reducing the search tree depth reduces the time to search each cell. As per the equation, 3 cycles are saved from the 3-cell repeating pattern for every reduction by 1 in the search tree. 20 02 Output Cell Length 28, Search Depth 12: (28x2 + 14x3 + 6 + 4)(1/3)(1.413) = 50.87 MHz tem be ep 9S Output Cell Length 32, Search Depth 9: (32x2 + 11x3 + 7 + 4)(1/3)(1.413) = 50.87 MHz r, Output Cell Length 30, Search Depth 11: (30x2 + 13x3 + 7 + 4)(1/3)(1.413) = 51.81 MHz io nT hu rsd ay ,1 Reducing the depth of the secondary search can often be achieved by more fully utilizing the primary search. For instance, a 4-PHY UNI application might concatenate the 2-bit PHYID with the 8-bit UNI VPI and the first 6 bits of the VCI into a 16-bit index to the primary search table. Most of the entries in that table would not have any associated connections, and thus would be coded to zero. Those entries in the table that did have associated connections would point to the base of secondary search trees. Because only 10 bits of the VCI remain to be resolved, the maximum search depth in the secondary tree will be 10. Thus, the total search will consume 12 cycles (1 primary + 10 secondary + 1 confirmation). fo liv ett Further reductions in the VPI or VCI range allowable permit further reductions in the secondary search depth. uo Increase ISYSCLK Frequency yV inv ef To the extent that a combination of search tree reduction and cell length reduction is insufficient to bring the required frequency below 50 or 52 MHz, ISYSCLK may be increased up to a maximum of 59.5 MHz. db However: Do wn loa de The ESYSCLK must not be raised above 57 MHz, and If a frequency other than 50 MHz or 52 MHz is used, then the HALFSECCLK input pin must be driven with an external half-second clock reference Pace Microprocessor SRAM Access The microprocessor SRAM access can be paced appropriately to ensure that the maximum average number of clock cycles required to guarantee full throughput is not exceeded. In the worst-case scenario, where the output cell length is 32 words and the search tree depth is 16, it is suggested that the microprocessor accesses to the SRAM be paced to 1 every 48 cell periods at most in order to guarantee full throughput at a maximum ISYSCLK rate of 59.5MHz. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 24 S/UNI-ATLAS-1k800 Data Sheet Errata Released :23 :31 PM In the worst-case scenario, the time for 3 cells (excluding microprocessor access) is 2x32 + 3x18 + 7 = 125 cycles. At 59.5MHz, this translates to 2101ns. Hence, at a rate of 1 access per 48-cell period (or 16 x 3 cell periods), the time interval between each access must be 16*2101ns = 33.614us. 02 11 Therefore, for every 3 cell period, an additional of 1/16*4 = 0.25 cycles must be added to the total number of clock cycles. At this rate, the maximum throughput will be 125.25/3 * 1.413MHz = 58.993MHz. tem be r, 20 If the microprocessor access is not paced as described above, then either the output cell length or search tree depth must be reduced in order to guarantee full throughput at 59.5MHz. ep At an output cell length of 32 words, the search tree depth must be reduced to 15 as shown in the calculation below: 9S (3x32 + 2x(15+2) + 7 +4)(1/3)(1.413) = 59.35MHz ay ,1 At a search tree depth of 16, the output cell length must be reduced to 30 as shown in the calculation below: rsd (3x30 + 2x(16+2) + 7 +4)(1/3)(1.413) = 58.88MHz nT hu This guarantees that full throughput is achieved. io Avoid the use of Clear-On-Read or Masked-Write operations fo liv ett If microprocessor accesses are limited to simple read and simple write operations, then each access requires only 1 cycle. inv ef uo As an example, consider the case of an output length of 32 with a secondary search depth of 16, and constant clear-on-read or masked-write operations that all fall in the worst-case position so that they affect throughput. In this case, microprocessor accesses must be paced to no more than 1 in 16x3 = 1 in 48 cell periods. db yV (3x32 + 2x(16+2) + 7 + 4/16 )(1/3)(1.413) = 58.993 MHz Do wn loa de By comparison, if only simple reads and writes were involved, the pacing can be reduced to 1 in 4x3 = 1 in 12 cell periods. (3x32 + 2x(16+2) + 7 + 1/4 )(1/3)(1.413) = 58.993 MHz 3.4.3 Performance with Workaround The device is able to process a full OC-12 worth of traffic so long as the ISYSCLK Freq > (1.413 x106) (Time for 3 cells)/3, where Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 25 S/UNI-ATLAS-1k800 Data Sheet Errata Released :31 PM Time for 3 cells = 2(Out_Cell_Len) + 3(Sec_Search_Depth + 2) + Fixed_Latency + Provision for Microprocessor Access F4 OAM cells are discarded at NNI connections if they have an unexpected Payload Type Identifier (PTI) 3.5.1 Description 02 11 :23 3.5 9S ep tem be r, 20 ITU I.361 (1999) states that F4 OAM cells shall only be generated with PTI = 000 or PTI = 010; It also states that the PTI shall not be evaluated on reception of these cells. However, if F4 OAM cells with PTI not equal to 000 or 010 arrive at the ATLAS-1k800, and the connection is defined as an NNI connection (NNI = 1 in the Ingress VC Table), then these cells will be declared as Invalid PTI/VCI cells; these will not be processed as OAM cells, and may be dropped (if DropInvPTIVCI = 1 in Register 0x220 ) and/or copied to the microprocessor (INVPTIVCItoUP = 1 in Register 0x220). Workaround ay 3.5.2 ,1 F5 connections and UNI connections are not affected by this issue. io nT hu rsd Most applications will not experience any difficulties due to this issue, because F4 OAM cells are normally only generated with PTI = 000 or 010. However, if some network function alters the MSB or LSB of the PTI of these OAM cells, then OAM cells may be lost. In this case, the recommended workaround is to set the NNI bit in the Ingress VC Record Table to logic 0 for affected connections. liv ett The workaround will have the following effects: uo fo - The marking of F4 OAM cells with non-standard PTI as invalid will cease. db yV inv ef - In order for the four MSBs of the VPI to be translated, the GFC bit must be logic 0 in Register 0x200. This implies that all UNI connections will have their GFC bits replaced by ATLAS1k800; this should not be an issue since few networks use the GFC function. If GFC = 1, then the four MSBs of the VPI for all connections with NNI=0 will be passed through transparently, and the ATLAS-1k800 will place the four MSBs of the VPI field in the VC Record Table into the four MSBs of any generated AIS or CC or Forward PM cells. Do wn loa de - There is no effect on the generation of RDI or Backwards PM cells. - No confirmation will be done on the four MSBs of the VPI for these connections. That is, if a search error occurs, and the received cell's VPI differs from the connection's VPI by only the four MSBs, this configuration error would not be caught and flagged. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 26 S/UNI-ATLAS-1k800 Data Sheet Errata Released Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S ep tem be r, 20 02 11 :23 :31 PM Notes Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2011076 Issue 2 27