ETC PM8316?

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TEMUX-84 Production Release Errata
Released
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PM8316
TM
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TEMUX-84
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TEMUX-84
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High Density 84-Channel T1/E1/J1
Framer with Integrated VT/TU Mappers
and M13 Muxs
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PRODUCTION RELEASE ERRATA
Proprietary and Confidential
Released
Issue 2: August, 2002
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
TEMUX-84 Production Release Errata
Released
PM
Legal Information
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:48
Copyright
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© 2002 PMC-Sierra, Inc.
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02
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal
use. In any event, you cannot reproduce any part of this document, in any form, without the
express written consent of PMC-Sierra, Inc.
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PMC-2020509 (r2)
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Disclaimer
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None of the information contained in this document constitutes an express or implied warranty by
PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such
information or the fitness, or suitability for a particular purpose, merchantability, performance,
compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any
portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all
representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
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In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
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Trademarks
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SBI, TEMUX, and PMC-Sierra are trademarks of PMC-Sierra, Inc. Other product and company
names mentioned herein may be the trademarks of their respective owners.
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Patents
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The technology discussed is protected by one or more of the following Patents:
U.S. Patent No. 5,640,398 Canadian patent 2,161,921
Relevant patent applications and other patents may also exist.
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TEMUX-84 Production Release Errata
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Contacting PMC-Sierra
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PMC-Sierra
8555 Baxter Place Burnaby, BC
Canada V5A 4V7
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Tel: +1.604.415.6000
Fax: +1.604.415.6204
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Document Information: [email protected]
Corporate Information: [email protected]
Technical Support: [email protected]
Web Site: http://www.pmc-sierra.com
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Revision History
Issue Date
Details of Change
1
April 2002
This document refers to device and documentation errata for
Revision C, the production release TEMUX-84 device.
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Issue No.
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The predecessor TEMUX-84 Rev B Errata document, PMC2012298 Issue 3 refers to Revision B of the TEMUX-84. All Errata
items in that document indicated as “To be fixed in Rev C” have
been implemented and tested in the Rev C TEMUX-84 device.
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August 2002
Additional device errata: Items 2.9 to 2.12
Additional documentation errata: Items 3.2 to 3.23
Appendix A: Using the Line Side SBI of the TEMUX-84
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All documentation errata described in the Rev B Errata have
subsequently been included in the latest data sheet and/or register
documents.
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
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Table of Contents
:48
Legal Information ................................................................................................................................ i
:52
Contacting PMC-Sierra ...................................................................................................................... ii
DEVICE IDENTIFICATION ................................................................................................1
1.2
REFERENCES ..................................................................................................................1
20
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1.1
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TEMUX-84 Functional Deficiency List........................................................................................2
5 National Use Bits in E1 TS0 cannot be simultaneously encoded...................................2
2.2
E1 Framer may falsely assert continuous CRC multiframe errors ....................................3
2.3
Demapping DS3 when CLK52M = 51.84 MHz not recommended for new designs .........4
2.4
TICLK Duty Cycle tolerance does not meet spec for a specific configuration...................5
2.5
Unstable DS3/E3 transmit clock may trigger data corruption in unchannelized
modes ................................................................................................................................6
2.6
Unchannelized DS3/E3 Loss of Signal requires SBI tributary reset..................................7
2.7
Start-up condition where 77.76 MHz SBI or Telecom Bus may see data corruption.........8
2.8
Non-ideal jitter performance in M13 mode when SBI bus is not synchronous................16
2.9
F-bit delay on H-MVIP bus is inconsistent in T1 mode....................................................17
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Introduction.................................................................................................................................1
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Table of Contents .............................................................................................................................. iii
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2.10 Multiframe Pulse Signaling inserted incorrectly for CAS applications in transmit
path
18
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2.11 Synchronization between TelecomBus and SBI Bus in OC-12/STM-4 Applications .......19
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TEMUX-84 Documentation Issues...........................................................................................26
Notification of Changes in AC Parameters ......................................................................26
3.2
SLCÒ96 support must be implemented using SBI bus ...................................................26
3.3
Transmux mode must meet Section 12.2.2 timing specification .....................................26
3.4
Transmux mode: T1/E1 Mapper configured before SONET/SDH blocks .......................27
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3.1
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2.12 TEMUX-84 supports line side SBI bus ............................................................................25
3.5
FI_EMPTY_ENBL bit works for all SPE_TYPEs .............................................................27
3.6
INSBI FIFO Underrun Status Register correction............................................................27
3.7
Correction to BSDL version number ................................................................................27
3.8
LAOE/LATPL is a tristate output ......................................................................................28
3.9
TSADDR is 5 bits .............................................................................................................28
3.10 TRIB_ENBL bit should be ENBL bit.................................................................................28
3.11 FIFO underrun and overrun blocking description ............................................................28
3.12 INSBI Control register bit is Reserved.............................................................................28
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3.13 APAGE bit in Register 0x0E61 ........................................................................................28
3.14 SREFCLK specification in serial DS3 mode....................................................................29
:48
3.15 DS3 Looptiming is not hitless ..........................................................................................29
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3.16 Demapped DS3 clock must be de-jittered for unstructured DS3 CES using SRTS........29
11
3.17 T1/E1 HDLC (THDL) minimum packet size is 2 bytes ....................................................29
02
3.18 Initialization time for T1/E1 Transmitter blocks ................................................................29
20
3.19 DS3 and E3 Diagnostic Loopback correction ..................................................................30
3.20 ETSEN bit description clarified ........................................................................................30
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3.21 Register default differs from actual chip value.................................................................30
3.22 TFPI/TMFPI[3:1] bit clarification ......................................................................................30
Appendix A: Configuring Line Side SBI on TEMUX-84...........................................................32
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3.23 TGAPCLK diagram is 1 pulse wider ................................................................................31
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TEMUX-84 Production Release Errata
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Introduction
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In this document:
Section 2 lists the known functional errata for Revision C, the production version of the
PM8316 TEMUX-84 Device.
·
Section 3 lists documentation errors found in Issue 7 of the TEMUX-84 Data Sheet (PMC1991437) and Issue 5 of the TEMUX-84 Register Description (PMC-2000034).
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·
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DEVICE IDENTIFICATION
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Figure 1. PM8316 TEMUX-84 Branding Format.
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The device revision code is marked at the end of the Wafer Batch Code on the face of the device
as shown below.
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Ball A1
Index Marks
TEMUX Logo
TM
TEMUX-84
Part Number
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PMC Logo
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PM8316-PI
C
C
Myyww
Philippines
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REFERENCES
Assembly Date Code
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1.2
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Country of
Assembler
Wafer Batch Code
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PMC-1991437 High Density T1/E1 Framer with Integrated VT/TU Mappers and M13
Multiplexers Telecom Standard Product Data Sheet, Issue 7.
PMC- 2000034 High Density T1/E1 Framer with Integrated VT/TU Mapper and M13
Multiplexer Telecom Standard Product Register Description, Issue 5.
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TEMUX-84 Production Release Errata
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TEMUX-84 Functional Deficiency List
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5 National Use Bits in E1 TS0 cannot be simultaneously encoded
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This section lists the known functional deficiencies (as of the publication date of this document)
for the production version of the TEMUX-84. For each deficiency, the workaround, if available,
is described. A comparison is given for the performance of the device with and without the
implementation of the workaround.
Description
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In timeslot 0 of the E1 frame (TS0-Odd of E1 double frame), there are 5 reserved National Bits
sometimes used for additional signaling in European or Asian networks. The TEMUX-84 has the
ability to only modify one of the E1 National Bits - SaX (where X = 4-8) at a given time with a
user-selectable 4-bit repeating code word. This differs from how the E1 National bits functioned
in the PM8315 TEMUX device. In the TEMUX, once a code word was setup to be transmitted on
an SaX bit, it would keep on being transmitted until the SaX_EN[1:4] were modified. The
TEMUX allowed five different code words to be transmitted on the SaX bits.
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In the TEMUX-84 however, using SaSEL[2:0], the E1 TRAN enables selection of the SaX bits
(where X = 4-8) upon which to transmit the SaX[1:4] code word. Transmission of the code word
is enabled by setting the bits in SaX_EN[1:4]. Selecting a new SaX bit, by changing SaSEL[2:0],
will cause the previously selected SaX bit to pass through unmodified and the newly selected SaX
bit will contain the code word. This effectively allows transmission of only one SaX bit at a time.
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Workaround
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To simultaneously support multiple user-selectable SaX bits, they must be inserted via the system
backplane. Setting the INDIS bit to 1 disables the TEMUX-84’s ability to insert international and
national bits into timeslot 0. As a result, transparent passing of bits occurs from TS0 of either the
SBI or H-MVIP system side interface.
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Registers 0x016A-0x016F: T1/E1 Transmitter Indirect Channel Data Registers
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
XDIS
CASDIS
TS16AIS
FEBEDIS
GENCRC
INDIS
FDIS
11
Bit 6
20
Bit 7
Bit 0
Default (‘b)
AIS
00000000
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0x016A
Offset
02
Address
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E1 Bit Map:
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INDIS:
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INDIS controls the insertion of the international and national bits into TS0. When INDIS is set to
logic 0, the international and national bits are inserted. The bit values used for the international
bits are dependent upon the GENCRC, FEBEDIS, and Si[1:0] context bits. The bit values used
for the national bits are dependent upon SaSEL[2:0], Sax_EN[1:4], and SaX[1:4]. When INDIS
is a logic 1, the international and national bits are taken directly from the system interface.
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Performance with Workaround
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Normal operation.
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Performance without Workaround
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E1 Framer may falsely assert continuous CRC multiframe errors
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2.2
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If setting the E1 National bits is not required, device performance is unaffected. If modifying
National bits is required, only one SaX bit can be set at a time.
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Description
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When the TEMUX-84 device is configured for E1 CRC-4 multiframe, it is possible that one or
more of the 63 tributaries incorrectly declares continuous CMFERI and FEBEI errors. This false
assertion of CRC multiframe errors may occur when the line side is configured for bit
asynchronous demapping or G.747 demultiplexing. This condition does not occur when byte
synchronous demapping from SONET/SDH.
This false error assertion only occurs when the new E1 multiframe alignment is exactly 8 frames
from the previous, established multiframe alignment. In other words, subframe II thinks it is
subframe I.
These two conditions, if seen together, are a good indicator of these false error assertions:
1. Continuous FEBE errors, roughly 500 errors per second, AND
2. Basic Frame is still in in-frame condition.
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The Far End Block Error holding register, FEBE[9:0] counts of Register 0x0186, can be used to
determine the FEBE error frequency. Monitoring this count will help determine if false error
assertions are occurring.
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Workaround
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If excessive FEBE errors occur, roughly 500 errors per second, and basic frame is still intact, a
reframe should be forced. To do this, the REFR bit of Register 0x0174 can be set to logic 0 then
set to 1 as detailed in register bit description below. This forces an out of frame, and establishes
the correct multiframe alignment, as per the “CRC Multiframe Alignment Procedure” section of
the Data Sheet.
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Performance with Workaround
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The reframing procedure may occasionally cause the corruption of DS0s at the system interface
for a few milliseconds then normal operation will resume.
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Performance without Workaround
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Demapping DS3 when CLK52M = 51.84 MHz not recommended
for new designs
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There is no data corruption despite the persistance of CRC multiframe error indications. Basic
frame is still correct and all the DSOs are still error-free. Operation of the TEMUX-84 is
otherwise normal.
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Description
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In the TEMUX-84 Data Sheet, there is a choice between two clock frequencies for CLK52M
input (Pin AB10):
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"52 MHz Clock Reference (CLK52M): The 52 Mhz clock reference is used to generate a
gapped DS3 clock when demapping a DS3 from the SONET stream and also to generate
a gapped DS3/E3 clock when receiving a DS3/E3 from the SBI bus interface. This clock
has two nominal values. The first is a nominal 51.84 MHz 50% duty cycle clock. The
second is a nominal 44.928 MHz 50% duty cycle clock. The expected frequency is
determined by the FASTCLKFREQ bit of the SONET/SDH Master DS3 Clock
Generation Control register. If E3 data rates are being supported, CLK52M must be 51.84
MHz."
Repetitive data corruption with demapped DS3 may occur in systems using the 51.84 MHz clock.
This is not an issue if the alternate clock frequency, 44.928 MHz, is used.
At this time, full characterization of the tolerance of the 51.84 MHz frequency relative to the
TelecomBus rate is not complete. Some systems may generate the 51.84 MHz clock from the
TelecomBus clock (LREFCLK) and it is not known if this will avoid the possible data corruption.
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Workaround
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1. When configured to demap DS3 payloads from SONET STS1/SDH AU3, the CLK52M input
must be 44.928 MHz to avoid possible data corruption to the DS3 stream. Thus, the
FASTCLKFREQ bit of Register 0x709 must be cleared to logic 0. Using the 44.928 MHz
clock has always been a fully supported mode and has been tested in-house.
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2. If E3 data is to be transferred across the SBI bus, then FASTCLKFREQ must be set to logic 1
and the CLK52M input must be a 51.84 MHz input.
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3. In the event that both 1 and 2 above are to be supported by the TEMUX-84 on a single card,
then external logic will be required to switch between the two crystal frequencies. Note that
you will have to choose either mode 1 or mode 2 as the operational mode of the entire
TEMUX-84 at any given time, as the CLK52M input is the clock source for all 3 ports of the
device.
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Performance with Workaround
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Performance without Workaround
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If the 44.928MHz clock frequency is used for CLK52M while demapping DS3s from SONET
STS1/SDH AU3, the risk of data corruption in this mode no longer exists. It is highly
recommended to use this clock frequency when demapping DS3s.
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TICLK Duty Cycle tolerance does not meet spec for a specific
configuration
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When demapping DS3s from SONET/SDH payloads, if the CLK52M input is set to 51.84MHz,
there is a risk of data corruption.
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Description
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Transmit input clock (Input pins T4, V4, Y2): TICLK[3:1] provides the transmit direction
timing for the three DS3s or E3s in the TEMUX-84. TICLK[3:1] are nominally 44.736 MHz or
34.368 MHz, 50% duty cycle clocks. The TICLK duty cycle tolerance specification requires that
low pulse width meet 7.7.
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The TICLK Duty Cycle tolerance does not meet specification for a very specific configuration
controlled in Register 0x0202+1x100*N, DS3 and E3 Master Unchannelized Interface Options.
The set-up is when using a gapped output clock (Bit 6, TXGAPEN=1) and also sampling on the
falling edge of this clock (Bit 7, TDATIFALL=1). Therefore, any SBI bus applications are not
affected.
Workaround
The suggested workaround is to sample on the rising edge when using a gapped output clock.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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TEMUX-84 Production Release Errata
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Performance with Workaround
:48
With the suggested workaround, the TEMUX-84 meets its TICLK duty cycle specification.
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Performance without Workaround
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Unstable DS3/E3 transmit clock may trigger data corruption in
unchannelized modes
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Configuring the TEMUX-84 with gapped output clock and sampling on the falling edge may
result in data corruption of the transmit DS3/E3.
Description
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Permanent data corruption may occur when the TEMUX-84 is configured in DS3/E3 framer only
mode over the SBI system interface as egress clock master. This may be triggered by a single
event such as an unstable DS3/E3 transmit clock.
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The extract SBI bus FIFO provides direct indications of the error state. It is recommended to
enable the interrupt service routines to monitor the FIFO depth, underrun and overflow conditions
of this block. The workaround detailed below eliminates the effect of this loss of signal or frame
event in DS3 unchannelized while TEMUX-84 is egress clock master.
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Workaround
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The following workaround has been verified and is highly recommended:
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WHILE (EXSBI has under-run,over-run or depth-check errors) {
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Reset DS3 block for failing SPE
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Reconfigure DS3 block for failing SPE
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Clear SBI interrupts caused by resetting DS3
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{
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Check SBI interrupts to see if failure is persisting
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Performance with Workaround
When workaround is implemented, egress data corruption will be eliminated.
Performance without Workaround
Underflows and overflows that may occur in EXSBI as a result of arbitrary transmit clocking may
fail to recover. Permanent transmit DS3/E3 data corruption may occur. Implementation of the
suggested workaround is recommended.
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Unchannelized DS3/E3 Loss of Signal requires SBI tributary
reset
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2.6
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Description
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11
In unchannelized DS3/E3 over SBI mode, whenever the TEMUX-84 recovers from a DS3/E3
loss of signal condition, there is a chance that its SBI tributary will fail in the ingress path.
20
Workaround
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Whenever the state of DS3 LOS transitions from LOS to healthy signal, the failed link in the
INSBI (Insert SBI) must be re-provisioned.
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This workaround has also been implemented in the TEMUX-84 Production Release Device
Driver in the following manner:
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Performance with Workaround
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When a DS3 LOS interrupt occurs, the interrupt routine checks to see if LOSV is zero
(i.e. we now have signal). An additional check is done to ensure the DS3 is configured for
unchannelized (the configuration at risk of link failures). If so, the INSBI block is reset
by disabling and re-enabling the link for the SPE in question. In order for the driver to be
able to do this, the DS3 LOS interrupt must be properly enabled in software as per the
Driver Manual.
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When the corresponding INSBI link is reprovisioned upon signal integrity transition, the
TEMUX-84 device operates normally. Correct frame and data will be received while in
unchannelized DS3 mode.
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Performance without Workaround
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If the corresponding link is not reset upon signal integrity recovery, there is a chance of remaining
in a permanent error state irregardless of loop timing or internal clocking. Data may be corrupted
at the SBI drop bus. Roughly 1 in 10 times the LOS occurs while in unchannelized DS3 mode,
the DS3 gets corrupted. Implementation of the suggested workaround is recommended to avoid
any data integrity problems.
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Start-up condition where 77.76 MHz SBI or Telecom Bus may see
data corruption
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2.7
:52
Description
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The TEMUX-84 has the option to operate the system side SBI bus in either 19.44 or 77.76 MHz
SBI mode. There is a digital delay-locked loop (DLL) needed to simultaneously meet the output
propagation delay as well as the setup and hold time requirements for the 77.76 MHz SBI bus
interface. The DLL is used to minimize output delay on all bus outputs. The DLL measures the
phase difference between the external clock and a reference clock and generates an internal clock,
which reduces the phase difference between the external clock and the reference clock to zero.
Similarly, the same DLL is required for the TelecomBus line side 77.76 MHz operation.
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There is a start-up condition in the TEMUX-84 that may cause the DLL of the 77.76 MHz SBI or
the TelecomBus to lock up. Hence, extracting data from the TelecomBus may have integrity
issues and the SBI drop bus has been observed to tristate when in 77.76 MHz mode. This lock-up
condition can be avoided if the start-up interrupt service routine includes the register accesses
below, and is implemented upon device configuration.
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One possible cause of this data corruption start-up issue is the inability to absorb phase hits within
80us of TEMUX-84 device initialization.
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For 77.76 MHz SBI bus DLL:
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The following 6 registers are not currently revealed in the TEMUX-84 Register Descriptions, but
need to be accessed to avoid the start-up condition described.
Type
Default
Unused
X
Unused
X
R/W
Reserved
0
R/W
Reserved
0
Unused
X
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Function
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Bit
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Bit 7
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Bit 4
db
Bit 6
Bit 5
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Register 0x1C4: DLL Configuration (77.76 MHz SBI Bus)
Bit 3
Bit 2
R/W
ERRORE
X
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
0
The DLL Configuration Register controls the basic operation of the DLL.
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ERRORE:
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The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When
ERRORE is set high, the INTB output is asserted low upon assertion of the ERROR bit
of the DLL Control Status register. When ERRORE is set low, changes in the ERROR bit
does not generate an interrupt.
20
02
Reserved:
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The reserved bits must be set low for correct operation.
Function
Default
Bit 7
R
TAP[7]
Bit 6
R
TAP[6]
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Bit 5
R
TAP[5]
Bit 4
R
TAP[4]
Bit 3
R
TAP[3]
Bit 2
R
TAP[2]
X
Bit 1
R
TAP[1]
X
Bit 0
R
TAP[0]
X
X
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X
X
X
X
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Bit
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Type
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Register 0x1C6: DLL Delay Tap Status
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The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the
outgoing clock.
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TAP[7:0]:
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yV
Writing to this register performs a software reset of the DLL. A software reset requires a
maximum of 24*256 SREFCLK cycles for the DLL to regain lock. During this time the SBI
output propagation delays may vary.
The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is using to
generate its outgoing clock.
When TAP[7:0] is logic zero, the DLL is using the delay line tap with minimum phase delay.
When TAP[7:0] is equal to 255, the DLL is using the delay line tap with maximum phase delay.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
9
TEMUX-84 Production Release Errata
Released
X
X
Bit 6
R
DLLCLKI
X
Bit 5
R
ERRORI
X
Bit 4
Unused
X
Bit 3
Unused
X
ERROR
X
Unused
X
Bit 1
R
RUN
X
ay
Bit 0
9S
R
,1
Bit 2
11
SREFCLKI
02
R
ep
Bit 7
:48
Unused
:52
Default
20
Bit 8
Function
r,
Type
tem
be
Bit
PM
Register 0x1C7: DLL Control Status
rsd
The DLL Control Status Register provides information of the DLL operation.
nT
hu
RUN:
fo
liv
ett
io
The DLL lock status register bit (RUN) indicates the DLL found a delay line tap in which the
phase difference between the rising edge of the variable delay clock and the rising edge of
SREFCLK is zero. After system reset, RUN is logic zero until the phase detector indicates an
initial lock condition. When the phase detector indicates lock, RUN is set to logic 1.
uo
The RUN register bit is cleared only by a hardware or a software reset.
inv
ef
ERROR:
db
yV
The delay line error register bit (ERROR) indicates the DLL has run out of dynamic range.
When the DLL attempts to move beyond the end of the delay line, ERROR is set high.
ERROR is set low when the DLL captures lock again.
Do
wn
loa
de
When this bit is a logic 1, it is recommended the DLL be re-initialized by writing any value to
the DLL Delay Tap Status register.
ERRORI:
The delay line error event register bit (ERRORI) indicates the ERROR register bit has
gone high. When the ERROR register changes from a logic zero to a logic one, the ERRORI
register bit is set to logic one and is cleared upon read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
PM
DLLCLKI:
:52
:48
The reference clock event register bit DLLCLKI provides a method to monitor activity on the
variable delay clock. When the internal DLLCLK changes from a logic zero to a logic one,
the DLLCLKI register bit is set to logic one and cleared upon read.
20
02
11
In the unlikely event this bit is logic 0, the DLL shall be re-initiated by writing any value to
the DLL Delay Tap Status register.
r,
SREFCLKI:
ay
Workaround for 77.76 MHz SBI mode
,1
9S
ep
tem
be
The system clock event register bit SREFCLKI provides a method to monitor activity on the
SREFCLK input clock. When the SREFCLK primary input changes from a logic zero to a
logic one, the SREFCLKI register bit is set to logic one. The SREFCLKI register bit is
cleared immediately after it is read, thus acknowledging the event has been recorded.
nT
hu
rsd
The registers shown above are needed to implement the appropriate start-up error checks when
operating the TEMUX-84 in 77.76 MHz SBI mode. This will avoid the potential tristating of the
SBI drop bus after device configuration.
ett
io
The recommended sequence of register accesses is shown below. When operating in 77.76 MHz
SBI mode:
inv
ef
uo
fo
liv
1. Set ERRORE (ERROR interrupt enable) bit to 1 in Register 0x1C4: DLL Configuration.
In doing so, an interrupt will be generated upon assertion event of the ERROR indicator
status in Register 0x1C7: DLL Control Status. This ERROR bit is set high when the DLL
has run out of dynamic range and attempts to move beyond the end of the delay line.
Polling may also be used.
Do
wn
loa
de
db
yV
2. If the ERROR bit is set high indicating the DLL is locking up, a DLL software reset
must be invoked for the DLL to regain lock. Writing any values to Register 0x1C6: DLL
Delay Tap Status does this and ensures the SBI drop bus will not tristate. ERRORE
should remain a logic 1 (regular polling is an alternative). Although the problem has only
ever been seen at startup, the theoretical possibility exists for the condition to be triggered
at any time due to discontinuities in phase of SREFCLK.
Note:
The SBIDLLINT bit is available as bit 6 in Register 0x0015 Master Interrupt Source SBI.
Below is the bit description:
SBIDLLINT:
This bit only has significance if the S77 input in pulled high. If the SBIDLLINT bit is a
logic 1, the SBI DLL has generated an interrupt indicating it has errored. Register
0x01C7 DLL Control Status must be read to clear this interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
:48
PM
The following registers need to be accessed to avoid potential start-up conditions when operating
in TelecomBus mode:
Bit 7
Unused
X
Bit 6
Unused
X
Reserved
0
Bit 4
R/W
Reserved
0
Unused
X
X
Bit 1
R/W
Reserved
Bit 0
R/W
Reserved
9S
ERRORE
,1
R/W
0
0
rsd
Bit 2
ay
Bit 3
20
R/W
ep
Bit 5
11
Default
02
Function
r,
Type
tem
be
Bit
:52
Register 0x073C: DLL Configuration (TelecomBus)
hu
The DLL Configuration Register controls the basic operation of the DLL.
nT
ERRORE:
uo
fo
liv
ett
io
The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When
ERRORE is set high, the INTB output is asserted low upon assertion of the ERROR bit
in the DLL Control Status register. When ERRORE is set low, changes in the ERROR bit
does not generate an interrupt.
ef
Reserved:
Do
wn
loa
de
db
yV
inv
The reserved bits must be set low for correct operation.
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
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Default
Bit 7
R
TAP[7]
X
Bit 6
R
TAP[6]
X
Bit 5
R
TAP[5]
X
Bit 4
R
TAP[4]
X
Bit 3
R
TAP[3]
X
Bit 2
R
TAP[2]
X
Bit 1
R
TAP[1]
X
Bit 0
R
TAP[0]
X
:48
Function
9S
ep
tem
be
r,
20
02
11
:52
Type
,1
Bit
PM
Register 0x073E: DLL Delay Tap Status
rsd
ay
The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the
outgoing clock.
io
nT
hu
Writing to this register performs a software reset of the DLL. A software reset requires a
maximum of 24*256 LREFCLK cycles for the DLL to regain lock. During this time the
TelecomBus output propagation delays may vary.
ett
TAP[7:0]:
uo
fo
liv
The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is using to
generate its outgoing clock. .
Do
wn
loa
de
db
yV
inv
ef
When TAP[7:0] is logic zero, the DLL is using the delay line tap with minimum phase delay.
When TAP[7:0] is equal to 255, the DLL is using the delay line tap with maximum phase delay.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
X
X
Bit 6
R
DLLCLKI
X
Bit 5
R
ERRORI
X
Bit 4
Unused
X
Bit 3
Unused
X
ERROR
X
Unused
X
Bit 1
R
RUN
X
ay
Bit 0
9S
R
,1
Bit 2
11
LREFCLKI
02
R
ep
Bit 7
:48
Unused
:52
Default
20
Bit 8
Function
r,
Type
tem
be
Bit
PM
Register 0x073F: DLL Control Status
rsd
The DLL Control Status Register provides information of the DLL operation.
nT
hu
RUN:
fo
liv
ett
io
The DLL lock status register bit (RUN) indicates the DLL found a delay line tap in which the
phase difference between the rising edge of the variable delay clock and the rising edge of
LREFCLK is zero. After system reset, RUN is logic zero until the phase detector indicates an
initial lock condition. When the phase detector indicates lock, RUN is set to logic 1.
uo
The RUN register bit is cleared only by a hardware or a software reset.
inv
ef
ERROR:
db
yV
The delay line error register bit (ERROR) indicates the DLL has run out of dynamic range.
When the DLL attempts to move beyond the end of the delay line, ERROR is set high.
ERROR is set low when the DLL captures lock again.
Do
wn
loa
de
When this bit is a logic 1, it is recommended the DLL be re-initialized by writing any value to
the DLL Delay Tap Status register.
ERRORI:
The delay line error event register bit (ERRORI) indicates the ERROR register bit has
gone high. When the ERROR register changes from a logic zero to a logic one, the ERRORI
register bit is set to logic one and is cleared upon read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
PM
DLLCLKI:
:52
:48
The reference clock event register bit DLLCLKI provides a method to monitor activity on the
variable delay clock. When the internal DLLCLK changes from a logic zero to a logic one,
the DLLCLKI register bit is set to logic one and cleared upon read.
20
02
11
In the unlikely event this bit is logic 0, the DLL shall be re-initiated by writing any value to
the DLL Delay Tap Status register.
r,
LREFCLKI:
9S
ep
tem
be
The line clock event register bit LREFCLKI provides a method to monitor activity on the
LREFCLK input clock. When the LREFCLK primary input changes from a logic zero to a
logic one, the LREFCLKI register bit is set to logic one. The LREFCLKI register bit is
cleared immediately after it is read, thus acknowledging the event has been recorded.
,1
Workaround for TelecomBus mode
rsd
ay
The registers shown above are needed to implement the appropriate start-up error checks when
operating the TEMUX-84 in 77.76 MHz TelecomBus mode.
nT
hu
The recommended sequence of register accesses is shown below. When operating in TelecomBus
mode:
uo
fo
liv
ett
io
1. Set ERRORE (ERROR interrupt enable) bit to 1 in Register 0x073C: DLL
Configuration. In doing so, an interrupt will be generated upon assertion event of the
ERROR indicator status in Register 0x073F: DLL Control Status. This ERROR bit is set
high when the DLL has run out of dynamic range and attempts to move beyond the end
of the delay line. Polling may also be used.
The TBUSDLLINT bit is available as bit 7 in Register 0x0012 Master Interrupt Source
SDH #1. Below is the bit description:
Do
wn
loa
de
Note:
db
yV
inv
ef
2. If the ERROR bit is set high indicating the DLL is locking up, a DLL software reset
must be invoked for the DLL to regain lock. Writing any values to Register 0x073E:
DLL Delay Tap Status does this and ensures TelecomBus propagation delays are within
specification. ERRORE should remain a logic 1 (regular polling is an alternative).
Although the problem has only ever been seen at startup, the theoretical possibility exists
for the condition to be triggered at any time due to discontinuities in phase of LREFCLK.
TBUSDLLINT:
This bit only has significance if the L77 input in pulled high. If the TBUSDLLINT bit is
a logic 1, the TelecomBus DLL has generated an interrupt indicating it has errored.
Register 0x073F DLL Control Status must be read to clear this interrupt.
Performance with Workaround
Normal operation.
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
PM
Performance without Workaround
:52
:48
When operating the TEMUX-84 in 77.76 MHz SBI bus or TelecomBus modes, the rare
occurrence of DLL lock-up conditions is not deterministic. Symptoms of this lock-up include
out-of-spec propagation delays on each of the buses or tristating of the bus itself.
20
Non-ideal jitter performance in M13 mode when SBI bus is not
synchronous
Telecom
Bus Line
Side
VT/TU Mapper
T1/E1 Framers
DS3
Line
Side
ay
DS3
Framers
SBI
System
Interface
Link Layer
Device or
T1/E1 LIU
TEMUX-84
hu
rsd
DS3 LIU
,1
M13 MUX
ep
DS3 Mapper
9S
SONET/
SDH
Framer
tem
be
r,
2.8
02
11
However, it is known with certainty that this is a start-up condition that can be avoided by
implementing the workaround described above.
io
nT
Description
liv
ett
There is a specific system configuration and operating mode in which T1 and E1 jitter
performance may be less than desired:
uo
fo
1. System side SBI Bus running in slave mode, and the T1’s or E1 are not synchronous with the
SBI bus clock, hence, there is a presence of SBI bus T1/E1 tributary pointer adjustments.
db
yV
inv
ef
This configuration is most frequently used when the SBI system bus is connected to one of
PMC-Sierra’s AAL1gator devices or perhaps a customer provided system side device
requiring non-synchronous SBI bus operation. If the system bus is connected to an LIU
(typically the PM4318 or PM4319) and each T1 or E1 must be independently timed then the
TEMUX-84 will be configured in slave mode and will be operating asynchronously.
Do
wn
loa
de
There is no jitter issue whatsoever when the TEMUX-84 is the SBI Add bus timing master
(for example when the TEMUX-84 device interfaces with PMC-Sierra’s FREEDM, IMA,
SBS or other TEMUX devices) or when the T1’s or E1’s are synchronous (locked) to the SBI
bus.
2. TEMUX-84 is configured in M13 or G.747 multiplexing modes where SBI-sourced data
from the system SBI bus is routed through the M13 multiplexer and then either to be DS3mapped into SONET/SDH (out the line side telecom bus) or outputted as channelized DS3
via the TEMUX-84’s DS-3 serial port.
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
:48
PM
Note that jitter performance will not be a concern if the SBI-sourced T1/E1s are directly
VT/TU-mapped into SONET/SDH, or when unchannelized DS-3 is being taken from the SBI
system-side bus.
02
11
:52
Preliminary jitter results indicate that if both of these conditions apply, the applicable T1/E1 jitter
standards can be met, however with less-than-ideal design margin. Note that there are no data
integrity issues in the TEMUX-84 in any mode. The following discussion is with respect only to
jitter performance of T1 or E1 multiplexed within a DS-3.
ep
tem
be
r,
20
Evaluating jitter performance is complex and highly dependant on the overall network and system
in which the TEMUX-84 may operate. Further, the appropriate jitter test scenarios are not always
clearly defined in the standards. PMC-Sierra provides an Applications Note detailing the
extensive jitter testing performed, the configurations used, and the results achieved for the most
common system configurations involving the TEMUX-84 and other PMC devices.
F-bit delay on H-MVIP bus is inconsistent in T1 mode
rsd
2.9
ay
,1
9S
It is recommended that the Applications Note be reviewed in detail. Customers operating in SBI
bus timing slave mode with independent T1/E1 clocking and routing traffic through the device’s
internal M13 multiplexer can contact PMC-Sierra to discuss these issues.
nT
hu
Description
liv
ett
io
In the TEMUX-84, it is possible to transparently carry T1 F-bits over the H-MVIP bus interface.
Currently, the TEMUX-84 Data Sheet states that F-bits output on the H-MVIP interface are
delayed by one T1 frame (Table 42). This delay creates a single frame shift in the multiframe
alignment of the subsequent SF or ESF formatted data stream.
ef
uo
fo
Subsequent testing has revealed that in fact the T1 F-bit can be either advanced or delayed by one
T1 frame. This behavior depends on the internal alignment of specific read and write pointers
inside the TEMUX-84. Both T1 SF and ESF framing formats are affected by this problem.
db
yV
inv
It is further possible that internal conditions may change; thereby causing the F-bits alignment to
the data frame to switch between advanced and delayed by one T1 frame. In such a scenario,
SLCÒ96 applications will be impacted because the F-bit stream will be corrupted.
Do
wn
loa
de
This deficiency does not impact or corrupt data on the H-MVIP bus, nor does it apply to the SBI
bus mode of operation. E1 modes are unaffected.
Workaround
The switching between advanced and delayed frame alignment is determined by internal
conditions that are not readily discernable to the external circuitry. There is no workaround.
PMC-Sierra recommends that designs requiring frame-aligned access to the F-bits (such as
SLCÒ96 framing support) should be based on the SBI bus rather than the H-MVIP bus. Refer to
Application Note PMC-2020593, “TEMUX-84 SBI FPGA for SLCÒ96 Applications”.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
PM
Performance with workaround
:48
There is currently no workaround to deterministically handle F-bits on the H-MVIP bus.
02
11
:52
In general, the functionality of designs based on H-MVIP can be readily replaced with designs
using the SBI bus operating in synchronous mode. Since the H-MVIP and SBI bus modes share
pins, it is usually possible to convert from an H-MVIP bus to a synchronous SBI bus with
minimal changes to the circuitry.
20
Performance without workaround
9S
ep
tem
be
r,
The shift in alignment created by the single frame F-bit delay or advancement results in F-bit
signaling corruption in the form of missed or repeated F-bits. If these F-bits are not corrected (i.e.
they are left associated with the framed data as is) then apparent frame slips and CRC6 errors in
far-end equipment or during diagnostic loopbacks will result. No data corruption will occur, but
any CAS signaling within the data stream will become misaligned with the T1 frame, resulting is
CAS signaling corruption.
rsd
ay
,1
2.10 Multiframe Pulse Signaling inserted incorrectly for CAS
applications in transmit path
hu
Description
fo
liv
ett
io
nT
The current TEMUX-84 datasheet provides the system side interface option of H-MVIP or SBI
bus when implementing SLCÒ96. Therefore, connecting an external FPGA to the H-MVIP
system bus is one way of supporting SLCÒ96. Because the TEMUX-84 does not actually
process the F-bits, the H-MVIP multiframe pulse is used instead as the mechanism to determine
the appropriate frame into which to insert signaling. In the transmit direction, robbed bit signaling
must be inserted every 6 T1 frames in the TEMUX-84.
yV
inv
ef
uo
It has been discovered that robbed bit signaling insertion has the possibility of not being aligned
with the signaling multiframe pattern being inserted on the F-bits aligned to the signaling
multiframe pulse. That is, the robbed bits may not necessarily end up in frames 6, 12, 18, etc but
could end up in any frame. This would result in the far end extracting the incorrect robbed bit
signaling data.
Do
wn
loa
de
db
In general, any time the TEMUX-84’s transmit elastic stores are enabled, there is this possibility
that multiframe pulse signaling is not used correctly. When using the H-MVIP system interface,
the transmit elastic stores are inherently enabled. However, when using the SBI bus, there is the
option to disable the transmit elastic stores. The transmit elastic stores must be disabled for
proper operation. This does not affect E1 operation. It is believed to only be an issue for
SLCÒ96 applications.
Workaround
The suggested workaround is to design the external FPGA for SLCÒ96 processing to interface
with the TEMUX-84 SBI bus rather than the H-MVIP bus. Further, the transmit elastic stores
need to be bypassed, thus allowing the multiframe alignment to be passed correctly. This ensures
signal insertion into the proper T1 frames in the transmit direction.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
18
TEMUX-84 Production Release Errata
Released
:52
:48
PM
In general, the functionality of designs based on H-MVIP can be readily replaced with designs
using the SBI bus operating in synchronous mode. Since the H-MVIP and SBI bus modes share
pins, it is usually possible to convert from an H-MVIP bus to a synchronous SBI bus with
minimal changes to the circuitry.
11
This has been described in an Application Note: PMC-2020593, “TEMUX-84 SBI FPGA for
SLCÒ96 Applications”.
20
02
Performance with Workaround
tem
be
r,
When the system side SBI bus is utilized instead of the H-MVIP in SLCÒ96 applications and the
transmit elastic stores are bypassed, the TEMUX-84 will operate normally. As a result, TEMUX84 can be used in conjunction with an external FPGA to support SLCÒ96 applications.
ep
Performance without Workaround
rsd
ay
,1
9S
Since multiframe signaling information is not used to properly insert signaling into a T1 frame,
signaling information may overwrite data. This T1 data corruption affecting SLCÒ96 operation
can be avoided by implementing the suggested workaround. This does not affect E1 operations.
nT
hu
2.11 Synchronization between TelecomBus and SBI Bus in OC12/STM-4 Applications
ett
io
Description
uo
fo
liv
The TEMUX-84’s interfaces are selectable between 19.44 and 77.76 MHz on both the line side
TelecomBus and the system-side SBI Bus. The bus interface combinations between the
TelecomBus and SBI Bus are:
ef
1. 19.44 MHz Telecom Bus and 19.44 MHz SBI Bus
yV
inv
2. 77.76 MHz Telecom Bus and 77.76 MHz SBI Bus
db
3. 19.44 MHz Telecom Bus and 77.76 MHz SBI Bus*
Do
wn
loa
de
4. 77.76 MHz Telecom Bus and 19.44 MHz SBI Bus*
*Modes 3 and 4 above must be handled with care in OC-12/STM-4 designs.
When four TEMUX-84s share the same 77.76 MHz SBI bus and interface to a single link-layer
device such as PM7388 FREEDM-336, a single SBI drop bus frame pulse (SDC1FP) is shared by
all four TEMUX-84s. Hence, Section 12.2.2 of the TEMUX-84 datasheet, suggesting four
separate SDC1FPs does not apply.
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Document ID: PMC-2020509, Issue 2
19
TEMUX-84 Production Release Errata
Released
:52
:48
PM
In order for multiplexed OC-12/STM-4 data to appear on the SBI Drop Bus to the link-layer
device, and be properly aligned data, the four 19.44 MHz TelecomBus Drop buses on TEMUX84’s line side must each have unique phase, with respect to the 77.76 MHz SREFCLK (system
reference clock) and SDC1FP frame pulse.
02
11
Hence, each of the four TEMUX-84s must be provided with separate LREFCLK TelecomBus
reference clocks. The phase relationship (not accounting for propagation delays) is shown in
Figure 2.
tem
be
r,
20
SDC1FP
Sampling Edge
9S
ep
77 MHz SREF
19 MHz LREF
SSTM[1:0]=00
ay
,1
SDC1FP
hu
19 MHz LREF
SSTM{1:0}=01
rsd
1 SREF
Cycle
19 MHz LREF
SSTM[1:0]=11
io
liv
3 SREF
Cycles
ett
19 MHz LREF
SSTM[1:0]=10
nT
2 SREF
Cycles
db
yV
inv
ef
uo
fo
0 SREF
Cycles
Figure 2: Required TelecomBus Phase Offsets
Do
wn
loa
de
Providing unique phase to each TEMUX-84 via its TelecomBus becomes a timing issue when
only a single TelecomBus reference clock (LREFCLK) is presented to the four TEMUX-84s. An
example is with PM5313 SPECTRA-622 or PM5316 SPECTRA-4x155. Each of these devices
can only provide a single LREFCLK and not the required one-per-TEMUX-84. With propagation
delays greater than 13ns (worst-case is 23ns), timing violations occur.
PMC-Sierra highly recommends using the 77.76 MHz TelecomBus when the 77.76 MHz SBI is
used (i.e. multiple TEMUX-84s share common SBI bus) rather than 4 independent 19.44 MHz
TelecomBuses on the line side of TEMUX-84.
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
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PM
Workaround
:52
:48
Note that the following recommendations are specific for systems using the TEMUX-84 in 19.44
MHz TelecomBus to 77.76 MHz SBI bus. For systems that use 77.76 MHz TelecomBus to 19.44
MHz SBI, the equal but opposite workarounds as below apply.
11
There are three possible workarounds to avoid timing violations in your OC-12/STM-4 system:
20
02
Workaround #1
tem
be
r,
Use 77.76 MHz TelecomBus and 77.76 MHz SBI Bus. Avoid mixing 19.44 MHz with 77.76
MHz. Follow the recommendations in section 12.2 of the datasheet.
Workaround #2:
9S
ep
Use buffering delay logic on 1 Add bus and 1 Drop bus to eliminate timing violations.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
For one of four 19.44 MHz TelecomBus Add buses and one of four 19.44 MHz TelecomBus
Drop, buffering logics needs to be added to the bus to prevent timing violations. The resulting
bus structure is shown in Figure (shown with SPECTRA-4x155). Note that this workaround has
not been tested but is believed to avoid the timing violations.
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
Released
:48
:52
LREFCLK1
LREFCLK2
LREFCLK3
LREFCLK4
11
TIMING
GENERATION
PM
SREFCLK
SDC1FP
tem
be
r,
20
02
ADD Frame Pulse
Drop Frame Pulse
ACK
DCK
LREFCLK
LAC1
ep
DFP
9S
AC1J1V11
APL1
ADP1
AD[7:0]
hu
rsd
ay
,1
DC1J1V11
DPL1
DDP1
DD[7:0]
io
nT
AC1J1V12
APL2
ADP2
AD[15:8]
liv
DFF
fo
SPECTRA
4x155
ett
DC1J1V12
DPL2
DDP2
DD[15:8]
LREFCLK3
LDC1J1V1
LDPL
LDDP
LDDATA [7:0]
LREFCLK
LAC1
LAC1J1V1
LAPL
LADP
LADATA[7:0]
LDC1J1V1
LDPL
LDDP
LDDATA [7:0]
ef
uo
AC1J1V13
APL3
ADP3
AD[23:16]
LAC1J1V1
LAPL
LADP
LADATA[7:0]
DC1J1V13
DPL3
DDP3
DD[23:16]
LDC1J1V1
LDPL
LDDP
LDDATA [7:0]
TEMUX-84
#2
TEMUX-84
#3
LREFCLK
LAC1
LREFCLK2
AC1J1V14
APL4
ADP4
AD[31:24]
TEMUX-84
#1
LREFCLK
LAC1
inv
yV
db
Do
wn
loa
de
LAC1J1V1
LAPL
LADP
LADATA[7:0]
DFF
DC1J1V14
DPL4
DDP4
DD[31:24]
LAC1J1V1
LAPL
LADP
LADATA[7:0]
LDC1J1V1
LDPL
LDDP
LDDATA [7:0]
TEMUX-84
#4
Figure 3: Delay Flip Flops Implementation
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Document ID: PMC-2020509, Issue 2
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TEMUX-84 Production Release Errata
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Workaround #3:
11
:52
:48
Implement the 19.44 MHz TelecomBus to 77.76 MHz SBI bus is using an FPGA rather than
delay logic. Each of the four TEMUX-84s sharing the common 77.76 MHz SBI bus will be
given the same LREFCLK. This causes all four TEMUX-84 devices to have the same internal
phase alignment at the TelecomBus interfaces.
20
02
In turn, this requires that each of the four TEMUX-84s have the same phase alignment at their
SBI Bus interfaces. There are two equivalent ways to accomplish this:
tem
be
r,
1. All four TEMUX-84s share the same SBI Bus frame pulses and share the same
SSTM[1:0] settings, OR
2. Providing four unique frame pulses and four unique SSTM[1:0] bits settings.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
The result from either of the two options is that the four TEMUX-84s will sample/update the SBI
Bus during the same timeslots. An FPGA is required on the system side SBI interface to delay
the data to/from each TEMUX-84 by a unique number of cycles (0,1,2,3). This allows the linklayer device to update/sample data to/from the four TEMUX-84s at unique time intervals. On the
contrary, the four TEMUX-84s update/sample data at the same time intervals. See Figure 3
below for a simplified illustration of this set-up. PMC-Sierra, Inc has successfully tested this
implementation.
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Document ID: PMC-2020509, Issue 2
23
SREFCLK
:52
11
02
tem
be
r,
20
SDC1FP
SAC1FP
AD[7:0]
DD[7:0]
SDC1FP
SAC1FP
AD[7:0]
DD[7:0]
,1
9S
F-336
ay
F
P
G
A
SDC1FP
SAC1FP
ep
AD[7:0]
DD[7:0]
AD[7:0]
DD[7:0]
uo
fo
T-84
#4
BUS
rsd
T-84
#3
REFCLK
hu
SREFCLK
SBI
nT
T-84
#2
SDC1FP
SAC1FP
io
SREFCLK
AD[7:0]
DD[7:0]
ett
T-84
#1
SDC1FP
SAC1FP
liv
SREFCLK
:48
Timing
Generation
PM
TEMUX-84 Production Release Errata
Released
ef
Figure 3: FPGA Implementation
yV
inv
This errata item only applies where four TEMUX-84 devices are used, i.e. in OC-12/STM-4
designs. In such cases, the four TEMUX-84s share a common SBI bus with link-layer devices.
db
Performance with Workaround
Do
wn
loa
de
If one of the three suggested workarounds is implemented, no timing violations should occur in
your OC-12/STM-4 system. Preserving timing this way and following Section 12.2.2 of the
TEMUX-84 datasheet will guarantee data integrity.
Performance without Workaround
If a single 19.44 MHz LREFCLK is fed into the four TEMUX-84s sharing a common 77.76 MHz
SBI bus, timing violations will occur. It is highly recommended to use 77.76 MHz TelecomBus
and 77.76 MHz SBI Bus concurrently in OC-12/STM-4 systems.
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2.12 TEMUX-84 supports line side SBI bus
11
:52
:48
The TEMUX-84 has fully been validated to support line side SBI bus. This is a new interface in
addition to the line side 19.44/77.76 MHz TelecomBus and the DS3/E3 LIU interface. The line
side SBI feature allows additional connectivity to PM4318 OCTLIU and PM4319 OCTLIU-SH,
PMC-Sierra’s High-Density T1/E1/J1 Line Interface Units.
20
02
Further, the TEMUX-84’s well-known system-side SBI bus remains available to connect to PMCSierra’s link-layer solutions including AAL1gator, FREEDM, SBS and IMA devices.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
Full details are available in Appendix A: “Using the Line Side SBI Bus of TEMUX-84”. PMCSierra’s Knowledge Base (www.pmc-sierra.com/techsupport/kb/) can also be consulted for
details.
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TEMUX-84 Production Release Errata
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TEMUX-84 Documentation Issues
PM
3
11
:52
:48
This section lists documentation errors found in Issue 7 of the TEMUX-84 Data Sheet (PMC1991437) and in Issue 5 of the TEMUX-84 Register Description (PMC-2000034). It also
highlights any major changes from previous data sheet and register description documents that
may be of particular interest to existing TEMUX-84 customers.
02
Notification of Changes in AC Parameters
20
3.1
ep
Parameters
tPTELOE
,1
9S
Parameter Description
LREFCLK rising to all
Telecom Bus tristateable
Outputs going valid from
tristate (19.44MHZ)
SREFCLK to All SBI DROP
BUS Outputs Valid
(19.44MHZ)
SREFCLK to All SBI DROP
BUS Outputs Tristate
(19.44MHZ)
tem
be
r,
TEMUX-84 characterization has recommended the following changes to AC parameters
originally stated in Issue 5 of the TEMUX-84 Data Sheet (PMC-1991437). These changes are
reflected in Issue 7 of the datasheet.
Change Spec Max from 15 ns to 17ns
(Table 59)
Change Spec Max from 15ns to 16ns
(Table 59)
ett
SLCÒ96 support must be implemented using SBI bus
liv
3.2
io
nT
hu
tZSBIDROP
rsd
ay
tPSBIDROP
Change reflected in Issue 6 of Datasheet
Changed Spec Max from 13ns to 14ns
(Table 59)
ef
uo
fo
All references to SLCÒ96 using H-MVIP implementation in the TEMUX-84 datasheet should be
ignored. The synchronous SBI bus on the TEMUX-84’s system side must be used when
interfacing to an FPGA for data link insertion/extraction.
yV
Transmux mode must meet Section 12.2.2 timing specification
db
3.3
inv
Refer to PMC- 2020592: “TEMUX-84 SBI FPGA for SLCÒ96 Applications” for details.
Do
wn
loa
de
When configuring TEMUX-84 for transmultiplexing (“transmux”) mode, keep in mind the
following recommendations:
1. When using a 77.76MHz LREFCLK, use the same LREFCLK for SREFLCK.
2. Generate an external frame pulse that is 38,880 SREFCLK cycles (2 kHz) or set the
SDC1FPMSTR=1 in Register 0x1C1 to configure the TEMUX-84 to generate the frame
pulse. Tie this frame pulse to LAC1 and SDC1FP.
3. Follow Table 15 in Section 12.2.3 of the TEMUX-84 datasheet. This table shows that
LSTM[1:0] and SSTM[1:0] should be equal when LAC1 and SDC1FP are locked.
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Generating an external frame pulse is recommended in all modes where at least one of the buses
is operating at 77.76 MHz.
:48
Transmux mode: T1/E1 Mapper configured before SONET/SDH
blocks
11
:52
3.4
FI_EMPTY_ENBL bit works for all SPE_TYPEs
ep
3.5
tem
be
Refer to Section 5.7 of the TEMUX-84 Programmer’s Guide.
r,
20
02
Transmultiplexing (“Transmux”) mode in the TEMUX-84 must be configured according to the
TEMUX-84 Programmer’s Guide to avoid loss of pointer errors. The line side mode must be set
for T1/E1 or DS3 mapping before the remainder of the blocks are configured. The final
requirement for Transmux mode must be switching the line mode to DS3 LIU.
9S
Location
rsd
ay
,1
In Register 0x01DF: Extract External ReSynch Interrupt Status, the FI_EMPTY_ENBL bit
description implies this bit only affects T1/E1 mode. This bit is intended to work for all
SPE_TYPEs. See modified wording below.
hu
Original Wording
ett
io
nT
If FI_EMPTY_ENBL is logic 1, no data bytes are emitted when a link FIFO empties. If
FI_EMPTY_ENBL is logic 0, stuff bytes are generated when a FIFO is empty, thus causing slips.
This bit is used globally to control the behavior for all T1/E1 links.
fo
liv
Replacement Wording
INSBI FIFO Underrun Status Register correction
yV
3.6
inv
ef
uo
If FI_EMPTY_ENBL is logic 1, no data bytes are emitted when a link FIFO empties. If
FI_EMPTY_ENBL is logic 0, stuff bytes are generated when a FIFO is empty, thus causing slips.
This bit is used globally to control the behavior for all SPE_TYPEs.
Do
wn
loa
de
db
The description for Register 0x01E1: INSBI FIFO Underrun Status makes incorrect references to
FIFO “overruns” and “overflows”. These references should refer to “underruns” instead.
All original statements equally apply for underruns.
3.7
Correction to BSDL version number
In Section 11.1, Table 11 of the TEMUX-84 datasheet, the BSDL version number should read
“0x2”, rather than “0x0”.
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LAOE/LATPL is a tristate output
PM
3.8
TSADDR is 5 bits
11
3.9
:52
:48
In the Pin Description section for pin AB11, LAOE/LATPL is a “tristate output”. It is only listed
as “output” in Issue 7 of the TEMUX-84 datasheet.
02
In Registers 0x0050, 0x0068, 0x0100, 0x0150, TSADDR should be changed to TSADDR[4:0].
r,
20
3.10 TRIB_ENBL bit should be ENBL bit
tem
be
In Register 0x01E1, 0x01E2, 0x01D1, 0x0D2, TRIB_ENBL bit should read “ENBL” bit.
ep
3.11 FIFO underrun and overrun blocking description
ay
,1
9S
The following text should be appending to Registers 0x09C1: Byte Synchronous Mapping FIFO
Underrun Interrupt Status and Register 0x09C2: Byte Synchronous Mapping FIFO Overrun
Interrupt Status in the TEMUX-84 Register Description document:
nT
hu
rsd
This Underrun/Overrun interrupt register is the output of a priority encoder of the
under/overrun history of all links. The most significant links have the highest priority
and will be reported first if under/overruns simultaneously occur on multiple links.
ett
io
If bit 0 is logic zero, no links have under/overrun since the last read, and all pending
under/overrun notifications have been reported. Bits 1-7 should be ignored.
ef
uo
fo
liv
If bit 0 is logic one, the register contents are valid, and indicate a link has under/overrun
since the last read, or a prior notification was still pending. Continue reading this
register, recording all entries, until bit 0 is zero, indicating that no more pending entries
are present.
db
yV
inv
Note that if a tributary is misbehaving so that it frequently under/overruns, the reporting
of the multiple under/overruns can prevent the reporting of under/overruns on lower
priority links. Such misbehaving links should be disabled (TRIB_ENBL=0) to obtain the
complete FIFO under/overrun history.
Do
wn
loa
de
3.12 INSBI Control register bit is Reserved
In Register 0x01E0: INSBI Control, Bit 1 should be labelled as “Reserved” not “Unused”. The
bit type should be “R/W” and the Default value “0”.
3.13 APAGE bit in Register 0x0E61
In the bit description for the PAGE bit in Register 0xE62, an incorrect reference is made to the
APAGE bit in Register 0x061H. The APAGE bit is in Register 0x0E61.
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3.14 SREFCLK specification in serial DS3 mode
:52
:48
Serial DS3 mode refers to the TEMUX-84 using the DS3/E3 LIU interface rather than the
TelecomBus (mapper) interface on the line side.
11
The following statement should be appended to the SREFCLK pin description (pin C10):
02
When operating in serial DS3 mode, the SREFCLK can be +/-50ppm.
r,
20
3.15 DS3 Looptiming is not hitless
tem
be
In Register 0x0201 + 0x100*N: DS3 and E3 Master Data Source, the DS3 LOOPT bit description
should be clarified with this additional statement:
9S
ep
The transition from internal to looptiming is not hitless. This will not cause any long-term
problems.
rsd
ay
,1
3.16 Demapped DS3 clock must be de-jittered for unstructured DS3
CES using SRTS
nT
hu
The recovered DS3 output clock when demapped from SONET STS-1 payload must be dejittered when connecting TEMUX-84 to the PM73122 AAL1gator-32 for unstructured DS3 CES
(circuit emulation) using SRTS. This is achieved with an external DS3 jitter attenuator (JAT).
liv
ett
io
Refer to Application Note for details: PMC-2020180 “Configuring SBI Compatible Devices”,
Section 4.3.5: Unstructured CES Clocking Modes.
fo
3.17 T1/E1 HDLC (THDL) minimum packet size is 2 bytes
inv
ef
uo
In Section 12.10 of the TEMUX-84 datasheet: Using the Internal T1/E1 Data Link Transmitter,
the minimum packet size for THDL is 2 bytes. This was not previously documented.
yV
3.18 Initialization time for T1/E1 Transmitter blocks
Do
wn
loa
de
db
When the T1/E1 Transmitter (TRAN) blocks come out of reset, time is needed for their RAMs to
get fully initialized to '0'. After a reset of the TEMUX-84, each block of indirect RAM will
complete a built in self-test (BIST). During the RAM BIST, the BUSY bit will be logic '1'
indicating that indirect accesses to the indirect RAM are not permitted.
During the RAM BIST of the T1/E1 TRAN indirect RAM, the CBUSY bit of Register 0x0168
will NOT be logic '1'. Indirect accesses initiated by writing the T1/E1 Transmitter Indirect Status
Register (0x0168) will appear to be permitted but any indirect access to the TRAN indirect RAM
during the RAM BIST will not be successful.
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PM
The time required for the TRAN RAM BIST to complete is 26.39us (513 19.44MHz SREFCLK
cycles or 2052 77.76MHz SREFCLK cycles) after the device comes out of reset. Indirect
accesses to the TRAN RAM during this time should not be attempted, as they will not be
successful.
11
3.19 DS3 and E3 Diagnostic Loopback correction
20
02
The following sentence should be removed from Section 12.14: DS3 and E3 Diagnostic
Loopback:
tem
be
r,
“While this mode is active, AIS may be substituted for the DS3 payload being transmitted
on the TPOS/TDAT and TNEG/TMFP outputs.”
ep
The diagram was fixed in Issue 7 of the TEMUX-84 datasheet so this sentence is no longer valid.
9S
3.20 ETSEN bit description clarified
ay
,1
In Register 0x0702: SONET/SDH Master Egress Configuration, the following statement should
be removed from the ETSEN bit description:
hu
rsd
“This is necessary when the egress tributaries are being processed by the egress VTPP
block as controlled by the EVTPPBYP register bit.”
io
nT
3.21 Register default differs from actual chip value
ett
Default value in the register description is different from the actual default value on the chip.
fo
liv
Register Description documents 0x1D9 = 0x64 default
uo
Actual value 0x1D9 = 0xFE default
inv
ef
The actual value when Register 0x1D9 is read will be 0xFE.
db
Location
yV
3.22 TFPI/TMFPI[3:1] bit clarification
Do
wn
loa
de
Pin description of TFPI/TMFPI[3:1] in Issue 7 of the TEMUX-84 datasheet.
Original Wording
TFPI/TMFPI[3:1] are sampled on the rising edge of the associated TICLK. TDATI[3:1] can be
configured to be sampled on the falling edge of the associated TICLK by setting the TDATIFALL
bit to 1 in the DS3 and E3 Master Unchannelized Interface Options register.
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Replacement Wording
11
:52
:48
TFPI/TMFPI[3:1] are sampled on the rising edge of the associated TICLK. TFPI/TMFPI[3:1]
can be configured to be sampled on the falling edge of the associated TICLK by setting the
TDATIFALL bit to 1 in Register 0x0202 + 0x100*N: DS3 and E3 Master Unchannelized
Interface Options.
02
3.23 TGAPCLK diagram is 1 pulse wider
tem
be
r,
20
Figure 53: Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK of the TEMUX-84
datasheet, Issue 7 shows a timing diagram for the gapped TGAPCLK. It shows TGAPCLK
gapping out what is supposed to be the first 12 bits of the E3 frame. The original diagram
incorrectly shows only 11 bits being gapped out instead of 12.
Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
In fact, the gapped clock in the diagram should be 1 pulse wider in Figure 53.
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Appendix A: Configuring Line Side SBI on TEMUX-84
PM
4
:52
:48
Scope
20
02
11
The PM8316 High Density T1/E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers
(TEMUX-84) is a feature-rich device for use in any applications requiring high-density link
termination over T1 and E1 (G.747) channelized DS3 or T1 and E1 channelized SONET/SDH
facilities.
tem
be
r,
The currently available TEMUX-84 datasheet supports the following interfaces:
Line Side: TelecomBus (operating at either 19.44MHz or 77.76MHz) or DS3 LIU
·
System Side: Either H-MVIP or SBI Bus (operating at either 19.44MHz or 77.76MHz)
ep
·
,1
9S
This Appendix describes the hardware and software implementation to support one additional line
side interface, the SBI Bus option.
nT
hu
rsd
ay
This interface enables high-density, byte-serial SBI connectivity of TEMUX-84 to PMC-Sierra’s
high-density T1/E1/J1 line interface unit: PM4318 OCTLIU and PM4318 OCTLIU-SH. Further,
TEMUX-84’s system-side SBI bus will still be available to seamlessly connect to the industry’s
highest-density link-layer devices, offered by PMC-Sierra, Inc. (S/UNI-IMA, FREEDM,
AAL1gator, SBS family of devices).
uo
fo
liv
ett
io
This line side SBI feature has been fully validated at PMC-Sierra and will hence be supported by
our Applications Group. The production-release TEMUX-84 Software Device Driver will not
include support for line side SBI. We recommend reference to Section 4 of this document for
register accesses required.
Do
wn
loa
de
db
yV
inv
ef
Please contact [email protected] for detailed questions.
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Document ID: PMC-2020509, Issue 2
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PM
Hardware
:52
:48
For the TEMUX-84 to use its line side SBI interface to connect with PM4318 OCTLIU or
PM4319 OCTLIU-SH, the pin connection diagram shown below in Figure 4 must be used:
OCTLIU
11
TEMUX84
20
02
19.44MHz
LREFCLK
tem
be
r,
LAC1
NC
LAC1J1V1
ep
LADATA[7:0]
9S
LADP
,1
LAOE/LATPL
LAV5
rsd
hu
LDC1J1V1
nT
LDDATA[7:0]
io
LDDP
ett
LDTPL
AC1FP
ADATA[7:0]
ADP
APL
AV5
DC1FP
DDATA[7:0]
DDP
DPL
DV5
liv
LDV5
C1FPOUT
ay
NC
LAPL
REFCLK
inv
ef
uo
fo
L77
Do
wn
loa
de
db
yV
Figure 4: Pin Connection Diagram between TEMUX-84 (line side) and OCTLIU
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Software
11
:52
:48
Using TEMUX-84’s in line side SBI mode essentially means that the device is acting as a
T1/E1/J1 Framer only. This line side interface will typically be connected to multiple PMCSierra’s T1/E1/J1 line interface units, PM4318 OCTLIU or PM4319 OCTLIU-SH.
r,
20
02
The line side SBI bus is based upon the Byte-Synchronous Mapper mode, currrently documented
in the TEMUX-84 Register Descriptions (PMC-2000034). Therefore, one would essentially
configure the TEMUX-84 for Byte Synchronous Mapper mode and with the following
modifications to software, the Byte-Synchronous Mappers will simulate the SBI bus format:
tem
be
1) Set IVTPPBYP=1 in Register 0x0704
ep
2) Set EVTPPBYP=1 in Register 0x0701
9S
3) Set LAJ1EN=1 in Register 0x0702.
ay
hu
rsd
6) Set ITUG3=1 in Register 0x0704
7) Set OTUG3=1 in Register 0x0704
,1
5) Set LAV1EN=1 in Register 0x0702
io
nT
8) Set Reserved bit 7 in Register 0x0700 to '1'
ett
9) Set LATPLSEL=1 in Register 0x704
fo
liv
10) Set OTUG3 in Register 0x0703
uo
11) Set EPTRBYP[3:1]= ‘111’ in Register 0x0704
inv
ef
When enabling the individual tributaries in the Byte Synchronous Mapper:
yV
1) Set the TRIB_TYP bits to ‘01’
db
2) Set ENBL=1
Do
wn
loa
de
When enabling the individual tributaries in the Byte Synchronous Demapper:
1) Set ENBL=1.
The above-listed register accesses will enable connectivity between the TEMUX-84 device and
multiple OCTLIU devices over TEMUX-84’s line side SBI interface. The production-release
TEMUX-84 Software Device Driver will not include support for line side SBI.
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Do
wn
loa
de
db
yV
inv
ef
uo
fo
liv
ett
io
nT
hu
rsd
ay
,1
9S
ep
tem
be
r,
20
02
11
:52
:48
PM
Notes
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2020509, Issue 2
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