2GHz ANY DIFF. IN-TO-LVPECL ULTRA Precision Edge™ LOW-JITTER AND SKEW 1:4 FANOUT SY89831U FINAL BUFFER/TRANSLATOR W/ INTERNAL TERMINATION FEATURES ■ Guaranteed AC performance over temperature and voltage • > 2.0GHz fMAX • < 20ps within-device skew • < 225ps rise/fall times ■ Low jitter design • < 1ps(rms) cycle-to-cycle • < 10ps(pk-pk) total jitter ■ Unique input termination and VT pin for DC-coupled and AC-coupled inputs (CML, HSTL, and LVPECL) ■ Fully differential I/O design ■ Low power 2.5V and 3.3V power supply ■ TTL/CMOS compatible enable input ■ Wide operating temperature range: –40°C to +85°C ■ Available in 16-pin (3mm × 3mm) MLF™ package Precision Edge™ DESCRIPTION The SY89831U is a high-speed, 2GHz differential LVPECL 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20ps (5ps typ.) over supply voltage and temperature. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF–AC reference output is included for AC-coupled applications. The SY89831U is a part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, consult Micrel’s website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators and clock generators. APPLICATIONS ■ ■ ■ ■ Processor clock distribution SONET clock distribution Fibre Channel clock distribution Gigabit Ethernet clock distribution FUNCTIONAL BLOCK DIAGRAM TYPICAL PERFORMANCE 155MHz Output Q0 /Q0 Output Swing (150mV/div.) /Q Q1 IN VT /IN /Q1 50Ω 50Ω Q2 TA = 25°C VCC = 3.3V VEE GND VIN = 800mV Q /Q2 EN VREF—AC D Q Q3 TIME (1ns/div.) /Q3 Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. Rev.: C 1 Amendment: /0 Issue Date: February 2003 Precision Edge™ SY89831U Micrel PACKAGE/ORDERING INFORMATION /Q0 Q0 VCC GND Ordering Information 16 15 14 13 Q1 1 12 IN /Q1 2 11 Q2 /Q2 3 4 10 9 VT VREF–AC /IN Part Number Package Type Operating Range Package Marking SY89831UMI MLF-16 Industrial 831U SY89831UMITR* MLF-16 Industrial 831U *Tape and Reel Q3 /Q3 VCC EN 5 6 7 8 16-Pin MLF™ PIN DESCRIPTION Pin Number Pin Name 15, 16 1, 2, 3, 4, 5, 6 (Q0, /Q0) to (Q3, /Q3) Pin Function LVPECL Differential (Outputs): Terminate to VCC–2V. See “Termination Recommendations” section. Unused output pairs may be left floating with no impact on jitter. 8 EN TTL/CMOS Compatible Synchronous Enable: When EN goes LOW, Q outputs will go LOW and /Q outputs will go HIGH on the next LOW transition at D inputs. Input threshold is VCC/2V. Includes a 25kΩ pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal (IN, /IN). 9, 12 /IN, IN 10 VREF–AC Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC–coupled applications. Maximum sink/source current is 0.5mA. See “Input Interface Applications” section. When using VREF–AC, bypass with a 0.01µF capacitor to VCC. 11 VT Termination Center-Tap: For CML inputs, leave this pin floating. Otherwise, see Figures 2a to 2e in “Input Interface Applications” section. 13, Exposed Pad GND Ground. Exposed pad is internally connected to GND and must be connected to a ground plane for proper thermal operation. 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors. Differential Clock (Inputs): Internal 50Ω termination resistors to VT pin. See “Input Interface Applications” section. TRUTH TABLE IN /IN EN Q /Q 0 1 1 0 1 1 0 1 1 0 0 0(1) 1(1) X Note 1. X On next negative transition of the input signal (IN). 2 Precision Edge™ SY89831U Micrel Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) ............................... –0.5V to VCC +0.5V Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Input Current (IN, /IN) ............................................... ±50mA VT Current (IVT) ....................................................... ±100µA Input Sink/Source Current (VREF–AC), Note 3 ......... ±0.5mA Lead Temperature (soldering, 10sec.) ...................... 220°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage Range .......................... +2.375V to +3.63V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance MLF™ (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF™ (ΨJB), Note 4 Junction-to-Board ............................................ 32°C/W Note 1. Note 2. Note 3. Note 4. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Due to the limited drive capability use for input of the same package only. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. DC ELECTRICAL CHARACTERISTICS(Note 1, 2) TA = –40°C to +85°C Symbol Parameter VCC Power Supply Voltage Range ICC Power Supply Current RIN Differential Input Resistance (IN, /IN) VIH Input HIGH Voltage (IN, /IN) Note 3 VIL Input LOW Voltage (IN, /IN) Note 3 VIN Input Voltage Swing VDIFF_IN |IIN| Note 1. Note 2. Note 3. Condition Min Typ Max Units 3.63 V 47 70 mA 100 120 Ω 1.2 VCC V 0 VCC–0.1 V Note 3, see Figure 1a, and 1b. VT floating for VIN (max.) 0.1 2.8 V Differential Input Voltage Swing, see Figure 1a, and 1b. Note 3 0.2 Input Current (IN, /IN) Note 3 2.375 No load, maximum supply voltage 80 V 35 mA The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product ony. Due to the internal termination (see “Differential Input” ) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit. LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS(Note 1) VCC = 2.375V to 3.63V; VEE = 0V; TA = –40°C to +85°C Symbol Parameter VIH Input HIGH Voltage VIL Max Units 2.0 VCC V Input LOW Voltage 0 0.8 V IIH Input HIGH Current 20 –125 µA IIL Input LOW Current –300 µA Note 1. Condition Min Specification for packaged product ony. 3 Typ Precision Edge™ SY89831U Micrel 2.5V (100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(Note 1, 2) VCC = 2.5V ±5%; VEE = 0V; TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage RL = 50Ω to VCC–2V 1355 1480 1605 mV VOL Output LOW Voltage RL = 50Ω to VCC–2V 555 680 805 mV VOUT Output Voltage Swing see Figure 1a, and 1b 550 800 1050 mV VDIFF_OUT Differential Output Voltage Swing see Figure 1a, and 1b 1100 1600 2100 mV Note 1. Note 2. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Parameters are for VCC = 2.5V. They vary 1:1 with VCC. Specification for packaged product only. 3.3V (100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(Note 1, 2) VCC = 3.3V ±10%; VEE = 0V; TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage RL = 50Ω to VCC–2V 2155 2280 2405 mV VOL Output LOW Voltage RL = 50Ω to VCC–2V 1355 1480 1605 mV VREF–AC Reference Voltage, Note 2 1755 1875 1975 mV Note 1. Note 2. Note 3. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Single-ended input operation is limited to VCC ≥ 3.0V. 4 Precision Edge™ SY89831U Micrel AC ELECTRICAL CHARACTERISTICS(Note 1, 2) VCC = 2.375 to 3.63V; VEE = 0V; TA = –40°C to +85°C, output loading is 50Ω to VCC–2V, unless otherwise noted. Symbol Parameter Condition Min Typ fMAX Maximum Frequency Output Swing ≥ 450mV 2.0 2.5 tPLH tPHL Propagation Delay-to-Output (Differential) Input Swing: 100mV tSKEW Within-Device Skew (Differential) Note 3 Input Swing: 800mV 250 Max Units GHz 390 0 ps 350 450 ps 5 20 ps 150 ps Part-to-Part Skew (Differential) tS Set-Up Time (EN to IN, /IN) Note 4 300 ps tH Hold Time (EN to IN, /IN) Note 4 300 ps tJITTER Cycle-to-Cycle Jitter (rms) Note 5 1 ps(rms) Total Jitter Note 6 10 ps(pk-pk) 225 ps t r, t f Output Rise/Fall Times (20% to 80%) 70 150 Note 1. Measured with 400mV input signal, 50% duty cycle, all loading with 50Ω to VCC–2V. Output swing is ≥ 450mV. Note 2. Specification for packaged product only. Note 3. Skew is measured between outputs under identical transitions. Note 4. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold times do not apply. Note 5. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn –Tn+1, where T is the time between rising edges of the output signal. Note 6. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. TIMING DIAGRAM EN VCC/2 tS VCC/2 tH /IN IN VIN tPLH, tPLH /Q VOUT Swing Q DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING QOUT QOUT VIN, VOUT 800mV (typical) VDIFF_IN, VDIFF_OUT 1.6V (typical) /QOUT /QOUT Figure 1a. Single-Ended Swing Figure 1b. Differential Swing 5 Precision Edge™ SY89831U Micrel TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, VEE = GND, TA = 25°C, unless otherwise stated. Output Swing vs. Frequency 390 PROPAGATION DELAY (ps) 900 AMPLITUDE (mV) 800 700 600 500 400 300 200 100 0 0 380 370 360 350 340 330 320 310 300 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 3000 Propagation Delay vs. Input Voltage Swing 25 425 400 375 350 15 10 5 325 300 100 t SKEW vs. Temperature 20 tSKEW (ps) PROPAGATION DELAY (ps) 450 1000 2000 FREQUENCY (MHz) Propagation Delay vs. Temperature 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 300 500 700 900 INPUT VOLTAGE SWING (V) 6 Precision Edge™ SY89831U Micrel FUNCTIONAL CHARACTERISTICS VCC = 3.3V, VEE = 0V, VIN = 800mV, TA = 25°C, unless otherwise stated. 622MHz Output 155MHz Output /Q Output Swing (150mV/div.) Output Swing (150mV/div.) /Q Q Q TIME (200ps/div.) TIME (1ns/div.) 1GHz Output Output Swing (150mV/div.) /Q Q TIME (150ps/div.) 7 Precision Edge™ SY89831U Micrel FUNCTIONAL BLOCK DIAGRAM Q0 /Q0 Q1 IN VT /IN /Q1 50Ω 50Ω Q2 /Q2 EN D Q Q3 VREF—AC /Q3 DIFFERENTIAL INPUT VCC IN 50Ω VT 50Ω /IN SY89831U Figure 2. Input Stage 8 Precision Edge™ SY89831U Micrel INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC VCC VCC D PECL D D /D PECL SY89831U /D Rpd CML /D VCC Rpd VT SY89831U SY89831U VCC —2V 0.01µF VT VREF—AC 50Ω VBB Figure 3a. DC-Coupled PECL Input Interface VCC VCC VT For 2.5V, Rpd = 50Ω For 3.3V, Rpd = 100Ω Figure 3b. AC-Coupled PECL Input Interface VCC VCC D IN CML HSTL /D /IN SY89831U SY89831U VCC NC 0.01µF VT VREF—AC VT NC VREFÐAC 0.01µF Figure 3d. AC-Coupled CML Input Interface Figure 3e. HSTL Input Interface 9 Figure 3c. DC-Coupled CML Input Interface Precision Edge™ SY89831U Micrel OUTPUT TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω +3.3V +3.3V +3.3V Z = 50Ω Z = 50Ω ZO = 50Ω 50Ω R2 82Ω 50Ω source R2 82Ω Vt = VCC —2V destination 50Ω Rb C1 0.01µF (optional) Figure 5. Three-Resistor “Y-Termination” Figure 4. Parallel Termination—Thevenin Equivalent Note 1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω Note 1. Power-saving alternative to Thevenin termination. Note 2. For +3.3V systems: R1 = 130Ω, R2 = 82Ω Note 2. Place termination resistors as close to destination inputs as possible. Note 3. Rb resistor sets the DC bias voltage, equal to Vt. For +2.5V systems Rb = 39Ω. For +3.3V systems Rb = 46Ω to 50Ω. Note 4. +3.3V +3.3V Q C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. +3.3V R1 130Ω R1 130Ω V = VCC —1.3V R4 t +3.3V 1kΩ ZO = 50Ω /Q R3 1.6kΩ Vt = VCC —2V R2 82Ω R2 82Ω Figure 6. Terminating Unused I/O Note 1. Note 2. Note 3. Unused output (/Q) must be terminated to balance the output. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ. For +3.3V systems: R1 = 130Ω, R2 = 82Ω, R3 = 1.6kΩ, R4 = 1k. Unused output pairs (Q and /Q) may be left floating. RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89830U 1:4 LVPECL Fanout Buffer w/2:1 Mux Input www.micrel.com/product-info/products/sy89830u.shtml SY89832U 2GHz Ultra Low-Jitter and Skew 1:4 LVPECL Fanout Buffer/Translator w/Internal Termination www.micrel.com/product-info/products/sy89832u.shtml SY89833U 2GHz Any Diff. In-to-LVDS Out 1:4 Fanout Buffer/Translator w/Internal Termination www.micrel.com/product-info/products/sy89833u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml 16-MLF™ Manufacturing Guidelines Exposed Pad Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0301.pdf 10 Precision Edge™ SY89831U Micrel 16 LEAD EPAD MicroLeadFrame™ (MLF-16) 0.42 +0.18 –0.18 0.23 +0.07 –0.05 0.85 +0.15 –0.65 0.01 +0.04 –0.01 3.00BSC 1.60 +0.10 –0.10 0.65 +0.15 –0.65 0.20 REF. 2.75BSC 0.42 PIN 1 ID +0.18 –0.18 N 16 1 1 0.50 DIA 2 2 2.75BSC 3.00BSC 3 3 1.60 +0.10 –0.10 4 4 12° max 0.5 BSC 0.42 +0.18 –0.18 SEATING PLANE 0.40 +0.05 –0.05 1.5 REF BOTTOM VIEW TOP VIEW CC 0.23 +0.07 –0.05 CL 4 0.01 +0.04 –0.01 SECTION "C-C" SCALE: NONE 0.5BSC 1. 2. 3. 4. DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS FOR EVEN TERMINAL/SIDE Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Note 2. Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 11