Precision Edge® 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89874U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89874U FANOUT BUFFER WITH INTERNAL TERMINATION Micrel, Inc. FEATURES ■ Integrated programmable clock divider and 1:2 fanout buffer ■ Guaranteed AC performance over temperature and voltage: • > 2.5GHz fMAX • < 250ps tr/tf • < 15ps within device skew ■ Low jitter design: • < 10psPP total jitter • < 1psRMS cycle-to-cycle jitter ■ Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL ■ TTL/CMOS inputs for select and reset ■ 100k EP compatible LVPECL outputs ■ Parallel programming capability ■ Programmable divider ratios of 1, 2, 4, 8 and 16 ■ Low voltage operation 2.5V or 3.3V ■ Output disable function ■ –40°C to 85°C temperature range ■ Available in 16-pin (3mm × 3mm) MLF® package Precision Edge® DESCRIPTION This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). TYPICAL PERFORMANCE APPLICATIONS ■ SONET/SDH line cards ■ Transponders ■ High-end, multiprocessor sensors OC-12 to OC-3 Translator/Divider FUNCTIONAL BLOCK DIAGRAM LVDS 622MHz Clock In Divide-by-4 LVPECL 155.5MHz Clock Out S2 /RESET Enable FF 622MHz In Q0 Enable MUX IN /Q0 MUX Q1 IN Divided by 2, 4, 8 or 16 R0 VT R1 /IN /Q1 /IN Q0 155.5MHz Out S0 Decoder S1 VREF-AC /Q0 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. M9999-020707 [email protected] or (408) 955-1690 Rev.: D 1 Amendment: /0 Issue Date: February 2007 Precision Edge® SY89874U Micrel, Inc. S0 S1 VCC GND PACKAGE/ORDERING INFORMATION 16 15 14 13 Ordering Information(1) /Q0 2 11 VT Q1 3 10 VREF-AC /Q1 4 9 6 7 8 VCC IN /RESET 12 NC 1 S2 Q0 5 Package Operating Type Range Part Number /IN Package Marking Lead Finish SY89874UMI MLF-16 Industrial 874U Sn-Pb SY89874UMITR(2) MLF-16 Industrial 874U Sn-Pb SY89874UMG(3) MLF-16 Industrial 874U with Pb-Free bar line indicator NiPdAu Pb-Free SY89874UMGTR(2, 3) MLF-16 Industrial 874U with Pb-Free bar line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 16-Pin MLF® (MLF-16) PIN DESCRIPTION Pin Number Pin Name Pin Function 12, 9 IN, /IN 1, 2, 3, 4 Q0, /Q0 Q1, /Q1 16, 15, 5 S0, S1, S2 6 NC 8 /RESET /DISABLE LVTTL/CMOS Logic Levels: Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected. Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a synchronous disable/enable function. The reset and disable function occurs on the next high-to-low clock input transition. Input threshold is VCC/2. 10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.). Used for AC-coupled applications only. Decouple the VREF-AC pin with a 0.01µF capacitor. See “Input Interface Applications” section. 11 VT 7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor. 13 GND Ground. Differential Input: Internal 50Ω termination resistors to VT input. Flexible input accepts any differential input. See “Input Interface Applications” section. Differential Buffered LVPECL Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.” Unused PECL outputs may be left floating with no impact on jitter performance. Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2. No Connect. Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, see Figures 2a to 2f “Input Interface Applications” section. TRUTH TABLE /RESET(1) S2 S1 S0 Outputs 1 0 X X Reference Clock (pass through) 1 1 0 0 Reference Clock ÷2 1 1 0 1 Reference Clock ÷4 1 1 1 0 Reference Clock ÷8 1 1 1 1 Reference Clock ÷16 0(1) 1 X X Q = LOW, /Q = HIGH Clock Disable Note 1. Reset/Disable function is asserted on the next clock input (IN, /IN) high-to-low transition. M9999-020707 [email protected] or (408) 955-1690 2 Precision Edge® SY89874U Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) .................................. –0.5V to VCC+0.3 ECL Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Input Current IN, /IN (IIN) .......................................... ±50mA VT Current (IVT) ...................................................... ±100mA VREF-AC Sink/Source Current (IVREF-AC), Note 3 ....... ±2mA Lead Temperature (soldering 20 sec.) ...................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCC) ................ +3.3V ±10% or +2.5V ±5% Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance MLF® (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF® (ψJB), Note 4 Junction-to-Board ............................................ 32°C/W Note 1. Note 2. Note 3. Note 4. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Due to the limited drive capability use for input of the same package only. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the pcb. DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) TA= –40°C to +85°C; Unless otherwise stated. Symbol Parameter VCC Power Supply ICC Power Supply Current RIN Differential Input Resistance (IN-to-/IN) VIH Input High Voltage (IN, /IN) VIL Max Units 3.63 V 50 75 mA 90 100 110 Ω Note 3 0.1 – VCC+0.3 V Input Low Voltage (IN, /IN) Note 3 –0.3 – VCC+0.2 V VIN Input Voltage Swing Notes 3, 4 0.1 – 3.6 V VDIFF_IN Differential Input Voltage Swing Notes 3, 4, 5 0.2 – |IIN| Input Current (IN, /IN) Note 3 – – VREF-AC Reference Voltage Note 6 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Condition Min Typ 2.375 No load, max. VCC V 45 VCC–1.525 VCC–1.425 VCC–1.325 mA V The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Due to the internal termination (see “Input Structures” ) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! See “Timing Diagram” for VIN definition. VIN (Max) is specified when VT is floating. See “Typical Operating Characteristics” section for VDIFF definition. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin. (100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50Ω to VCC –2V; Unless otherwise stated. Symbol Parameter VOH Output High Voltage VCC–1.145 VCC–1.020 VCC–0.895 V VOL Output Low Voltage VCC–1.945 VCC–1.820 VCC–1.695 V VOUT Output Voltage Swing 550 800 1050 mV VDIFF_OUT Differential Output Voltage Swing 1.10 1.60 2.10 V Note 1. Note 2. Condition Min Typ Max The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. M9999-020707 [email protected] or (408) 955-1690 3 Units Precision Edge® SY89874U Micrel, Inc. LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Note 1. Note 2. Condition Min Typ Max 2.0 V 0.8 V 20 µA –300 µA –125 The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. M9999-020707 [email protected] or (408) 955-1690 4 Units Precision Edge® SY89874U Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Output Toggle Frequency Output Swing ≥ 400mV 2.5 GHz Maximum Input Frequency Divide by 2, 4, 8, 16 3.2 GHz Differential Propagation Delay IN to Q Input Swing < 400mV 540 650 790 ps Input Swing ≥ 400mV 480 600 730 ps Within-Device Skew (diff.) Q0–Q1 Note 3 7 15 ps Part-to-Part Skew (diff.) Note 3 250 ps tRR Reset Recovery Time Note 4 Tjitter Cycle-to-Cycle Jitter Note 5 1 psRMS Total Jitter Note 6 10 psPP 250 ps tPD tSKEW tr,tf Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Typ Max 600 Rise/Fall Time (20% to 80%) 70 Units ps 150 Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 50Ω to VCC–2V, unless otherwise stated. Specification for packaged product only. Skew is measured between outputs under identical transitions. See “Timing Diagram.” Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1, where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. TIMING DIAGRAM /RESET VCC/2 tRR IN VIN /IN VIN Swing tPD /Q VOUT Swing Q M9999-020707 [email protected] or (408) 955-1690 5 Precision Edge® SY89874U Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, VIN = 400mV, TA = 25°C, unless otherwise stated. QA Output Amplitude vs. Frequency IN to Q Propagation Delay vs. Input Swing 900 QA AMPLITUDE (mV) 800 700 600 500 400 300 200 800 700 600 500 400 300 200 100 0 3500 3000 2500 2000 1500 1000 0 0 500 100 800 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 900 IN to Q Propagation Delay vs. Temperature 0 200 400 600 800 1000 1200 INPUT SWING (mV) 700 600 500 400 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FREQUENCY (MHz) 622MHz Output 1.25GHz Output Output Swing (100mV/div.) Output Swing (100mV/div.) /Q /Q Q Q TIME (200ps/div.) TIME (200ps/div.) 2.5GHz Output Output Swing (100mV/div.) /Q Q TIME (100ps/div.) M9999-020707 [email protected] or (408) 955-1690 6 Precision Edge® SY89874U Micrel, Inc. DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING VIN, VOUT VDIFF_IN, VDIFF_OUT 800mV (typical) 1600mV (typical) Figure 1a. Single-Ended Swing Figure 1b. Differential Swing INPUT BUFFER STRUCTURE VCC VCC 1.86kΩ 1.86kΩ 1.86kΩ 25kΩ R S0 S1 S2 /RESET 1.86kΩ R IN 50Ω VT 50Ω GND GND /IN Figure 2a. Simplified Differential Input Buffer M9999-020707 [email protected] or (408) 955-1690 Figure 2b. Simplified TTL/CMOS Input Buffer 7 Precision Edge® SY89874U Micrel, Inc. INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC VCC VCC IN PECL IN IN /IN CML CML NC GND VT NC VCC–2V* GND SY89874U SY89874U GND SY89874U /IN /IN VT VCC VREF-AC VREF-AC VT 0.01µF 50Ω NC VCC * Bypass with 0.01µF to GND 0.01µF Figure 3a. DC-Coupled CML Input Interface VCC VREF-AC Figure 3b. AC-Coupled CML Input Interface Figure 3c. DC-Coupled PECL Input Interface VCC VCC VCC VCC VCC IN PECL Rpd* Rpd* VCC GND GND *Note. 3.3V = Rpd = 100Ω IN IN /IN HSTL LVDS SY89874U SY89874U SY89874U VT VREF-AC /IN /IN GND 0.01µF GND NC VT NC VREF-AC 2.5V = Rpd = 50Ω VT NC VREF-AC GND Figure 3d. AC-Coupled PECL Input Interface Figure 3e. LVDS Input Interface Figure 3f. HSTL Input Interface RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89871U 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination http://www.micrel.com/product-info/products/sy89871u.shtml HBW Solutions MLF® Application Note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf New Products and Applications http://www.micrel.com/product-info/products/solutions.shtml M9999-020707 [email protected] or (408) 955-1690 8 Precision Edge® SY89874U Micrel, Inc. LVPECL OUTPUT TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω R2 82Ω R2 82Ω +3.3V ZO = 50Ω Vt = VCC –2V Figure 4a. Parallel Termination–Thevenin Equivalent Note 1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω +3.3V +3.3V Z = 50Ω Z = 50Ω 50Ω 50Ω “source” 50Ω Rb “destination” (Optional) C1 0.01µF Figure 4b. Three-Resistor “Y–Termination” Note 1. Power-saving alternative to Thevenin termination. Note 2. Place termination resistors as close to destination inputs as possible. Note 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +2.5V systems Rb = 39Ω Note 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. +3.3V +3.3V Q +3.3V R1 130Ω R1 130Ω V = VCC –1.3V R3 t +3.3V 1kΩ ZO = 50Ω /Q R4 1.6kΩ Vt = VCC –2V R2 82Ω R2 82Ω Figure 4d. Terminating Unused I/O Note 1. Unused output (/Q) must be terminated to balance the output. Note 2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ. M9999-020707 [email protected] or (408) 955-1690 9 Precision Edge® SY89874U Micrel, Inc. 16-PIN MicroLeadFrame® (MLF-16) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-020707 [email protected] or (408) 955-1690 10