. SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 Integrated 0.15-Ω Power MOSFET 3-V to 8-V Operation Digital Programmable Current Limit from 0 to 3 A Electronic Circuit Breaker Function 1µA ICC When Disabled Programmable on Time Programmable Start Delay Fixed 3% Duty Cycle Unidirectional Switch Thermal Shutdown Fault-Output Indicator Maximum-Output Current Can Be Set to 1 A Above the Programmed Fault Level or to a Full 4 A Power SOIC, Low-Thermal Resistance Packaging description The UCC3912 hot swap power manager provides complete power management, hot swap capability, and circuit breaker functions. The only component required to operate the device, other than supply bypassing, is the fault timing capacitor, CT. All control and housekeeping functions are integrated, and externally programmable. These include the fault current level, maximum output-sourcing current, maximum fault time, and startup delay. In the event of a constant fault, the internal fixed 3% duty cycle ratio limits average output power. The internal 4-bit DAC allows programming of the fault level current from 0 to 3 A with 0.25-A resolution. The IMAX control pin sets the maximum sourcing current to 1 A above the fault level when driven low, and to a full 4 A when driven high for applications which require fast output capacitor charging. When the output current is below the fault level, the output MOSFET is switched on with a nominal on resistance of 0.15 Ω. When the output current exceeds the fault level, but is less than the maximum sourcing level, the output remains switched on, but the fault timer starts charging CT. Once CT charges to a preset threshold, the switch is turned off, and remains off for 30 times the programmed fault time. When the output current reaches the maximum sourcing level, the MOSFET transitions from a switch to a constant current source. (continued) block diagram H=4A IMAX 2 VIN 3 VIN 14 VOUT 15 VOUT 1 SHTDWN 10 + REVERSE VOLTAGE COMPARATOR CHARGE PUMP 30 mV – + V OUT CURRENT SENSE 4A POWER FET + MAX CURRENT LEVEL – LINEAR CURRENT AMPLIFIER H = OPEN 1A ABOVE FAULT CURRENT FAULT LEVEL 0A TO 3 A ON TIME CONTROL + – 3% DUTY CYCLE THERMAL SHUTDOWN OVERCURRENT COMPARATOR 0 A–3 A 0.25 RES INTERNAL BIAS 6 7 8 9 5 B3 B2 B1 B0 GND 4 BIT DAC 4 13 12 HEATSINK GND PINS 11 16 CT FAULT 1.5 V + – UDG-99146 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated !$%'#)!%$ !( *''$) ( % &*"!)!%$ ) '%*)( %$%'# )% (&!!)!%$( &' ) )'#( % ,( $()'*#$)( ()$' +''$)- '%*)!%$ &'%((!$ %( $%) $(('!"- !$"* )()!$ % "" &'#)'( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 description (continued) The UCC3912 is designed for unidirectional current flow, emulating an ideal diode in series with the power switch. This feature is particularly attractive in applications where many devices are powering a common bus, such as with SCSI Termpwr. The UCC3912 can be put into sleep mode drawing only 1-µA of supply current. The SHTDWN pin has a preset threshold hysteresis which allows the user the ability to set a time delay upon startup to achieve sequencing of power. Other features include an open drain FAULT output indicator, thermal shutdown, under voltage lockout, and a low thermal resistance small outline package. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V FAULT sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA FAULT voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Limiting Input voltage (B0, B1, B2, B3, IMAX, SHTDWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 150°C Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Interface Products Data book (TI Literature Number SLUD002) for thermal limitations and considerations of packages. package information TSSOP-24, PWP Package (TOP VIEW) DIL-16, SOIC-16 N, DP Package (TOP VIEW) *Pin 5 serves as lowest impedance to the electrical ground; Pins 4, 12, and 13 serve as heat sink/ground. These pins should be connected to large etch areas to help dissipate heat. For N package, pins 4, 12, and 13 are N/C. 2 POST OFFICE BOX 655303 SHTDWN1 24 FAULT VIN 2 23 VOUT VIN 3 22 VOUT N/C 4 21 N/C GND* 5 20 GND* GND* 6 19 GND* GND* 7 18 GND* GND* 8 17 GND* EGND* 9 16 GND* B3 10 15 CT B2 11 14 IMAX B1 12 13 B0 *Pin 9 serves as lowest impedance to the electrical ground; other GND pins serve as heat sink/ground. These pins should be connected to large etch areas to help dissipate heat. • DALLAS, TEXAS 75265 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 electrical characteristics, these specifications apply for TA = 0°C to 70°C, VIN = 5 V, IMAX = 0.4 V, SHTDWN = 2.4 V, (unless otherwise stated) supply section PARAMETER TEST CONDITIONS Voltage input range MIN TYP Supply current Sleep mode current MAX 3.0 SHTDWN = 0.2 V UNITS 8.0 V 1.0 2.0 mA 0.5 5.0 µA NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. output section PARAMETER Voltage drop TEST CONDITIONS MIN TYP MAX UNITS IOUT = 1 A IOUT = 2 A 0.15 0.22 V 0.3 0.45 V IOUT = 3 A IOUT = 1A, 0.45 0.68 V VIN = 3 V 0.17 0.27 V IOUT = 2 A, IOUT = 3 A, VIN = 3 V 0.35 0.56 V VIN = 3 V 0.5 0.8 V VIN < VOUT , See Note 2 SHTDWN = 0.2 V, VOUT = 5 V 5 20 µA Initial startup time Short circuit response See Note 2 100 ns Thermal shutdown See Note 2 170 °C Thermal hysteresis See Note 2 10 °C Reverse leakage current µs 100 NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. NOTE 2: Ensured by design. Not production tested. DAC section PARAMETER Output leakage Trip current TEST CONDITIONS MIN TYP MAX UNITS 0 20 µA Code = 0100 0.1 0.25 0.45 A Code = 0101 0.25 0.50 0.75 A Code = 0110 0.5 0.75 1.0 A Code = 0111 0.75 1.00 1.25 A Code = 1000 1.0 1.25 1.5 A Code = 1001 1.25 1.50 1.75 A Code = 1010 1.5 1.75 2.0 A Code = 1011 1.7 2.00 2.3 A Code = 1100 1.9 2.25 2.58 A Code = 1101 2.1 2.50 2.9 A Code = 1110 2.3 2.75 3.2 A Code = 1111 2.5 3.0 3.5 A 0.02 mA Code = 0000–0011 Max output current Code = 0000 to 0011 Max output current over trip (current source mode) Code = 0100 to 1111, IMAX = 0 V 0.5 1.0 1.8 A Max output current (current source mode) Code = 0100 to 1111, IMAX = 2.4 V 3.0 4.0 5.2 A NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 electrical characteristics, these specifications apply for TA = 0°C to 70°C, VIN = 5 V, IMAX = 0.4 V, SHTDWN = 2.4 V, (unless otherwise stated) timer section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS –45.0 -36.0 –22.0 µA CT discharge current VCT = 1.0 V VCT = 1.0 V 0.72 1.2 1.5 µA Output duty cycle VOUT = 0 V CT charge current 2.0 3.0 6.0 % CT fault threshold 1.3 1.5 1.7 V CT reset threshold 0.4 0.5 0.6 V NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. shutdown section PARAMETER TEST CONDITIONS Shutdown threshold MIN TYP 1.1 Shutdown hysteresis Input current MAX 1.5 UNITS 1.9 100 SHTDWN = 1 V 100 V mV 500 nA fault output section PARAMETER TEST CONDITIONS MIN TYP MAX Output leakage current Low level output voltage IOUT = 10 mA 0.4 UNITS 500 nA 0.8 V TTL input dc characteristics section PARAMETER TTL input voltage high TEST CONDITIONS (can be connected to VIN) MIN TYP MAX 2.0 V TTL input voltage low TTL input high current TTL input low current UNITS VIH = 2.4 V VIL = 0.4 V 3 0.8 V 10 µA 1 µA NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. pin description B0–B3: These pins provide digital input to the DAC which sets the fault current threshold. They can be used to provide a digital soft-start, adaptive current limiting. CT: A capacitor connected to ground sets the maximum fault time. The maximum fault time must be more than the time to charge the external capacitance in one cycle. The maximum fault time is defined as FAULT = 27.8 × 103 × CT. Once the fault time is reached the output will shutdown for a time given by: TSD = 833 × 103 × CT, this equates to a 3% duty cycle. FAULT: Open drain output which pulls low upon any condition which causes the output to open: fault, thermal shutdown, or shutdown. IMAX: When this pin is set to logic low the maximum sourcing current will always be 1 A above the programmed fault level. When set to logic high, the maximum sourcing current will be a constant 4 A for applications which require fast charging of load capacitance. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 pin description (continued) SHTDWN: When this pin is brought to a logic low, the IC is put into a sleep mode drawing typically less than 1 µA of ICC. The input threshold is hysteretic, allowing the user to program a startup delay with an external RC circuit. VIN: Input voltage to the UCC3912. The recommended voltage range is 3 V to 8 V. Both VIN pins should be connected together and to the power source. VOUT: Output voltage from the UCC3912. When switched the output voltage will be approximately VIN − (0.15 Ω × IOUT). Both VOUT pins should be connected together and to the load. APPLICATION INFORMATION 4 VIN 2 R1 CIN 12 13 HEAT SINK GND PINS VIN 5 GND VOUT 3 D1 VOUT 14 15 RL COUT UCC3912 LED S6 16 FAULT VIN SHTDWN 1 11 CT CT RSD B3 B2 B1 B0 IMAX 6 7 8 9 10 CSD VIN S1 S2 S3 S4 S5 DIP SWITCH NOTE: For demonstration board schematic see Design Note DN-58 (TI Literature Number SLUA187). UDG-99171 Figure 1. Evaluation Circuit protecting the UCC3912 from voltage transients The parasitic inductance associated with the power distribution can cause a voltage spike at VIN if the load current is suddenly interrupted by the UCC3912. It is important to limit the peak of this spike to less than 8 V to prevent damage to the UCC3912. This voltage spike can be minimized by: Reducing the power distribution inductance (e.g., twist the positive and negative leads of the power supply feeding VIN, locate the power supply close to the UCC3912, use a PCB ground plane,...etc.). Decoupling VIN with a capacitor, CIN (refer to Figure 1), located close to pins 2 and 3. This capacitor is typically less than 1 µF to limit the inrush current. Clamping the voltage at VIN below 8 V with a zener diode, D1 (refer to Figure 1), located close to pins 2 and 3. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 APPLICATION INFORMATION UDG-93019-4 Figure 2. Load Current, Timing-Capacitor Voltage, and Output Voltage of the UCC3912 Under Fault Conditions. estimating maximum load capacitance For hot-swap applications, the rate at which the total output capacitance can be charged depends on the maximum output current available and the nature of the load. For a constant-current current-limited controller, the output will come up if the load asks for less than the maximum available short-circuit current. To ensure recovery of a duty-cycle from a short-circuited load condition, there is a maximum total output capacitance which can be charged for a given unit ON time (fault time). The design value of ON or fault time can be adjusted by changing the timing capacitor CT. For worst-case constant-current load of value just less than the trip limit; COUT(max) can be estimated from: C OUT(max) MAX ILOAD I 28 10 3 CT V OUT where VOUT is the output voltage. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 APPLICATION INFORMATION For a resistive load of value RL, the value of COUT(max) can be estimated from: 28 103 CT C OUT(max) RL n 1 V 1 OUT I MAXRL The overcurrent comparator senses both the DAC output and a representation of the output current. When the output current exceeds the programmed level the timing capacitor CT charges with 36 µA of current. If the fault occurs for the time it takes for CT to charge up to 1.5 V, the fault latch is set and the output switch is opened. The output remains opened until CT discharges to 0.5 V with a 1.2-µA current source. Once the 0.5 V is reached the output is enabled and will either appear as a switch, if the fault is removed, or a current source if the fault remains. If the over current condition is still present, then CT will begin charging, starting the cycle over, resulting in approximately a 3% on time. UDG-94019-1 Figure 3. UCC3912 On-Time Circuitry POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLUS241B – MARCH 1994 - REVISED - DECEMBER 2000 APPLICATION INFORMATION UDG-94019-1 Figure 4. RDS(on) vs. Temperature at 2-A Load Current. safety recommendations Although the UCC3912 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3912 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3912 will prevent the fuse from blowing virtually for all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated