User’s Manual µPD178054 Subseries 8-Bit Single-Chip Microcontrollers µPD178053 µPD178054 µPD178F054 Document No. U15104EJ2V0UD00 (2nd edition) Date Published January 2002 N CP(K) © Printed in Japan 2001 [MEMO] 2 User’s Manual U15104EJ2V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP and IEBus are trademarks of NEC Corporation. Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. Ethernet is a trademark of Xerox Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. User’s Manual U15104EJ2V0UD 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: µPD178F054GC-8BT The customer must judge the need for license: µPD178053GC-×××-8BT, 178054GC-×××-8BT • The information in this document is current as of October, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC’s data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer’s equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC’s data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC’s willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 4 User’s Manual U15104EJ2V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 User’s Manual U15104EJ2V0UD 5 Major Revisions in This Edition Page Description Throughout Change of µPD178053, 178054, and 178F054 status from under development to development completed pp.8, 9 Modification of Related Documents p.25 Modification of 1.5 Development of 8-Bit DTS Series p.55 Modification of bit units for manipulation for OSTS in Table 3-4 Special Function Registers p.84 Deletion of pins P10 to P15 from Table 4-3 Port Mode Register and Output Latch Settings When Using Alternate Functions p.124 Modification of description in (3) Oscillation stabilization time select register (OSTS) in 8.3 Registers Controlling Watchdog Timer p.240 Addition of CHAPTER 19 ELECTRICAL SPECIFICATIONS p.250 Addition of CHAPTER 20 PACKAGE DRAWING p.251 Addition of CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS p.253 Modification of Figure A-1 Configuration of Development Tools pp.255, 256 Addition of A.1 Software Package and A.3 Control Software p.255 Addition of Note 2 to A.2 Language Processing Software p.257 Addition of description for IE-78K0-NS-A to A.5 Debugging Tools (Hardware) p.260 Deletion of MX78K0 from A.7 Embedded Software The mark 6 shows major revised points. User’s Manual U15104EJ2V0UD PREFACE Readers This manual has been prepared for user engineers who wish to understand the functions of the µPD178054 Subseries and design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the functions described in the Organization below. The µPD178054 Subseries manual is separated into two parts: this manual and the Organization instruction edition (common to the 78K/0 Series). µPD178054 78K/0 Series Subseries User’s Manual User’s Manual Instruction • Pin functions • Internal block functions • Interrupt • Other on-chip peripheral functions • Electrical specifications How to Read This Manual • CPU functions • Instruction set • Explanation of each instruction Before reading this manual, you should have general knowledge of electric and logic circuits and microcomputers. • When you want to understand the functions in general: → Read this manual in the order of the contents. • To know the µPD178054 Subseries instruction function in detail: → Refer to the 78K/0 Series User’s Manual Instructions (U12326E) • How to interpret the register format: → For the circled bit number, the bit name is defined as a reserved word in DF178054 and RA78K0, and in CC78K0, already defined in the header file named sfrbit.h. • To know the electrical specifications of the µPD178054 Subseries: → Refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. Conventions Data representation weight: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text. Caution: Information requiring particular attention Remark: Supplementary information Numeral representations: Binary ... ×××× or ××××B Decimal ... ×××× Hexadecimal ... ××××H User’s Manual U15104EJ2V0UD 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µPD178054 Subseries User’s Manual This manual 78K/0 Series Instruction User’s Manual U12326E 78K/0 Series Application Note Basics (I) U12704E Documents Related to Development Tools (Software) (User’s Manuals) Document Name RA78K0 Assembler Package CC78K0 C Compiler Document No. Operation U14445E Assembly Language U14446E Structured Assembly Language U11789E Operation U14297E Language U14298E SM78K0S, SM78K0 System Simulator Ver.2.10 or Later Windows™ Based Operation U14611E SM78K Series System Simulator Ver.2.10 or Later External Part User Open Interface Specifications U15006E ID78K0-NS Integrated Debugger Ver.2.00 or Later Windows Based Operation U14379E ID78K0 Integrated Debugger Windows Based Reference U11539E Guide U11649E Fundamental U11537E Installation U11536E RX78K0 Real-Time OS Project Manager Ver. 3.12 or Later (Windows-Based) U14610E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 8 User’s Manual U15104EJ2V0UD Documents Related to Development Tools (Hardware) (User’s Manuals) Document Name Document No. IE-78K0-NS In-Circuit Emulator U13731E IE-78K0-NS-A In-Circuit Emulator U14889E IE-178054-NS-EM1 Emulation Board To be prepared Documents Related to Flash ROM Writing Document Name PG-FP3 Flash Memory Programmer User’s Manual Document No. U13502E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE -Products & Packages- X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User’s Manual U15104EJ2V0UD 9 TABLE OF CONTENTS CHAPTER 1 OUTLINE ....................................................................................................................... 1.1 Features.............................................................................................................................. 1.2 Applications ....................................................................................................................... 1.3 Ordering Information ........................................................................................................ 1.4 Pin Configuration (Top View) .......................................................................................... 1.5 Development of 8-Bit DTS Series ................................................................................... 1.6 Block Diagram ................................................................................................................... 1.7 Functional Outline ............................................................................................................ 21 21 22 22 23 25 26 27 CHAPTER 2 PIN FUNCTION ............................................................................................................. 2.1 Pin Function List ............................................................................................................... 2.2 Description of Pin Functions .......................................................................................... 28 28 30 2.2.1 P00 to P06 (Port 0) .............................................................................................................. 30 2.2.2 P10 to P15 (Port 1) .............................................................................................................. 30 2.2.3 P30 to P37 (Port 3) .............................................................................................................. 30 2.2.4 P40 to P47 (Port 4) .............................................................................................................. 31 2.2.5 P50 to P57 (Port 5) .............................................................................................................. 31 2.2.6 P60 to P67 (Port 6) .............................................................................................................. 31 2.2.7 P70 to P77 (Port 7) .............................................................................................................. 31 2.2.8 P120 to P125 (Port 12) ........................................................................................................ 32 2.2.9 P130 to P132 (Port 13) ........................................................................................................ 32 2.2.10 EO0, EO1 .............................................................................................................................. 32 2.2.11 VCOL, VCOH ........................................................................................................................ 32 2.2.12 AMIFC ................................................................................................................................... 33 2.2.13 FMIFC ................................................................................................................................... 33 2.2.14 RESET .................................................................................................................................. 33 2.2.15 X1, X2 ................................................................................................................................... 33 2.2.16 REGOSC ............................................................................................................................... 33 2.2.17 REGCPU ............................................................................................................................... 33 2.2.18 VDD ......................................................................................................................................... 33 2.2.19 GND ...................................................................................................................................... 33 2.2.20 VDDPORT .............................................................................................................................. 33 2.2.21 GNDPORT ............................................................................................................................ 33 2.2.22 VDDPLL .................................................................................................................................. 33 2.2.23 GNDPLL ................................................................................................................................ 33 2.2.24 VPP (µPD178F054 only) ....................................................................................................... 33 2.2.25 IC (Mask ROM version only) ................................................................................................ 34 Pin I/O Circuits and Recommended Connections of Unused Pins ........................... 35 CHAPTER 3 CPU ARCHITECTURE ................................................................................................. 3.1 Memory Space ................................................................................................................... 38 38 2.3 10 3.1.1 Internal program memory space .......................................................................................... 42 3.1.2 Internal data memory space ................................................................................................ 43 3.1.3 Special Function Register (SFR) area ................................................................................. 43 3.1.4 Data memory addressing ..................................................................................................... 44 User’s Manual U15104EJ2V0UD 3.2 3.3 Processor Registers ......................................................................................................... 47 3.2.1 Control registers ................................................................................................................... 47 3.2.2 General-purpose registers ................................................................................................... 50 3.2.3 Special Function Registers (SFR) ....................................................................................... 52 Instruction Address Addressing .................................................................................... 56 3.3.1 Relative addressing .............................................................................................................. 56 3.3.2 Immediate addressing .......................................................................................................... 57 3.3.3 Table indirect addressing ..................................................................................................... 58 3.3.4 Register addressing ............................................................................................................. 59 Operand Address Addressing ........................................................................................ 60 3.4.1 Implied addressing ............................................................................................................... 60 3.4.2 Register addressing ............................................................................................................. 61 3.4.3 Direct addressing .................................................................................................................. 62 3.4.4 Short direct addressing ........................................................................................................ 63 3.4.5 Special Function Register (SFR) addressing ...................................................................... 64 3.4.6 Register indirect addressing ................................................................................................ 65 3.4.7 Based addressing ................................................................................................................. 66 3.4.8 Based indexed addressing ................................................................................................... 67 3.4.9 Stack addressing .................................................................................................................. 67 CHAPTER 4 PORT FUNCTIONS ...................................................................................................... 4.1 Port Functions ................................................................................................................... 4.2 Port Configuration ............................................................................................................ 68 68 70 3.4 4.2.1 Port 0 ..................................................................................................................................... 70 4.2.2 Port 1 ..................................................................................................................................... 71 4.2.3 Port 3 ..................................................................................................................................... 72 4.2.4 Port 4 ..................................................................................................................................... 74 4.2.5 Port 5 ..................................................................................................................................... 75 4.2.6 Port 6 ..................................................................................................................................... 76 4.2.7 Port 7 ..................................................................................................................................... 77 4.2.8 Port 12 ................................................................................................................................... 80 4.2.9 Port 13 ................................................................................................................................... 82 Registers Controlling Port Functions ............................................................................ Port Function Operations ................................................................................................ 83 87 4.4.1 Writing to I/O ports ............................................................................................................... 87 4.4.2 Reading from I/O ports ......................................................................................................... 87 4.4.3 Operations on I/O ports ........................................................................................................ 87 CHAPTER 5 CLOCK GENERATOR ................................................................................................. 5.1 Functions of Clock Generator ......................................................................................... 5.2 Configuration of Clock Generator .................................................................................. 5.3 Register Controlling Clock Generator ........................................................................... 5.4 System Clock Oscillator .................................................................................................. 88 88 89 90 91 4.3 4.4 5.5 5.6 5.4.1 System clock oscillator ......................................................................................................... 91 5.4.2 Divider ................................................................................................................................... 93 Clock Generator Operations ........................................................................................... Changing System Clock and CPU Clock Settings ....................................................... 94 95 5.6.1 95 Time required for switching between system clock and CPU clock .................................. User’s Manual U15104EJ2V0UD 11 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 ............................................................. 96 6.1 Functions of 8-Bit Timer/Event Counters 50 to 53 ...................................................... 96 6.2 Configuration of 8-Bit Timer/Event Counters 50 to 53 ................................................ 99 6.3 Registers Controlling 8-Bit Timer/Event Counters 50 to 53 ....................................... 101 6.4 Operations of 8-Bit Timer/Event Counters 50 to 53 ..................................................... 105 6.5 6.4.1 Operation as interval timer (8-bit) ........................................................................................ 105 6.4.2 Operation as external event counter (timers 50 to 52) ....................................................... 109 6.4.3 Square wave output operation (8-bit resolution) (timers 50 to 52) .................................... 110 6.4.4 8-bit PWM output operation (timers 50 to 52) ..................................................................... 111 6.4.5 Interval timer operation (16-bit) ........................................................................................... 114 Notes on 8-Bit Timer/Event Counters 50 to 53 ............................................................. 115 CHAPTER 7 BASIC TIMER ............................................................................................................... 7.1 Function of Basic Timer .................................................................................................. 7.2 Configuration of Basic Timer .......................................................................................... 7.3 Operation of Basic Timer ................................................................................................. 117 117 117 118 CHAPTER 8 WATCHDOG TIMER .................................................................................................... 8.1 Functions of Watchdog Timer ........................................................................................ 8.2 Configuration of Watchdog Timer .................................................................................. 8.3 Registers Controlling Watchdog Timer ......................................................................... 8.4 Operations of Watchdog Timer ....................................................................................... 119 119 121 121 125 8.4.1 Watchdog timer operation .................................................................................................... 125 8.4.2 Interval timer operation ........................................................................................................ 126 CHAPTER 9 BUZZER OUTPUT CONTROLLER ............................................................................. 9.1 Functions of Buzzer Output Controllers ....................................................................... 9.2 Configuration of Buzzer Output Controllers ................................................................. 9.3 Registers Controlling Buzzer Output Controllers ........................................................ 127 127 128 128 9.4 9.3.1 BEEP0 ................................................................................................................................... 128 9.3.2 BUZ ....................................................................................................................................... 129 Operation of Buzzer Output Controllers ....................................................................... 129 CHAPTER 10 A/D CONVERTER ...................................................................................................... 10.1 Functions of A/D Converter ............................................................................................. 10.2 Configuration of A/D Converter ...................................................................................... 10.3 Registers Controlling A/D Converter ............................................................................. 10.4 Operations of A/D Converter ........................................................................................... 130 130 130 133 136 10.4.1 Basic operations of A/D converter ....................................................................................... 136 10.4.2 Input voltage and conversion results ................................................................................... 138 10.4.3 A/D converter operating mode ............................................................................................. 139 10.5 Notes on A/D Converter ................................................................................................... 145 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 ................................................................. 11.1 Functions of Serial Interfaces SIO30 to SIO32 ............................................................. 11.2 Configuration of Serial Interfaces SIO30 to SIO32 ...................................................... 11.3 Registers Controlling Serial Interfaces SIO30 to SIO32 ............................................. 11.4 Operations of Serial Interfaces SIO30 to SIO32 ........................................................... 12 147 147 149 150 152 11.4.1 Operation stop mode ............................................................................................................ 152 11.4.2 3-wire serial I/O mode .......................................................................................................... 153 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS ......................................................................................... 12.1 Interrupt Function Types ................................................................................................. 12.2 Interrupt Sources and Configuration ............................................................................. 12.3 Registers Controlling Interrupt Functions .................................................................... 12.4 Interrupt Servicing Operations ....................................................................................... 156 156 156 160 166 12.4.1 Non-maskable interrupt request acknowledgement operation ........................................... 166 12.4.2 Maskable interrupt request acknowledgement operation ................................................... 169 12.4.3 Software interrupt request acknowledgement operation .................................................... 172 12.4.4 Multiple interrupt servicing ................................................................................................... 173 12.4.5 Pending interrupt requests ................................................................................................... 176 CHAPTER 13 PLL FREQUENCY SYNTHESIZER ........................................................................... 13.1 Function of PLL Frequency Synthesizer ....................................................................... 13.2 Configuration of PLL Frequency Synthesizer .............................................................. 13.3 Registers Controlling PLL Frequency Synthesizer ..................................................... 13.4 Operation of PLL Frequency Synthesizer ..................................................................... 177 177 179 181 185 13.4.1 Operation of each block of PLL frequency synthesizer ...................................................... 185 13.4.2 Operation to set N value of PLL frequency synthesizer ..................................................... 189 13.5 PLL Disable Status ........................................................................................................... 194 13.6 Notes on PLL Frequency Synthesizer ........................................................................... 194 CHAPTER 14 FREQUENCY COUNTER ........................................................................................... 14.1 Function of Frequency Counter ...................................................................................... 14.2 Configuration of Frequency Counter ............................................................................. 14.3 Registers Controlling Frequency Counter .................................................................... 14.4 Operation of Frequency Counter .................................................................................... 14.5 Notes on Frequency Counter .......................................................................................... 195 195 195 197 199 201 CHAPTER 15 STANDBY FUNCTION .............................................................................................. 203 15.1 Standby Function and Configuration ............................................................................. 203 15.1.1 Standby function ................................................................................................................... 203 15.1.2 Register controlling standby function .................................................................................. 204 15.2 Operations of Standby Function .................................................................................... 205 15.2.1 HALT mode ........................................................................................................................... 205 15.2.2 STOP mode .......................................................................................................................... 208 CHAPTER 16 RESET FUNCTION .................................................................................................... 16.1 Reset Function .................................................................................................................. 16.2 Power Failure Detection Function .................................................................................. 16.3 4.5 V Voltage Detection Function ................................................................................... 211 211 218 219 CHAPTER 17 µPD178F054 ............................................................................................................... 17.1 Memory Size Switching Register (IMS).......................................................................... 17.2 Internal Expansion RAM Size Switching Register (IXS) .............................................. 17.3 Flash Memory Programming ........................................................................................... 220 221 222 223 17.3.1 Selecting communication mode ........................................................................................... 223 17.3.2 Flash memory programming function .................................................................................. 224 17.3.3 Connecting Flashpro III ........................................................................................................ 224 17.3.4 Setting example for Flashpro III (PG-FP3) .......................................................................... 225 User’s Manual U15104EJ2V0UD 13 CHAPTER 18 INSTRUCTION SET ................................................................................................... 226 18.1 Conventions ....................................................................................................................... 227 18.1.1 Operand symbols and description ....................................................................................... 227 18.1.2 Description of “operation” column ........................................................................................ 228 18.1.3 Description of “flag operation” column ................................................................................ 228 18.2 Operation List .................................................................................................................... 229 18.3 Instructions Listed by Addressing Type ....................................................................... 237 CHAPTER 19 ELECTRICAL SPECIFICATIONS .............................................................................. 240 CHAPTER 20 PACKAGE DRAWING ............................................................................................... 250 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS ........................................................ 251 APPENDIX A DEVELOPMENT TOOLS ............................................................................................ A.1 Software Package ............................................................................................................. A.2 Language Processing Software ...................................................................................... A.3 Control Software ............................................................................................................... A.4 Flash Memory Writing Tools ........................................................................................... A.5 Debugging Tools (Hardware) .......................................................................................... A.6 Debugging Tools (Software) ........................................................................................... A.7 Embedded Software ......................................................................................................... A.8 System Upgrade from Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A .......................................................................................... 252 255 255 256 256 257 259 260 261 APPENDIX B REGISTER INDEX ...................................................................................................... 264 B.1 Register Index ................................................................................................................... 264 B.2 Register Index (Symbol) .................................................................................................. 267 APPENDIX C REVISION HISTORY .................................................................................................. 270 14 User’s Manual U15104EJ2V0UD LIST OF FIGURES (1/4) Figure No. Title Page 2-1 Pin I/O Circuits .................................................................................................................................... 36 3-1 Memory Map of µ PD178053 .............................................................................................................. 39 3-2 Memory Map of µ PD178054 .............................................................................................................. 40 3-3 Memory Map of µ PD178F054 ............................................................................................................ 41 3-4 Data Memory Addressing of µPD178053 .......................................................................................... 44 3-5 Data Memory Addressing of µPD178054 .......................................................................................... 45 3-6 Data Memory Addressing of µPD178F054 ........................................................................................ 46 3-7 Configuration of Program Counter ..................................................................................................... 47 3-8 Configuration of Program Status Word .............................................................................................. 47 3-9 Configuration of Stack Pointer ........................................................................................................... 49 3-10 Data to Be Saved to Stack Memory ................................................................................................... 49 3-11 Data to Be Restored from Stack Memory .......................................................................................... 49 3-12 Configuration of General-Purpose Register ...................................................................................... 51 4-1 Port Types ........................................................................................................................................... 68 4-2 Block Diagram of P00 to P04 ............................................................................................................. 70 4-3 Block Diagram of P05 and P06 .......................................................................................................... 71 4-4 Block Diagram of P10 to P15 ............................................................................................................. 71 4-5 Block Diagram of P30 to P32 and P35 .............................................................................................. 72 4-6 Block Diagram of P33 and P34 .......................................................................................................... 73 4-7 Block Diagram of P36 and P37 .......................................................................................................... 73 4-8 Block Diagram of P40 to P47 ............................................................................................................. 74 4-9 Block Diagram of Key Input Detector ................................................................................................ 75 4-10 Block Diagram of P50 to P57 ............................................................................................................. 75 4-11 Block Diagram of P60 to P67 ............................................................................................................. 76 4-12 Block Diagram of P70, P74, and P77 ................................................................................................ 77 4-13 Block Diagram of P71 and P75 .......................................................................................................... 78 4-14 Block Diagram of P72 and P76 .......................................................................................................... 78 4-15 Block Diagram of P73 ......................................................................................................................... 79 4-16 Block Diagram of P120 and P123 ...................................................................................................... 80 4-17 Block Diagram of P121 and P124 ...................................................................................................... 81 4-18 Block Diagram of P122 and P125 ...................................................................................................... 81 4-19 Block Diagram of P130 to P132 ......................................................................................................... 82 4-20 Format of Port Mode Registers .......................................................................................................... 85 4-21 Format of Pull-up Resistor Option Register 4 (PU4) ......................................................................... 86 5-1 Format of DTS System Clock Select Register (DTSCK) .................................................................. 88 5-2 Block Diagram of Clock Generator .................................................................................................... 89 5-3 Format of Processor Clock Control Register (PCC) ......................................................................... 90 5-4 External Circuit of System Clock Oscillator ....................................................................................... 91 5-5 Examples of Incorrect Resonator Connection ................................................................................... 92 User’s Manual U15104EJ2V0UD 15 LIST OF FIGURES (2/4) Figure No. 16 Title Page 6-1 Block Diagram of 8-Bit Timer/Event Counter 50 ............................................................................... 97 6-2 Block Diagram of 8-Bit Timer/Event Counter 51 ............................................................................... 97 6-3 Block Diagram of 8-Bit Timer/Event Counter 52 ............................................................................... 98 6-4 Block Diagram of 8-Bit Timer 53 ........................................................................................................ 98 6-5 Format of Timer Clock Select Registers 50 to 52 (TCL50 to TCL52) .............................................. 101 6-6 Format of Timer Clock Select Register 53 (TCL53) .......................................................................... 102 6-7 Format of 8-Bit Timer Mode Control Registers 50 to 52 (TMC50 to TMC52) ................................. 103 6-8 Format of 8-Bit Timer Mode Control Register 53 (TMC53) .............................................................. 104 6-9 Timing of Interval Timer Operation .................................................................................................... 106 6-10 Operation Timing of External Event Counter (with Rising Edge Specified) ..................................... 109 6-11 Timing of Square Output Operation ................................................................................................... 110 6-12 Operation Timing of PWM Output ...................................................................................................... 112 6-13 Timing of Operation When CR5n Is Changed ................................................................................... 113 6-14 Operation Timing of 16-Bit Resolution Cascade Mode (Timers 50 and 51) .................................... 115 6-15 Start Timing of 8-Bit Timer Counter ................................................................................................... 115 6-16 Timing After Changing Compare Register Value During Timer Count Operation ........................... 116 7-1 Block Diagram of Basic Timer ............................................................................................................ 117 7-2 Operation Timing of Basic Timer ....................................................................................................... 118 7-3 Operating Timing to Poll BTMIF0 Flag .............................................................................................. 118 8-1 Block Diagram of Watchdog Timer .................................................................................................... 119 8-2 Format of Watchdog Timer Clock Select Register (WDCS) ............................................................. 122 8-3 Format of Watchdog Timer Mode Register (WDTM) ........................................................................ 123 8-4 Format of Oscillation Stabilization Time Select Register (OSTS) .................................................... 124 9-1 Block Diagram of BEEP0 .................................................................................................................... 127 9-2 Block Diagram of BUZ ........................................................................................................................ 127 9-3 Format of BEEP Clock Select Register 0 (BEEPCL0) ...................................................................... 128 9-4 Format of Clock Output Select Register (CKS) ................................................................................. 129 10-1 Block Diagram of A/D Converter ........................................................................................................ 131 10-2 Format of A/D Converter Mode Register 3 (ADM3) .......................................................................... 133 10-3 Format of Analog Input Channel Specification Register 3 (ADS3) .................................................. 134 10-4 Format of Power-Fail Comparison Mode Register 3 (PFM3) ........................................................... 135 10-5 A/D Converter Basic Operation .......................................................................................................... 137 10-6 Relationship Between Analog Input Voltage and A/D Conversion Result ....................................... 138 10-7 A/D Conversion Operation .................................................................................................................. 140 10-8 Power-Fail Comparison Threshold Value Register 3 (PFT3) ........................................................... 141 10-9 A/D Conversion Operation in Power-Fail Comparison Mode ........................................................... 142 10-10 Example of Reducing Current Consumption in Standby Mode ........................................................ 145 10-11 A/D Conversion End Interrupt Request Generation Timing .............................................................. 146 User’s Manual U15104EJ2V0UD LIST OF FIGURES (3/4) Figure No. Title Page 11-1 Block Diagram of Serial Interface SIO30 ........................................................................................... 147 11-2 Block Diagram of Serial Interface SIO31 ........................................................................................... 148 11-3 Block Diagram of Serial Interface SIO32 ........................................................................................... 148 11-4 Format of Serial Operating Mode Registers 30 to 32 (CSIM30 to CSIM32) ................................... 150 11-5 Format of Serial Port Select Register 32 (SIO32SEL) ...................................................................... 151 11-6 Timing in 3-Wire Serial I/O Mode ....................................................................................................... 154 12-1 Basic Configuration of Interrupt Function .......................................................................................... 158 12-2 Format of Interrupt Request Flag Registers (IF0L, IF0H) ................................................................. 161 12-3 Format of Interrupt Mask Flag Registers (MK0L, MK0H) ................................................................. 162 12-4 Format of Priority Specification Flag Registers (PR0L, PR0H) ........................................................ 163 12-5 Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) ................................................................... 164 12-6 Configuration of Program Status Word (PSW) .................................................................................. 165 12-7 Flowchart from Generation of Non-Maskable Interrupt Request to Acknowledgement .................. 167 12-8 Non-Maskable Interrupt Request Acknowledgement Timing ............................................................ 167 12-9 Non-Maskable Interrupt Request Acknowledgement Operation ....................................................... 168 12-10 Interrupt Request Acknowledgement Processing Algorithm ............................................................. 170 12-11 Interrupt Request Acknowledgement Timing (Minimum Time) ......................................................... 171 12-12 Interrupt Request Acknowledgement Timing (Maximum Time) ........................................................ 171 12-13 Multiple Interrupt Servicing Example ................................................................................................. 174 12-14 Pending Interrupt Request ................................................................................................................. 176 13-1 Block Diagram of PLL Frequency Synthesizer .................................................................................. 179 13-2 Format of PLL Mode Select Register (PLLMD) ................................................................................. 181 13-3 Format of PLL Reference Mode Register (PLLRF) ........................................................................... 182 13-4 Format of PLL Unlock F/F Judge Register (PLLUL) ......................................................................... 183 13-5 Format of PLL Data Transfer Register (PLLNS) ............................................................................... 184 13-6 Configuration of Input Select Block and Programmable Divider ...................................................... 185 13-7 Configuration of Reference Frequency Generator ............................................................................ 186 13-8 Configuration of Phase Comparator, Charge Pump, and Unlock F/F .............................................. 186 13-9 Relationship Between f r, fN, UP, and DW .......................................................................................... 187 13-10 Configuration of Error Out Output ...................................................................................................... 188 14-1 Block Diagram of Frequency Counter ................................................................................................ 196 14-2 Format of IF Counter Mode Select Register (IFCMD) ...................................................................... 197 14-3 Format of IF Counter Control Register (IFCCR) ............................................................................... 198 14-4 Format of IF Counter Gate Judge Register (IFCJG) ......................................................................... 198 14-5 Block Diagram of Input Pin and Mode Selection ............................................................................... 199 14-6 Gate Timing of Frequency Counter .................................................................................................... 200 14-7 Frequency Counter Input Pin Circuit .................................................................................................. 201 14-8 Gate Status When HALT Instruction Is Executed ............................................................................. 201 User’s Manual U15104EJ2V0UD 17 LIST OF FIGURES (4/4) Figure No. 18 Title Page 15-1 Format of Oscillation Stabilization Time Select Register (OSTS) .................................................... 204 15-2 HALT Mode Release upon Interrupt Generation ............................................................................... 206 15-3 HALT Mode Release by RESET Input ............................................................................................... 207 15-4 STOP Mode Release by Interrupt Request Generation ................................................................... 209 15-5 Release by STOP Mode RESET Input .............................................................................................. 210 16-1 Reset Function Block Diagram ........................................................................................................... 212 16-2 Timing of Reset by RESET Input ....................................................................................................... 213 16-3 Timing of Reset due to Watchdog Timer Overflow ........................................................................... 214 16-4 Timing of Reset by Power-on Clear ................................................................................................... 215 16-5 Format of POC Status Register (POCS) ........................................................................................... 218 16-6 Format of POC Status Register (POCS) ........................................................................................... 219 17-1 Format of Memory Size Switching Register (IMS) ............................................................................ 221 17-2 Format of Internal Expansion RAM Size Switching Register (IXS) .................................................. 222 17-3 Format of Communication Mode Selection ....................................................................................... 223 17-4 Connection of Flashpro III in 3-Wire Serial I/O Mode ....................................................................... 224 A-1 Configuration of Development Tools .................................................................................................. 253 A-2 EV-9200GC-80 Package Drawing (for Reference Only) ................................................................... 262 A-3 EV-9200GC-80 Recommended Board Mounting Pattern (for Reference Only) .............................. 263 User’s Manual U15104EJ2V0UD LIST OF TABLES (1/2) Table No. Title Page 2-1 Pin I/O Circuit Type and Recommended Connections of Unused Pins ........................................... 35 3-1 Internal Memory Capacities ................................................................................................................ 42 3-2 Vector Table ........................................................................................................................................ 42 3-3 Absolute Address of General-Purpose Registers ............................................................................. 50 3-4 Special Function Registers ................................................................................................................. 53 4-1 Port Functions ..................................................................................................................................... 69 4-2 Port Configuration ............................................................................................................................... 70 4-3 Port Mode Register and Output Latch Settings When Using Alternate Functions .......................... 84 5-1 Configuration of Clock Generator ...................................................................................................... 89 5-2 Maximum Time Required for CPU Clock Switching .......................................................................... 95 6-1 Configuration of 8-Bit Timer/Event Counters 50 to 53 ...................................................................... 99 8-1 Watchdog Timer Inadvertent Program Loop Detection Times ......................................................... 120 8-2 Interval Time ....................................................................................................................................... 120 8-3 Configuration of Watchdog Timer ...................................................................................................... 121 8-4 Watchdog Timer Inadvertent Program Loop Detection Time ........................................................... 125 8-5 Interval Timer Interval Time ............................................................................................................... 126 9-1 Configuration of Buzzer Output Controllers ....................................................................................... 128 10-1 Configuration of A/D Converter .......................................................................................................... 130 11-1 Configuration of Serial Interfaces SIO30 to SIO32 ........................................................................... 149 12-1 Interrupt Sources ................................................................................................................................ 157 12-2 Various Flags Corresponding to Interrupt Request Sources ............................................................ 160 12-3 Times from Maskable Interrupt Request Generation to Interrupt Servicing .................................... 169 12-4 Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing ................... 173 13-1 Division Mode, Input Pin, and Division Value .................................................................................... 178 13-2 Configuration of PLL Frequency Synthesizer .................................................................................... 179 13-3 Error Out Output Signal ...................................................................................................................... 188 13-4 Operation of Each Block and Register Status in PLL Disabled Status ............................................ 194 14-1 Configuration of Frequency Counter .................................................................................................. 195 15-1 HALT Mode Operating Status ............................................................................................................ 205 15-2 Operation After HALT Mode Release ................................................................................................ 207 15-3 STOP Mode Operating Status ............................................................................................................ 208 15-4 Operation After STOP Mode Release ............................................................................................... 210 User’s Manual U15104EJ2V0UD 19 LIST OF TABLES (2/2) Table No. Title 16-1 Hardware Status After Reset ............................................................................................................. 216 17-1 Differences Between µ PD178F054 and Mask ROM Versions ......................................................... 220 17-2 Set Value of Memory Size Switching Register .................................................................................. 221 17-3 Set Value of Internal Expansion RAM Size Switching Register ....................................................... 222 17-4 Communication Modes ....................................................................................................................... 223 17-5 Major Functions of Flash Memory Programming .............................................................................. 224 17-6 Setting Example for Flashpro III (PG-FP3) ........................................................................................ 225 18-1 Operand Symbols and Descriptions .................................................................................................. 227 21-1 Surface Mounting Type Soldering Conditions ................................................................................... 251 A-1 System Upgrade Method from Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A ............................................................................................................ 20 Page User’s Manual U15104EJ2V0UD 261 CHAPTER 1 OUTLINE 1.1 Features • Internal ROM and RAM Item Program Memory Data Memory Part Number Internal High-Speed RAM µPD178053 ROM 24 KB µPD178054 32 KB µPD178F054 • 1024 bytes Flash memory 32 KB Instruction set suitable for system control • Bit processing across entire address space • Multiplication/division instructions • • General-purpose I/O ports: 62 pins Hardware for PLL frequency synthesizer • Dual modulus prescaler (160 MHz MAX.) • Programmable divider • Phase comparator • Charge pump • • • Frequency counter 8-bit resolution A/D converter: 6 channels Serial interface: 3 channels • 3-wire serial I/O mode: 2 channels • 3-wire serial I/O mode (on-chip time-division transfer function): 1 channel • Timer: 6 channels • Basic timer (timer carry FF): 1 channel • • • 8-bit timer/event counter: 4 channels • Watchdog timer: 1 channel Buzzer output Vectored interrupt Item InterruptNote Part Number µPD178053, 178054, 178F054 1 source Note Maskable InterruptNote Non-Maskable External 5 sources Software Interrupt Internal 11 sources 1 source Either a non-maskable interrupt or maskable interrupt (internal) can be selected as the interrupt source of the watchdog timer (INTWDT). • • • Test input: • Power-on clear circuit 1 pin Instruction cycle: 0.45/0.89/1.78/3.56/7.11 µ s (with 4.5 MHz crystal resonator) Supply voltage: VDD = 4.5 to 5.5 V (with CPU, PLL operating) VDD = 3.5 to 5.5 V (with CPU operating) User’s Manual U15104EJ2V0UD 21 CHAPTER 1 OUTLINE 1.2 Applications Car stereos 1.3 Ordering Information Part Number Package µPD178053GC-×××-8BT 80-pin plastic QFP (14 × 14) µPD178054GC-×××-8BT 80-pin plastic QFP (14 × 14) µPD178F054GC-8BT 80-pin plastic QFP (14 × 14) Remark 22 ××× indicates ROM code suffix. User’s Manual U15104EJ2V0UD CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14) P120/SI32 P121/SO32 P122/SCK32 P123/SI321 P124/SO321 P125/SCK321 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P04/INTP4 P05 P06 REGCPU GND X2 X1 REGOSC VDD RESET µPD178053GC-×××-8BT, 178054GC-×××-8BT, 178F054GC-8BT P10/ANI0 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P11/ANI1 2 59 P36/BEEP0 P12/ANI2 3 58 P35 P13/ANI3 4 57 P34/TI51 P14/ANI4 5 56 P33/TI50 P15/ANI5 6 55 P32 P70/SI30 7 54 P31 P71/SO30 8 53 P30 P72/SCK30 9 52 P67 P73 10 51 P66 P37/BUZ 43 P56 P41 19 42 P55 P42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P54 P53 P40 P52 P57 P51 44 18 P50 17 EO1 P132/TO52 IC (VPP) P60 EO0 P61 45 GNDPLL 46 16 VCOL 15 P131/TO51 VCOH P130/TO50 FMIFC P62 VDDPLL P63 47 AMIFC 48 14 P47 13 P77/TI52 P46 P76/SCK31 P45 P64 P44 P65 49 P43 50 12 VDDPORT 11 GNDPORT P74/SI31 P75/SO31 Cautions 1. Directly connect the IC (Internally Connected) pin and VPP pin to GND. 2. Keep the VDDPORT and VDDPLL pins as same potential as that at the VDD pin. 3. Keep the GNDPORT and GNDPLL pins as same potential as that at GND. 4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1 µF capacitor. Remark ( ): µPD178F054 only User’s Manual U15104EJ2V0UD 23 CHAPTER 1 OUTLINE Pin Name AMIFC: AM intermediate frequency counter input P130 to P132: Port 13 ANI0 to ANI5: A/D converter input REGCPU: Regulator for CPU power supply BEEP0, BUZ: Buzzer output REGOSC: Regulator for oscillator EO0, EO1: Error out output RESET: Reset input FMIFC: FM intermediate frequency counter input SCK30, SCK31,: Serial (SIO3) clock input/output GND: Ground SCK32, SCK321 GNDPLL: PLL ground SI30, SI31, SI32,: Serial (SIO3) data input GNDPORT: Port ground SI321 IC: Internally connected SO30, SO31,: Serial (SIO3) data output INTP0 to INTP4: Interrupt input SO32, SO321 P00 to P06: Port 0 TI50 to TI52: 8-bit timer clock input P10 to P15: Port 1 TO50 to TO52: 8-bit timer output P30 to P37: Port 3 VCOL, VCOH: Local oscillation input P40 to P47: Port 4 VDD: Power supply P50 to P57: Port 5 VDDPLL: PLL power supply P60 to P67: Port 6 VDDPORT: Port power supply P70 to P77: Port 7 VPP Note: Programming power supply P120 to P125: Port 12 X1, X2: Crystal resonator Note 24 µ PD178F054 only User’s Manual U15104EJ2V0UD CHAPTER 1 OUTLINE 1.5 Development of 8-Bit DTS Series Products in mass production Products under development Mask ROM version Flash memory version or PROM version 80 pins µ PD178F048 80 pins µPD178048 Subseries On-chip OSD controller 8-bit PWM × 4 channels 14-bit PWM × 1 channel On-chip OSD controller 8-bit PWM × 4 channels 14-bit PWM × 1 channel 100 pins µPD178098 Subseries On-chip IEBus controller 100 pins µ PD178F098 On-chip IEBusTM controller, UART 100 pins µPD178078 Subseries On-chip UART 80 pins µ PD178F054 80 pins Enhanced timer, 3-wire serial I/O Enhanced timer, 3-wire serial I/O 80 pins µ PD178F124 80 pins On-chip UART 80 pins µPD178054 Subseries µPD178024 Subseries On-chip UART 80 pins µ PD178018A Subseries 80 pins µPD178003 Subseries µ PD178P018A Limits functions of µ PD178018A Subseries User’s Manual U15104EJ2V0UD 25 CHAPTER 1 OUTLINE 1.6 Block Diagram TI50/P33 TO50/P130 8-bit timer/ event counter50 Port 0 7 P00 to P06 TI51/P34 TO51/P131 8-bit timer/ event counter51 Port 1 6 P10 to P15 TI52/P77 TO52/P132 8-bit timer/ event counter52 Port 3 8 P30 to P37 Port 4 8 P40 to P47 Port 5 8 P50 to P57 Basic timer Port 6 8 P60 to P67 SI30/P70 SO30/P71 SCK30/P72 Serial interface30 Port 7 8 P70 to P77 SI31/P74 SO31/P75 SCK31/P76 Port 12 6 P120 to P125 Serial interface31 Port 13 3 P130 to P132 SI32/P120 SO32/P121 SCK32/P122 SI321/P123 SO321/P124 SCK321/P125 Serial interface32 A/D converter 6 ANI0/P10 to ANI5/P15 78K/0 CPU Core 8-bit timer53 ROM Flash memory Watchdog timer INTP0/P00 to INTP4/P04 BEEP0/P36 BUZ/P37 RAM 1024 bytes Frequency counter 5 Interrupt control PLL Buzzer output PLL voltage regulator RESET X1 X2 VDDPORT GNDPORT VDD System control REGOSC REGCPU GND Voltage regulator RESET CPU PERIPHERAL VOSC VCPU Remarks 1. The internal ROM capacity differs depending on the product. 2. ( ): µPD178F054 26 User’s Manual U15104EJ2V0UD AMIFC FMIFC EO0 EO1 VCOL VCOH VDDPLL GNDPLL IC (Vpp) CHAPTER 1 OUTLINE 1.7 Functional Outline µPD178053 Item Internal ROM High-speed RAM µPD178054 24 KB (Mask ROM) 32 KB (Mask ROM) µPD178F054 32 KB (Flash memory) 1024 bytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.45 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (with crystal resonator of fX = 4.5 MHz) Instruction set • • • • I/O ports Total: 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. 62 pins • CMOS I/O: 53 pins • CMOS input: 6 pins • N-ch open-drain output: 3 pins A/D converter 8-bit resolution × 6 channels Serial interface • 3-wire serial I/O mode: 2 channels • 3-wire serial I/O mode (on-chip time-division transfer): 1 channel Timer • Basic timer (timer carry FF (10 Hz)) : 1 channel • 8-bit timer/event counter: 4 channels • Watchdog timer: Buzzer output Vectored interrupt sources PLL frequency synthesizer 1 channel BEEP pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz BUZ pin: 549 Hz, 1.10 kHz, 2.20 kHz, 4.39 kHz Maskable Internal : 11 External: 5 Non-maskable Internal: 1 Software 1 Division mode 2 types • Direct division mode (VCOL pin) • Pulse swallow mode (VCOL and VCOH pins) Reference frequency Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz) Charge pump Error out output: 2 pins Phase comparator Unlock detectable with program Frequency counter Frequency measurement • AMIFC pin: For 450 kHz counting • FMIFC pin: For 450 kHz/10.7 MHz counting Reset • Reset by RESET pin • Internal reset by watchdog timer • Reset by power-on clear circuit • Detection of less than 4.5 VNote (reset does not occur, however) • Detection of less than 3.5 VNote (during CPU operation) • Detection of less than 2.2 VNote (in STOP mode) Supply voltage • VDD = 4.5 to 5.5 V (during CPU, PLL operation) • VDD = 3.5 to 5.5 V (during CPU operation) Package 80-pin plastic QFP (14 × 14) Note For details, refer to CHAPTER 16 RESET FUNCTION. User’s Manual U15104EJ2V0UD 27 CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1) Port pins Pin Name P00 to P04 I/O I/O P05, P06 Function After Reset Port 0 7-bit I/O port Input/output can be specified in 1-bit units. Input INTP0 to INTP4 — P10 to P15 Input Port 1 6-bit input port Input P30 to P32 I/O Port 3 8-bit I/O port. Input/output can be specified in 1-bit units. Input P33 Alternate Function ANI0 to ANI5 — TI50 P34 TI51 P35 — P36 BEEP0 P37 BUZ P40 to 47 I/O Port 4 8-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Input — Interrupt function by key input is provided. P50 to P57 I/O Port 5 8-bit I/O port Input/output can be specified in 1-bit units. Input — P60 to P67 I/O Port 6. 8-bit I/O port. Input/output can be specified in 1-bit units. Input — P70 I/O Port 7 8-bit I/O port Input/output can be specified in 1-bit units. Input P71 SI30 SO30 P72 SCK30 P73 — P74 SI31 P75 SO31 P76 SCK31 P77 TI52 P120 I/O P121 Port 12 6-bit I/O port Input/output can be specified in 1-bit units. Input SI32 SO32 P122 SCK32 P123 SI321 P124 SO321 P125 SCK321 P130 P131 Output Port 13 3-bit output port N-ch open-drain output port (12 V tolerance) P132 28 Low-level output TO50 TO51 TO52 User’s Manual U15104EJ2V0UD CHAPTER 2 PIN FUNCTION (2) Pins other than port pins Pin Name I/O Function After Reset INTP0 to INTP4 Input External maskable interrupt input whose valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input SI30 Serial data input to serial interface. Input Input Alternate Function P00 to P04 P70 S131 P74 S132 P120 SI321 P123 SO30 Output Serial data output from serial interface. Input P71 SO31 P75 SO32 P121 SO321 P124 SCK30 I/O Serial clock input/output to/from serial interface. Input P72 SCK31 P76 SCK32 P122 SCK321 P125 TI50 Input TI51 External count clock input to 8-bit timer 50 Input P33 External count clock input to 8-bit timer 51 TI52 P34 External count clock input to 8-bit timer 52 TO50 Output 8-bit timer 50 output TO51 8-bit timer 51 output TO52 8-bit timer 52 output BEEP0 Output Buzzer output P77 Low-level output P130 P131 P132 Input P36 BUZ P37 ANI0 to ANI5 Input Analog input to A/D converter EO0, EO1 Output Error out output from charge pump of PLL frequency synthesizer – – VCOL Input Inputs local oscillation frequency of PLL (in HF and MF modes) – – Input Input to AM intermediate frequency counter VCOH Input P10 to P15 Inputs local oscillation frequency of PLL (in VHF mode) AMIFC FMIFC Input – Input to FM or AM intermediate frequency counter RESET Input System reset input – – X1 Input Connection of crystal resonator for system clock oscillation. – – X2 – – – REGOSC – Regulator for oscillator. Connect this pin to GND via 0.1 µF capacitor. – – REGCPU – Regulator for CPU power supply. Connect this pin to GND via 0.1 µF capacitor. – – VDD – Positive power supply – – GND – Ground – – VDDPORT – Port power supply – – GNDPORT – Port ground – – VDDPLLNote 1 – PLL positive power supply – – GNDPLLNote 1 – PLL ground – – IC – Internally connected. Directly connect this pin to GND. – – VPPNote 2 – Pin to apply high voltage at program writing/verifying. Directly connect this pin to GND in normal operating mode. – – Notes 1. Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins. 2. µPD178F054 only. User’s Manual U15104EJ2V0UD 29 CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P06 (Port 0) P00 to P06 constitute a 7-bit I/O port. In addition to I/O port pins, P00 to P06 also function as external interrupt inputs. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as a 7-bit I/O port for which input or output can be specified in 1-bit units using port mode register 0 (PM0). (2) Control mode These pins function as external interrupt input pins (INTP0 to INTP4). These external interrupt input pins can specify valid edges (rising edge, falling edge, and both rising and falling edges). 2.2.2 P10 to P15 (Port 1) P10 to P15 constitute a 6-bit input port. In addition to input port pins, P10 to P15 function as A/D converter analog inputs. The following operating modes can be specified in 1 bit units. (1) Port mode These pins function as a 6-bit input port. (2) Control mode These pins function as A/D converter analog input pins (ANI0 to ANI5). 2.2.3 P30 to P37 (Port 3) P30 to P37 constitute an 8-bit I/O port . In addition to I/O port pins, P30 to P37 function as timer inputs and buzzer outputs. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as an 8-bit I/O port for which input or output can be specified in 1-bit units using port mode register 3 (PM3). (2) Control mode These pins function as timer inputs (TI50, T51) and buzzer outputs (BEEP0, BUZ). (a) TI50, TI51 Pins for external clock input to the 8-bit timer/event counter. (b) BEEP0, BUZ Buzzer output pins. 30 User’s Manual U15104EJ2V0UD CHAPTER 2 PIN FUNCTION 2.2.4 P40 to P47 (Port 4) P40 to P47 constitute an 8-bit I/O port. These pins can be specified as input or output in 1-bit units using port mode register 4 (PM4). On-chip pull-up resistors can be specified by pull-up resistor option register 4 (PU4). An interrupt function via key input is also provided. 2.2.5 P50 to P57 (Port 5) P50 to P57 constitute an 8-bit I/O port. These pins can be specified as input or output in 1-bit units using port mode register 5 (PM5). 2.2.6 P60 to P67 (Port 6) P60 to P67 constitute an 8-bit port. These pins can be specified as input or output in 1-bit units using port mode register 6 (PM6). 2.2.7 P70 to P77 (Port 7) P70 to P77 pins constitute an 8-bit I/O port. In addition to port pins, P70 to P77 also function as serial interface data I/O, clock I/O, and a timer input. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as an 8-bit I/O port for which input or output can be specified in 1-bit units using port mode register 7 (PM7). (2) Control mode These pins function as serial interface data I/O, clock I/O, and timer input pins. (a) SI30, SO30, SI31, SO31 Serial data I/O pins of the serial interface. (b) SCK30, SCK31 Serial clock I/O pins of the serial interface. (c) TI52 External clock input pin to 8-bit timer/event counter. User’s Manual U15104EJ2V0UD 31 CHAPTER 2 PIN FUNCTION 2.2.8 P120 to P125 (Port 12) P120 to P125 constitute a 6-bit I/O port. In addition to I/O port pins, P120 to P125 also function as serial interface data I/O and clock I/O. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as an 8-bit I/O port for which input or output can be specified in 1-bit units using port mode register 7 (PM7). (2) Control mode These pins function as serial interface data I/O and clock I/O pins. (a) SI32, SO32, SI321, SO321 Serial data I/O pins of the serial interface. (b) SCK32, SCK321 Serial clock I/O pins of the serial interface. 2.2.9 P130 to P132 (Port 13) P130 to P132 constitute a 3-bit N-ch open-drain output port with a 12 V tolerance. In addition to output port pins, P130 to P132 also function as timer outputs. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as a 3-bit output port. (2) Control mode These pins function as output pins for the 8-bit timer/event counter. TO50, TO51, TO52 These pins are output pins for the 8-bit timer/event counter. 2.2.10 EO0, EO1 These are the output pins of the charge pump of the PLL frequency synthesizer. They output the result of phase comparison between the frequency divided by the programmable divider of the local oscillation input (VCOL and VCOH pins) and the reference frequency. 2.2.11 VCOL, VCOH These pins input the local oscillation frequency (VCO) of the PLL. Because signals are input to these pins via an AC amplifier, cut the DC component of the input signals using a capacitor. • VCOL • HF, MF input • This pin becomes active when the HF or MF mode is selected by software; otherwise, the pin is in the status set by bit 2 (VCOLDMD) of the PLL mode select register (PLLMD). If VCOLDMD is reset to 0 (to connect a pull-down resistor), however, the VCOL pin does not become active even if the HF or MF mode is selected. In this case, set VCOLDMD to 1 (high-impedance state). 32 User’s Manual U15104EJ2V0UD CHAPTER 2 • PIN FUNCTION VCOH • VHF input • This pin becomes active when the FM mode is selected by software; otherwise the pin is in the status set by bit 3 (VCOHDMD) of the PLL mode select register (PLLMD). If VCOHDMD is reset to 0 (to connect a pull-down resistor), however, the VCOL pin does not become active even if the FM mode is selected. In this case, set VCOHDMD to 1 (high-impedance state). 2.2.12 AMIFC Input pin of the AM intermediate frequency counter. 2.2.13 FMIFC Input pin of the FM intermediate frequency counter or AM intermediate frequency counter. 2.2.14 RESET Low-level active system reset input pin. 2.2.15 X1, X2 Crystal resonator connection pins for system clock oscillation. 2.2.16 REGOSC Regulator pin for oscillator. Connect to GND via a 0.1 µF capacitor. 2.2.17 REGCPU Regulator pin for CPU power supply. Connect to GND via a 0.1 µF capacitor. 2.2.18 VDD Positive power supply pin. 2.2.19 GND Ground potential pin. 2.2.20 VDDPORT Positive power supply pin for port. 2.2.21 GNDPORT Ground potential pin for port. 2.2.22 VDDPLL Positive power supply pin for PLL. 2.2.23 GNDPLL Ground potential pin for PLL. 2.2.24 VPP (µPD178F054 only) This pin applies a high voltage when the flash memory programming mode is set or when a program is written or verified. In the normal operation mode, directly connect this pin to GND. User’s Manual U15104EJ2V0UD 33 CHAPTER 2 PIN FUNCTION 2.2.25 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µPD178054 Subseries at delivery. Connect it directly to the GND pin with the shortest possible wire in the normal operating mode. When a potential difference is produced between the IC pin and GND pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally. Connect IC pin to GND pin directly. GND IC As short as possible 34 User’s Manual U15104EJ2V0UD CHAPTER 2 PIN FUNCTION 2.3 Pin I/O Circuits and Recommended Connections of Unused Pins Table 2-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins when they are not used. For the configuration of the I/O circuit of each pin, refer to Figure 2-1. Table 2-1. Pin I/O Circuit Type and Recommended Connections of Unused Pins Pin Name P00/INTP0 to P04/INTP4 I/O Circuit Type I/O Recommended Connection of Unused Pin 8 I/O Input: Connect to VDD, VDDPORT, GND, or GNDPORT via a resistor. Output: Leave open. 25 Input Connect to VDD, VDDPORT, GND, or GNDPORT. P30 to P32 5 I/O P33/TI50 5-K Input: Connect to VDD, VDDPORT, GND, or GNDPORT via a resistor. Output: Leave open. Output Leave open. Input Disable PLL in software and select pull-down. P05, P06 P10/ANI0 to P15/ANI5 P34/TI51 P35 5 P36/BEEP0 P37/BUZ P40 to P47 5-A P50 to P57 5 P60 to P67 P70/SI30 5-K P71/SO30 5 P72/SCK30 5-K P73 5 P74/SI31 5-K P75/SO31 5 P76/SCK31 5-K P77/TI52 P120/SI32 P121/SO32 5 P122/SCK32 5-K P123/SI321 P124/SO321 5 P125/SCK321 5-K P130/TO50 19 P131/TO51 P132/TO52 EO0, EO1 DTS-EO1 VCOL, VCOH DTS-AMP AMIFC, FMIFC Set these pins in general-purpose input port mode by software and connect each of them to VDD, VDDPORT, GND, or GNDPORT via a resistor. REGOSC, REGCPU RESET VDDPLL GNDPLL – 2 – Connect these pins to GND via 0.1 µF capacitor. Input – – – Connect to VDD. Directly connect to GND or GNDPORT. IC (Mask ROM version) VPP (µPD178F054) User’s Manual U15104EJ2V0UD 35 CHAPTER 2 PIN FUNCTION Figure 2-1. Pin I/O Circuits (1/2) Type 2 Type 5 VDD Data P-ch IN/OUT IN Output disable Schmitt-triggered input with hysteresis characteristics Type 5-A N-ch Input enable Type 5-K VDD VDD Pull-up enable Data Data P-ch IN/OUT P-ch IN/OUT Output disable P-ch VDD Output disable N-ch N-ch Input enable Input enable Type 8 Type 19 VDD Data OUT P-ch IN/OUT Output disable Remark N-ch VDD and GND are the positive power supply and ground pins for all port pins. Read VDD and GND as VDDPORT and GNDPORT. 36 N-ch User’s Manual U15104EJ2V0UD CHAPTER 2 PIN FUNCTION Figure 2-1. Pin I/O Circuits (2/2) Type 25 Type DTS-EO1 VDDPLL P-ch Comparator DW + P-ch – N-ch VREF (Threshold voltage) IN OUT UP Input enable N-ch GNDPLL Type 25 VDDPLL IN Note GNDPLL Note This switch is selectable by software only for the VCOL and VCOH pins. Remark VDD and GND are the positive power supply and ground pins for all port pins. Read VDD and GND as VDDPORT and GNDPORT. User’s Manual U15104EJ2V0UD 37 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The initial value of the memory size switching register (IMS) is CFH. The following values must be set to the registers of each model. Part Number 38 IMS µPD178053 C6H µPD178054 C8H µPD178F054 Value equivalent to mask ROM version User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE (1) µPD178053 Set the value of the memory size switching register (IMS) to C6H. The initial value is CFH. Figure 3-1. Memory Map of µPD178053 FFFFH Special function registers (SFRs) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits 5FFFH FB00H FAFFH Program area Data memory space 1000H 0FFFH CALLF entry area Reserved 0800H 07FFH Program area 0080H 007FH CALLT table area 6000H 5FFFH Program memory space Internal ROM 24576 × 8 bits 0040H 003FH Vector table area 0000H 0000H User’s Manual U15104EJ2V0UD 39 CHAPTER 3 CPU ARCHITECTURE (2) µPD178054 Set the value of the memory size switching register (IMS) to C8H. The initial value is CFH. Figure 3-2. Memory Map of µPD178054 FFFFH Special function registers (SFRs) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits 7FFFH FB00H FAFFH Program area Data memory space 1000H 0FFFH CALLF entry area Reserved 0800H 07FFH Program area 0080H 007FH CALLT table area 8000H 7FFFH Program memory space Internal ROM 32768 × 8 bits Vector table area 0000H 0000H 40 0040H 003FH User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE (3) µPD178F054 Set the value of the memory size switching register (IMS) to the value corresponding to that of the mask ROM versions. The initial value is CFH. Figure 3-3. Memory Map of µPD178F054 FFFFH Special function registers (SFRs) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits 7FFFH FB00H FAFFH Program area Data memory space 1000H 0FFFH CALLF entry area Reserved 0800H 07FFH Program area 0080H 007FH CALLT table area 8000H 7FFFH Program memory space Flash memory 32768 × 8 bits 0040H 003FH Vector table area 0000H 0000H User’s Manual U15104EJ2V0UD 41 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space Programs and table data are stored in internal program memory space, and are usually addressed by the program counter (PC). The µPD178054 Subseries has internal ROM (or flash memory) as shown in the following table. Table 3-1. Internal Memory Capacities Part Number Structure µPD178053 Capacity 24576 × 8 bits (0000F to 5FFFH) Mask ROM µPD178054 32768 × 8 bits (0000H to 7FFFH) µPD178F054 Flash memory The following areas are assigned to the internal program memory space. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-2. Vector Table Vector Table Address 42 Interrupt Request 0004H INTWDT 0006H INTP0 0008H INTP1 000AH INTP2 000CH INTP3 000EH INTP4 0010H INTKY 0012H INTCSI31 0014H INTBTM0 0016H INTAD3 0018H INTCSI32 001AH INTCSI30 001CH INTTM50 001EH INTTM51 0020H INTTM52 0022H INTTM53 003EH BRK User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space The µPD178054 Subseries products incorporate the following RAMs. (1) Internal high-speed RAM The µPD178053, 178054, and 178F054 have a RAM structure of 1024 × 8 bits. In this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory area. 3.1.3 Special Function Register (SFR) area An on-chip peripheral hardware special function register (SFR) is allocated in the area FF00H to FFFFH. Refer to Table 3-4 Special Function Registers. Caution Do not access addresses where the SFR is not assigned. User’s Manual U15104EJ2V0UD 43 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, refer to 3.3 Instruction Address Addressing). Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the µPD178054 Subseries, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and generalpurpose registers are available for use. Data memory addressing is illustrated in Figures 3-4 to 3-6. For the details of each addressing mode, refer to 3.4 Operand Address Addressing. Figure 3-4. Data Memory Addressing of µPD178053 FFFFH Special function registers (SFRs) 256 × 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 × 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 × 8 bits FE20H FE1FH FB00H FAFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 6000H 5FFFH Internal ROM 24576 × 8 bits 0000H 44 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Data Memory Addressing of µPD178054 FFFFH Special function registers (SFRs) 256 × 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 × 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 × 8 bits FE20H FE1FH FB00H FAFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 8000H 7FFFH Internal ROM 32768 × 8 bits 0000H User’s Manual U15104EJ2V0UD 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing of µPD178F054 FFFFH Special function registers (SFRs) 256 × 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 × 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 × 8 bits FE20H FE1FH FB00H FAFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 8000H 7FFFH Flash memory 32768 × 8 bits 0000H 46 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µPD178054 Subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-7. Configuration of Program Counter 15 PC 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETB, RETI and POP PSW instructions. Reset input sets the PSW to 02H. Figure 3-8. Configuration of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 0 User’s Manual U15104EJ2V0UD ISP CY 47 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all the interrupts are disabled (DI) except the non-maskable interrupt. When IE = 1, the interrupts are enabled (EI). At this time, the acknowledging of interrupts is controlled by the in-service priority flag (ISP), the interrupt mask flag corresponding to each interrupt, and the interrupt priority specification flag. The IE is reset to 0 upon DI instruction execution or interrupt acknowledgement and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, acknowledging the vectored interrupt requests to which a low priority is assigned by the priority specification flag registers (PR0L, PR0H) (refer to 12.3 (3) Priority specification flag registers (PR0L, PR0H) is disabled. Whether an interrupt request is actually accepted depends on the status of the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. 48 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH for µPD178053, 178054, and 178F054) can be set as the stack area. Figure 3-9. Configuration of Stack Pointer 15 SP 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of a write (save) to the stack memory and is incremented after a read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-10 and 3-11. Caution Since reset input makes SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-10. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt and BRK instruction CALL, CALLF, and CALLT instruction SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Register pair lower SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Register pair upper SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP SP Figure 3-11. Data to Be Restored from Stack Memory POP rp instruction SP RETI and RETB instruction RET instruction SP Register pair lower SP PC7 to PC0 SP PC7 to PC0 SP + 1 Register pair upper SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP User’s Manual U15104EJ2V0UD SP + 3 49 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers are mapped at particular address FEE0H to FEFFH in the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). They can be written with function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt for each bank. Table 3-3. Absolute Address of General-Purpose Registers Bank BANK0 BANK1 50 Register Absolute Function Name Absolute Name Address H R7 F E F F H L R6 D Bank BANK2 Register Absolute Function Name Absolute Name Address H R7 F E E F H F E F E H L R6 F E E E H R5 F E F D H D R5 F E E D H E R4 F E F C H E R4 F E E C H B R3 F E F B H B R3 F E E B H C R2 F E F A H C R2 F E E A H A R1 F E F 9 H A R1 F E E 9 H X R0 F E F 8 H X R0 F E E 8 H H R7 F E F 7 H H R7 F E E 7 H L R6 F E F 6 H L R6 F E E 6 H D R5 F E F 5 H D R5 F E E 5 H E R4 F E F 4 H E R4 F E E 4 H B R3 F E F 3 H B R3 F E E 3 H C R2 F E F 2 H C R2 F E E 2 H A R1 F E F 1 H A R1 F E E 1 H X R0 F E F 0 H X R0 F E E 0 H BANK3 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Configuration of General-Purpose Register (a) Absolute Name 16-bit processing 8-bit processing FEFFH R7 BANK0 RP3 R6 FEF8H R5 BANK1 RP2 R4 FEE0H R3 RP1 BANK2 R2 FEE8H R1 RP0 BANK3 R0 FEE0H 15 0 7 0 (b) Function Name 16-bit processing 8-bit processing FEFFH H BANK0 HL L FEF8H D BANK1 DE E FEF0H B BC BANK2 C FEE8H A AX BANK3 X FEE0H 15 User’s Manual U15104EJ2V0UD 0 7 0 51 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFR) Unlike a general-purpose register, each special function register has special functions. SFRs are allocated in the FF00H to FFFFH area. SFRs are can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units: 1, 8, and 16, depends on the special function register type. The manipulatable bit units can be specified as follows. • 1-bit manipulation Use the symbol reserved in the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. • 8-bit manipulation Use the symbol reserved in the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. • 16-bit manipulation Use the symbol reserved in the assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, use an even address. Table 3-4 gives a list of special function registers. The meanings of items in the table are as follows. • Symbol This is a symbol to indicate an address of the special function register. These symbols are reserved for the DF178054 and RA78K0, and defined by header file sfrbit.h for the CC78K0. They can be written as instruction operands when the RA78K0, ID78K0, or ID78K0-NS is used. • R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: Read only R&Reset: Read only (reset to 0 when read) W: Write only • Bit units for manipulation indicates the manipulatable bit units: 1, 8, and 16. – indicates the bit units that cannot be manipulated. • After reset Indicates each register status upon reset. The values of special function registers whose addresses are not shown in the table are undefined at reset. 52 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (1/3) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FF00H Port 0 P0 R/W — FF01H Port 1 P1 R — FF03H Port 3 P3 R/W — FF04H Port 4 P4 — FF05H Port 5 P5 — FF06H Port 6 P6 — FF07H Port 7 P7 — FF0CH Port 12 P12 — FF0DH Port 13 P13 — FF10H A/D conversion result register 3Note 1 ADCR3 FF11H — — R — R/W — 00H — — — Undefined — 00H FF12H A/D converter mode register 3 ADM3 FF13H Analog input channel specification register 3 ADS3 — — FF15H Power-fail comparison threshold value register 3 PFT3 — — FF16H Power-fail comparison mode register 3 PFM3 FF1BH POC status register POCS FF20H Port mode register 0 PM0 FF23H Port mode register 3 PM3 — FF24H Port mode register 4 PM4 — FF25H Port mode register 5 PM5 — FF26H Port mode register 6 PM6 — FF27H Port mode register 7 PM7 — FF2CH Port mode register 12 PM12 — FF34H Pull-up resistor option register 4 PU4 — FF40H Clock output select register CKS — FF41H BEEP clock select register 0 BEEPCL0 — FF42H Watchdog timer clock select register WDCS — FF48H External interrupt rising edge enable register EGP — FF49H External interrupt falling edge enable register EGN — FF69H Serial port select register 32 SIO32SEL — FF6AH Serial I/O shift register 32 SIO32 FF6BH Serial operating mode register 32 CSIM32 FF6CH Serial I/O shift register 31 SIO31 FF6DH Serial operating mode register 31 CSIM31 — R&Reset — R/W — — — RetainedNote 2 — FFH 00H — Undefined — 00H — Undefined — 00H Notes 1. This register can be accessed only in 8-bit units. When ADCR3 is read, the value of FF11H is read. 2. The value of this register is 03H only at reset by power-on clear. This register is not reset by the RESET pin or watchdog timer. Caution Do not access addresses to which no SFR is assigned. User’s Manual U15104EJ2V0UD 53 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (2/3) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset 1 Bit FF6EH Serial I/O shift register 30 SIO30 FF6FH Serial operating mode register 30 CSIM30 FF70H 8-bit compare register 52 CR52 FF71H 8-bit compare register 53 CR53 FF72H 8-bit timer counter 52 TM523 TM52 FF73H 8-bit timer counter 53 TM53 FF74H Timer clock select register 52 TCL52 FF75H 8-bit timer mode control register 52 TMC52 FF77H Timer clock select register 53 TLC53 FF78H 8-bit timer mode control register 53 TMC53 FF80H 8-bit compare register 50 CR50 — — FF81H 8-bit compare register 51 CR51 — — FF82H 8-bit timer counter 50 TM501 TM50 FF83H 8-bit timer counter 51 TM51 FF84H Timer clock select register 50 TCL50 FF85H 8-bit timer mode control register 50 TMC50 FF87H Timer clock select register 51 TCL51 FF88H 8-bit timer mode control register 51 TMC51 — FFA0H PLL mode select register PLLMD — FFA1H PLL reference mode register PLLRF — 0FH FFA2H PLL unlock F/F judge register PLLUL R&Reset — RetainedNote 1 FFA3H PLL data transfer register PLLNS W — 00H FFA6H PLL data registers FFA7H PLL data register L PLLR PLL data register H R/W 8 Bits 16 Bits W R — — Undefined — 00H — — Undefined — — — 00H — R/W — — — — — — R — Undefined 00H — R/W — — — — PLLRL — R/W Undefined PLLRH FFA8H PLL data register 0 PLLR0 — FFA9H IF counter mode select register IFCMD — 00H FFAAH DTS system clock select register DTSCK — 00HNote 2 FFABH IF counter gate judge register IFCJG R — 00H FFACH IF counter control register IFCCR W — FFAEH IF counter register IFCR FFAFH IFCRL IFCRH R — — — — Notes 1. Undefined by power-on clear reset only. 2. Though the initial value of the DTS system clock select register (DTSCK) is 00H, be sure to set this register to 01H before using it. Caution Do not access addresses to which no SFR is assigned. 54 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (3/3) Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFD0H | FFDFH External access areaNote 1 FFE0H Interrupt request flag register 0L FFE1H Interrupt request flag register 0H FFE4H Interrupt mask flag register 0L FFE5H Interrupt mask flag register 0H FFE8H Priority specification flag register 0L FFE9H Priority specification flag register 0H FFF0H Memory size switching register IMS — — CFHNote 2 FFF4H Internal expansion RAM size switching register IXS — — 0CHNote 3 FFF9H Watchdog timer mode register WDTM — 00H FFFAH Oscillation stabilization time switching register OSTS — 04H FFFBH Processor clock control register PCC R/W IF0 — IF0L Undefined 00H IF0H MK0 MK0L FFH MK0H PR0 PR0L PR0H — — Notes 1. The external access area cannot be accessed by means of SFR addressing. Use direct addressing to access this area. 2. The initial value of the memory size switching register (IMS) is CFH. Set the values of these registers of each model as follows: Part Number IMS µPD178053 C6H µPD178054 C8H µPD178F054 Value equivalent to mask ROM version 3. Do not assign a value other than the initial value to the internal expansion RAM size switching register (IXS). Caution Do not access addresses to which no SFR is assigned. User’s Manual U15104EJ2V0UD 55 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents, and the contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 User’s Manual Instruction (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit. That is, using relative addressing, the program branches in the range –128 to +127 relative to the first address of the next instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC indicates the start address of the instruction after the BR instruction. PC + 15 8 α 7 0 6 S jdisp8 15 0 PC When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. 56 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !add16 instructions can be used to branch to any location in the memory. The CALLF !addr11 instruction is used to branch to the area between 0800H through 0FFFH. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low Addr. High Addr. 15 8 7 0 PC In the case of CALLF !addr11 instruction 7 6 4 3 fa10_8 0 CALLF fa7_0 15 PC 0 11 10 0 0 0 8 7 0 1 User’s Manual U15104EJ2V0UD 57 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This addressing is used when the CALLT [addr5] instruction is executed. This instruction references an address stored in the memory table between 40H through 7FH, and can be used to branch to any location in the memory. [Illustration] 7 Operation code 6 1 5 1 1 ta4–0 1 15 Effective address 0 7 0 0 0 0 0 0 Memory (Table) 0 8 7 6 0 0 1 5 1 0 0 0 Low Addr. Effective address+1 High Addr. 15 8 7 PC 58 User’s Manual U15104EJ2V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 0 X 8 7 0 PC User’s Manual U15104EJ2V0UD 59 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The registers that functions as an accumulator (A and AX) among the general-purpose registers are automatically addressed (implied). Of the µPD178054 Subseries instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA/ADJBS A register for storage of numeric values which become decimal correction targets ROR4/ROL4 A register for storage of digit data which undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Example] In the case of MULU X With an 8-bit × 8-bit multiply instruction, the product of register A and register X is stored in AX. In this example, the A and AX registers are specified by implied addressing. 60 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] This addressing mode is used to access a general-purpose register as an operand. The register to be accessed is specified by the register bank select flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Symbol Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL 'r' and 'rp' can be written with function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) as well as absolute names (R0 to R7 and RP0 to RP3). [Example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specification code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specification code User’s Manual U15104EJ2V0UD 61 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory with immediate data in an instruction word is directly addressed. [Operand format] Symbol Description addr16 Label or 16-bit immediate data [Example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 Op code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (low order) addr16 (high order) Memory 62 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the fixed 256-byte space FE20H to FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is one part of all the SFR areas. In this area, ports which are frequently accessed in a program and a compare register and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration] below. [Operand format] Symbol Description saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immediate data (even address only) [Example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 Op code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 8 7 15 Effective address 1 1 1 1 1 1 1 0 α When 8-bit immediate data is 20H to FFH, α = 0 When 8-bit immediate data is 00H to 1FH, α = 1 User’s Manual U15104EJ2V0UD 63 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special Function Register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Symbol Description sfr Special function register name sfrp 16-bit manipulatable special function register name (even address only) [Example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 8 7 15 Effective address 64 1 1 1 1 1 1 1 1 User’s Manual U15104EJ2V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] This addressing is used to address the memory to be manipulated by using the contents of the register pair specified by the register pair code in an instruction word as the operand address. The register pair specified is in the register bank specified by the register bank select flags (RBS0 and RBS1). This addressing can be used for the entire memory space. [Operand format] Symbol — Description [DE], [HL] [Example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 15 DE 8 7 E D 7 7 0 Memory 0 0 A User’s Manual U15104EJ2V0UD 65 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] This addressing mode is used to address a memory location specified by the result of adding the 8-bit immediate data to the contents of the HL register pair which is used as a base register. The HL register pair accessed is the register in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Symbol — Description [HL + byte] [Example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 66 User’s Manual U15104EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] This addressing mode is used to address a memory location specified by the result of adding the contents of the B or C register specified in the instruction word to the contents of the HL register pair which is used as a base register. The HL, B, and C registers accessed are the registers in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Symbol — Description [HL + B], [HL + C] [Example] In the case of MOV A, [HL + B] Operation code 1 0 1 0 1 0 1 1 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/restored upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. [Example] In the case of PUSH DE Operation code 1 0 1 1 0 1 0 1 User’s Manual U15104EJ2V0UD 67 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µPD178054 Subseries units incorporate input, output, and I/O ports consisting of 6, 3, and 53 pins, respectively. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins. Figure 4-1. Port Types Port 5 P50 Port 6 P60 Port 7 P70 Port 12 P120 Port 13 P130 P00 P06 P57 P10 68 P15 P30 P67 P37 P40 P77 P47 P125 P132 User’s Manual U15104EJ2V0UD Port 0 Port 1 Port 3 Port 4 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name P00 to P04 I/O I/O P05, P06 Function Port 0 7-bit I/O port Alternate Function INTP0 to INTP4 — Input/output can be specified in 1-bit units. P10 to P15 Input Port 1 6-bit input port P30 to P32 I/O Port 3 8-bit I/O port P33 ANI0 to ANI5 — TI50 Input/output can be specified in 1-bit units. P34 TI51 P35 — P36 BEEP0 P37 BUZ P40 to 47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Interrupt function by key input is provided. — P50 to P57 I/O Port 5 8-bit I/O port Input/output can be specified in 1-bit units. — P60 to P67 I/O Port 6 8-bit I/O port Input/output can be specified in 1-bit units. — P70 I/O Port 7 8-bit I/O port Input/output can be specified in 1-bit units. P71 P72 SI30 SO30 SCK30 P73 — P74 SI31 P75 SO31 P76 SCK31 P77 TI52 P120 I/O P121 Port 12 6-bit I/O port Input/output can be specified in 1-bit units. SI32 SO32 P122 SCK32 P123 SI321 P124 SO321 P125 SCK321 P130 P131 Output Port 13 3-bit output port N-ch open-drain output port (12 V tolerance) P132 TO50 TO51 TO52 User’s Manual U15104EJ2V0UD 69 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration The ports consist of the following hardware. Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 3 to 7, 12) Port Total: 62 port pins (6 inputs, 3 outputs, 53 I/Os) 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Input or output mode can be specified for port 0 in 1-bit units using port mode register 0 (PM0). Alternate functions include external interrupt request input. Reset input sets port 0 to the input mode. Figures 4-2 and 4-3 show the block diagrams of port 0. Caution Because port 0 also serves as an external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1. Figure 4-2. Block Diagram of P00 to P04 Alternate function Selector Internal bus RD WRPORT P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P04/INTP4 Output latch (P00 to P04) WRPM PM00 to PM04 PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal 70 User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P05 and P06 RD Internal bus Selector WRPORT Output latch (P05, P06) P05, P06 WRPM PM05, PM06 PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal 4.2.2 Port 1 Port 1 is a 6-bit input port. Alternate functions include A/D converter analog input. Figure 4-4 shows the block diagram of port 1. Figure 4-4. Block Diagram of P10 to P15 Internal bus RD + P10/ANI0 to P15/ANI5 A/D converter _ VREF RD : Port 1 read signal User’s Manual U15104EJ2V0UD 71 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 3 in 1-bit units using port mode register 3 (PM3). Alternate functions include timer input and buzzer output. Reset input sets port 3 to the input mode. Figures 4-5 to 4-7 show the block diagrams of port 3. Figure 4-5. Block Diagram of P30 to P32 and P35 RD Internal bus Selector WRPORT Output latch (P30 to P32, P35) P30 to P32, P35 WRMM PM30 to PM32, PM35 PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal 72 User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P33 and P34 Alternate function Internal bus Selector RD WRPORT P33/TI50 P34/TI51 Output latch (P33, P34) WRPM PM33, PM34 PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal Figure 4-7. Block Diagram of P36 and P37 RD Internal bus Selector WRPORT Output latch (P36, P37) P36/BEEP0 P37/BUZ WRPM PM36, PM37 Alternate function PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal User’s Manual U15104EJ2V0UD 73 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 4 in 1-bit units using port mode register 4 (PM4). Connection of pull-up resistors can be specified in 1-bit units using pull-up resistor option register 4 (PU4). The interrupt request flag (KYIF) can be set to 1 by detecting key inputs. When using this function, be sure to set the MEM register to 01H. Reset input sets port 4 to input mode. Figures 4-8 and 4-9 show a block diagram of port 4 and block diagram of the key input detector, respectively. Figure 4-8. Block Diagram of P40 to P47 VDD WRPU PU40 to PU47 P-ch RD Internal bus Selector WRPORT Output latch (P40 to P47) WRPM PM40 to PM47 PU: Pull-up resistor option register PM: Port mode register RD: Port 4 read signal WR: Port 4 write signal 74 User’s Manual U15104EJ2V0UD P40 to P47 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Key Input Detector P40 P41 P42 P43 Key input detector P44 INTKR P45 “1” when MEM = 01H P46 P47 Cautions 1. This register is valid only when the MEM register is set to 01H. 2. Key return can be detected only when all the pins of P40 to P47 are high level. When any one is low level, even if falling edge is generated at the other pins, the key return signal cannot be detected. 4.2.5 Port 5 Port 5 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 5 in 1-bit units using port mode register 5 (PM5). Reset input sets port 5 to the input mode. Figure 4-10 shows the block diagram of port 5. Figure 4-10. Block Diagram of P50 to P57 RD Internal bus Selector WRPORT Output latch (P50 to P57) P50 to P57 WRPM PM50 to PM57 PM: Port mode register RD: Port 5 read signal WR: Port 5 write signal User’s Manual U15104EJ2V0UD 75 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 Port 6 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 6 in 1-bit units using port mode register 6 (PM6). Reset input sets port 6 to the input mode. Figure 4-11 shows the block diagram of port 6. Figure 4-11. Block Diagram of P60 to P67 RD Internal bus Selector WRPORT Output latch (P60 to P67) P60 to P67 WRPM PM60 to PM67 PM: Port mode register RD: Port 6 read signal WR: Port 6 write signal 76 User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 Port 7 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 7 in 1-bit units using port mode register 7 (PM7). Alternate functions include serial interface data I/O, clock I/O, and timer input. Reset input sets port 7 to the input mode. Figures 4-12 to 4-15 show the block diagrams of port 7. Figure 4-12. Block Diagram of P70, P74, and P77 Alternate function Selector Internal bus RD WRPORT Output latch (P70, P74, P77) P70/SI30 P74/SI31 P77/TI52 WRPM PM70, PM74, PM77 PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal User’s Manual U15104EJ2V0UD 77 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P71 and P75 RD Internal bus Selector WRPORT Output latch (P71, P75) P71/SO30 P75/SO31 WRPM PM71, PM75 Alternate function PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal Figure 4-14. Block Diagram of P72 and P76 Alternate function Selector Internal bus RD WRPORT Output latch (P72, P76) P72/SCK30 P76/SCK31 WRPM PM72, PM76 Alternate function PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal 78 User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P73 RD Internal bus Selector WRPORT Output latch (P73) P73 WRMM PM73 PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal User’s Manual U15104EJ2V0UD 79 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 12 Port 12 is a 6-bit I/O port with an output latch. Input or output mode can be specified for port 12 in 1-bit units using port mode register 12 (PM12). Alternate functions include serial interface data I/O and clock I/O. Reset input sets port 12 to the input mode. Figures 4-16 to 4-18 show the block diagrams of port 12. Figure 4-16. Block Diagram of P120 and P123 Alternate function Selector Internal bus RD WRPORT P120/SI32 P123/SI321 Output latch (P120, P123) WRPM PM120, PM123 PM: Port mode register RD: Port 12 read signal WR: Port 12 write signal 80 User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P121 and P124 RD Internal bus Selector WRPORT Output latch (P121, P124) P121/SO32 P124/SO321 WRPM PM121, PM124 Alternate function PM: Port mode register RD: Port 12 read signal WR: Port 12 write signal Figure 4-18. Block Diagram of P122 and P125 Alternate function Selector Internal bus RD WRPORT Output latch (P122, P125) P122/SCK32 P125/SCK321 WRPM PM122, PM125 Alternate function PM: Port mode register RD: Port 12 read signal WR: Port 12 write signal User’s Manual U15104EJ2V0UD 81 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 13 Port 13 is a 3-bit N-ch open-drain output port with an output latch. The pins of this port are also used as timer output pins. Reset input sets port 13 in the general-purpose output port mode. The port 13 block diagram is shown in Figure 4-19. Figure 4-19. Block Diagram of P130 to P132 Internal bus RD WRPORT P130/TO50 P131/TO51 P132/TO52 Output latch (P130 to P132) Alternate function RD: Port 13 read signal WR: Port 13 write signal 82 User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Functions The following two types of registers control the ports. • Port mode registers (PM0, PM3 to PM7, PM12) • Pull-up resistor option register (PU4) (1) Port mode registers (PM0, PM3 to PM7, PM12) These registers are used to set the port input/output mode in 1-bit units. PM0, PM3 to PM7, and PM12 are independently set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets these registers to FFH. When using a port pin as an alternate-function pin, set the values of the port mode registers and the output latches as shown in Table 4-3. Cautions 1. P10 to P17 are input-only pins, and P130 to P132 are output-only pins. 2. As port 0 has an alternate function as an external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. User’s Manual U15104EJ2V0UD 83 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name Alternate Functions Name PM×× P×× I/O P00 to P04 INTP0 to INTP4 Input 1 × P33 TI50 Input 1 × P34 TI51 Input 1 × P36 BEEP0 Output 0 0 P37 BUZ Output 0 0 P70 SI30 Input 1 × P71 SO30 Output 0 0 P72 SCK30 Input 1 × Output 0 0 P74 SI31 Input 1 × P75 SO31 Output 0 0 P76 SCK31 Input 1 × Output 0 0 P77 TI52 Input 1 × P120 SI32 Input 1 × P121 SO32 Output 0 0 P122 SCK32 Input 1 × Output 0 0 P123 SI321 Input 1 × P124 SO321 Output 0 0 P125 SCK321 Input 1 × Output 0 0 Output — 0 P130 to P132 TO50 to TO52 Caution When using the above alternate function pins as an output port, be sure to set the output latch (P××) to 0. Remark ×: Don’t care PM××: Port mode register P××: 84 Output latch of port User’s Manual U15104EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-20. Format of Port Mode Registers Address After reset R/W PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R/W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H FFH R/W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R/W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W FF2CH FFH R/W Symbol 7 PM0 1 PM12 1 6 1 5 4 3 2 1 0 PM125 PM124 PM123 PM122 PM121 PM120 PMmn Pmn pin input/output mode selection (m = 0, 3 to 7, 12 : n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User’s Manual U15104EJ2V0UD 85 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option register 4 (PU4) This register is used to specify the use of the internal pull-up resistors of port 4. A pull-up resistor can only be used internally for the bit specified by PU4. PU4 can be set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets PU4 to 00H. Figure 4-21. Format of Pull-up Resistor Option Register 4 (PU4) Symbol PU4 PU4n 86 7 6 5 4 3 2 1 0 Address After reset R/W PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 Selection of internal pull-up resistor for P4n (n = 0 to 7) 0 Internal pull-up resistor not used 1 Internal pull-up resistor used User’s Manual U15104EJ2V0UD FF34H 00H R/W CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O ports (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, for a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 Reading from I/O ports (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O ports (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is off, the pin status does not change. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, for a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. User’s Manual U15104EJ2V0UD 87 CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. This system clock oscillator is connected to 4.5 MHz crystal resonator. At this time, set bit 0 (DTSCK0) of the DTS system clock select register (DTSCK) to 1. Set the DTSCK0 flag after power application and reset by the RESET pin, and before using the basic timer, buzzer output control circuit, PLL frequency synthesizer, and frequency counter. Oscillation can be stopped by executing the STOP instruction. Figure 5-1. Format of DTS System Clock Select Register (DTSCK) Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W DTSCK 0 0 0 0 0 0 0 DTSCK0 FFAAH 00H R/W DTSCK0 88 Selects system clock 1 4.5 MHz 0 Setting prohibited User’s Manual U15104EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator System clock oscillator Figure 5-2. Block Diagram of Clock Generator Prescaler X2 System clock oscillator Clock to peripheral hardware Prescaler fX fX 2 fX fX 4 f X 23 2 2 2 Selector X1 Standby controller Wait controller CPU clock (fCPU) 3 STOP 0 0 0 0 0 PCC2 PCC1 PCC0 Processor clock control register (PCC) Internal bus User’s Manual U15104EJ2V0UD 89 CHAPTER 5 CLOCK GENERATOR 5.3 Register Controlling Clock Generator The clock generator is controlled by the processor clock control register (PCC). PCC sets the CPU clock. PCC is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets PCC to 04H. Figure 5-3. Format of Processor Clock Control Register (PCC) Symbol 7 6 5 4 3 PCC 0 0 0 0 0 R/W 2 Address After reset R/W FFFBH 04H R/WNote CPU cIock (fCPU) selection (0.45 µs) 0 0 0 fX 0 0 1 fX/2 (0.89 µ s) 0 1 0 fX/2 (1.78 µ s) 0 1 1 fX/23 (3.56 µ s) 1 0 0 fX/24 (7.11 µ s) Note 0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 Other than above 1 2 Setting prohibited Bits 3 to 7 are read only. Remarks 1. fX: System clock oscillation frequency 2. ( ): Minimum instruction execution time: 2/fCPU at fX = 4.5 MHz operation 90 User’s Manual U15104EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 System clock oscillator The system clock oscillator oscillates with a crystal resonator (4.5 MHz TYP.) connected to the X1 and X2 pins. Figure 5-4 shows an external circuit of the system clock oscillator. Figure 5-4. External Circuit of System Clock Oscillator Crystal oscillation X2 X1 IC Crystal resonator Caution When using a system clock oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-4 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. User’s Manual U15104EJ2V0UD 91 CHAPTER 5 CLOCK GENERATOR Figure 5-5 shows examples of incorrectly connected resonators. Figure 5-5. Examples of Incorrect Resonator Connection (1/2) (a) Wiring of connection (b) Signal lines cross circuits is too long each other PORTn (n = 0, 1, 3 to 7, 12, 13) X2 X1 IC X2 (c) High fluctuating current is near a signal lines X1 IC (d) Current flows through the ground line of the oscillator (potential at points A, B, and C fluctuate) VDD PORTn (n = 0, 1, 3 to 7, 12, 13) X2 X1 IC X2 High current A X1 B High current 92 User’s Manual U15104EJ2V0UD IC C CHAPTER 5 CLOCK GENERATOR Figure 5-5. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched X2 X1 IC 5.4.2 Divider The divider divides the system clock oscillator output (fX) and generates various clocks. User’s Manual U15104EJ2V0UD 93 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode, such as the standby mode. • System clock • CPU clock fX fCPU • Clock to peripheral hardware The following clock generator functions and operations are determined by the processor clock control register (PCC). (a) Upon generation of the RESET signal, the lowest speed mode of the system clock (7.11 µs when operated at 4.5 MHz) is selected (PCC = 04H). System clock oscillation stops while a low level is applied to the RESET pin. (b) One of the five CPU clock types (0.45, 0.89, 1.78, 3.56, 7.11 µs at 4.5 MHz) can be selected by setting PCC. (c) Two standby modes, STOP and HALT, are available. (d) The system clock is divided and supplied to the peripheral hardware. The peripheral hardware also stops if the system clock is stopped. 94 User’s Manual U15104EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.6 Changing System Clock and CPU Clock Settings 5.6.1 Time required for switching between system clock and CPU clock The system clock and CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). The actual switching operation is not performed directly after writing to PCC, but operation continues on the preswitched clock for several instructions (refer to Table 5-2). Table 5-2. Maximum Time Required for CPU Clock Switching Set Values Before Switching Set Values After Switching PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 8 instructions 0 1 0 4 instructions 4 instructions 0 1 1 2 instructions 2 instructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction Remark 16 instructions 0 0 1 1 1 0 0 16 instructions 16 instructions 16 instructions 8 instructions 8 instructions 8 instructions 4 instructions 4 instructions 2 instructions 1 instruction One instruction is the minimum instruction execution time with the preswitched CPU clock. User’s Manual U15104EJ2V0UD 95 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.1 Functions of 8-Bit Timer/Event Counters 50 to 53 8-bit timer/event counters 50 to 53 have the following two modes. • Mode in which an 8-bit timer/event counter is used alone (single mode) • Mode in which the two timer/event counters are cascaded (cascade mode with a resolution of 16 bits) These two modes are explained below. (1) Mode in which an 8-bit timer/event counter is used alone (single mode) The timer/event counter operates as an 8-bit timer/event counter. In this mode, the following functions can be used. • Interval timer • External event counter • Square wave output • PWM output Caution Timer 53 can be used only as an interval timer since it does not include timer input and output pins. (2) Mode in which the two timer/event counters are cascaded (cascade mode with a resolution of 16 bits) By connecting timer 50 or timer 52 as a lower timer and timer 51 or timer 53 as a higher timer in cascade, they operate as a 16-bit timer/event counter. In this mode, the following functions can be used: • Interval timer with 16-bit resolution • External event counter with 16-bit resolution • Square wave output with 16-bit resolution Figures 6-1 to 6-4 show the block diagrams of 8-bit timer/event counters 50 to 53. 96 User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-1. Block Diagram of 8-Bit Timer/Event Counter 50 Match Selector TI50/P33 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Selector S Q INV 8-bit timer counter OVF 50 (TM50) R INTTM50 Selector 8-bit compare register 50 (CR50) Mask circuit Internal bus TO50/P130 Clear Output latch (P130) S 3 Level inversion R Selector TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Timer mode control register 50 (TMC50) TCL502 TCL501 TCL500 Timer clock select register 50 (TCL50) Internal bus Figure 6-2. Block Diagram of 8-Bit Timer/Event Counter 51 Match Selector TI51/P34 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Selector S Q INV 8-bit timer counter OVF 51 (TM51) R INTTM51 Selector 8-bit compare register 51 (CR51) Mask circuit Internal bus TO51/P131 Clear S 3 R Selector TCL512 TCL511 TCL510 Timer clock select register 51 (TCL51) Output latch (P131) Level inversion TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer mode control register 51 (TMC51) Internal bus User’s Manual U15104EJ2V0UD 97 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-3. Block Diagram of 8-Bit Timer/Event Counter 52 Match Selector TI52/P77 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Selector INTTM52 S Q INV 8-bit timer counter OVF 52 (TM52) R TO52/P132 Clear Output latch (P132) S 3 Level inversion R Selector TCE52 TMC526 TMC524 LVS52 LVR52 TMC521 TOE52 Timer mode control register 52 (TMC52) TCL522 TCL521 TCL520 Timer clock select register 52 (TCL52) Internal bus Figure 6-4. Block Diagram of 8-Bit Timer 53 Internal bus Match Selector fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 INTTM53 Mask circuit 8-bit compare register 53 (CR53) 8-bit timer counter 53 (TM53) Clear 3 Selector LVS51 LVR51 TCL532 TCL531 TCL530 Timer clock select register 53 (TCL53) Timer mode control register 53 (TMC53) Internal bus 98 Selector 8-bit compare register 52 (CR52) Mask circuit Internal bus User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.2 Configuration of 8-Bit Timer/Event Counters 50 to 53 8-bit timer/event counters 50 to 53 consist of the following hardware. Table 6-1. Configuration of 8-Bit Timer/Event Counters 50 to 53 Item Configuration Timer registers 8-bit timer counters 50, 51, 52, and 53 (TM50 to TM53) Registers 8-bit compare registers 50, 51, 52, and 53 (CR50 to CR53) Timer outputs 3 lines (TO50 to TO52) Control registers • Timer clock select registers 50, 51, 52, and 53 (TCL50 to TCL53) • 8-bit timer mode control registers 50, 51, 52, and 53 (TMC50 to TMC53) (1) 8-bit timer counters 50, 51, 52, and 53 (TM50 to TM53) TM5n is an 8-bit read-only register that counts the count pulses. The counter is incremented at the rising edge of the count clock. TM50 and TM51 or TM52 and TM53 can be cascaded and used as a 16-bit timer. When TM50 and TM51 are cascaded and used as a 16-bit timer, its value can be read using a 16-bit memory manipulation instruction. However, because TM50 and TM51 are connected with the internal 8-bit bus, they are read one at a time. Therefore, read the value of TM50 and TM51 when used as a 16-bit timer two times for comparison, taking changes in the values during counting into consideration. When TM52 and TM53 are cascaded and used as a 16-bit timer, its value can be read using a 16-bit memory manipulation instruction. However, because TM52 and TM53 are connected with the internal 8-bit bus, they are read one at a time. Therefore, read the value of TM52 and TM53 when used as a 16-bit timer two times for comparison, taking changes in the values during counting into consideration. If the count value is read while the timer is operating, stop input of the count clock, and read the count value at that point. The count value is cleared to 00H in the following cases. <1> RESET input <2> Clearing TCE5n <3> Match between TM5n and CR5n in mode in which the timer is cleared and started on match between TM5n and CR5n Caution When TM50 and TM51 or TM52 and TM53 are cascaded, the value of the timer is cleared to 00H even if the least significant bit (TCE50 or TCE52) of timer mode control register 50 (TMC50) or 52 (TMC52) is cleared. Remark n = 0 to 3 User’s Manual U15104EJ2V0UD 99 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) 8-bit compare registers 50, 51, 52, and 53 (CR50 to CR53) The value set to CR5n is always compared with the value of 8-bit timer counter 5n (TM5n). When the value of a compare register matches the count value of the corresponding counter, an interrupt request (INTTM5n) is generated (in a mode other than PWM mode). If TM50 and TM51 are cascaded and used as a 16-bit timer, CR50 and CR51 operate together as a 16-bit compare register. The 16-bit counter value and 16-bit compare register value are compared, and when the two values match, an interrupt request (INTTM50) is generated. At this time, the interrupt request INTTM51 is also generated. Therefore, mask INTTM51 when using TM50 and TM51 in the cascade mode. If TM52 and TM53 are cascaded and used as a 16-bit timer, CR52 and CR53 operate together as a 16-bit compare register. The 16-bit counter value and 16-bit compare register value are compared, and when the two values match, an interrupt request (INTTM52) is generated. At this time, the interrupt request INTTM53 is also generated. Therefore, mask INTTM53 when using TM52 and TM53 in the cascade mode. Caution When TM50 and TM51 or TM52 and TM53 are cascaded, be sure to change the CR5n setting value after stopping the timer operation of cascaded TM5n. Remark 100 n = 0 to 3 User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.3 Registers Controlling 8-Bit Timer/Event Counters 50 to 53 The following two types of registers control the 8-bit timer/event counters 50 to 53. • Timer clock select registers 50 to 53 (TCL50 to TCL53) • 8-bit timer mode control registers 50 to 53 (TMC50 to TMC53) (1) Timer clock select registers 50 to 52 (TCL50 to TCL52) These registers select the count clock of 8-bit timer counter 5n (TM5n) and the valid edge of the TI5n input. TCL5n is set with an 8-bit memory manipulation instruction. Reset input clears TCL50 to TCL52 to 00H. Remark n = 0 to 2 Figure 6-5. Format of Timer Clock Select Registers 50 to 52 (TCL50 to TCL52) Symbol 7 6 5 4 3 TCL50 0 0 0 0 0 7 6 5 4 3 0 0 0 0 0 7 6 5 4 3 0 0 0 0 0 TCL51 TCL52 TCL5n2 TCL5n1 TCL5n0 2 1 0 TCL502 TCL501 TCL500 2 1 1 After reset R/W FF84H 00H R/W FF87H 00H R/W FF74H 00H R/W 0 TCL512 TCL511 TCL510 2 Address 0 TCL522 TCL521 TCL520 Count clock selection 0 0 0 Falling edge of TI5n 0 0 1 Rising edge of TI5n 0 1 0 fX/2 0 1 1 fX/23 (563 kHz) 1 0 0 fX/25 (141 kHz) 1 0 1 fX/27 (35.2 kHz) 1 1 0 fX/29 (8.79 kHz) 1 1 1 fX/211 (2.20 kHz) (2.25 MHz) Cautions 1. Before changing the data of TCL5n, be sure to stop the timer operation. 2. Be sure to set bits 3 to 7 to 0. Remarks 1. In the cascade mode, the setting of bits TCL50 or TCL52 of the lower timer (TM50 or TM52) is valid, and the setting of bits TCL51 or TCL53 of the higher timer (TM51 or TM53) is invalid. 2. n = 0 to 2 3. fX: System clock oscillation frequency 4. ( ): fX = 4.5 MHz User’s Manual U15104EJ2V0UD 101 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) Timer clock select register 53 (TCL53) This register selects the count clock of 8-bit timer counter 53 (TM53). TCL53 is set with an 8-bit memory manipulation instruction. Reset input clears TCL53 to 00H. Figure 6-6. Format of Timer Clock Select Register 53 (TCL53) Symbol 7 6 5 4 3 TCL53 0 0 0 0 0 TCL532 TCL531 TCL530 2 1 0 TCL532 TCL531 TCL530 Address After reset R/W FF77H 00H R/W Count clock selection 0 0 0 Setting prohibited 0 0 1 Setting prohibited 0 1 0 fX/2 0 1 1 fX/23 (563 kHz) 1 0 0 fX/25 (141 kHz) 1 0 1 fX/27 (35.2 kHz) 1 1 0 fX/29 (8.79 kHz) 1 1 1 fX/211 (2.20 kHz) (2.25 MHz) Cautions 1. Before changing the data of TCL53, be sure to stop the timer operation. 2. Be sure to reset bits 3 to 7 to 0. Remarks 1. In the cascade mode, the setting of bit TCL53 of the higher timer (TM53) is invalid. 2. fX: System clock oscillation frequency 3. ( ): fX = 4.5 MHz (3) 8-bit timer mode control registers 50 to 52 (TMC50 to TMC52) The TMC5n register is used for the following. <1> Controlling count operation of 8-bit timer counter 5n (TM5n) <2> Selecting operation mode of 8-bit timer counter 5n (TM5n) <3> Selecting single mode or cascade mode <4> Setting status of timer output F/F (flip-flop) <5> Controlling timer F/F or selecting active level in PWM (free-running) mode <6> Controlling timer output TMC5n can be set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears TMC5n to 00H. Remark 102 n = 0 to 2 User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-7. Format of 8-Bit Timer Mode Control Registers 50 to 52 (TMC50 to TMC52) Symbol <7> 6 5 TMC50 TCE50 TMC506 0 <7> 5 6 TMC51 TCE51 TMC516 0 <7> 5 6 TMC52 TCE52 TMC526 0 4 <3> <2> 1 <0> After reset R/W FF85H 00H R/W FF88H 00H R/W FF75H 00H R/W TMC504 LVS50 LVR50 TMC501 TOE50 4 <3> <2> 1 <0> TMC514 LVS51 LVR51 TMC511 TOE51 4 <3> <2> 1 <0> TMC524 LVS52 LVR52 TMC521 TOE52 TCE5n Control of count operation of TM5n 0 Clears counter to 0 and disables count operation (disables prescaler) 1 Starts count operation TMC5n6 Selection of operating mode of TM5n 0 Mode of clearing and starting TM5n on match between TM5n and CR5n 1 PWM (free-running) mode TMC5n4 0 1Note Selection of single mode or cascade mode Single mode Cascade mode (connected to lower timer) LVS5n LVR5n Setting status of timer output F/F 0 0 Not affected 0 1 Resets timer output F/F to 0 1 0 Sets timer output F/F to 1 1 1 Setting prohibited TMC5n1 Other than PWM mode (TMC5n6 = 0) PWM mode (TMC5n6 = 1) Control of timer F/F Selection of active level 0 Disables inversion operation High active 1 Enables inversion operation Low active TOE5n Note Address Control of timer output 0 Disables output (port mode) 1 Enables output Since the higher timer settings become valid, the lower timer TMC504/TMC524 settings become invalid. Caution Be sure to reset bit 4 (TMC5n4) to 0. Remarks 1. The PWM output becomes inactive when TCE5n = 0 in the PWM mode. 2. LVS5n and LVR5n are 0 when read after data has been set. 3. n = 0 to 2 User’s Manual U15104EJ2V0UD 103 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (4) 8-bit timer mode control register 53 (TMC53) The TMC53 register is used for the following. <1> Controlling count operation of 8-bit timer counter 53 (TM53) <2> Selecting single mode or cascade mode TMC53 can be set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears TMC53 to 00H. Figure 6-8. Format of 8-Bit Timer Mode Control Register 53 (TMC53) Symbol <7> TMC53 TCE53 6 5 4 3 2 1 0 Address After reset R/W 0 0 TMC534 0 0 0 0 FF78H 00H R/W TCE53 Control of count operation of TM53 0 Clears counter to 0 and disables count operation (disables prescaler) 1 Starts count operation TMC534 104 Selection of single mode or cascade mode 0 Single mode 1 Cascade mode (connected to lower timer (TM52)) User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4 Operations of 8-Bit Timer/Event Counters 50 to 53 6.4.1 Operation as interval timer (8-bit) The 8-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at the interval specified by the count value set in advance in 8-bit compare register 5n (CRn). When the count value of 8-bit timer counter 5n (TM5n) matches the value set in CR5n, the value of TM5n is cleared to 0. TM5n continues counting and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected by using bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register 5n (TCL5n). For the operation if the value of the compare register is changed while the timer count operation, refer to (2) in 6.5 Notes on 8-Bit Timer/Event Counters 50 to 53. [Setting] <1> Set each register. • TCL5n: Select a count clock. • CR5n: Compare value • TMC5n: Select a mode in which TM5n is cleared and started on match between TM5n and CR5n (TMC5n = 0000×××0B: × = Don’t care). <2> The count operation is started when TEC5n is set to 1. <3> INTTM5n is generated if the values of TM5n and CR5n match (TM5n is cleared to 00H). <4> After that, INTTM5n is repeatedly generated at fixed intervals. To stop the count operation, clear TCE5n to 0. Remark n = 0 to 3 User’s Manual U15104EJ2V0UD 105 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-9. Timing of Interval Timer Operation (1/3) (a) Basic operation t Count clock TM5n count value 00H 01H Count starts CR5n N N 00H 01H N 00H Cleared Cleared N N 01H N N TCE5n INTTM5n Interrupt request acknowledged Interrupt request acknowledged Interval time Interval time TO5n Interval time Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH 2. n = 0 to 3 106 User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-9. Timing of Interval Timer Operation (2/3) (b) When CR5n = 00H t Count clock TM5n 00H 00H 00H CR5n 00H 00H TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH t Count clock 01 TM5n CR5n FF FE FF 00 FE FF FF 00 FF TCE5n INTTM5n Interrupt acknowledged TO5n Interrupt acknowledged Interval time n = 0 to 3 User’s Manual U15104EJ2V0UD 107 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-9. Timing of Interval Timer Operation (3/3) (d) Operation when CR5n is changed (M < N) Count clock TM5n N 00H M N FFH 00H N CR5n M 00H M TCE5n H INTTM5n TO5n CR5n is changed. TM5n overflows because M < N (e) Operation when CR5n is changed (M > N) Count clock TM5n CR5n N–1 N 00H 01H N N M–1 M TCE5n H INTTM5n TO5n CR5n is changed. n = 0 to 3 108 User’s Manual U15104EJ2V0UD M 00H 01H CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.2 Operation as external event counter (timers 50 to 52) The external event counter counts the number of clock pulses input from an external source to the TI5n pin using 8-bit timer counter 5n (TM5n). Each time the valid edge specified by timer clock select register 5n (TCL5n) has been input to TI5n, the value of TM5n is incremented. As the valid edge, either the rising or falling edge can be selected. When the count value of TM5n matches the value of 8-bit compare register 5n (CR5n), TM5n is cleared to 0, and an interrupt request signal (INTTM5n) is generated. After that, each time the value of TM5n matches the value of CR5n, INTTM5n is generated. [Setting] <1> Set each register. • TCL5n: Select the valid edge of TI5n input. • CR5n: Compare value • TMC5n: Select a mode in which TM5n is cleared and started on match between TM5n and CR5n. <2> The count operation is started when TEC5n is set to 1. <3> INTTM5n is generated if the values of TM5n and CR5n match (TM5n is cleared to 00H). <4> After that, INTTM5n is generated each time the value of TM5n matches the value of CR5n. To stop the count operation, clear TCE5n to 0. Remark n = 0 to 2 Figure 6-10. Operation Timing of External Event Counter (with Rising Edge Specified) TI5n TM5n count value 00 01 02 03 04 05 CR5n N–1 N 00 01 02 03 N INTTM5n n = 0 to 2 User’s Manual U15104EJ2V0UD 109 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.3 Square wave output operation (8-bit resolution) (timers 50 to 52) 8-bit timer/event counter TM5n can be used to output a square wave with any frequency at time interval specified by the value set in advance in 8-bit compare register 5n (CR5n). When bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) is set to 1, the output status of TO5n is inverted at the interval specified by the count value set in advance to CR5n. In this way, a square wave (duty factor = 50%) of any frequency can be output. [Setting] <1> Set each register. • Reset the port latch and port mode register to “0”. • TCL5n: Select a count clock. • CR5n: Compare value • TMC5n: Mode in which TM5n is cleared and started on match between TM5n and CR5n LVS5n LVR5n Sets Status of Timer Output F/F 1 0 High-level output 0 1 Low-level output Enable inverting the timer F/F. Enable the timer output → TOE5n = 1. <2> When TCE5n is set to 1, the count operation is started. <3> When the value of TM5n matches the value of CR5n, the timer output F/F is inverted. In addition, INTTM5n is generated, and TM5n is cleared to 00H. <4> After that, the timer output F/F is inverted at fixed intervals, and a square wave is output from TO5n. Remark n = 0 to 2 Figure 6-11. Timing of Square Output Operation Count clock TM5n count value 00H 01H 02H N–1 N 00H 01H 02H N–1 N 00H Count starts CR5n N INTTM5n TO5nNote Note The initial value of the TO5n output can be set using bits 2 and 3 (LVR5n and LVS5n) of 8-bit timer mode control register 5n (TMC5n). Remark 110 n = 0 to 2 User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.4 8-bit PWM output operation (timers 50 to 52) The 8-bit timer/event counter can be used for PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. A pulse with a duty factor determined by the value set in 8-bit compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n. The active level is selected by bit 1 (TMC5n) of TMC5n. The count clock can be selected by bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register n (TCL5n). PWM output can be enabled or disabled by bit 0 (TOE5n) of TMC5n. Caution The value of CR5n can be rewritten only once in one cycle in the PWM mode. Remark n = 0 to 2 (1) Basic operation of PWM output [Setting] <1> Set port latches (P130 and P131) to 0. <2> Select the active level width using the 8-bit compare register (CR5n). <3> Select the count clock by using timer clock select register 5n (TCL5n). <4> Select the active level using bit 1 (TMC5n1) of TMC5n. <5> When bit 7 (TCE5n) of TMC5n is set to 1, the count operation is started. To stop the count operation, reset TCE5n to 0. [Operation of PWM output] <1> When the count operation is started, the PWM output (output from TO5n) remains inactive until an overflow occurs. <2> When an overflow occurs, the active level set in step <1> above is output. This active level is output until the value of CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> The PWM output remains inactive after CR5n and the count value of TM5n match, until an overflow occurs again. <4> After that, <2> and <3> are repeated until the count operation is stopped. <5> When the count operation is stopped because TCE5n is cleared to 0, PWM output becomes inactive. Remark n = 0 to 2 User’s Manual U15104EJ2V0UD 111 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-12. Operation Timing of PWM Output (a) Basic operation (when active level = H) Count clock TM5n 00H 01H CR5n N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n Active level Inactive level Active level (b) When CR5n = 0 Count clock TM5n 00H 01H CR5n 00H FFH 00H 01H 02H N N+1N+2 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n L Inactive level Inactive level (c) When CR5n = FFH TM5n 00H 01H CR5n FFH FFH 00H 01H 02H N N+1N+2 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n Inactive level Active level n = 0 to 2 112 User’s Manual U15104EJ2V0UD Active level Inactive level Inactive level CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) Operation when CR5n is changed Figure 6-13. Timing of Operation When CR5n Is Changed (a) If value of CR5n is changed from N to M before overflow of TM5n Count clock TM5n N N+1 N+2 CR5n N TCE5n INTTM5n FFH 00H 01H 02H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 M H TO5n CR5n changed (N M) (b) If value of CR5n is changed from N to M after overflow of TM5n Count clock TM5n N N+1 N+2 CR5n TCE5n INTTM5n N FFH 00H 01H 02H 03H N N+1 N+2 FFH 00H 01H 02H N M M+1 M+2 M H TO5n CR5n changed (N M) (c) If value of CR5n is changed from N to M for duration of 2 clocks immediately after overflow of TM5n Count clock TM5n N N+1 N+2 CR5n TCE5n INTTM5n N FFH 00H 01H 02H N N+1 N+2 N FFH 00H 01H 02H M M+1 M+2 M H TO5n CR5n changed (N M) n = 0 to 2 Caution The value of CR5n can be changed only once in one cycle in the PWM mode. User’s Manual U15104EJ2V0UD 113 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.5 Interval timer operation (16-bit) When using the 8-bit timer/counters as a 16-bit timer, be sure to use a combination of timers 50 and 51 or timers 52 and 53. The following section describes the case when using timers 50 and 51. When using timers 52 and 53, read “50” as “52” and “51” as “53”. The 8-bit timer/event counters are used together in 16-bit timer/counter mode when bit 4 (TMC514) of 8-bit timer mode control register 51 (TM51) is set to 1. In this mode, the 8-bit timer/event counters are used as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance in the 8-bit compare registers (CR50 and CR51). At this time, CR50 serves as the lower 8 bits of the 16-bit compare register, and CR51 serves as the higher 8 bits. [Setting] <1> Set each register. • TCL50: Select the count clock for TM50. The count clock for TM51, which is cascaded, does not have to be set. • CR50 and CR51: Compare values. (Each compare value can be set in a range of 00H to FFH.) • TMC50 and TMC51: Select a mode in which the interval timer is cleared and started on match between TM50 and CR50 (or between TM51 and CR51). TM50 → TMC50 = 0000×××0B ×: Don’t care TM51 → TMC51 = 0001×××0B ×: Don’t care <2> The count operation is started by setting TCE51 of TMC51 to 1 first, and then TCE50 of TMC50 to 1. <3> If the value of cascaded timer TM50 matches the value of CR50, INTTM50 of TM50 is generated (TM50 and TM51 are cleared to 00H). <4> After that, INTTM50 is repeatedly generated at fixed intervals. Cautions 1. Be sure to set the compare registers (CR50 and CR51) after stopping the timer operation. 2. Even if the 8-bit timers/counters are cascaded, INTTM51 of TM51 is generated when the count value of TM51 matches CR51. Be sure to mask TM51 to disable this interrupt. 3. Set TCE50 and TCE51 in the order of TM51 and TM50. 4. Counting can be restarted or stopped by setting or resetting TCE50 of TM50 to 1 or 0. Figure 6-14 shows a timing example in the 16-bit resolution cascade mode. 114 User’s Manual U15104EJ2V0UD CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-14. Operation Timing of 16-Bit Resolution Cascade Mode (Timers 50 and 51) Count clock TM50 00H TM51 00H 01H N N+1 FFH 00H FFH 00H 01H 02H FFH 00H 01H M–1 M N 00H 01H A 00H 00H B 00H N CR50 M CR51 TCE50 TCE51 INTTM50 Interval time TO50 Interrupt request generated. Level inverted. Counter cleared. Operation enabled. Count starts. Operation stops 6.5 Notes on 8-Bit Timer/Event Counters 50 to 53 (1) Error on starting timer An error of up to 1 clock occurs after the timer has been started until a match signal is generated. This is because 8-bit timer counter 5n (TM5n) is started asynchronously with the count pulse. Figure 6-15. Start Timing of 8-Bit Timer Counter Count pulse TM5n count value 00H 01H 02H 03H 04H Timer starts n = 0 to 3 User’s Manual U15104EJ2V0UD 115 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) Operation after changing compare register during timer count operation If a new value of 8-bit compare register 5n (CR5n) is less than the value of 8-bit timer counter 5n (TM5n), counting continues, and TM5n overflows and starts counting from 0. If the new value of CR5n (M) is less than the old value (N), therefore, it is necessary to restart the timer after changing CR5n. Figure 6-16. Timing After Changing Compare Register Value During Timer Count Operation Count pulse CR5n TM5n count value N X–1 M X FFH 00H 01H 02H Caution Be sure to clear TCE5n to 0 to set the STOP status, except when TI5n input is selected. Remarks 1. N > X > M 2. n = 0 to 3 (3) Reading TM5n (n = 0 to 3) during timer operation When TM5n is read during operation, the count clock is temporarily stopped. Therefore, select a count clock with a high/low level longer than two cycles of the CPU clock. For example, when the CPU clock (fCPU) is fX, the count clock to be selected should be fX/4 or less in order that TM5n can be read. Remark 116 n = 0 to 3 User’s Manual U15104EJ2V0UD CHAPTER 7 BASIC TIMER The basic timer is used for time management during program execution. 7.1 Function of Basic Timer The basic timer generates an interrupt request signal (INTBTM0) at time intervals of 100 ms. 7.2 Configuration of Basic Timer Figure 7-1. Block Diagram of Basic Timer 4.5 MHz Divider INTBTM0 Caution Use the basic timer after setting bit 0 (DTSCK0) of the DTS system clock select register (DETSCK) to 1 after power application, and after reset by the RESET pin (refer to 5.1 Functions of Clock Generator). The first interrupt request signal (INTBTM0) after the DTSCK0 flag has been set is generated within 100 to 140 ms. The second signal and those that follow are generated at intervals of 100 ms. User’s Manual U15104EJ2V0UD 117 CHAPTER 7 BASIC TIMER 7.3 Operation of Basic Timer An example of the operation of the basic timer is shown below. In this example, the basic timer operates as an interval timer that repeatedly generates an interrupt at time intervals of 100 ms. Interrupt request signal (INTBTM0) is generated every 100 ms. The timer clock frequency is 10 Hz. Figure 7-2. Operation Timing of Basic Timer Timer clock (10 Hz) INTBTM0 Interrupt acknowledged Interval time (100 ms) Interval time Interrupt acknowledged Interval time By polling the interrupt request flag (BTMIF0) of this basic timer by software, time management can be carried out. Note that BTMIF0 is not a Read & Reset flag. Figure 7-3. Operating Timing to Poll BTMIF0 Flag Timer clock (10 Hz) BTMIF0 flag 0 is written by software Always 1 unless 0 is written by software 1 when polled by software For the registers controlling the basic timer, refer to CHAPTER 12 INTERRUPT FUNCTIONS. 118 User’s Manual U15104EJ2V0UD CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The watchdog timer has the following functions. • Watchdog timer • Interval timer • Selecting oscillation stabilization time Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (WDTM). (The watchdog timer and interval timer cannot be used simultaneously.) Figure 8-1 shows a block diagram. Figure 8-1. Block Diagram of Watchdog Timer fX/28 Clock input controller Divided clock selector Divider INTWDT Output controller RESET RUN Division mode selector 3 WDT mode signal OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS) WDCS2 WDCS1 WDCS0 Watchdog timer clock select register (WDCS) RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus User’s Manual U15104EJ2V0UD 119 CHAPTER 8 WATCHDOG TIMER (1) Watchdog timer mode An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable interrupt request or reset can be generated. Table 8-1. Watchdog Timer Inadvertent Program Loop Detection Times Inadvertent Program Loop Detection Time 212/fX (910 µs) 213/fX (1.82 ms) 214/fX (3.64 ms) 215/fX (7.28 ms) 216/fX (14.6 ms) 217/fX (29.1 ms) 218/fX (58.3 ms) 220/fX (233 ms) Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 8-2. Interval Time Interval Time 212 /fX (910 µs) 213/fX (1.82 ms) 214/fX (3.64 ms) 215/fX (7.28 ms) 216/fX (14.6 ms) 217/fX (29.1 ms) 218/fX (58.3 ms) 220/fX (233 ms) Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz 120 User’s Manual U15104EJ2V0UD CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Control registers Configuration Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS) 8.3 Registers Controlling Watchdog Timer The following three types of registers are used to control the watchdog timer. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) • Oscillation stabilization time select register (OSTS) User’s Manual U15104EJ2V0UD 121 CHAPTER 8 WATCHDOG TIMER (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer and overflow time of the interval timer. WDCS is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears WDCS to 00H. Figure 8-2. Format of Watchdog Timer Clock Select Register (WDCS) Symbol 7 6 5 4 3 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 2 1 WDCS2 WDCS1 WDCS0 Watchdog timer/interval timer overflow time 0 0 0 212/fX (910 µ s) 0 0 1 213/fX (1.82 ms) 0 1 0 214/fX (3.64 ms) 0 1 1 215/fX (7.28 ms) 1 0 0 216/fX (14.6 ms) 1 0 1 217/fX (29.1 ms) 1 1 0 218/fX (58.3 ms) 1 1 1 220/fX (233 ms) Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz 122 0 User’s Manual U15104EJ2V0UD Address After reset R/W FF42H 00H R/W CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears WDTM to 00H. Figure 8-3. Format of Watchdog Timer Mode Register (WDTM) Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W Watchdog timer operating mode selectionNote RUN 0 Count stop 1 Counter is cleared and counting starts. 1 Watchdog timer operating mode selectionNote 2 WDTM4 WDTM3 0 × Interval timer modeNote 3 (Maskable interrupt occurs upon generation of an overflow.) 1 0 Watchdog timer mode 1 (Non-maskable interrupt occurs upon generation of an overflow.) 1 1 Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.) Notes 1. Once set to 1, RUN cannot be cleared to 0 by software. Therefore, use RESET input to clear RUN to 0. 2. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 3. WDTM starts interval timer operation at a time RUN is set to 1. Caution When RUN is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the timer clock select register (WDCS). Remark ×: Don’t care User’s Manual U15104EJ2V0UD 123 CHAPTER 8 WATCHDOG TIMER (3) Oscillation stabilization time select register (OSTS) This register is used to select the time required for oscillation to stabilize after the RESET signal has been input or the STOP mode has been released. This register is set with an 8-bit memory manipulation instruction. Reset input sets OSTS to 04H. Therefore, it takes 217/fX to release the STOP mode by RESET input. Figure 8-4. Format of Oscillation Stabilization Time Select Register (OSTS) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W OSTS2 OSTS1 OSTS0 0 0 0 0 1 0 0 1 1 0 Other than above Selection of oscillation stabilization time 0 212/fX (910 µs) 1 214/fX (3.64 ms) 0 215/fX (7.28 ms) 1 216/fX (14.6 ms) 0 217/fX (29.1 ms) Setting prohibited Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz 124 User’s Manual U15104EJ2V0UD CHAPTER 8 WATCHDOG TIMER 8.4 Operations of Watchdog Timer 8.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (WDCS0 to WDCS2) of timer clock select register 2 (WDCS). A watchdog timer count operation is started by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer count operation starts, set RUN to 1 within the set inadvertent program loop time interval. The watchdog timer can be cleared and counting started by setting RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time has elapsed, a system reset or a non-maskable interrupt request is generated according to the value of WDTM bit 3 (WDTM3). The watchdog timer continues operating in the HALT mode but stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Caution The actual inadvertent program loop detection time may be shorter than the set time by a maximum of 0.5%. Table 8-4. Watchdog Timer Inadvertent Program Loop Detection Time Inadvertent Program Loop Detection Time 212/fX (910 µs) 213/fX (1.82 ms) 214/fX (3.64 ms) 215/fX (7.28 ms) 216/fX (14.6 ms) 217/fX (29.1 ms) 218/fX (58.3 ms) 220/fX (233 ms) Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz User’s Manual U15104EJ2V0UD 125 CHAPTER 8 WATCHDOG TIMER 8.4.2 Interval timer operation The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The count clock (interval time) can be selected by using bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer. When the watchdog timer operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flag (WDTPR) are validated and the maskable request interrupt (INTWDT) can be generated. Among maskable interrupt requests, the INTWDT default has the highest priority. The interval timer continues operating in the HALT mode but stops in STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET is input. 2. The interval time just after setting by WDTM may be shorter than the set time by a maximum of 0.5%. Table 8-5. Interval Timer Interval Time Interval Time 212/fX (910 µs) 213/fX (1.82 ms) 214/fX (3.64 ms) 215/fX (7.28 ms) 216/fX (14.6 ms) 217/fX (29.1 ms) 218/fX (58.3 ms) 220/fX (233 ms) Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz 126 User’s Manual U15104EJ2V0UD CHAPTER 9 BUZZER OUTPUT CONTROLLER 9.1 Functions of Buzzer Output Controllers The µPD178054 Subseries has the following two types of buzzer output controllers. • BEEP0 • BUZ BEEP0 outputs a square wave of the buzzer frequency selected by BEEP clock select register 0 (BEEPCL0) from the BEEP0/P36 pin. BUZ outputs a square wave of the buzzer frequency selected by the clock output select register (CKS) from the BUZ/P37 pin. Figures 9-1 and 9-2 show the block diagrams of BEEP0 and BUZ. Figure 9-1. Block Diagram of BEEP0 1 kHz 1.5 kHz 3 kHz Selector 4 kHz BEEP0/P36 Output latch (P36) PM36 BEEP BEEP BEEP BEEP clock select CL02 CL01 CL00 register 0 (BEEPCL0) Internal bus Figure 9-2. Block Diagram of BUZ fX/210 fX/211 Selector BUZ/P37 fX/212 fX/213 Output latch (P37) BZOE BCS1 BCS0 PM37 Clock output select register (CKS) Internal bus Remark fX: System clock frequency User’s Manual U15104EJ2V0UD 127 CHAPTER 9 BUZZER OUTPUT CONTROLLLER 9.2 Configuration of Buzzer Output Controllers The buzzer output controllers consist of the following hardware. Table 9-1. Configuration of Buzzer Output Controllers (1) BEEP0 Item Configuration Control register BEEP clock select register 0 (BEEPCL0) (2) BUZ Item Configuration Control register Clock output select register (CKS) 9.3 Registers Controlling Buzzer Output Controllers 9.3.1 BEEP0 BEEP0 is controlled by the following register. • BEEP clock select register 0 (BEEPCL0) (1) BEEP clock select register 0 (BEEPCL0) This register selects the frequency of the buzzer output. BEEPCL0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 9-3. Format of BEEP Clock Select Register 0 (BEEPCL0) Symbol BEEP 7 0 6 5 0 4 0 0 3 0 2 1 0 BEEP BEEP BEEP Address After reset R/W FF41H 00H R/W CL02 CL01 CL00 CL0 BEEP CL02 BEEP CL01 BEEP CL00 Selection of frequency of BEEP0 output 0 × × Disables buzzer output (port function) 1 0 0 1 kHz 0 0 1 3 kHz 1 1 0 4 kHz 1 1 1 1.5 kHz Caution The selected clock may not be correctly output during the period of 1 cycle immediately after the output clock has been changed. 128 User’s Manual U15104EJ2V0UD CHAPTER 9 BUZZER OUTPUT CONTROLLER 9.3.2 BUZ BUZ is controlled by the following register. • Clock output select register (CKS) (1) Clock output select register (CKS) This register enables/disables buzzer output and sets the clock of the buzzer output. CKS is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 9-4. Format of Clock Output Select Register (CKS) Symbol <7> 6 5 CKS BZOE BCS1 BCS0 BZOE 4 3 2 1 0 Address After reset R/W 0 0 0 0 0 FF40H 00H R/W Enables/disables output of BUZ 0 Low-level output 1 Enables buzzer output BCS1 0 0 1 1 BCS0 Selects output clock of BUZ 0 fX/210 (4.39 kHz) 1 fX/211 (2.20 kHz) 0 fX/212 (1.10 kHz) 1 fX/213 (549 Hz) Remarks 1. fX: System clock frequency 2. ( ): fX = 4.5 MHz 9.4 Operation of Buzzer Output Controllers The buzzer frequency is output by the following procedure. (1) BEEP0 <1> Select a buzzer output frequency using bits 0 to 2 (BEEPCL00 to BEEPCL02) of BEEP clock select register 0 (BEEPCL0). <2> Set the output latch of P36 to 0. <3> Set bit 6 (PM36) of the port mode register 3 to 0 (set the output mode). (2) BUZ <1> Select a buzzer output frequency by using bits 5 and 6 (BCS0 and BCS1) of the clock output select register (CKS) (disable buzzer output). <2> Set bit 7 (BZOE) of CKS to 1 and enable buzzer output. <3> Set the output latch of P37 to 0. <4> Set bit 7 (PM37) of the port mode register 3 to 0 (set output mode). User’s Manual U15104EJ2V0UD 129 CHAPTER 10 A/D CONVERTER 10.1 Functions of A/D Converter The A/D converter converts analog inputs into digital values and consists of 6 channels (ANI0 to ANI5) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in 8-bit A/D conversion result register 3 (ADCR3). Conversion is started by setting A/D converter mode register 3. Select one analog input channel from ANI0 to ANI5 and carry out A/D conversion. When A/D conversion is complete, the next A/D conversion is started immediately. Each time an A/D conversion operation ends, an interrupt request (INTAD3) is generated. 10.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 10-1. Configuration of A/D Converter Item 130 Configuration Analog inputs 6 channels (ANI0 to ANI5) Control registers A/D converter mode register 3 (ADM3) Analog input channel specification register 3 (ADS3) Power-fail comparison mode register 3 (PFM3) Registers Successive approximation register (SAR) A/D conversion result register 3 (ADCR3) Power-fail comparison threshold value register 3 (PFT3) User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER Figure 10-1. Block Diagram of A/D Converter ANI0/P10 Selector ANI2/P12 ANI3/P13 Tap selector Sample & hold circuit ANI1/P11 Voltage comparator ANI4/P14 ANI5/P15 VDD ADCS3 Successive approximation register (SAR) GND INTAD3 Controller Controller A/D conversion result register 3 (ADCR3) 4 ADS33 ADS32 ADS31 ADS30 ADCS3 0 FR32 FR31 FR30 Analog input channel specification register 3 (ADS3) 0 0 0 Voltage comparator Power-fail comparison threshold value register 3 (PFT3) PFEN3 PFCM3 PFHRM3 A/D converter mode register 3 (ADM3) Power-fail comparison mode register 3 (PFM3) Internal bus User’s Manual U15104EJ2V0UD 131 CHAPTER 10 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is set (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register. (2) A/D conversion result register 3 (ADCR3) This register is an 8-bit register to store the A/D conversion result. Each time A/D conversion terminates, the conversion result is loaded from the successive approximation register (SAR). ADCR is read with an 8-bit memory manipulation instruction. Reset input makes ADCR undefined. Caution When data is written to A/D converter mode register 3 (ADM3) and analog input channel specification register 3 (ADS3), the contents of ADCR3 may be undefined. Read the result of conversion after conversion has been completed and before writing data to ADM3 and ADS3; otherwise the correct conversion result may not be read. (3) Power-fail comparison threshold value register 3 (PFT3) This register sets a threshold value to be compared with the value of A/D conversion result register 3 (ADCR3). PFT3 is read or written with an 8-bit memory manipulation instruction. (4) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (5) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (6) Resistor string The resistor string is connected between VDD and GND, and generates a voltage to be compared to the analog input. (7) ANI0 to ANI5 pins These are the 6-channel analog input pins through which analog signals to undergo A/D conversion are input to the A/D converter. Cautions 1. Use the ANI0 to ANI5 input voltages within the specified range. If a voltage higher than VDD or lower than GND is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes undefined and may adversely affect the converted values of other channels. 2. The analog input pins (ANI0 to ANI5) are also used as input port pins (P10 to P15). When one of ANI0 to ANI5 is selected for A/D conversion, do not execute an input instruction to port 1; otherwise the conversion resolution may drop. If a digital pulse is applied to the pin adjacent to the pin executing A/D conversion, the A/D conversion value may not be obtained as expected due to coupling noise. Do not apply a pulse to the pin adjacent to the pin executing A/D conversion. 132 User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER 10.3 Registers Controlling A/D Converter The following three registers control the A/D converter. • A/D converter mode register 3 (ADM3) • Analog input channel specification register 3 (ADS3) • Power-fail comparison mode register 3 (PFM3) (1) A/D converter mode register 3 (ADM3) This register selects the conversion time of the analog input to be converted and starts or stops the conversion operation. ADM3 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-2. Format of A/D Converter Mode Register 3 (ADM3) Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W ADM3 ADCS3 0 FR32 FR31 FR30 0 0 0 FF12H 00H R/W ADCS3 Control of A/D conversion operation 0 Stops conversion operation 1 Enables conversion operation FR32 FR31 FR30 0 0 0 288/fX (64.0 µs) 0 0 1 240/fX (53.3 µs) 0 1 0 192/fX (42.7 µs) 1 0 0 144/fX (32.0 µs) 1 0 1 120/fX (26.7 µs) 1 1 0 96/fX (21.3 µs) Other than above Selection of conversion time Setting prohibited Cautions 1. The conversion result is undefined immediately after bit 7 (ADCS3) has been set to 1. 2. To change the data of bits 3 to 5 (FR30 to FR32), stop the A/D conversion operation. Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz User’s Manual U15104EJ2V0UD 133 CHAPTER 10 A/D CONVERTER (2) Analog input channel specification register 3 (ADS3) This register specifies the input channel of the analog voltage to be converted. ADS3 is set with an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-3. Format of Analog Input Channel Specification Register 3 (ADS3) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W ADS3 0 0 0 0 ADS33 ADS32 ADS31 ADS30 FF13H 00H R/W ADS33 ADS32 ADS31 ADS30 0 0 0 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 Other than above 134 Specification of analog input channel Setting prohibited User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER (3) Power-fail comparison mode register 3 (PFM3) PFM3 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-4. Format of Power-Fail Comparison Mode Register 3 (PFM3) Symbol PFM3 <7> PFEN3 PFEN3 <5> PFCM3 PFHRM3 4 3 2 1 0 Address After reset R/W 0 0 0 0 0 FF16H 00H R/W Enable/disable of power-fail comparison 0 Disables power-fail comparison 1 Enables power-fail comparison PFCM3 Selection of power-fail comparison mode 0 Generates interrupt request (INTAD) when ADCR3 ≥ PFT 1 Generates interrupt request (INTAD) when ADCR3 < PFT Note PFHRM3 Note <6> Selection of power-fail HALT repeat mode 0 Disables power-fail HALT repeat mode 1 Enables power-fail HALT repeat mode When bit 5 (PFHRM3) is set to 1, power-fail comparison manipulation is enabled in the HALT mode in which A/D conversion is repeated until an interrupt request (INTAD3) is generated (this bit is reset to 0 when INTAD3 is generated). User’s Manual U15104EJ2V0UD 135 CHAPTER 10 A/D CONVERTER 10.4 Operations of A/D Converter 10.4.1 Basic operations of A/D converter (1) Select one channel for A/D conversion with A/D converter analog input channel specification register 3 (ADS3). (2) Sample the voltage input to the selected analog input channel with the sample & hold circuit. (3) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of A/D conversion. (4) Bit 7 of the successive approximation register (SAR) is set and the tap selector sets the series resistor string voltage tap to (1/2) VDD. (5) The voltage difference between the series resistor string voltage tap and analog input is compared with a voltage comparator. If the analog input is greater than (1/2) VDD, the MSB of SAR remains set. If the input is smaller than (1/2) VDD, the MSB is reset. (6) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. • Bit 7 = 1: (3/4) VDD • Bit 7 = 0: (1/4) VDD The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows. • Analog input voltage ≥ Voltage tap: Bit 6 = 1 • Analog input voltage < Voltage tap: Bit 6 = 0 (7) Comparison of this sort continues up to bit 0 of SAR. (8) Upon completion of the comparison of 8 bits, any valid digital resultant value remains in SAR and the resultant value is transferred to and latched in A/D conversion result register 3 (ADCR3). At the same time, the A/D conversion termination interrupt request (INTAD3) can also be generated. Caution The value immediately after A/D conversion has been started may not satisfy the ratings. 136 User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER Figure 10-5. A/D Converter Basic Operation Conversion time Sampling time A/D converter operation Sampling SAR Undefined A/D conversion 80H C0H or 40H Conversion result Conversion result ADCR3 INTAD3 A/D conversion operations are performed continuously until bit 7 (ADCS3) of the ADM is reset (0) by software. If a write to ADM3 or ADS3 is performed during an A/D conversion operation, the conversion operation is initialized, and if the ADCS3 bit is set (1), conversion starts again from the beginning. After reset input, the value of ADCR3 is undefined. User’s Manual U15104EJ2V0UD 137 CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI5) and the A/D conversion result (the value stored in A/D conversion result register 3 (ADCR3) is shown by the following expression. ADCR3 = INT ( VIN VDD × 256 + 0.5) or VDD 256 (ADCR3 – 0.5) × Remark INT( ): ≤ VIN < (ADCR3 + 0.5) × VDD 256 Function which returns integer parts of value in parentheses. VIN: Analog input voltage VDD: VDD pin voltage ADCR3: A/D conversion result register 3 (ADCR3) value Figure 10-6 shows the relationship between the analog input voltage and the A/D conversion result. Figure 10-6. Relationship Between Analog Input Voltage and A/D Conversion Result 255 254 A/D conversion results (ADCR3) 253 3 2 1 0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 Input voltage/VDD 138 User’s Manual U15104EJ2V0UD 1 CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operating mode The A/D converter has the following two modes: • A/D conversion operation mode: In this mode, the voltage applied to the analog input pin selected from ANI0 to ANI5 is converted into a digital signal. The result of the A/D conversion is stored in A/D conversion result register 3 (ADCR3), and at the same time, an interrupt request signal (INTAD3) is generated. • Power-fail comparison mode: The digital value resulting from A/D conversion is compared with the value assigned to power-fail comparison threshold value register 3 (PFT3) is compared. If the result of the comparison matches the condition set by bit 6 (PFCM3) of power-fail comparison mode register 3 (PFM3), an interrupt request signal (INTAD3) is generated. (1) A/D conversion operation mode When bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) is set to 1, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 0 to 3 (ADS30 to ADS33) of ADS3. Upon termination of the A/D conversion, the conversion result is stored in A/D conversion result register 3 (ADCR3) and the interrupt request signal (INTAD3) is generated. After one A/D conversion operation is started and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation continues repeatedly until new data is written to ADM3. If data is written to ADCS3 again during A/D conversion, the converter suspends its A/D conversion operation and starts A/D conversion on the newly written data. If data with ADCS3 set to 0 is written to ADM3 during A/D conversion, the A/D conversion operation stops immediately. User’s Manual U15104EJ2V0UD 139 CHAPTER 10 A/D CONVERTER Figure 10-7. A/D Conversion Operation Conversion start ADCS3 = 1 A /D conversion Stop ANIn ADS3 rewrite ANIn ANIn ANIm ADM3 rewrite ADCS3 = 0 ANIm Conversion suspended Conversion results are not stored UndefinedNote ADCR3 ANIn Stop ANIm INTAD3 (when PFEN3 = 0) Remarks 1. n = 0, 1, ... , 5 2. m = 0, 1, ... , 5 Note The conversion result is illegal immediately after bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) has been set to 1 (to enable conversion). Caution Reset bit 5 (PFHRM3) of power-fail comparison mode register 3 (PFM3) to 0. 140 User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER (2) Power-fail comparison mode In the power-fail comparison mode, the digital value converted from analog input is compared in units of 8 bits. If the result of the comparison matches the condition set by bit 6 (PFCM3) of power-fail comparison mode register 3 (PFM3), an interrupt request (INTAD3) is generated. Moreover, the power-fail comparison mode can be used in the HALT mode. At this time, the HALT mode can be released by generating the interrupt request signal (INTAD3) as a result of comparison (however, the A/ D operation must be executed before the HALT instruction is executed). To set the power-fail comparison mode, set bit 7 (PEEN3) of PFM3 to 1, set bit 6 (PFCM3) to the generation condition of INTAD, and assign the threshold value to be compared with the value of A/D conversion result register 3 (ADCR3) to power-fail comparison threshold value register 3 (PFT3). By setting bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) to 1, the voltage applied to the analog input pin specified by ADS3 is converted into a digital signal. When the A/D conversion has been completed, the result of the conversion is stored in ADCR3. This conversion result is compared with the value set in PFT3 and if the result of the comparison matches the condition set by bit 6 (PFCM3) of PFM3, an interrupt request signal (INTAD3) is generated. Figure 10-8. Power-Fail Comparison Threshold Value Register 3 (PFT3) Symbol PFT3 7 6 5 4 3 2 1 0 Address After reset R/W PFT37 PFT36 PFT35 PFT34 PFT33 PFT32 PFT31 PFT30 FF15H 00H R/W Remark Bit 7 (PFT37) is the MSB, and bit 0 (PFT30) is the LSB. For the setting value, refer to 10.4.2 Input voltage and conversion results. Cautions 1. In the power-fail comparison mode, the first result (A/D conversion result and interrupt request (INTAD)) of the A/D conversion (started by setting bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) to 1) is not correct. 2. When executing A/D conversion in the HALT mode using the power-fail HALT repeat mode, clear the interrupt request flag (ADIF) after the first conversion has been completed immediately after bit 7 (ADCS3) of ADM3 has been set to 1, and bit 5 (PFHRM3) of powerfail comparison mode register 3 (PFM3) has been set to 1, before executing the HALT instruction. 3. To set the power-fail comparison mode in the HALT mode, be sure to set bit 5 (PFHRM3) of PFM3 to 1 before executing the HALT instruction; otherwise comparison cannot be performed correctly because the conversion result in the HALT mode is not stored in A/ D conversion result register 3 (ADCR3). If bit 5 (PFHRM3) of PFM3 is set in the normal operating mode (other than HALT mode), the A/D conversion is not performed correctly. Therefore, be sure to clear this bit to 0 in the normal mode. User’s Manual U15104EJ2V0UD 141 CHAPTER 10 A/D CONVERTER Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (1/3) (1) In normal mode (other than HALT mode) Conversion starts ADS3 rewrite ADM3 rewrite ADCS3 = 1 A/D conversion Stop ADCS3 = 0 ANIn ANIn ANIn ANIm ANIm conversion stopped PFT3, PFM3 set ADCR3 ANIn UndefinedNote 1 ANIn ANIn Stop ANIm INTAD3 (when PFEN3 = 1) Note 2 Comparison condition does not match Comparison condition matches Comparison condition does not match Notes 1. The conversion data is undefined immediately after bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) is set to 1 (to start conversion). 2. The first result of the A/D conversion (A/D conversion result and interrupt request) is not correct. Do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. Caution Set power-fail comparison threshold value register 3 (PFT3) and power-fail comparison mode register 3 (PFM3) before starting conversion. Be sure to reset bit 5 (PFHRM3) of PFM3 to 0 (to disable HALT repeat mode setting). Remark n = 0, 1, ... 5 m = 0, 1, ... 5 142 User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (2/3) (2) In HALT repeat mode (when generation of interrupt (INTAD3) is used to release HALT mode) Conversion starts ADCS3 = 1 A/D conversion Stop ADIF clear HALT instructionNote 2 PFHRM3 = 1 HALT operation ANIn ANIn ANIn ANIn ADM3 rewrite ADCS3 = 0 Interrupt request releases HALT mode ANIn ANIn Stop PFT3, PFM3 set ADCR3 UndefinedNote 1 ANIn ANIn ANIn ANIn INTAD3 (when PFEN3 = 1) Note 3 Comparison condition Comparison condition does not match matches Comparison condition Comparison matches condition does (PFHRM3 is reset) not match Notes 1. The conversion data is undefined immediately after bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) is set to 1 (to start conversion). 2. When executing A/D conversion in the HALT mode by using the power-fail comparison mode, clear the interrupt request flag (ADIF) after the first conversion has been completed immediately after bit 7 (ADCS3) of ADM3 has been set to 1, and bit 5 (PFHRM3) of power-fail comparison mode register 3 (PFM3) has been set to 1, before executing the HALT instruction. 3. The first result of the A/D conversion (A/D conversion result and interrupt request) is not correct. Do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. Caution Be sure to set bit 5 (PFHRM3) of PFM3 to 1 (to enable the HALT repeat mode setting). Remark n = 0, 1, ... 5 User’s Manual U15104EJ2V0UD 143 CHAPTER 10 A/D CONVERTER Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (3/3) (3) In HALT repeat mode (when generation of interrupt (INTAD3) is not used to release HALT mode) HALT instructionNote 2 Conversion starts ADCS3 = 1 ADIF clear PFHRM3 = 1 HALT operation Interrupt request (INTAD) does not release HALT mode A/D conversion Stop ANIn ANIn ANIn ANIn ANIn ... UndefinedNote 1 ANIn Previous conversion result Previous conversion result ... PFT3, PFM3 set ADCR3 A/D conversion is in progress but conversion operation is stopped INTAD3 (when PFEN3 = 1) Note 3 Comparison condition does not match Comparison condition matches (PFHRM3 is reset) Notes 1. The conversion data is undefined immediately after bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) is set to 1 (to start conversion). 2. When executing A/D conversion in the HALT mode by using the power-fail HALT repeat mode, clear the interrupt request flag (ADIF) after the first conversion has been completed immediately after bit 7 (ADCS3) of ADM3 has been set to 1, and bit 5 (PFHRM3) of power-fail comparison mode register 3 (PFM3) has been set to 1, before executing the HALT instruction. 3. The first result of the A/D conversion (A/D conversion result and interrupt request) is not correct. Do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. Caution Be sure to set bit 5 (PFHRM3) of PFM3 to 1 (to enable the HALT repeat mode setting). Remark 144 n = 0, 1, ... 5 User’s Manual U15104EJ2V0UD CHAPTER 10 A/D CONVERTER 10.5 Notes on A/D Converter (1) Current consumption in standby mode The A/D converter is stopped in the standby mode. At this time, the current consumption can be reduced by stopping the conversion operation (by resetting bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) to 0). Figure 10-10 shows how to reduce the current consumption in the standby mode. Figure 10-10. Example of Reducing Current Consumption in Standby Mode VDD ADCS3 P-ch Series resistor string GND (2) Input range of ANI0 to ANI5 The input voltages of ANI0 to ANI5 should be within the specified range. In particular, if a voltage above VDD or below GND is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined. The conversion values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between writing A/D conversion result register 3 (ADCR3) on completion of conversion and reading ADCR3 by an instruction Reading ADCR3 takes precedence. After ADCR3 has been read, a new conversion result is written to ADCR3. <2> Conflict between writing ADCR3 on completion of conversion and writing A/D converter mode register 3 (ADM3) or writing analog input channel specification register 3 (ADS3) Writing ADM3 or ADS3 takes precedence. ADCR3 is not written. Nor is the conversion completion interrupt request signal (INTAD3) generated. User’s Manual U15104EJ2V0UD 145 CHAPTER 10 A/D CONVERTER (4) ANI0 to ANI5 The analog input pins ANI0 to ANI5 also function as input port (P10 to P15) pins. When A/D conversion is performed with any of pins ANI0 to ANI5 selected, be sure not to execute a PORT1 input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if analog input channel specification register 3 (ADS3) is changed. Caution is therefore required since, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS3 rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended. When the A/D conversion is stopped and then resumed, clear ADIF before it is resumed. Figure 10-11. A/D Conversion End Interrupt Request Generation Timing ADM3 rewrite (Start of ANIn conversion) A /D conversion ANIn ADS3 rewrite (Start of ANIm conversion) ANIn ANIn ADCR3 ANIm ANIn ADIF is set but ANIm conversion has not ended ANIm ANIm ANIm INTAD3 Remarks 1. n = 0, 1, ..., 5 2. m = 0, 1, ..., 5 (6) Conversion result immediately after starting A/D conversion The first A/D conversion result value is undefined immediately after the A/D conversion operation has been started. Poll the A/D conversion completion interrupt request (INTAD3) and discard the first conversion result. (7) Reading A/D conversion result register 3 (ADCR3) If data is written to A/D converter mode register 3 (ADM3) and analog input channel specification register 3 (ADS3), the contents of ADCR3 can be undefined. Read the conversion value before writing ADM3 and ADS3 after the conversion operation has been completed; otherwise the correct conversion result may not be read. 146 User’s Manual U15104EJ2V0UD CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.1 Functions of Serial Interfaces SIO30 to SIO32 The serial interface SIO3n has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not performed. For details, refer to 11.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB first) In this mode, 8-bit data is transferred by using three lines: serial clock (SCK3n), serial output (SO3n), and serial input (SI3n) lines. Because transmission and reception can be executed simultaneously in this mode, the processing time of data transfer can be shortened. The first bit of the 8-bit data to be transferred is the MSB. The 3-wire serial I/O mode is useful for connecting a peripheral I/O or display controller with a clocked serial interface. For details, refer to 11.4.2 3-wire serial I/O mode. Figures 11-1 to 11-3 show the block diagrams of the serial interface SIO3n. Remark n = 0 to 2 Figure 11-1. Block Diagram of Serial Interface SIO30 Internal bus 8 Serial I/O shift register 30 (SIO30) SI30/P70 PM71 SO30/P71 P71 output latch Serial clock counter SCK30/P72 Serial clock controller PM72 Interrupt request signal generator INTCSI30 4 Selector fX/25 fX/26 fX/2 P72 output latch User’s Manual U15104EJ2V0UD 147 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 Figure 11-2. Block Diagram of Serial Interface SIO31 Internal bus 8 Serial I/O shift register 31 (SIO31) SI31/P74 PM75 SO31/P75 P75 output latch Interrupt request signal generator Serial clock counter SCK31/P76 Serial clock controller PM76 Selector INTCSI31 fX/24 5 fX/26 fX/2 P76 output latch Figure 11-3. Block Diagram of Serial Interface SIO32 Internal bus 8 SI32/P120 Serial I/O shift register 32 (SIO32) Selector SI321/P123 PM121 P121 output latch SO32/P121 Selector SO321/P124 P124 output latch PM124 SCK32/P122 Selector SCK321/P125 PM122 148 Interrupt request signal generator P122 output latch Selector PM125 Serial clock counter Serial clock controller P125 output latch User’s Manual U15104EJ2V0UD Selector INTCSI32 fX/24 fX/25 fX/26 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.2 Configuration of Serial Interfaces SIO30 to SIO32 The serial interface SIO3n consists of the following hardware. Table 11-1. Configuration of Serial Interfaces SIO30 to SIO32 Item Configuration Register Serial I/O shift registers 30 to 32 (SIO30 to SIO32) Control registers Serial operating mode registers 30 to 32 (CSIM30 to CSIM32) Serial port select register 32 (SIO32SEL) (1) Serial I/O shift registers 30 to 32 (SIO30 to SIO32) These 8-bit registers convert parallel data into serial data and transmit or receive the serial data (shift operation) in synchronization with a serial clock. SIO3n is set with an 8-bit memory manipulation instruction. Serial operation is started by writing or reading data to or from SIO3n when bit 7 (CSIE3n) of serial operating mode register 3n (CSIM3n) is 1. Data written to SIO3n is output to a serial output line (SO3n) for transmission. Data is read to SIO3n from a serial input line (SI3n) for reception. Reset input makes the values of these registers undefined. Caution Do not execute access other than that for the transfer start trigger to SIO3n during a transfer operation (the read operation is disabled when MODE3n = 0, and the write operation is disabled when MODE3n = 1). Remark n = 0 to 2 User’s Manual U15104EJ2V0UD 149 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.3 Registers Controlling Serial Interfaces SIO30 to SIO32 The following registers control the serial interface SIO3n. • Serial operating mode registers 30 to 32 (CSIM30 to CSIM32) • Serial port select register 32 (SIO32SEL) (1) Serial operating mode register 30 to 32 (CSIM30 to CSIM32) These registers select the serial clock of SIO3n and an operating mode, and enable or disable the operation. CSIM3n is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears these registers to 00H. Figure 11-4. Format of Serial Operating Mode Registers 30 to 32 (CSIM30 to CSIM32) Symbol <7> CSIM30 CSIE30 <7> CSIM31 CSIE31 <7> CSIM32 CSIE32 6 5 4 3 0 0 0 0 6 5 4 3 0 0 0 0 6 5 4 3 0 0 0 0 1 2 0 MODE30 SCL301 SCL300 1 2 1 R/W FF6FH 00H R/W FF6DH 00H R/W FF6BH 00H R/W 0 MODE32 SCL321 SCL320 CSIE3n After reset 0 MODE31 SCL311 SCL310 2 Address Enable/disable of SIO3n operation Shift register operation Serial counter Port 0 Disables operation Cleared Port functionNote 1 1 Enables operation Enables counter operation Serial function + port functionNote 2 MODE3n Transfer operation mode flag Operating mode Transfer start trigger SO3n output 0 Transmit or transmit/receive mode SIO3n write Serial output 1 Receive only mode SIO3n read Fixed to low levelNote 3 SCL3n1 SCL3n0 Clock selection 0 0 External clock input to SCK3n 0 1 fX/24 (281 kHz) 1 0 fX/25 (141 kHz) 1 1 fX/26 (70.3 kHz) Notes 1. The SI3n, SO3n, and SCK3n pins can be used as port pins when CSIE3n = 0 (when SIO3n operation is stopped). 2. When CSIE3n = 1 (when SIO3n operation is enabled), the SI3n pin can be used as a port pin if only the transmission function is used, and the SO3n pin can be used as a port pin in the receive mode. 3. The SO3n pin can be used as a port pin. Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz 150 User’s Manual U15104EJ2V0UD CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 Caution Set the port mode register (PM××) as follows in the 3-wire serial I/O mode. Set the output latch to 0. Serial Type Serial Interface SIO30 Operation Mode Serial clock output (master transmission or reception) Serial Interface SIO31 Serial Interface SIO32 S32SEL0 = 0 S32SEL0 = 1 PM72 = 0 (set P72/SCK30 pin to output mode) PM76 = 0 (set P76/SCK31 pin to output mode) PM122 = 0 (set P122/SCK32 pin to output mode) PM125 = 0 (set P125/SCK321 pin to output mode) Serial clock input PM72 = 1 (slave transmission or reception) (set P72/SCK30 pin to input mode) PM76 = 1 (set P76/SCK31 pin to input mode) PM122 = 1 (set P122/SCK32 pin to input mode) PM125 = 1 (set P125/SCK321 pin to input mode) In transmit or transmit/receive mode In receive mode PM71 = 0 PM75 = 0 PM121 = 0 (set P71/SO30 pin to (set P75/SO31 pin to (set P121/SO32 pin PM124 = 0 (set P124/SO321 pin output mode) output mode) to output mode) to output mode) PM70 = 1 (set P70/SI30 pin to input mode) PM74 = 1 (set P74/SI31 pin to input mode) PM120 = 1 (set P120/SI32 pin to input mode) PM123 = 1 (set P123/SI321 pin to input mode) (2) Serial port select register 32 (SIO32SEL) This register selects the port used for serial interface SIO32. SIO32SEL is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 11-5. Format of Serial Port Select Register 32 (SIO32SEL) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W SIO32SEL 0 0 0 0 0 0 0 S32SEL0 FF69H 00H R/W S32SEL0 Serial interface SIO32 port selection SI pin SO pin SCK pin 0Note 1 P120/SI32 P121/SO32 P122/SCK32 1Note 2 P123/SI321 P124/SO321 P125/SCK321 Notes 1. The P123/SI321, P124/SO321, P125/SCK321 pins can be used as port pins. 2. The P120/SI32, P121/SO32, P122/SCK32 pins can be used as port pins. User’s Manual U15104EJ2V0UD 151 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.4 Operations of Serial Interfaces SIO30 to SIO32 This section explains the two modes of the serial interfaces SIO30 to SIO32. 11.4.1 Operation stop mode In this mode, serial transfer is not performed. The alternate-function pins used for the serial interface can be used as ordinary I/O port pins. (1) Register setting The operation stop mode is set using serial operating mode register 3n (CSIM3n). CSIM3n is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Symbol <7> 6 5 4 3 CSIM30 CSIE30 0 0 0 0 <7> 6 5 4 3 CSIE31 0 0 0 0 <7> 6 5 4 3 CSIE32 0 0 0 0 CSIM31 CSIM32 CSIE3n 2 1 0 MODE30 SCL301 SCL300 2 1 1 After reset R/W FF6FH 00H R/W FF6DH 00H R/W FF6BH 00H R/W 0 MODE31 SCL311 SCL310 2 Address 0 MODE32 SCL321 SCL320 Enable/disable of SIO3n operation Shift register operation Serial counter Port functionNote 1 0 Disables operation Cleared Port 1 Enables operation Enables count operation Serial function + port functionNote 2 Notes 1. The SI3n, SO3n, and SCK3n pins can be used as port pins when CSIE3n = 0 (when SIO3n operation is stopped). 2. When CSIE3n = 1 (when SIO3n operation is enabled), the SI3n pin can be used as a port pin if only the transmission function is used, and the SO3n pin can be used as a port pin in the receive mode. Remark 152 n = 0 to 2 User’s Manual U15104EJ2V0UD CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connecting a peripheral I/O or display controller equipped with a clocked serial interface. In this mode, communication is executed by using three lines: serial clock (SCK3n), serial output (SO3n), and serial input (SI3n) lines. (1) Register setting The 3-wire serial I/O mode is set using serial operating mode register 3n (CSIM3n). These registers are set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears these registers to 00H. Symbol <7> 6 5 4 3 CSIM30 CSIE30 0 0 0 0 <7> 6 5 4 3 CSIE31 0 0 0 0 <7> 6 5 4 3 CSIE32 0 0 0 0 CSIM31 CSIM32 CSIE3n 2 1 0 MODE30 SCL301 SCL300 2 1 1 After reset R/W FF6FH 00H R/W FF6DH 00H R/W FF6BH 00H R/W 0 MODE31 SCL311 SCL310 2 Address 0 MODE32 SCL321 SCL320 Enable/disable of SIO3n operation Shift register operation Serial counter Port functionNote 1 0 Disables operation Cleared Port 1 Enables operation Enables counter operation Serial function + port functionNote 2 MODE3n Transfer operation mode flag Operating mode Transfer start trigger SO3n output 0 Transmit or transmit/receive mode SIO3n write Serial output 1 Receive-only mode SIO3n read Fixed to low levelNote 3 SCL3n1 SCL3n0 Clock selection 0 0 External clock input to SCK3n 0 1 fX/24 (281 kHz) 1 0 fX/25 (141 kHz) 1 1 fX/26 (70.3 kHz) Notes 1. The SI3n, SO3n, and SCK3n pins can be used as port pins when CSIE3n = 0 (when SIO3n operation is stopped). 2. When CSIE3n = 1 (when SIO3n operation is enabled), the SI3n pin can be used as a port pin if only the transmission function is used, and the SO3n pin can be used as a port pin in the receive mode. 3. The SO3n pin can be used as a port pin. Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz User’s Manual U15104EJ2V0UD 153 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 Caution Set the port mode register (PM××) as follows in the 3-wire serial I/O mode. Set the output latch to 0. Serial Type Operation Mode Serial clock output (master transmission or reception) Serial Interface SIO30 Serial Interface SIO31 Serial Interface SIO32 S32SEL0 = 0 S32SEL0 = 1 PM72 = 0 (set P72/SCK30 pin to output mode) PM76 = 0 (set P76/SCK31 pin to output mode) PM122 = 0 (set P122/SCK32 pin to output mode) PM125 = 0 (set P125/SCK321 pin to output mode) Serial clock input PM72 = 1 (slave transmission or reception) (set P72/SCK30 pin to input mode) PM76 = 1 (set P76/SCK31 pin to input mode) PM122 = 1 (set P122/SCK32 pin to input mode) PM125 = 1 (set P125/SCK321 pin to input mode) In transmit or transmit/receive mode In receive mode PM71 = 0 PM75 = 0 PM121 = 0 (set P71/SO30 pin to (set P75/SO31 pin to (set P121/SO32 pin PM124 = 0 (set P124/SO321 pin output mode) output mode) to output mode) to output mode) PM70 = 1 (set P70/SI30 pin to input mode) PM74 = 1 (set P74/SI31 pin to input mode) PM120 = 1 (set P120/SI32 pin to input mode) PM123 = 1 (set P123/SI321 pin to input mode) (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Data is transmitted or received in synchronization with the serial clock. The shift operation of serial I/O shift register 3n (SIO3n) is performed at the falling edge of the serial clock (SCK3n). The transmit data is retained in SO3n latch and is output from the SO3n pin. The receive data input to the SI3n pin is latched to SIO3n at the falling edge of the serial clock. When 8-bit data has been transferred, the operation of SIO3n is automatically stopped, and an interrupt request flag (CSIIF3n) is set. Figure 11-6. Timing in 3-Wire Serial I/O Mode SCK3n 1 2 3 4 5 6 7 8 SI3n DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO3n DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSIIF3n Transfer ends Transfer starts at falling edge of SCK3n 154 User’s Manual U15104EJ2V0UD CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 (3) Starting transfer Serial transfer is started by writing (or reading) the transfer data to serial I/O shift register 3n (SIO3n) when the following conditions are satisfied. • Operation control bit of SIO3n (bit 7 (CSIE3n) of serial operation mode register 3n (CSIM3n)) = 1 • If the internal serial clock is stopped or SCK3n is high level after transfer of 8-bit serial data • Transmit/receive mode Transfer is started if SIO3n is written when bit 7 (CSIE3n) of CSIM3n = 1, and bit 2 (MODE3n) = 0 • Receive mode Transfer is started if SIO3n is read when bit 7 (CSIE3n) of CSIM3n = 1, and bit 2 (MODE3n) = 1 Caution Serial transfer is not started even if 1 is written to CSIE3n after data is written to SIO3n. On completion of transfer of the 8-bit data, serial transfer is automatically stopped, and an interrupt request flag (CSIIF3n) is set. User’s Manual U15104EJ2V0UD 155 CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupts This type of interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag register (PR). Multiple interrupt servicing is possible if a high-priority interrupt is generated while a low-priority interrupt is being serviced. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (refer to Table 12-1). A standby release signal is generated. Maskable interrupts are provided for each product as follows. • µPD178053, 178054, 178F054 Internal: 11, external: 5 (3) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even in an interruptdisabled state. The software interrupt does not undergo interrupt priority control. 12.2 Interrupt Sources and Configuration The µPD178053, 178054, and 178F054 have a total of 17 sources (non-maskable interrupt, maskable interrupt, software interrupt) (refer to Table 12-1). Remark Either a non-maskable interrupt or a maskable interrupt (internal) can be selected for the watchdog timer interrupt source (INTWDT). 156 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Table 12-1. Interrupt Sources Interrupt Type Default PriorityNote 1 Interrupt Source Name Trigger Internal/ External Vector Table Address Basic Configuration TypeNote 2 Internal 0004H (A) Non-maskable – INTWDT Overflow of watchdog timer (when watchdog timer mode 1 is selected) Maskable 0 INTWDT Overflow of watchdog timer (when interval timer mode is selected) 1 INTP0 Pin input edge detection 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTP4 000EH 6 INTKY Detection of key input of port 4 7 INTCSI31 End of transfer by serial interface SIO31 0012H 8 INTBTM0 Generation of basic timer match signal 0014H 9 INTAD3 End of conversion by A/D converter 0016H 10 INTCSI32 End of transfer by serial interface SIO32 0018H 11 INTCSI30 End of transfer by serial interface SIO30 001AH 12 INTTM50 Generation of match signal of 8-bit timer/ 001CH (B) External Internal 0006H 0010H (C) (B) event counter 50 Software 13 INTTM51 Generation of match signal of 8-bit timer/ event counter 51 001EH 14 INTTM52 Generation of match signal of 8-bit timer/ event counter 52 0020H 15 INTTM53 Generation of match signal of 8-bit timer 53 0022H – BRK Execution of BRK instruction – 003EH (D) Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. The default priority 0 is the highest, and 15 is the lowest. 2. (A) to (D) under the heading Basic Configuration Type correspond to (A) to (D) in Figure 12-1. User’s Manual U15104EJ2V0UD 157 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Vector table address generator Priority controller Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Vector table address generator Priority controller IF Standby release signal (C) External maskable interrupt Internal bus External interrupt mode register (EGP, EGN) Interrupt request Edge detector MK IE IF PR Priority controller ISP Vector table address generator Standby release signal 158 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (2/2) (D) Software interrupt Internal bus Interrupt request Remark Priority controller IF: Interrupt request flag IE: Interrupt enable flag Vector table address generator ISP: Inservice priority flag MK: Interrupt mask flag PR: Priority specification flag User’s Manual U15104EJ2V0UD 159 CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Registers Controlling Interrupt Functions The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H) • Interrupt mask flag register (MK0L, MK0H) • Priority specification flag register (PR0L, PR0H) • External interrupt rising edge enable register (EGP) • External interrupt falling edge enable register (EGN) • Program status word (PSW) Table 12-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 12-2. Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Register IF0L Priority Specification Flag Register INTWDT WDTIF INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTKY KYIF KYMK KYPR INTCSI31 CSIIF31 CSIMK31 CSIPR31 INTBTM0 BTMIF0 IF0H WDTMK BTMMK0 MK0L Register MK0H WDTPR BTMPR0 INTAD3 ADIF ADMK ADPR INTCSI32 CSIIF32 CSIMK32 CSIPR32 INTCSI30 CSIIF30 CSIMK30 CSIPR30 INTTM50 TMIF50 TMMK50 TMPR50 INTTM51 TMIF51 TMMK51 TMPR51 INTTM52 TMIF52 TMMK52 TMPR52 INTTM53 TMIF53 TMMK53 TMPR53 160 User’s Manual U15104EJ2V0UD PR0L PR0H CHAPTER 12 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. IF0L and IF0H are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register IF0, use a 16-bit memory manipulation instruction for the setting. Reset input clears these registers to 00H. Figure 12-2. Format of Interrupt Request Flag Registers (IF0L, IF0H) Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W IF0L CSIIF31 KYIF PIF4 PIF3 PIF2 PIF1 PIF0 WDTIF FFE0H 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> ADIF BTMIF0 FFE1H 00H R/W IF0H TMIF53 TMIF52 TMIF51 TMIF50 CSIIF30 CSIIF32 ××IF× Interrupt request flag 0 No interrupt request signal 1 Interrupt request signal is generated; Interrupt request state Cautions 1. WDTIF flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog timer is used in watchdog timer mode 1, set WDTIF flag to 0. 2. To operate the timers, serial interface, and A/D converter after the standby mode has been released, clear the interrupt request flag, because the interrupt request flag may be set by noise. 3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared before entering the interrupt routine. User’s Manual U15104EJ2V0UD 161 CHAPTER 12 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing and to set standby clear enable/disable. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting. Reset input sets these registers to FFH. Figure 12-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H) <5> <4> <3> <2> <1> <0> Address After reset R/W MK0L CSIMK31 KYMK PMK4 PMK3 PMK2 PMK1 PMK0 WDTMK FFE4H FFH R/W <7> <5> <4> <3> <2> <1> <0> FFE5H FFH R/W Symbol <7> <6> <6> MK0H TMMK53 TMMK52 TMMK51 TMMK50 CSIMK30 CSIMK32 ADMK BTMMK0 ××MK× Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1. If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1, MK0 value becomes undefined. 2. Because port 0 functions alternately as the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 162 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H) The priority specification flags are used to set the corresponding maskable interrupt priority orders. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting. Reset input sets these registers to FFH. Figure 12-4. Format of Priority Specification Flag Registers (PR0L, PR0H) <5> <4> <3> <2> <1> <0> Address After reset R/W PR0L CSIPR31 KYPR PPR4 PPR3 PPR2 PPR1 PPR0 WDTPR FFE8H FFH R/W <7> <5> <4> <3> <2> <1> <0> FFE9H FFH R/W Symbol <7> <6> <6> PR0H TMPR53 TMPR52 TMPR51 TMPR50 CSIPR30 CSIPR32 ADPR BTMPR0 ××PR× Priority level selection 0 High priority level 1 Low priority level Caution When the watchdog timer is used in watchdog timer mode 1, set the WDTPR flag to 1. User’s Manual U15104EJ2V0UD 163 CHAPTER 12 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers set the valid edge for INTP0 to INTP4. EGP and EGN are set with a 1-bit or 8-bit memory manipulation instructions. Reset input clears these registers to 00H. Figure 12-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W EGP 0 0 0 EGP4 EGP3 EGP2 EGP1 EGP0 FF48H 00H R/W 7 6 5 4 3 2 1 0 0 0 0 EGN4 EGN3 EGN2 EGN1 EGN0 FF49H 00H R/W EGN 164 EGPn EGNn INTPn pin valid edge selection (n = 0 to 4) 0 0 Interrupt prohibited 0 1 Falling edge 1 0 Rising edge 1 1 Both falling and rising edges User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register that holds the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of PSW are automatically saved into a stack and the IE flag is reset to 0. When a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The acknowledged interrupt is also saved into the stack with the PUSH PSW instruction. It is restored from the stack with the RETI, RETB, and POP PSW instructions. Reset input sets PSW to 02H. Figure 12-6. Configuration of Program Status Word (PSW) PSW 7 6 5 4 3 2 1 0 IE Z RBS1 AC RBS0 0 ISP CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being received High-priority interrupt servicing (low-priority interrupt disable) 1 Interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) IE Interrupt request acknowledge enable/disable 0 Disabled 1 Enabled User’s Manual U15104EJ2V0UD 165 CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operations 12.4.1 Non-maskable interrupt request acknowledgement operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgement disabled state. It does not undergo interrupt priority control and has the highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved to the stack, the program status word (PSW) and the program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. Figure 12-7 shows the flowchart from generation of the non-maskable interrupt request to acknowledging it. Figure 12-8 shows the timing of acknowledging the non-maskable interrupt request, and Figure 12-9 shows the operation performed if a more than one non-maskable interrupt request occurs. 166 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-7. Flowchart from Generation of Non-Maskable Interrupt Request to Acknowledgement Start WDTM4 = 1 (with watchdog timer mode selected)? No Interval timer Yes Overflow in WDT? No Yes WDTM3 = 0 (with non-maskable interrupt request selected)? No Reset processing Yes Interrupt request generation WDT interrupt servicing? No Interrupt request held pending Yes Interrupt control register unaccessed? No Yes Interrupt servicing start WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 12-8. Non-Maskable Interrupt Request Acknowledgement Timing CPU processing Instruction Instruction PSW and PC save, jump to interrupt servicing Interrupt servicing program WDTIF User’s Manual U15104EJ2V0UD 167 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-9. Non-Maskable Interrupt Request Acknowledgement Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine NMI request NMI request NMI request is held pending. Execution of one instruction Pending NMI request is serviced. (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main routine NMI request Execution of one instruction NMI request NMI request Held pending. Held pending. Only one NMI request is acknowledged even if two or more NMI requests are generated in duplicate. 168 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.4.2 Maskable interrupt request acknowledgement operation A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag of the interrupt request is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt servicing (with ISP flag reset to 0). Wait times from maskable interrupt request generation to interrupt request servicing are as follows. For the interrupt acknowledge timing, refer to Figures 12-11 and 12-12. Table 12-3. Times from Maskable Interrupt Request Generation to Interrupt Servicing Note Minimum Time Maximum TimeNote When ××PR = 0 7 clocks 32 clocks When ××PR = 1 8 clocks 33 clocks If an interrupt request is generated just before a divide instruction, the wait time is maximized. Remark 1 clock: 1 fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specification flag is acknowledged first. If two or more requests are specified as the same priority by the priority specification flag, the default priorities apply. Any pending interrupt requests are acknowledged when they become acknowledgeable. Figure 12-10 shows interrupt request acknowledgement algorithms. If a maskable interrupt request is acknowledged, the acknowledged interrupt request is saved to the stack, the program status word (PSW) and the program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged interrupt priority specification flag contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into the PC and branched. Return from the interrupt is possible with the RETI instruction. User’s Manual U15104EJ2V0UD 169 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Interrupt Request Acknowledgement Processing Algorithm Start No ××IF = 1? Yes (interrupt request generation) No ××MK = 0? Yes Interrupt request pending Yes (High priority) ××PR = 0? No (Low priority) Yes Any highpriority interrupt request among simultaneously generated ××PR = 0 interrupts? Interrupt request pending Any simultaneously generated ××PR = 0 interrupt requests? No No Interrupt request pending No Any simultaneously generated high-priority interrupt requests ? IE = 1? Yes Interrupt request pending Yes Vectored interrupt servicing Yes Interrupt request pending No IE = 1? No Interrupt request pending Yes ISP = 1? Yes No Interrupt request pending Vectored interrupt servicing ××IF: Interrupt request flag ××MK: Interrupt mask flag ××PR: Priority specification flag IE: Flag controlling acknowledging maskable interrupt request (1 = enable, 0 = disable) ISP: Flag indicating priority of interrupt currently being serviced (0 = interrupt with high priority serviced, 1 = interrupt request is not acknowledged, or interrupt with low priority serviced) 170 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-11. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks CPU processing Instruction Instruction PSW and PC save, jump to interrupt servicing Interrupt servicing program ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1 fCPU (fCPU: CPU clock) Figure 12-12. Interrupt Request Acknowledgement Timing (Maximum Time) CPU processing Instruction 25 clocks 6 clocks Divide instruction PSW and PC save, jump to interrupt servicing Interrupt servicing program ××IF (××PR = 1) 33 clocks ××IF (××PR = 0) 32 clocks Remark 1 clock: 1 fCPU (fCPU: CPU clock) User’s Manual U15104EJ2V0UD 171 CHAPTER 12 INTERRUPT FUNCTIONS 12.4.3 Software interrupt request acknowledgement operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, it is saved to the stack, the program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into the PC and branched. Return from the software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for returning from a software interrupt. 172 User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.4.4 Multiple interrupt servicing The acknowledgement of another interrupt request while an interrupt is being serviced is called multiple interrupt servicing. Multiple interrupt servicing does not take place unless the interrupts (except the non-maskable interrupt) are abled to be acknowledged (IE = 1). Acknowledging another interrupt request is disabled (IE = 0) when one interrupt has been acknowledged. Therefore, to enable multiple interrupt servicing, the EI flag must be set to 1 during interrupt servicing, to enable other interrupts. Multiple interrupt servicing may not occur even when interrupts are enabled. This is controlled by the priorities of the interrupts. Although two types of priorities, default priority and programmable priority, may be assigned to an interrupt, multiple interrupt servicing is controlled by using the programmable priority. If an interrupt with the same priority as or a higher priority than the interrupt currently being serviced occurs, that interrupt can be acknowledged and serviced. If an interrupt with a priority lower than that of the interrupt currently being serviced occurs, that interrupt cannot be acknowledged and serviced. An interrupt that is not acknowledged and serviced because it is disabled or it has a low priority is held pending. This interrupt is acknowledged after servicing of the current interrupt has been completed and one instruction of the main routine has been executed. Multiple interrupt servicing is not enabled while a non-maskable interrupt is being serviced. Table 12-4 shows the interrupts that can enter multiple interrupt servicing, and Figure 12-13 shows an example of multiple interrupt servicing. Table 12-4. Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Non-Maskable Request Interrupt Request Interrupt Being Serviced Maskable Interrupt Request PR = 0 PR = 1 IE = 1 IE = 0 IE = 1 IE = 0 Non-maskable interrupt D D D D D Maskable interrupt ISP = 0 E E D D D ISP = 1 E E D E D E E D E D Software interrupt servicing Remarks 1. E: Multiple interrupt servicing enabled 2. D: Multiple interrupt servicing disabled 3. ISP and IE are the flags contained in PSW ISP = 0: An interrupt with higher priority is being serviced ISP = 1: An interrupt request is not accepted or an interrupt with lower priority is being serviced IE = 0: Interrupt request acknowledgement is disabled IE = 1: Interrupt request acknowledgement is enabled 4. PR is a flag contained in PR0L and PR0R. PR = 0: Higher priority level PR = 1: Lower priority level User’s Manual U15104EJ2V0UD 173 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-13. Multiple Interrupt Servicing Example (1/2) Example 1. Example where multiple interrupt occurs two times Main processing INTxx service IE = 0 EI INTyy (PR = 0) INTzz service IE = 0 IE = 0 EI INTxx (PR = 1) INTyy service EI INTzz (PR = 0) RETI RETI RETI Two interrupt requests, INTyy and INTzz, are acknowledged while interrupt INTxx is serviced, and multiple interrupt occurs. Before each interrupt request is acknowledged, the EI instruction is always executed, and the interrupt is enabled. Example 2. Example where multiple interrupt does not occur because of priority control Main processing EI INTxx service INTyy service IE = 0 EI INTxx (PR = 0) INTyy (PR = 1) 1 instruction execution RETI IE = 0 RETI Interrupt request INTyy that is generated while interrupt INTxx is being serviced is not acknowledged because its priority is lower than that of INTxx, and therefore, multiple interrupt does not occur. INTyy request is held pending, and is acknowledged after one instruction of the main routine has been executed. PR = 0: High-priority level PR = 1: Low-priority level IE = 0: 174 Acknowledging interrupt request is disabled. User’s Manual U15104EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-13. Multiple Interrupt Servicing Example (2/2) Example 3. Example where multiple interrupt does not occur because interrupts are not enabled Main processing EI INTxx service INTyy service IE = 0 INTxx (PR = 0) 1 instruction execution INTyy (PR = 0) RETI IE = 0 RETI Because interrupts are not enabled (EI instruction is not issued) in interrupt servicing INTxx, interrupt request INTyy is not acknowledged, and multiple interrupt does not occur. The INTyy request is held pending, and is acknowledged after one instruction of the main routine has been executed. PR = 0: High priority level IE = 0: Acknowledging interrupts is disabled. User’s Manual U15104EJ2V0UD 175 CHAPTER 12 INTERRUPT FUNCTIONS 12.4.5 Pending interrupt requests Even if an interrupt request is generated, the following instructions hold it pending. • MOV PSW, #byte • MOV A, PSW • MOV PSW, A • MOV1 PSW.bit, CY • MOV1/AND1/OR1/XOR1 CY, PSW.bit • SET1/CLR1 PSW.bit • RETB • RETI • PUSH PSW • POP PSW • BT/BF/BTCLR PSW.bit, $addr16 • EI • DI • Instructions manipulating IF0L, IF0H, MK0L, MK0H, PR0L, and PR0H registers Caution Because the IE flag is cleared to 0 by the software interrupt (caused by execution of the BRK instruction), a maskable interrupt request is not acknowledged even if it occurs while the BRK instruction is executed. However, a non-maskable interrupt is acknowledged. Figure 12-14. Pending Interrupt Request CPU processing Instruction N Instruction M Save PSW and PC, jump to interrupt servicing ××IF Remarks 1. Instruction N: Instruction that holds interrupt request pending 2. Instruction M: Instruction that does not hold interrupt request pending 3. Operation of ××IF is not affected by value of ××PR. 176 User’s Manual U15104EJ2V0UD Interrupt servicing program CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.1 Function of PLL Frequency Synthesizer The PLL (Phase Locked Loop) frequency synthesizer is used to lock the frequency in the MF (Middle Frequency), HF (High Frequency), and VHF (Very High Frequency) ranges to a specific frequency by means of phase difference comparison. The PLL frequency synthesizer divides the frequency of the signal input from the VCOL or VCOH pin by using a programmable divider, and outputs the phase difference between the frequency of this signal and reference frequency from the EO0 and EO1 pin. The following input pin states and frequency division modes are used. (1) Direct division (MF) mode The VCOL pin is used. The VCOH pin is set in the status specified by bit 3 (VCOHDMD) of the PLL mode select register (PLLMD). (2) Pulse swallow (HF) mode The VCOL pin is used. The VCOH pin is set in the status specified by bit 3 (VCOHDMD) of PLLMD. (3) Pulse swallow (VHF) mode The VCOH pin is used. The VCOL pin is set in the status specified by bit 2 (VCOLDMD) of PLLMD. (4) VCOL and VCOH pin disable The VCOL and VCOH pins are set in the status specified by bits 2 (VCOLDMD) and 3 (VCOHDMD) of PLLMD. At this time, the phase comparator, reference frequency generator, and charge pump operate. (5) PLL disable The PLL disabled status is set by the PLL reference mode register (PLLRF). The VCOH and VCOL pins are set in the status specified by bits 2 (VCOLDMD) and 3 (VCOHDMD) of PLLMD. The EO0 and EO1 pins go into a high-impedance state. At this time, all the internal PLL operations are stopped. These division modes are selected by using the PLL mode select register (PLLMD). The division value (N value) is set to the programmable divider by using the PLL data register. Frequency division in each of the above modes is carried out according to the value (N value) set to the programmable divider. Table 13-1 shows the division modes, input pins used (VCOL pin or VCOH pin), and the value that can be set to the programmable divider. User’s Manual U15104EJ2V0UD 177 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Table 13-1. Division Mode, Input Pin, and Division Value Division Mode Pin Used Value That Can Be Set Direct division (MF) VCOL 32 to 212–1 Pulse swallow (HF) VCOL 1024 to 217–1 Pulse swallow (VHF) VCOH 1024 to 217–1 Caution For the frequencies that can be actually input, and input amplitude, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. 178 User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.2 Configuration of PLL Frequency Synthesizer The PLL frequency synthesizer consists of the following hardware. Table 13-2. Configuration of PLL Frequency Synthesizer Item Configuration Data registers PLL data register L (PLLRL) PLL data register H (PLLRH) PLL data register 0 (PLLR0) Control registers PLL PLL PLL PLL mode select register (PLLMD) reference mode register (PLLRF) unlock F/F judge register (PLLUL) data transfer register (PLLNS) Figure 13-1. Block Diagram of PLL Frequency Synthesizer Internal bus PLL mode select register (PLLMD) VCOH VCOL PLL PLL DMD DMD MD1 MD0 2 PLL data transfer register (PLLNS) PLL data register (PLLRL, PLLRH, PLLR0) 2 fN VCOH Mixer Input select block Programmable divider VCOL Voltage control generator Note PLL NS0 4.5 MHz fr Phase comparator ( φ -DET) Reference frequency generator EO1 Charge pump EO0 Unlock FF 4 Note Lowpass filter Note PLL PLL PLL PLL PLL RF3 RF2 RF1 RF0 UL0 PLL reference PLL unlock F/F judge register mode register (PLLUL) (PLLRF) Internal bus External circuit User’s Manual U15104EJ2V0UD 179 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (1) PLL data register L (PLLRL), PLL data register H (PLLRH), and PLL data register 0 (PLLR0) These registers set the division value of the PLL frequency synthesizer. The division value of the PLL frequency synthesizer is made up of 17 bits. The higher 16 bits of this value are set by PLL data register L (PLLRL) and PLL data register H (PLLRH). The higher 16 bits can also be set by the PLL data register (PLLR). The least significant bit is set by bit 7 (PLLSCN) of PLL data register 0 (PLLR0). Reset input makes the contents of these registers undefined. These registers hold the current values in the STOP and HALT modes. (2) Input select block The input select block consists of the VCOL and VCOH pins, and input amplifiers of the respective pins. (3) Programmable divider The programmable divider consists of two modulus prescalers, a programmable counter (12 bits), a swallow counter (5 bits), and a division mode select switch. (4) Reference frequency generator The reference frequency generator consists of a divider that generates the reference frequency fr of the PLL frequency synthesizer, and a multiplexer. (5) Phase comparator The phase comparator (φ-DET) compares the phase of the divided frequency output fN of the programmable divider with that of the reference frequency output fr of the reference frequency generator, and outputs an up request signal (UP) and down request signal (DW). (6) Unlock F/F The unlock F/F detects the unlock status of the PLL frequency synthesizer from the up request signal (UP) and down request signal (DW) of the phase comparator (φ-DET). (7) Charge pump The charge pump outputs the result of the output of the phase comparator from the error out pins (EO0 and EO1 pins). 180 User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.3 Registers Controlling PLL Frequency Synthesizer The PLL frequency synthesizer is controlled by the following four registers. • PLL mode select register (PLLMD) • PLL reference mode register (PLLRF) • PLL unlock F/F judge register (PLLUL) • PLL data transfer register (PLLNS) (1) PLL mode select register (PLLMD) This register selects the input pin and division mode of the PLL frequency synthesizer. PLLMD is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. In the STOP mode, only bits 3 and 2 (VCOHDMD and VCOLDMD) retain the previous value. Bits 1 and 0 (PLLMD1 and PLLMD0) are reset to 0. In the HALT mode, it holds the value immediately before the HALT mode was set. Figure 13-2. Format of PLL Mode Select Register (PLLMD) Symbol 7 6 5 4 PLLMD 0 0 0 0 <3> <2> <1> <0> VCOHDMD VCOLDMD PLLMD1 PLLMD0 VCOH DMD Address After reset R/W FFA0H 00H R/W Selection of disable status of VCOH pin 0 Connected to pull-down resistor. 1 High-impedance state VCOL Selection of disable status of VCOL pin DMD 0 Connected to pull-down resistor. 1 High-impedance state PLLMD1 PLLMD0 Selection of division mode of PLL frequency synthesizer and VCO input pin 0 0 Disables VCOL and VCOH pinsNote 0 1 Direct division (VCOL pin and MF mode) 1 0 Pulse swallow (VCOH pin and VHF mode) 1 1 Pulse swallow (VCOL pin and HF mode) Note This does not mean that the PLL is disabled. The VCOH and VCOL pins become the status specified by bit 3 (VCOHDMD) and bit 2 (VCOLDMD). The EO0 and EO1 pins go low. Remark Bits 4 to 7 are fixed to 0 by hardware. User’s Manual U15104EJ2V0UD 181 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (2) PLL reference mode register (PLLRF) This register selects the reference frequency fr of the PLL frequency synthesizer and sets the disabled status of the PLL frequency synthesizer. PLLRF is set with 1-bit or 8-bit memory manipulation instruction. The value of this register is set to 0FH after reset and in the STOP mode. In the HALT mode, it holds the value immediately before the HALT mode was set. Figure 13-3. Format of PLL Reference Mode Register (PLLRF) Symbol 7 6 5 4 PLLRF 0 0 0 0 <3> <2> <1> <0> PLLRF3 PLLRF2 PLLRF1 PLLRF0 PLLRF3 PLLRF2 PLLRF1 PLLRF0 After reset R/W FFA1H 0FH R/W Setting of reference frequency fr of PLL frequency synthesizer 0 0 0 0 50 kHz 0 0 0 1 25 kHz 0 0 1 0 12.5 kHz 0 0 1 1 9 kHz 0 1 0 0 1 kHz 0 1 0 1 3 kHz 0 1 1 0 10 kHz 0 1 1 1 Setting prohibited 1 × × × PLL disableNote Note Address When PLL disable is selected, the status of the VCOL, VCOH, EO0, and EO1 pins are as follows: VCOH, VCOL pins: Status specified by bit 3 (VCOHDMD) and bit 2 (VCOLDMD) of the PLL mode select register (PLLMD). EO0, EO1 pins: Remark High-impedance state Bits 4 to 7 are fixed to 0 by hardware. ×: Don’t care 182 User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER (3) PLL unlock F/F judge register (PLLUL) This register detects whether the PLL frequency synthesizer is in the unlock status. Because this register is an R&RESET register, it is reset to 0 after it has been read. Reset input sets this register to 0×HNote 1. In the STOP and HALT modes, this register holds the value immediately before the STOP or HALT mode was set. Figure 13-4. Format of PLL Unlock F/F Judge Register (PLLUL) Symbol PLLUL 7 6 0 5 0 0 4 0 3 2 0 1 0 0 PLLUL0 Address <0> PLLUL0 FFA2H After reset Note 1 0×H R/W R Note 2 Detection of status of unlock F/F 0 Unlock F/F = 0: PLL lock status 1 Unlock F/F = 1: PLL unlock status Notes 1. The value of bit 0 (PLLUL0) at reset differs depending on the type of reset that has been executed (refer to the table below). 2. Bit 0 (PLLUL0) is R&Reset. After reset Power-on clear 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Undefined Watchdog timer Retained RESET input Retained STOP mode Retained HALT mode Retained Remark Bits 1 to 7 are fixed to 0 by hardware. User’s Manual U15104EJ2V0UD 183 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (4) PLL data transfer register (PLLNS) This register transfers the values of the PLL data registers (PLLRL, PLLRH, and PLLR0) to the programmable counter and swallow counter. The value of this register is 00H after reset and in the STOP mode. In the HALT mode, this register holds the previous value immediately before the HALT mode is set. Figure 13-5. Format of PLL Data Transfer Register (PLLNS) Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W PLLNS 0 0 0 0 0 0 0 PLLNS0 FFA3H 00H W PLLNS0 0 Does not transfer 1 Transfers Remark 184 Transfers value of PLL data register to programmable counter and swallow counter Bits 1 to 7 are fixed to 0 by hardware. User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.4 Operation of PLL Frequency Synthesizer 13.4.1 Operation of each block of PLL frequency synthesizer (1) Operation of input select block and programmable divider The input select block and programmable divider select the input pin and division mode of the PLL frequency synthesizer and divide the frequency in the selected division mode, according to the setting of the PLL mode select register (PLLMD). The programmable counter (12 bits) and pulse swallow counter (5 bits) are binary counters. The division value (N value) is set to the programmable counter (12 bits) and swallow counter (5 bits) by the PLL data registers (PLLRL, PLLRH, and PLLR0). When the N value has been transferred to the programmable counter and swallow counter, frequency division is performed in the selected division mode according to the status of bit 0 (PLLNS0) of the PLL data transfer register. Figure 13-6 shows the configuration of the input select block and programmable divider. Figure 13-6. Configuration of Input Select Block and Programmable Divider VCOH VCOHDMD AMP VHF HF MF Swallow counter (5 bits) Two modulus prescalers (1/32, 1/33) VHF HF VCOL VCOLDMD AMP MF Programmable counter (12 bits) 12 bits To φ -DET fN 5 bits PLL data registers (PLLRL, PLLRH, PLLR0) PLL NS0 PLL data transfer register Internal bus (2) Operation of reference frequency generator The reference frequency generator divides the 4.5 MHz output of the crystal oscillator and generates seven types of reference frequency fr for the PLL frequency synthesizer. Reference frequency fr is selected by the PLL reference mode register (PLLRF). Figure 13-7 shows the configuration of the reference frequency generator. User’s Manual U15104EJ2V0UD 185 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Figure 13-7. Configuration of Reference Frequency Generator PLLRF3 to PLLRF0 4-16 decoder PLL disable signal MUX Divider 1 kHz 3 kHz 9 kHz 4.5 MHz fr To φ -DET 25 kHz 50 kHz (3) Operation of phase comparator (φ-DET) Figure 13-8 shows the configuration of the phase comparator (φ-DET), charge pump, and unlock F/F. The phase comparator (φ-DET) compares the phase of the divided frequency fN of the programmable divider with that of the reference frequency fr of the reference frequency generator, and outputs an up request signal, UP, or a down request signal, DW. If the divided frequency fN is lower than the reference frequency fr, the up request signal is output. If fN is higher than fr, the down request signal is output. Figure 13-9 shows the relation among reference frequency fr, divided frequency fN, up request signal UP, and down request signal DW. When the PLL is disabled, neither the up nor the down request signal is output. The up and down request signals are input to the charge pump and unlock F/F. Figure 13-8. Configuration of Phase Comparator, Charge Pump, and Unlock F/F Reference frequency generator fr UP Unlock F/F PLLUL Phase comparator ( φ -DET) EO1 Programmable divider fN DW EO0 PLL disable signal 186 Charge pump User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER Figure 13-9. Relationship Between fr, fN, UP, and DW (a) If fr advances fN in phase fr fN UP DW (b) If fN advances fr in phase fr fN UP DW (c) If fN and fr are in phase fr fN UP DW (d) If fN is lower than fr fr fN UP DW (4) Operation of charge pump The charge pump outputs the result of the up request (UP) or down request (DW) signal from the phase comparator (φ-DET) from the error out pins (EO0 and EO1 pins). Table 13-3 shows the output signals. The EO0 and EO1 pins are of voltage-driven type pins. Figure 13-10 shows the configuration of the error out pins. User’s Manual U15104EJ2V0UD 187 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Table 13-3. Error Out Output Signal Relationship Between Divided Frequency fN and Reference Frequency fr Error Out Output Signal When fr > fN Low level When fr < fN High level When fr = fN Floating (high impedance) Figure 13-10. Configuration of Error Out Output VDDPLL DW P-ch EO1 UP N-ch GNDPLL VDDPLL P-ch EO0 N-ch GNDPLL 188 User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER (5) Operation of unlock F/F The unlock F/F detects the unlock status of the PLL frequency synthesizer. The unlock status of the PLL frequency synthesizer is detected from the up request signal UP and down request signal DW of the phase comparator (φ-DET). Because either of the up request or down request signal outputs a low level in the unlock status, the unlock status can be detected by using this low-level signal. The status of the unlock F/F is detected by bit 0 (PLLUL0) of the PLL unlock F/F judge register (PLLUL). The unlock F/F is set at the cycle of reference frequency fr selected at that time. The PLL unlock F/F judge register is reset when its contents have been read. To read the PLLUL, therefore, it must be read at a cycle longer than the cycle (1/fr) of the reference frequency. 13.4.2 Operation to set N value of PLL frequency synthesizer The division value (N value) is set to the programmable counter (12 bits) and swallow counter (5 bits) by the PLL data registers (PLLRL, PLLRH, and PLLR0). When the N value has been transferred to the programmable counter and swallow counter by bit 0 (PLLNS0) of the PLL data transfer register (PLLNS), frequency division is carried out in the selected division mode. Examples of setting the N value in the respective division modes (MF, HF, and VHF) are shown below. (1) Direct division mode (MF) (a) Calculating division value N (value set to PLL data register) N= fVCOL fr where, fVCOL: Input frequency of VCOL pin f r: Reference frequency (b) Example of setting PLL data register An example of setting the PLL data register to receive broadcasting stations in the following MW band is shown below. Receive frequency: 1422 kHz (MW band) Reference frequency: 9 kHz Intermediate frequency: 450 kHz Division value N is calculated as follows: N= fVCOL fr = 1422 + 450 9 = 208 (decimal) = 0D0H (hexadecimal) User’s Manual U15104EJ2V0UD 189 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Data is set to the PLL data registers (PLLR and PLLR0) as follows. PLLR0 PLLR PLLRH PLLSCN PLLRL b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 Programmable counter value 0 0 0 0 1 1 0 0 1 0 D b3 b2 b1 b0 Don’t care 0 0 Fixed to 0 0 0 After setting the above PLL data registers (PLLR and PLLR0), data must be transferred to the programmable counter by setting bit 0 (PLLNS0) of the PLL data transfer register (PLLNS). (2) Pulse swallow mode (HF) (a) Calculating division value N (value set to PLL data register) N= fVCOL fr where, fVCOL: Input frequency of VCOL pin f r: Reference frequency (b) Example of setting PLL data register An example of setting the PLL data register to receive broadcasting stations in the following SW band is shown below. Receive frequency: 25.50 MHz (SW band) Reference frequency: 10 kHz Intermediate frequency: 450 kHz Division value N is calculated as follows: N= fVCOL fr = 25500 + 450 10 = 2595 (decimal) = 0A23H (hexadecimal) 190 User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER Because the least significant bit of the division value N must be set to bit 7 (PLLSCN) of PLL data register 0 (PLLR0), data must be set by shifting the result of the above calculation 1 bit to the right. Data is set to the PLL data registers (PLLR and PLLR0) as follows. Result of calculation (N value) 0 0 0 0 1 0 0 1 0 0 0 A 1 0 0 0 2 1 1 3 H Shifted 1 bit to right Value shifted 1 bit to right 0 0 0 0 0 1 0 0 1 0 0 5 0 1 0 0 1 0 1 1 0 H PLLR0 PLLR PLLRH PLLSCN PLLRL b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 Programmable counter value 0 0 0 0 0 0 1 0 5 1 0 b4 b3 b2 b1 b0 Swallow counter value 0 0 1 1 0 0 0 1 1 Fixed to 0 0 0 After setting the above PLL data registers (PLLR and PLLR0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (PLLNS0) of the PLL data transfer register (PLLNS). In this example, a value of half the N value is set to the high-order 16 bits of the PLL data register (PLLR) by shifting the N value resulting from calculation 1 bit to the right. If the N value is calculated as follows with the least significant bit of the N value in PLLSCN fixed to 0, the result of the calculation (NPLLR) can be set to the PLL data register (PLLR) as is. If the calculation result is set in this way, however, the input frequency (fVCOL) is 2 × fr (reference frequency) of the set value NPLLR. NPLLR = fVCOL 2fr User’s Manual U15104EJ2V0UD 191 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (3) Pulse swallow mode (VHF) (a) Calculating division value N (value set to PLL data register) N= fVCOH fr where, fVCOH: Input frequency of VCOH pin f r: Reference frequency (b) Example of setting PLL data register An example of setting the PLL data register to receive broadcasting stations in the following FM band is shown below. Receive frequency: 100.0 MHz (FM band) Reference frequency: 50 kHz Intermediate frequency: +10.7 MHz Division value N is calculated as follows: N= fVCOH fr = 100.0 + 10.7 0.05 = 2214 (decimal) = 08A6H (hexadecimal) Because the least significant bit of the division value N must be set to the PLL data register 0 (PLLR0), data must be set by shifting the value calculated by the above expression 1 bit to the right. Data is set to the PLL data registers (PLLR and PLLR0) as follows. Result of calculation (N value) 0 0 0 0 1 0 0 0 0 1 0 8 1 0 0 1 A 1 0 6 H Shifted 1 bit to right Value shifted 1 bit to right 0 0 0 0 0 1 0 0 0 0 1 4 0 1 0 0 5 1 1 3 0 H PLLR PLLR0 PLLRH PLLSCN PLLRL b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 Programmable counter value 0 0 0 0 192 0 0 1 0 4 0 0 b4 b3 b2 b1 b0 Swallow counter value 1 0 5 1 0 0 1 3 1 Fixed to 0 0 0 User’s Manual U15104EJ2V0UD CHAPTER 13 PLL FREQUENCY SYNTHESIZER After setting the above PLL data registers (PLLR and PLLR0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (PLLNS0) of the PLL data transfer register (PLLNS). In this example, a value of half the N value is set to the higher 16 bits of the PLL data register (PLLR) by shifting the N value resulting from calculation 1 bit to the right. If the N value is calculated as follows with the least significant bit of the N value in PLLSCN fixed to 0, the result of the calculation (NPLLR) can be set to the PLL data register (PLLR) as is. If the calculation result is set in this way, however, the input frequency (fVCOH) is 2 × fr (reference frequency) of the set value NPLLR. NPLLR = fVCOH 2fr User’s Manual U15104EJ2V0UD 193 CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.5 PLL Disable Status The PLL frequency synthesizer can be stopped (PLL disabled status) by performing any of the following settings while the PLL frequency synthesizer is operating. • Setting value of bit 3 (PLLRF3) of the PLL reference mode register (PLLRF) to 1 to set PLL disabled status • Setting STOP mode with the STOP instruction • Setting reset status with the reset function The following table shows the operation of each block and the status of each register in the PLL disabled status. Table 13-4. Operation of Each Block and Register Status in PLL Disabled Status Block/Register Status in PLL Disabled Status VCOL and VCOH pins Status set in bit 3 (VCOHDMD) and bit 2 (VCOLDMD) of PLLMD Programmable divider Division stops Reference frequency generator Output stops Phase comparator Output stops EO0 and EO1 pin High impedance PLL mode select register Retains value on execution of write instruction PLL data register PLL unlock F/F judge register 13.6 Notes on PLL Frequency Synthesizer • Notes on using PLL frequency synthesizer Because the input pins (VCOL and VCOH pins) of the PLL frequency synthesizer are provided with an AC amplifier, cut the DC component of the input signal by connecting a capacitor to the input pins in series. The potential of the selected input pin is intermediate (about 1/2VDD). The input pin not selected becomes the status set in bit 3 (VCOHDMD) and bit 2 (VCOLDMD) of the PLL mode select register (PLLMD). For the frequencies that can be actually input and input amplitude, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. 194 User’s Manual U15104EJ2V0UD CHAPTER 14 FREQUENCY COUNTER 14.1 Function of Frequency Counter The frequency counter counts the intermediate frequency (IF) of a tuner. The intermediate frequency input to the FMIFC or AMIFC pin is counted for a specific time (1 ms, 4 ms, 8 ms, or open) by a 16-bit counter. The count value of the frequency counter is stored in the IF counter register. For the range of the frequency that can be input to the FMIFC and AMIFC pins, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. 14.2 Configuration of Frequency Counter The frequency counter consists of the following hardware. Table 14-1. Configuration of Frequency Counter Item Configuration Counter register IF counter register (IFCR) Control registers IF counter mode select register (IFCMD) IF counter control register (IFCR) IF counter gate judge register (IFCJG) User’s Manual U15104EJ2V0UD 195 CHAPTER 14 FREQUENCY COUNTER Figure 14-1. Block Diagram of Frequency Counter 2 Gate time control block FMIFC IF counter register (IFCR) block Start/stop control block Input select block AMIFC 2 IFC IFC IFC IFC MD1 MD0 CK1 CK0 IF counter mode select register (IFCMD) IFC IFC ST RES IFC JG0 IF counter gate judge register (IFCJG) Internal bus IF counter control register (IFCCR) (1) IF counter input select block The IF counter input select block selects the pin to be used from the FMIFC and AMIFC pins, and a count mode. (2) Gate time control block The gate time control block sets a gate time (count time). (3) Start/stop control block The start/stop control block starts counting by the IF counter register and detects the end of counting. (4) IF counter register block The IF counter register block is a 16-bit register that counts up the frequency input in the set gate time. The count value is stored to the IF counter register (IFCR). When the count value reaches FFFFH, the IF counter register holds FFFFH at the next input, and stops counting. The value of this register is reset to 0000H after reset or in the STOP mode. In the HALT mode, it holds the current count value. 196 User’s Manual U15104EJ2V0UD CHAPTER 14 FREQUENCY COUNTER 14.3 Registers Controlling Frequency Counter The frequency counter is controlled by the following three registers. • IF counter mode select register (IFCMD) • IF counter control register (IFCCR) • IF counter gate judge register (IFCJG) (1) IF counter mode select register (IFCMD) This register selects the input pin of the frequency counter, and selects a mode and gate time (count time). This register is set with a 1-bit or 8-bit memory manipulation instruction. The value of this register is reset to 00H after reset or in the STOP mode. In the HALT mode, this register holds the value immediately before the HALT mode is set. Figure 14-2. Format of IF Counter Mode Select Register (IFCMD) Symbol 7 6 5 4 IFCMD 0 0 0 0 IFCMD1 IFCMD0 <3> <2> <1> <0> IFCMD1 IFCMD0 IFCCK1 IFCCK0 After reset R/W FFA9H 00H R/W Selection of frequency counter pin and mode 0 0 Disables FMIFC, AMIFC pinsNote 0 1 AMIFC pin, AMIF count mode 1 0 FMIFC pin, FMIF count mode 1 1 FMIFC pin, AMIF count mode IFCCK1 IFCCK0 Selection of gate time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 Open Note Address The FMIFC and AMFIC pins are in a high-impedance state. Remark Bits 4 to 7 are fixed to 0 by hardware. User’s Manual U15104EJ2V0UD 197 CHAPTER 14 FREQUENCY COUNTER (2) IF counter control register (IFCCR) This register starts counting by the IF counter register and clears the IF counter register. IFCCR is set with a 1-bit or 8-bit memory manipulation instruction. The value of this register is reset to 00H after reset and in the STOP mode. In the HALT mode, this register holds the value immediately before the HALT mode is set. Figure 14-3. Format of IF Counter Control Register (IFCCR) Symbol 7 6 5 4 3 2 <1> IFCCR 0 0 0 0 0 0 IFCST IFCRES IFCST <0> Address After reset R/W FFACH 00H W Setting of IF counter register start 0 Nothing is affected 1 Starts counting IFCRES Setting of data clear of IF counter register 0 Nothing is affected 1 Clears data of IF counter register Remark Bits 2 to 7 are fixed to 0 by hardware. (3) IF counter gate judge register (IFCJG) This register detects opening/closing of the gate of the frequency counter. The value of this register is reset to 00H after reset and in the STOP mode. In the HALT mode, this register holds the value immediately before the HALT mode is set. Figure 14-4. Format of IF Counter Gate Judge Register (IFCJG) Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W IFCJG 0 0 0 0 0 0 0 IFCJG0 FFABH 00H R IFCJG0 Detection of opening/closing of frequency counter gate 0 Gate is closed 1 • If gate Status • If gate Status Remark time is set to other than open until gate is closed after IFCST has been set to 1 time is set to open where gate is open as soon as it has been set to be opened Bits 1 to 7 are fixed to 0 by hardware. Caution IFCJG0 remains set even if the IF counter register overflows and stops counting, until the set gate time expires. 198 User’s Manual U15104EJ2V0UD CHAPTER 14 FREQUENCY COUNTER 14.4 Operation of Frequency Counter <1> Select an input pin, mode, and gate time using the IF counter mode select register (IFCMD). Figure 14-5 shows a block diagram of input pin and mode selection. <2> Set bit 0 (IFCRES) of the IF counter control register (IFCCR) to 1, and clear the data of the IF counter register. <3> Set bit 1 (IFCST) of the IF counter control register (IFCCR) to 1. <4> The gate is opened only for the set gate time since a 1 kHz internal signal has risen after IFCST was set. If the gate time is set to be opened, the gate is opened as soon as it has been specified to be opened. Bit 0 (IFCJG0) of the IF counter gate judge register (IFCJG) is automatically set to 1 as soon as IFCST has been set to 1. When the gate time has elapsed, bit 0 (IFCJG0) of the IF counter gate judge register (IFCJG) is automatically cleared to 0. If it is specified that the gate be open, however, IFCJG0 is not automatically cleared. In this case, set a gate time. Figure 14-6 shows the gate timing of the frequency counter. <5> While the gate opens the frequency input to the selected FMIFC or AMIFC pin, the IF counter register counts the frequency. If the FMIFC pin is used in the FMIF count mode, however, the input frequency is divided by half before it is counted. The relationship between the count value x (decimal), the input frequencies (fFMIFC and fAMIFC), and the gate time (TGATE) is shown below. • FMIF count mode (FMIFC pin) fFMIFC = x TGATE × 2 (kHz) • AMIF count mode (FMIFC or AMIFC pin) fAMIFC = x TGATE (kHz) Figure 14-5. Block Diagram of Input Pin and Mode Selection FMIF count mode FMIFC AMP 1/2 AMIF count mode IF counter register AMP AMIF count mode AMIFC AMP User’s Manual U15104EJ2V0UD 199 CHAPTER 14 FREQUENCY COUNTER Figure 14-6. Gate Timing of Frequency Counter (a) If gate time is set to 1, 4, or 8 ms H Internal 1 kHz L Gate time OPEN 1 ms CLOSE Counting ends if gate time is 1 ms. OPEN 4 ms CLOSE Counting ends if gate time is 4 ms. OPEN 8 ms CLOSE Gate time: 8 ms Gate time: 1 ms IFCJG0 Gate time: 1 ms Counting ends if gate time is 8 ms. Clears IFCJG0 Counting starts. Gate is opened at this point. Sets IFCST. IFCJG0 is automatically set at this point. (b) If gate is set to be open Internal 1 kHz H L Gate OPEN CLOSE Count period. If IFCST is set during this period, gate is closed after undefined time. IFCCK1 = IFCCK0 = 1. Gate is opened at this point. If gate is opened when IFCJG0 is opened, gate is closed after undefined time. Gate OPEN CLOSE Count period IFCCK1 = IFCCK0 = 1 Sets gate time by using IFCCK1 and IFCCK0 Caution If counting is started by using IFCST while this gate is open, the gate is closed after an undefined time. To open the gate, therefore, do not set IFCST to 1. Remark IFCST: Bit 1 of IF counter control register (IFCCR) IFCJG0: Bit 0 of IF counter gate judge register (IFCJG) IFCCK1, 0: Bits 1 and 0 of IF counter mode select register (IFCMD) 200 User’s Manual U15104EJ2V0UD CHAPTER 14 FREQUENCY COUNTER 14.5 Notes on Frequency Counter (1) Notes on using frequency counter Because signals are input to the frequency counter from an input pin (FMIFC or AMIFC pin) with an AC amplifier as shown in Figure 14-7, cut the DC component of the input signals by using capacitor C. If the FMIFC or AMIFC pin is selected by the IF counter mode select register, switch SW1 turns ON, and switch SW2 turns OFF. As a result, the voltage on the pin is about 1/2VDD. Unless the voltage has risen to a sufficient intermediate level at this time, counting may not be performed normally because the AC amplifier is not in the normal operating range. Therefore, make sure that sufficient wait time elapses after a pin has been selected and before counting is started (IFCST = 1). Figure 14-7. Frequency Counter Input Pin Circuit VDDPLL SW2 R SW1 C External frequency To internal counter FMIFC or AMIFC pin (2) Notes in HALT mode The FMIFC and AMIFC pins hold the status immediately before the HALT status was set. To release the HALT mode by using the interrupt of the frequency counter at this time, the following point must be noted. The gate will not be opened if the HALT instruction is executed after counting has been started by IFCST before the gate is actually opened. Therefore, wait for at least 1 ms before executing the HALT instruction. Figure 14-8. Gate Status When HALT Instruction Is Executed OPEN Gate CLOSE 1 ms MAX. Timing to open gate Interrupt request is not issued if HALT instruction is executed during this period because gate is not opened. Sets IFCST User’s Manual U15104EJ2V0UD 201 CHAPTER 14 FREQUENCY COUNTER (3) Error of frequency counter The error of the frequency counter includes an error of gate time and a count error. (1) Error of gate time The gate time of the frequency counter is created by dividing 4.5 MHz. Therefore, if 4.5 MHz is shifted “+x” ppm, the gate time is also shifted “–x” ppm. (2) Count error The frequency counter counts the frequency at the rising edge of the input signal. If a high level is input to the pin when the gate is opened, therefore, one excess pulse is counted. When the gate is closed, however, counting is not affected by the status of the pin. Therefore, the count error is “maximum + 1”. 202 User’s Manual U15104EJ2V0UD CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as in watch applications. Although the CPU stops operating, the peripheral functions can operate. To lower the current consumption, therefore, stop all unnecessary circuits before executing the HALT instruction. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops and the whole system stops. CPU current consumption can be considerably decreased. Data memory low-voltage hold (down to VDD = 2.2 V) is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. If the supply voltage drops below 2.2 V, the system is reset by means of power-on clear reset. For reset, refer to CHAPTER 16 RESET FUNCTION. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request. All the functions stop operating. Some registers of the PLL frequency synthesizer and frequency counter are reset, but the other functions are stopped with their current status retained. Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing the STOP instruction. 2. The following sequence is recommended for power consumption reduction of the A/D converter: first clear bit 7 (ADCS3) of ADM3 to 0 to stop the A/D conversion operation, then execute the HALT or STOP instruction. User’s Manual U15104EJ2V0UD 203 CHAPTER 15 STANDBY FUNCTION 15.1.2 Register controlling standby function A wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. Reset input sets OSTS to 04H. Figure 15-1. Format of Oscillation Stabilization Time Select Register (OSTS) Symbol 7 6 5 4 3 OSTS 0 0 0 0 0 2 1 0 OSTS2 OSTS1 OSTS0 Address After reset R/W FFFAH 04H R/W OSTS2 OSTS1 OSTS0 0 0 0 0 0 1 0 1 0 Selection of oscillation stabilization time when STOP mode is released 212/fX (910 µ s) 14 (3.64 ms) 15 (7.28 ms) 16 2 /fX 2 /fX 0 1 1 2 /fX (14.6 ms) 1 0 0 217/fX (29.1 ms) Other than above Setting prohibited Remark fX : System clock oscillation frequency ( ): fX = 4.5 MHz Caution The wait time when the STOP mode is released does not include the time required for the clock oscillation to start after the STOP mode has been released (see “a” in the figure below), regardless of whether the mode has been released by the RESET signal or an interrupt request. STOP mode release X1 pin voltage waveform a 204 User’s Manual U15104EJ2V0UD CHAPTER 15 STANDBY FUNCTION 15.2 Operations of Standby Function 15.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 15-1. HALT Mode Operating Status Item Status Clock generator Can oscillate system clock. Stops clock supply to CPU. CPU Stops operating. Port Holds status before HALT mode is set. 8-bit timer/event counter Holds operation before HALT mode is set and can operate. Basic timer Watchdog timer Buzzer output controller A/D converter Retains operation performed when HALT mode is set. However, comparison cannot be performed correctly in A/D conversion operation mode. In power-fail comparison mode, operation is as follows depending on setting of bit 5 (PFHRM3) of power-fail comparison mode register 3 (PFM3): • PFHRM3 = 0: Comparison cannot be performed normally. • PFHRM3: Power-fail comparison operation can be performed. Serial interface (SIO30 to SIO32) Retains operation performed when HALT mode is set and can operate. External interrupt Hold operation before HALT mode is set and can operate. PLL frequency synthesizer Frequency counter Retains operation performed before HALT mode is set. However, operation is not performed correctly though it is continued. Power-on clear circuit Reset when voltage of less than 3.5 V is detected. User’s Manual U15104EJ2V0UD 205 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following three types of sources. (a) Release upon unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If disabled, the next address instruction is executed. Figure 15-2. HALT Mode Release upon Interrupt Generation HALT instruction Interrupt request Wait Standby release signal Operation mode HALT mode Wait Operation mode Oscillation Clock Remarks 1. The broken lines indicate the case when the interrupt request that released the standby status is acknowledged. 2. Wait time will be as follows: • When vectored interrupt servicing is carried out: 8 to 9 clocks • When vectored interrupt servicing is not carried out: 2 to 3 clocks (b) Release upon non-maskable interrupt request When a non-maskable interrupt is generated, the HALT mode is released and vectored interrupt servicing is carried out whether interrupt acknowledgement is enabled or disabled. 206 User’s Manual U15104EJ2V0UD CHAPTER 15 STANDBY FUNCTION (c) Release by RESET input If the RESET signal is input, the HALT mode is released. As is the case with normal reset operation, the program is executed after branch to the reset vector address. Figure 15-3. HALT Mode Release by RESET Input Wait (217/fX: 29.1 ms) HALT instruction RESET signal Operation mode Clock HALT mode Reset period Oscillation Oscillation stop Oscillation stabilization wait status Operation mode Oscillation Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz Table 15-2. Operation After HALT Mode Release Release Source MK×× PR×× IE ISP Operation Maskable interrupt 0 0 0 × Next address instruction execution request 0 0 1 × Interrupt servicing execution 0 1 0 1 Next address instruction execution 0 1 × 0 0 1 1 1 Interrupt servicing execution 1 × × × HALT mode hold – – × × Interrupt servicing execution – – × × Reset processing Non-maskable interrupt request RESET input Remark ×: Don’t care User’s Manual U15104EJ2V0UD 207 CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X1 pin is pulled down to GND, and the X2 pin is internally pulled up to VDD to minimize the leakage current at the crystal oscillator block. 2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operation mode is set. The operating status in the STOP mode is described below. Table 15-3. STOP Mode Operating Status Item Status Clock generator Can oscillate system clock. Stops clock supply to CPU. CPU Stops operating. Port Holds status before HALT mode is set. 8-bit timer/event counter Operation stops and cannot operate. Basic timer Watchdog timer Buzzer output controller A/D converter Serial interface (SIO30 to SIO32) External interrupt Can operate. PLL frequency synthesizer Operation stops and cannot operate. Frequency counter Power-on clear circuit 208 RESET generated when detecting 2.2 V or less. User’s Manual U15104EJ2V0UD CHAPTER 15 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgement is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out. If interrupt request acknowledgement is disabled, the next address instruction is executed. Figure 15-4. STOP Mode Release by Interrupt Request Generation STOP instruction Interrupt request Wait (Time set by OSTS) Standby release signal Clock Operation mode STOP mode Oscillation stabilization wait status Oscillation Oscillation stop Oscillation Operation mode Remark The broken lines indicate the case when the interrupt request that released the standby status is acknowledged. User’s Manual U15104EJ2V0UD 209 CHAPTER 15 STANDBY FUNCTION (b) Release by RESET input If the RESET signal is input, the STOP mode is released, and after the lapse of oscillation stabilization time, a reset operation is carried out. Figure 15-5. Release by STOP Mode RESET Input Wait (217/fX: 29.1 ms) STOP instruction RESET signal Operating mode Reset period STOP mode Oscillation Oscillation stop Oscillation stabilization wait status Operating mode Oscillation Clock Remarks 1. fX: System clock oscillation frequency 2. ( ): fX = 4.5 MHz Table 15-4. Operation After STOP Mode Release Release Source Maskable interrupt request RESET input MK×× PR×× IE ISP 0 0 0 × Next address instruction execution 0 0 1 × Interrupt servicing execution 0 1 0 1 Next address instruction execution 0 1 × 0 0 1 1 1 Interrupt servicing execution 1 × × × STOP mode hold – – × × Reset processing Remark ×: Don’t care 210 User’s Manual U15104EJ2V0UD Operation CHAPTER 16 RESET FUNCTION 16.1 Reset Function The following three operations are available to generate the reset signal. (1) External reset input via a RESET pin (2) Internal reset by inadvertent program loop time detection watchdog timer (3) Internal reset by power-on clear (POC) (1) External reset input by RESET pin When a low level is input to the RESET pin, the device is reset, and each hardware unit enters the status shown in Table 16-1. While the reset signal is input and during the oscillation stabilization time immediately after the RESET signal has been deasserted, each pin goes into a high-impedance state (however, the P130 to P132 pins become low level, and the VCOH and VCOL pins are pulled down). The RESET signal is deasserted when a high level is input to the RESET pin, and the program execution is started after the oscillation stabilization time (217/fX) has elapsed. (2) Internal reset by inadvertent program loop time detection of watchdog timer Reset is effected and each hardware unit enters the status shown in Table 16-1 when the watchdog timer overflow. While reset is in effect and during the oscillation stabilization time immediately after the effect of reset has been cleared, each pin goes into a high-impedance state (however, the P130 to P132 pins become low level, and the VCOH and VCOL pins are pulled down). Reset by the watchdog timer is cleared immediately after reset has been effected, and the program execution is started after the oscillation stabilization time (217/fX) has elapsed. (3) Internal reset by power-on clear (POC) Reset is effected by means of power-on clear under the following conditions: • If supply voltage is less than 3.5 VNote on power application • If supply voltage drops to less than 2.2 VNote in STOP mode • If supply voltage drops to less than 3.5 VNote (including HALT mode) When these reset conditions of power-on clear are satisfied, reset is effected, and each hardware unit enters the status shown in Table 16-1. While the reset signal is input and during the oscillation stabilization time immediately after the reset signal has been deasserted, each pin goes into a high-impedance state (the P130 to P132 pins become low level, however). Reset by power-on clear is cleared if the supply voltage rises beyond a specific level, and the program execution is started after the oscillation stabilization time (217/fX) has elapsed. Note These voltage values are maximum values. Actually, reset is effected at a voltage lower than these. User’s Manual U15104EJ2V0UD 211 CHAPTER 16 RESET FUNCTION Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin. 2. During reset input, system clock oscillation remains stopped. 3. When the STOP mode is released by RESET input, the STOP mode register contents are held during reset input. However, the I/O port pin becomes high-impedance. Output dedicated port pin (P130 to P132) becomes low level regardless of the previous status. Figure 16-1. Reset Function Block Diagram Power-on clear circuit At STOP RESET Count clock Watchdog timer Stop 212 Reset signal Reset controller User’s Manual U15104EJ2V0UD Overflow Interrupt function CHAPTER 16 RESET FUNCTION Figure 16-2. Timing of Reset by RESET Input (a) In normal operation mode X1 Oscillation stabilization time wait Reset period (oscillation stop) Normal operation Normal operation (reset processing) RESET Internal reset signal Delay Delay High impedance I/O port pin Output port pin (P130 to P132) (b) In STOP mode X1 STOP instruction execution Stop status (oscillation stop) Normal operation Reset period (oscillation stop) Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay High impedance I/O port pin Output port pin (P130 to P132) User’s Manual U15104EJ2V0UD 213 CHAPTER 16 RESET FUNCTION Figure 16-3. Timing of Reset due to Watchdog Timer Overflow X1 Normal operation Watchdog timer overflow Reset period (oscillation stop) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal High impedance I/O port pin Output port pin (P130 to P132) 214 User’s Manual U15104EJ2V0UD CHAPTER 16 RESET FUNCTION Figure 16-4. Timing of Reset by Power-on Clear (a) At power application X1 Oscillation stabilization time wait Reset period (oscillation stop) Normal operation (reset processing) 4.5 V VDD 3.5 V 2.2 V Power-on clear voltage (3.5 V) Internal reset signal High impedance I/O port pin Output port pin (P130 to P132) L (b) In STOP mode X1 STOP instruction execution Stop status Normal operation (oscillation stop) Reset period (oscillation stop) 4.5 V Oscillation stabilization time wait Normal operation (reset processing) V VDD 3.5 2.2 V Power-on clear voltage (2.2 V) Internal reset signal High impedance I/O port pin Output port pin (P130 to P132) (c) In normal operating mode (including HALT mode) X1 Reset period (oscillation stop) Normal operation Oscillation stabilization time wait Normal operation (reset processing) 4.5 V VDD 3.5 V 2.2 V Power-on clear voltage (3.5 V) Internal reset signal High impedance I/O port pin Output port pin (P130 to P132) User’s Manual U15104EJ2V0UD 215 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (1/2) Hardware Program counter (PC)Note 1 Status After Reset Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Undefined RAM Port (output latch) Data memory UndefinedNote 2 General-purpose register UndefinedNote 2 Ports 0, 1, 3 to 7, 12, 13 (P0, P1, P3 to P7, P12, P13) 00H Port mode registers (PM0, PM3 to PM7, PM12) FFH Pull-up resistor option register 4 (PU4) 00H Processor clock control register (PCC) 04H Oscillation stabilization time select register (OSTS) 04H DTS system clock select register (DTSCK) 00HNote 3 Memory size switching register (IMS) CFHNote 4 Internal expansion RAM size switching register (IXS) 0CHNote 5 8-bit timer/event counter Counters 50 to 53 (TM50 to TM53) Compare registers 50 to 53 (CR50 to CR53) Watchdog timer Buzzer output controller Serial interface 00H Undefined Clock select registers 50 to 53 (TCL50 to TCL53) 00H Mode control registers 50 to 53 (TMC50 to TMC53) 00H Clock select register (WDCS) 00H Mode register (WDTM) 00H BEEP clock select register 0 (BEEPCL0) 00H Clock output select register (CKS) 00H Shift registers 30 to 32 (SIO30 to SIO32) Undefined Operating mode registers 30 to 32 (CSIM30 to CSIM32) 00H Port select register 32 (SIO32SEL) 00H Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. The status before reset is retained even after reset in the standby mode. 3. Though the initial value is 00H, be sure to set it to 01H before use. 4. The initial value is CFH. Set the following value to this register depending on the model: µPD178053: C6H µPD178054: C8H µPD178F054: Value corresponding to mask ROM versions 5. Do not assign a value other than 0CH. 216 User’s Manual U15104EJ2V0UD CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (2/2) Hardware A/D converter Mode register 3 (ADM3) A/D conversion result register 3 (ADCR3) Interrupt PLL frequency synthesizer Undefined 00H Power-fail comparison mode register 3 (PFM3) 00H Power-fail comparison threshold value register 3 (PFT3) 00H Request flag registers (IF0L and IF0H) 00H Mask flag registers (MK0L and MK0H) FFH Priority specification flag registers (PR0L and PR0H) FFH External interrupt rising edge enable register (EGP) 00H External interrupt falling edge enable register (EGN) 00H PLL mode select register (PLLMD) 00H PLL reference mode register (PLLRF) 0FH PLL unlock F/F judge register (PLLUL) RetainedNote 1 Undefined PLL data transfer register (PLLNS) 00H IF counter mode select register (IFCMD) 00H IF counter gate judge register (IFCJG) 00H IF counter control register (IFCCR) 00H IF counter register (IFCR) Power-on clear 00H Analog input channel specification register 3 (ADS3) PLL data registers (PLLRH, PLLRL, and PLLR0) Frequency counter Status After Reset POC status register (POCS) 0000H RetainedNote 2 Notes 1. Undefined only at power-on clear reset 2. 03H only at power-on clear reset User’s Manual U15104EJ2V0UD 217 CHAPTER 16 RESET FUNCTION 16.2 Power Failure Detection Function If reset is effected by means of power-on clear, bit 0 (POCM) of the POC status register (POCS) is set to 1. If reset is effected by the RESET pin or the watchdog timer, however, POCM holds the previous status. A power failure status can be detected by detecting this POCM after reset by power-on clear has been cleared (after program execution has been started from address 0000H). Figure 16-5. Format of POC Status Register (POCS) Symbol POCS 7 6 0 0 5 0 4 0 3 0 2 0 POCM 0 VM45 POCM Address FF1BH After reset Retained Note R/W R&Reset Detection of power-on clear occurrence status 0 Power-on clear does not occur 1Note Note 1 Reset is effected by power-on clear The value of this register is set to 03H only when reset is effected through power-on clearing. It is not reset by the RESET pin or watchdog timer. Remark The values of the special function registers, other than POCS and PLLUL, at power-on clear are the same as the values following a reset by the RESET pin or watchdog timer (see Table 16-1). 218 User’s Manual U15104EJ2V0UD CHAPTER 16 RESET FUNCTION 16.3 4.5 V Voltage Detection Function This function is used to detect a voltage drop on the VDD pin below 4.5 V (4.5 V ±0.3 V). If the voltage on the VDD pin drops below 4.5 V (4.5 V ±0.3 V), bit 1 (VM45) of the POC status register (POCS) is set. Note, however, that this 4.5 V voltage detection function does not cause internal reset. Figure 16-6. Format of POC Status Register (POCS) Symbol POCS 7 6 0 0 5 0 4 0 3 0 VM45 2 0 1 0 VM45 POCM Address FF1BH Retained Note R/W R&Reset Detection of voltage level of VDD pin 0 Does not detect if VDD pin is less than 4.5 V (4.3 V ±0.3 V) 1 Detects if VDD pin is less than 4.5 V (4.3 V ±0.3 V) Note After reset The value of this register is set to 03H only at power-on clear reset, and is not reset by the RESET pin and watchdog timer. Remark The values of the special function registers, other than POCS and PLLUL, at power-on clear are the same as the values following a reset by the RESET pin or watchdog timer (see Table 16-1). User’s Manual U15104EJ2V0UD 219 CHAPTER 17 µPD178F054 The µPD178F054 is provided with a flash memory to/from which data can be rewritten/erased with the device mounted on the printed circuit board. The differences between the flash memory (µPD178F054) and mask ROM versions (µPD178053 and 178054) are shown in Table 17-1. Table 17-1. Differences Between µPD178F054 and Mask ROM Versions µPD178F054 Item Internal memory µPD178053, 178054 ROM structure Flash memory Mask ROM ROM capacity 32 KB µPD178053: 24 KB µPD178054: 32 KB Internal ROM capacity selected by memory size switching register (IMS) Equivalent to mask ROM version µPD178053: C6H µPD178054: C8H IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications Refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. 220 User’s Manual U15104EJ2V0UD CHAPTER 17 µPD178F054 17.1 Memory Size Switching Register (IMS) The internal memory capacity of the µPD178F054 can be changed using the memory size switching register (IMS). By using this register, the memory of the µPD178F054 can be mapped in the same manner as a mask ROM version with a different internal memory capacity. IMS is set with an 8-bit memory manipulation instruction. Reset input sets this register to CFH. Be sure to set IMS to C6H or C8H. Figure 17-1. Format of Memory Size Switching Register (IMS) Symbol 7 6 5 4 IMS RAM2 RAM1 RAM0 0 3 2 1 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 1 0 512 bytes 1 1 0 1024 bytes After reset R/W FFF0H CFH R/W Setting prohibited ROM3 ROM2 ROM1 ROM0 Selection of internal ROM capacity 0 1 1 0 24 KB 1 0 0 0 32 KB Other than above Address Selection of internal high-speed RAM capacity 0 Other than above 0 Setting prohibited Table 17-2 shows the setting of IMS to perform the same memory mapping as that of a mask ROM version. Table 17-2. Set Value of Memory Size Switching Register Targeted Model Set Value of IMS µPD178053 C6H µPD178054 C8H User’s Manual U15104EJ2V0UD 221 CHAPTER 17 µPD178F054 17.2 Internal Expansion RAM Size Switching Register (IXS) The internal expansion RAM capacity of the µPD178F054 can be changed using the internal expansion RAM size switching register (IXS). By using this register, the memory of the µPD178F054 can be mapped in the same manner as a mask ROM version with a different internal expansion RAM capacity. IXS is set with an 8-bit memory manipulation instruction. Reset input sets this register to 0CH. Caution Do not set a value other than the initial value. Figure 17-2. Format of Internal Expansion RAM Size Switching Register (IXS) Symbol 7 6 5 IXS 0 0 0 4 3 2 1 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 1 Other than above 0 1 0 0 Address After reset R/W FFF4H 0CH R/W Selection of internal expansion RAM capacity 0 bytes Setting prohibited Table 17-3 shows the setting of IXS to perform the same memory mapping as that of a mask ROM version. Table 17-3. Set Value of Internal Expansion RAM Size Switching Register Targeted Model µPD178053, 178054 222 Set Value of IXS 0CH User’s Manual U15104EJ2V0UD CHAPTER 17 µPD178F054 17.3 Flash Memory Programming The program memory provided in the µPD178F054 is flash memory. The flash memory can be written on-board, i.e., with the µPD178F054 mounted on the target system. To do so, connect a dedicated flash programmer (Flashpro III (Part number: FL-PR3, PG-FP3)) to the host machine and target system. Remark FL-PR3 and PG-FP3 are products of Naito Densei Machida Mfg. Co., Ltd. 17.3.1 Selecting communication mode The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 17-4. To select a communication mode, the format shown in Figure 17-3 is used. Each communication mode is selected depending on the number of VPP pulses shown in Table 17-4. Table 17-4. Communication Modes Communication Mode 3-wire serial I/O (SIO3) Pins Used Number of VPP Pulses SI30/P70 SO30/P71 0 SCK30/P72 SI31/P74 SO31/P75 SCK31/P76 1 SI32/P120 SO32/P121 SCK32/P122 2 Caution Be sure to select a communication mode by the number of VPP pulses shown in Table 17-4. Figure 17-3. Format of Communication Mode Selection 10 V VPP VDD 1 2 n GND VDD RESET GND User’s Manual U15104EJ2V0UD 223 CHAPTER 17 µPD178F054 17.3.2 Flash memory programming function An operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. The major flash memory programming functions are listed in Table 17-5. Table 17-5. Major Functions of Flash Memory Programming Function Description Batch erase Erases all memory contents. Batch blank check Checks erased status of entire memory. Data write Writes data to flash memory starting from write start address and based on number of data (bytes) to be written). Batch verify Compares all contents of memory with input data. 17.3.3 Connecting Flashpro III The connection between Flashpro III and the µPD178F054 is shown in Figure 17-4. Figure 17-4. Connection of Flashpro III in 3-Wire Serial I/O Mode µ PD178F054 Flashpro III Note VPP VDD VDD VPPn VDDPORT RESET RESET SCK30, SCK31, SCK32 SCK SI30, SI31, SI32 SO SO30, SO31, SO32 SI GND GND GNDPORT Note 224 n = 1, 2 User’s Manual U15104EJ2V0UD CHAPTER 17 µPD178F054 17.3.4 Setting example for Flashpro III (PG-FP3) When writing data to flash memory using Flashpro III (PG-FP3), use the following settings. <1> Load parameter file. <2> Select the serial mode and serial cock using the type command. <3> An example of the settings for PG-FP3 is shown in Table 17-6. Table 17-6. Setting Example for Flashpro III (PG-FP3) Communication Mode 3-wire serial I/O (SIO3) Setting of Flashpro III COMM PORT SIO ch-0 CPU CLK On Target Board Number of VPP PulsesNote 0 In Flashpro 3-wire serial I/O (SIO31) On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT SIO-ch1 CPU CLK On Target Board 1 In Flashpro 3-wire serial I/O (SIO32) On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT SIO-ch2 CPU CLK On Target Board 2 In Flashpro Note On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz Number of VPP pulse supplied by Flashpro III (PG-FP3) when serial mode is initialized. This determines the pin used for the communication. Remark COMM PORT: Selection of serial port SIO CLK: Selection of serial clock frequency CPU CLK: Selection of CPU clock source to be input User’s Manual U15104EJ2V0UD 225 CHAPTER 18 INSTRUCTION SET This chapter describes each instruction set of the µPD178054 Subseries as list table. For details of its operation and operation code, refer to the 78K/0 Series User’s Manual Instruction (U12326E). 226 User’s Manual U15104EJ2V0UD CHAPTER 18 INSTRUCTION SET 18.1 Conventions 18.1.1 Operand symbols and description Operands are written in the “Operand” column of each instruction in accordance with the description of the instruction operand symbols (refer to the assembler specifications for detail). When there are two or more descriptions, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be written as they are. Each symbol has the following meaning. • #: Immediate data specification • !: Absolute address specification • $: Relative address specification • [ ]: Indirect address specification In the case of immediate data, write an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register symbols, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used. Table 18-1. Operand Symbols and Descriptions Symbol Description r rp sfr sfrp X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbolNote Special-function register symbol (16-bit manipulatable register even addresses only)Note saddr saddrp FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even address only) addr16 addr11 addr5 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RBn RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, refer to Table 3-4 Special Function Registers. User’s Manual U15104EJ2V0UD 227 CHAPTER 18 INSTRUCTION SET 18.1.2 Description of “operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag RBS: Register bank select flag IE: Interrupt request enable flag NMIS: Non-maskable interrupt servicing flag ( ): Memory contents indicated by address or register contents in parentheses ×H, ×L: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : ——: Exclusive logical sum (exclusive OR) Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 18.1.3 Description of “flag operation” column (Blank): Nt affected 0: Cleared to 0 1: Set to 1 ×: Set/cleared according to the result R: Previously saved value is restored 228 User’s Manual U15104EJ2V0UD CHAPTER 18 INSTRUCTION SET 18.2 Operation List Instruction Mnemonic Group 8-bit data transfer MOV Operands Byte r, #byte 2 Note 2 4 – Operation r ← byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 1 2 – A←r r, A Note 3 1 2 – r←A A, saddr 2 4 5 A ← (saddr) saddr, A 2 4 5 (saddr) ← A A, sfr 2 – 5 A ← sfr sfr, A 2 – 5 sfr ← A A, !addr16 3 8 9 A ← (addr16) !addr16, A 3 8 9 (addr16) ← A PSW, #byte 3 – 7 PSW ← byte A, PSW 2 – 5 A ← PSW PSW, A 2 – 5 PSW ← A A, [DE] 1 4 5 A ← (DE) [DE], A 1 4 5 (DE) ← A A, [HL] 1 4 5 A ← (HL) [HL], A 1 4 5 (HL) ← A A, [HL + byte] 2 8 9 A ← (HL + byte) [HL + byte], A 2 8 9 (HL + byte) ← A A, [HL + B] 1 6 7 A ← (HL + B) [HL + B], A 1 6 7 (HL + B) ← A A, [HL + C] 1 6 7 A ← (HL + C) 1 6 7 (HL + C) ← A 1 2 – A↔r A, r Note 3 Flag Z AC CY saddr, #byte [HL + C], A XCH Clock Note 1 A, saddr 2 4 6 A ↔ (saddr) A, sfr 2 – 6 A ↔ sfr A, !addr16 3 8 10 A ↔ (addr16) A, [DE] 1 4 6 A ↔ (DE) A, [HL] 1 4 6 A ↔ (HL) A, [HL + byte] 2 8 10 A ↔ (HL + byte) A, [HL + B] 2 8 10 A ↔ (HL + B) A, [HL + C] 2 8 10 A ↔ (HL + C) × × × × × × Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except “r = A” Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. User’s Manual U15104EJ2V0UD 229 CHAPTER 18 Instruction Mnemonic Group 16-bit data MOVW transfer Operands Byte Note 2 Operation 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX AX, sfrp 2 – 8 AX ← sfrp 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← rp rp, AX Note 3 1 4 – rp ← AX 3 10 12 AX ← (addr16) !addr16, AX XCHW AX, rp ADD A, #byte Note 3 saddr, #byte Flag Z AC CY 3 AX, !addr16 3 10 12 (addr16) ← AX 1 4 – AX ↔ rp 2 4 – A, CY ← A + byte × × × 3 6 8 (saddr), CY ← (saddr) + byte × × × 2 4 – A, CY ← A + r × × × r, A 2 4 – r, CY ← r + A × × × A, saddr 2 4 5 A, CY ← A + (saddr) × × × A, !addr16 3 8 9 A, CY ← A + (addr16) × × × A, r ADDC Clock Note 1 rp, #word sfrp, AX 8-bit operation INSTRUCTION SET Note 4 A, [HL] 1 4 5 A, CY ← A + (HL) × × × A, [HL + byte] 2 8 9 A, CY ← A + (HL + byte) × × × A, [HL + B] 2 8 9 A, CY ← A + (HL + B) × × × A, [HL + C] 2 8 9 A, CY ← A + (HL + C) × × × A, #byte 2 4 – A, CY ← A + byte + CY × × × saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte + CY × × × 2 4 – A, CY ← A + r + CY × × × 2 4 – r, CY ← r + A + CY × × × A, r Note 4 r, A A, saddr 2 4 5 A, CY ← A + (saddr) + CY × × × A, !addr16 3 8 9 A, CY ← A + (addr16) + CY × × × A, [HL] 1 4 5 A, CY ← A + (HL) + CY × × × A, [HL + byte] 2 8 9 A, CY ← A + (HL + byte) + CY × × × A, [HL + B] 2 8 9 A, CY ← A + (HL + B) + CY × × × A, [HL + C] 2 8 9 A, CY ← A + (HL + C) + CY × × × Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except “r = A” Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 230 User’s Manual U15104EJ2V0UD CHAPTER 18 Instruction Mnemonic Group 8-bit operation SUB Operands Byte A, #byte saddr, #byte Operation Flag Note 2 2 4 – A, CY ← A – byte × × × 3 6 8 (saddr), CY ← (saddr) – byte × × × Z AC CY 2 4 – A, CY ← A – r × × × 2 4 – r, CY ← r – A × × × A, saddr 2 4 5 A, CY ← A – (saddr) × × × A, !addr16 3 8 9 A, CY ← A – (addr16) × × × Note 3 A, [HL] 1 4 5 A, CY ← A – (HL) × × × A, [HL + byte] 2 8 9 A, CY ← A – (HL + byte) × × × A, [HL + B] 2 8 9 A, CY ← A – (HL + B) × × × A, [HL + C] 2 8 9 A, CY ← A – (HL + C) × × × A, #byte 2 4 – A, CY ← A – byte – CY × × × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte – CY × × × 2 4 – A, CY ← A – r – CY × × × 2 4 – r, CY ← r – A – CY × × × A, r Note 3 r, A AND Clock Note 1 r, A A, r SUBC INSTRUCTION SET A, saddr 2 4 5 A, CY ← A – (saddr) – CY × × × A, !addr16 3 8 9 A, CY ← A – (addr16) – CY × × × A, [HL] 1 4 5 A, CY ← A – (HL) – CY × × × A, [HL + byte] 2 8 9 A, CY ← A – (HL + byte) – CY × × × A, [HL + B] 2 8 9 A, CY ← A – (HL + B) – CY × × × A, [HL + C] 2 8 9 A, CY ← A – (HL + C) – CY × × × A, #byte 2 4 – A←A × 3 6 8 (saddr) ← (saddr) saddr, #byte byte byte × 2 4 – A←A r, A 2 4 – r←r A, saddr 2 4 5 A←A (saddr) × A, !addr16 3 8 9 A←A (addr16) × A, [HL] 1 4 5 A←A [HL] × A, [HL + byte] 2 8 9 A←A [HL + byte] × A, [HL + B] 2 8 9 A←A [HL + B] × A, [HL + C] 2 8 9 A←A [HL + C] × A, r Note 3 r × × A Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except “r = A” Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. User’s Manual U15104EJ2V0UD 231 CHAPTER 18 Instruction Mnemonic Group 8-bit operation OR Operands Byte A, #byte saddr, #byte Operation Flag Note 2 2 4 – A ← A byte × 3 6 8 (saddr) ← (saddr) byte × Z AC CY 2 4 – A←A r × 2 4 – r←r A × A, saddr 2 4 5 A ← A (saddr) × A, !addr16 3 8 9 A ← A (addr16) × A, [HL] 1 4 5 A ← A (HL) × A, [HL + byte] 2 8 9 A ← A (HL + byte) × A, [HL + B] 2 8 9 A ← A (HL + B) × A, [HL + C] 2 8 9 A ← A (HL + C) × Note 3 A, #byte 2 4 – A←A saddr, #byte 3 6 8 (saddr) ← (saddr) 2 4 – A←A r, A 2 4 – r←r A, saddr 2 4 5 A←A (saddr) × A, !addr16 3 8 9 A←A (addr16) × A, [HL] 1 4 5 A←A (HL) × A, [HL + byte] 2 8 9 A←A (HL + byte) × A, [HL + B] 2 8 9 A←A (HL + B) × A, [HL + C] 2 8 9 A←A (HL + C) × A, #byte 2 4 – A – byte × × × 3 6 8 (saddr) – byte × × × A, r CMP Clock Note 1 r, A A, r XOR INSTRUCTION SET Note 3 saddr, #byte × byte byte r × × × A 2 4 – A–r × × × r, A 2 4 – r–A × × × A, saddr 2 4 5 A – (saddr) × × × A, !addr16 3 8 9 A – (addr16) × × × A, r Note 3 A, [HL] 1 4 5 A – (HL) × × × A, [HL + byte] 2 8 9 A – (HL + byte) × × × A, [HL + B] 2 8 9 A – (HL + B) × × × A, [HL + C] 2 8 9 A – (HL + C) × × × Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except “r = A” Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 232 User’s Manual U15104EJ2V0UD CHAPTER 18 Instruction Mnemonic Group 16-bit operation Multiply/ divide Clock Note 1 Note 2 Operation Flag Z AC CY AX, #word 3 6 – AX, CY ← AX + word × × × SUBW AX, #word 3 6 – AX, CY ← AX – word × × × × × × CMPW AX, #word 3 6 – AX – word MULU X 2 16 – AX ← A × X DIVUW C 2 25 – AX (Quotient), C (Remainder) ← AX ÷ C r 1 2 – r←r+1 × × saddr 2 4 6 (saddr) ← (saddr) + 1 × × r 1 2 – r←r–1 × × saddr 2 4 6 (saddr) ← (saddr) – 1 × × rp 1 4 – rp ← rp + 1 DEC INCW BCD adjust Byte ADDW Increment/ INC decrement Rotate Operands INSTRUCTION SET DECW rp 1 4 – rp ← rp – 1 ROR A, 1 1 2 – (CY, A7 ← A0, Am–1 ← Am) × 1 time × ROL A, 1 1 2 – (CY, A0 ← A7, Am+1 ← Am) × 1 time × RORC A, 1 1 2 – (CY ← A0, A7 ← CY, Am–1 ← Am) × 1 time × × ROLC A, 1 1 2 – (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 time ROR4 [HL] 2 10 12 A3-0 ← (HL)3-0, (HL)7-4 ← A3-0, (HL)3-0 ← (HL)7-4 ROL4 [HL] 2 10 12 A3-0 ← (HL)7-4, (HL)3-0 ← A3-0, (HL)7-4 ← (HL)3-0 ADJBA 2 4 – Decimal Adjust Accumulator after Addition × × × ADJBS 2 4 – Decimal Adjust Accumulator after Subtract × × × CY, saddr.bit 3 6 7 CY ← (saddr.bit) × CY, sfr.bit 3 – 7 CY ← sfr.bit × CY, A.bit 2 4 – CY ← A.bit × CY, PSW.bit 3 – 7 CY ← PSW.bit × CY, [HL].bit 2 6 7 CY ← (HL).bit × saddr.bit, CY 3 6 8 (saddr.bit) ← CY sfr.bit, CY 3 – 8 sfr.bit ← CY Bit MOV1 manipulate A.bit, CY 2 4 – A.bit ← CY PSW.bit, CY 3 – 8 PSW.bit ← CY [HL].bit, CY 2 6 8 (HL).bit ← CY × × Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. User’s Manual U15104EJ2V0UD 233 CHAPTER 18 Instruction Mnemonic Group Bit AND1 manipulate OR1 XOR1 SET1 Operands Byte INSTRUCTION SET Clock Note 1 Note 2 Operation Flag Z AC CY CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × CY, A.bit 2 4 – CY ← CY A.bit × CY, PSW.bit 3 – 7 CY ← CY PSW.bit × CY, [HL].bit 2 6 7 CY ← CY (HL).bit × CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × CY, A.bit 2 4 – CY ← CY A.bit × CY, PSW.bit 3 – 7 CY ← CY PSW.bit × CY, [HL].bit 2 6 7 CY ← CY (HL).bit × CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × CY, A.bit 2 4 – CY ← CY A.bit × CY, PSW. bit 3 – 7 CY ← CY PSW.bit × (HL).bit × CY, [HL].bit 2 6 7 CY ← CY saddr.bit 2 4 6 (saddr.bit) ← 1 sfr.bit 3 – 8 sfr.bit ← 1 A.bit 2 4 – A.bit ← 1 PSW.bit 2 – 6 PSW.bit ← 1 [HL].bit 2 6 8 (HL).bit ← 1 saddr.bit 2 4 6 (saddr.bit) ← 0 sfr.bit 3 – 8 sfr.bit ← 0 A.bit 2 4 – A.bit ← 0 PSW.bit 2 – 6 PSW.bit ← 0 [HL].bit 2 6 8 (HL).bit ← 0 SET1 CY 1 2 – CY ← 1 1 CLR1 CY 1 2 – CY ← 0 0 NOT1 CY 1 2 – CY ← CY × CLR1 × × × × × × Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 234 User’s Manual U15104EJ2V0UD CHAPTER 18 Instruction Mnemonic Group Call/return Byte Clock Note 1 Note 2 Operation Flag Z AC CY CALL !addr16 3 7 – (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L, PC ← addr16, SP ← SP – 2 CALLF !addr11 2 5 – (SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L, PC15-11 ← 00001, PC10-0 ← addr11, SP ← SP – 2 CALLT [addr5] 1 6 – (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP – 2 BRK 1 6 – (SP – 1) ← PSW, (SP – 2) ← (PC + 1)H, (SP – 3) ← (PC + 1)L, PCH ← (003FH), PCL ← (003EH), SP ← SP – 3, IE ← 0 RET 1 6 – PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 6 – PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 R R R RETB 1 6 – PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3 R R R PSW 1 2 – (SP – 1) ← PSW, SP ← SP – 1 rp 1 4 – (SP – 1) ← rpH, (SP – 2) ← rpL, SP ← SP – 2 R R R Stack PUSH manipulate POP MOVW Unconditional branch Operands INSTRUCTION SET BR PSW 1 2 – PSW ← (SP), SP ← SP + 1 rp 1 4 – rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2 SP, #word 4 – 10 SP ← word SP, AX 2 – 8 SP ← AX AX, SP 2 – 8 AX ← SP !addr16 3 6 – PC ← addr16 $addr16 2 6 – PC ← PC + 2 + jdisp8 AX 2 8 – PCH ← A, PCL ← X $addr16 2 6 – PC ← PC + 2 + jdisp8 if CY = 1 $addr16 2 6 – PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 – PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 – PC ← PC + 2 + jdisp8 if Z = 0 Conditional BC branch BNC Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. User’s Manual U15104EJ2V0UD 235 CHAPTER 18 Instruction Mnemonic Group Conditional BT branch BF BTCLR DBNZ CPU control Operands Byte INSTRUCTION SET Clock Note 1 Note 2 Operation saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 – 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC ← PC + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if PSW. bit = 0 [HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 0 saddr.bit, $addr16 4 10 12 PC ← PC + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 – 12 PC ← PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PSW.bit, $addr16 4 – 12 PC ← PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit [HL].bit, $addr16 3 10 12 PC ← PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit B, $addr16 2 6 – B ← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 – C ← C –1, then PC ← PC + 2 + jdisp8 if C ≠ 0 saddr. $addr16 3 8 10 (saddr) ← (saddr) – 1, then PC ← PC + 3 + jdisp8 if(saddr) ≠ 0 RBn 2 4 – RBS1, 0 ← n NOP 1 2 – No Operation EI 2 – 6 IE ← 1(Enable Interrupt) DI 2 – 6 IE ← 0(Disable Interrupt) HALT 2 6 – Set HALT Mode STOP 2 6 – Set STOP Mode SEL Flag Z AC CY × × Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the PCC register. 2. This clock cycle applies to internal ROM program. 236 User’s Manual U15104EJ2V0UD × CHAPTER 18 INSTRUCTION SET 18.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd Operand #byte A rNote sfr saddr !addr16 PSW MOV MOV XCH XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP [DE] [HL] 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP sfr MOV MOV saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP [HL + byte] $addr16 [HL + B] [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1 None ROR ROL RORC ROLC INC DEC B, C DBNZ !addr16 DBNZ INC DEC MOV PSW MOV MOV [DE] MOV [HL] MOV [HL + byte] [HL + B] [HL + C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note Except r = A User’s Manual U15104EJ2V0UD 237 CHAPTER 18 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rpNote sfrp saddrp !addr16 SP None 1st Operand AX ADDW SUBW CMPW rp MOVW MOVWNote sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW XCHW MOVW MOVW MOVW MOVW INCW DECW PUSH POP MOVW SP MOVW Note MOVW Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None 1st Operand A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY 238 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 User’s Manual U15104EJ2V0UD SET1 CLR1 NOT1 CHAPTER 18 INSTRUCTION SET (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand AX !addr16 !addr11 [addr5] $addr16 1st Operand Basic instruction BR CALL BR CALLF CALLT Compound instruction BR BC BNC BZ BNZ BT BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U15104EJ2V0UD 239 CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Conditions VDD VDDPORT VDDPLL VPP Input voltage VI Output voltage VO Ratings Unit –0.3 to +6.0 V –0.3 to VDD + 0.3 Note 1 V –0.3 to VDD + 0.3 Note 1 V µPD178F054 only Excluding P130 to P132 –0.3 to +10.5 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V Output withstand voltage VBDS P130 to P132 N-ch open drain 16 V Analog input voltage VAN P10 to P15 Analog input pin –0.3 to VDD + 0.3 V Output current, high I OH Per pin –8 mA Total of P00 to P06, P30 to P37, P54 to P57, P60 to P67, and P120 to P125 –15 mA Total of P40 to P47, P50 to P53, and P70 to P77 –15 mA 16 mA 8 mA Output current, low I OLNote 2 Per pin Peak value rms value Total of P00 to P06, P30 to P37, Peak value 30 mA P40 to P47, P50 to P57, P60 to P67, rms value 15 mA –40 to +85 °C P70 to P77, P120 to P125, and P130 to P132 Operating temperature TA In normal operation mode During flash memory programming ( µPD178F054 only) Storage temperature 10 to 40 Tstg °C –55 to +125 Notes 1. Keep the voltage at VDDPORT and VDDPLL same as that at the VDD pin. 2. The rms value should be calculated as follows: [rms value] = [Peak value] x √Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Recommended Supply Voltage Ranges (TA = –40 to +85°C) Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit VDD1 When CPU and PLL are operating 4.5 5.0 5.5 V VDD2 When CPU is operating and PLL is stopped 3.5 5.0 5.5 V Data retention voltage VDDR When crystal oscillation stops 2.3 5.5 V Output withstand voltage VBDS P130 to P132 (N-ch open drain) 15 V 240 User’s Manual U15104EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) (1/2) Parameter Symbol Conditions MIN. Input voltage, high VIH1 P10 to P15, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P73, P75, P121, P124 VIH2 P00 to P06, P33, P34, P70, P72, P74, P76, P77, P120, P122, P123, P125, RESET VIL1 Input voltage, low Output voltage, high Output voltage, low Input leakage current, high Remark MAX. Unit 0.7 VDD VDD V 0.8 VDD VDD V P10 to P15, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P73, P75, P121, P124 0 0.3 VDD V VIL2 P00 to P06, P33, P34, P70, P72, P74, P76, P77, P120, P122, P123, P125, RESET 0 0.2 VDD V VOH1 P00 to P06, P30 to P37, P40 to P47, P50 to P57, 4.5 V ≤ VDD ≤ 5.5 V, I OH = –1 mA VDD – 1.0 V P60 to P67, P70 to P77, P120 to P125 3.5 V ≤ VDD < 4.5 V, I OH = –100 µ A VDD – 0.5 V VOH2 EO0, EO1 4.5 V ≤ VDD ≤ 5.5 V, I OH = –3 mA VDD – 1.0 V VOL1 P00 to P06, P30 to P37, P40 to P47, P50 to P57, 4.5 V ≤ VDD ≤ 5.5 V, I OL = 1 mA 1.0 V P60 to P67, P70 to P77, P120 to P125, P130 to P132 3.5 V ≤ VDD < 4.5 V, I OL = 100 µ A 0.5 V VOL2 EO0, EO1 VDD = 4.5 to 5.5 V, I OL = 3 mA 1.0 V ILIH1 P00 to P06, P30 to P37, P50 to P57, P70 to P77, RESET 3 µA P10 to P15, P40 to P47, P60 to P67, P120 to P125, VIN = VDD TYP. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User’s Manual U15104EJ2V0UD 241 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) (2/2) Parameter Symbol Conditions TYP. MAX. Unit VIN = 0 V –3 µA Input leakage current, low I LIL1 P00 to P06, P30 to P37, P50 to P57, P70 to P77, RESET Output off ILOH1 P130 to P132 VOUT = 15 V –3 µA leakage current ILOL1 P130 to P132 VOUT = 0 V 3 µA ILOH2 EO0, EO1 VOUT = VDD –3 µA ILOL2 EO0, EO1 VOUT = 0 V 3 µA I DD1 When CPU is operating and PLL is stopped. Sine wave input to X1 pin At fX = 4.5 MHz VIN = VDD µPD178053, µPD178054 2.5 15 mA µPD178F054 5.0 18 mA In HALT mode with PLL stopped. Sine wave input to X1 pin At fX = 4.5 MHz VIN = VDD µPD178053, µPD178054 0.2 0.8 mA µPD178F054 0.3 0.8 mA 5.5 V Supply current Note I DD2 P10 to P15, P40 to P47, P60 to P67, P120 to P125, MIN. Data retention VDDR1 When crystal resonator is oscillating 3.5 voltage VDDR2 When crystal oscillation is stopped Power-failure detection function 2.2 V Data memory retained 2.0 V VDDR3 Data retention current I DDR1 When crystal oscillation is stopped I DDR2 Note TA = 25°C, VDD = 5 V 2.0 4.0 µA TA = –40 to +85°C, VDD = 3.5 to 5.5 V 2.0 20 µA Excluding AVDD current and VDDPLL current. Remarks 1. fX : System clock oscillation frequency 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 242 User’s Manual U15104EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS Reference Characteristics (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V) Parameter Supply current Symbol I DD3 Conditions MIN. When CPU and PLL are operating. Sine wave input to VCOH pin At fIN = 160 MHz VIN = 0.15 VP-P TYP. MAX. 5 Unit mA AC Characteristics (1) Basic operation (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) Parameter Symbol Cycle time (minimum instruction execution time) TCY TI50, TI51 input frequency f TI5 TI50, TI51 input high-/low-level widths t TIH5 t TIL5 Interrupt input high-/low-level widths t INTH t INTL RESET pin low-level width tRSL Conditions f X = 4.5 MHz MIN. 0.44 INTP0 to INTP4 User’s Manual U15104EJ2V0UD TYP. MAX. Unit 7.11 µs 2 MHz 200 ns 1 µs 10 µs 243 CHAPTER 19 ELECTRICAL SPECIFICATIONS (2) Serial interface SIO3 (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) (a) 3-wire serial I/O mode (SCK3 ... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK3 cycle time t KCY1 800 ns SCK3 high/low-level width t KH1, tKL1 tKCY1/2 – 50 ns SI3 setup time to SCK3↑ tSIK1 100 ns SI3 hold time from SCK3↑ tKSI1 400 ns Output delay time from SCK3↓ to SO3 Note t KSO1 C = 100 pF Note 300 ns MAX. Unit C is the load capacitance of SCK3 and SO3 output line. (b) 3-wire serial I/O mode (SCK3 ... external clock input) Parameter Symbol Conditions MIN. TYP. SCK3 cycle time t KCY2 800 ns SCK3 high/low-level width t KH2, tKL2 400 ns SI3 setup time to SCK3↑ tSIK2 100 ns SI3 hold time from SCK3↑ tKSI2 400 ns Output delay time from SCK3↓ to SO3 t KSO2 SCK3 at rising or falling edge time t R2, tF2 Note 244 C = 100 pF Note C is the load capacitance of SO3 output line. User’s Manual U15104EJ2V0UD 300 ns 1000 ns CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Timing Test Point (Excluding X1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test points TI Timing 1/fTI5 tTIL5 tTIH5 TI50, TI51, TI52 Interrupt Input Timing tINTL tINTH INTP0 to INTP4 RESET Input Timing tRSL RESET User’s Manual U15104EJ2V0UD 245 CHAPTER 19 ELECTRICAL SPECIFICATIONS Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm tFn tRn SCK3 tSIKm SI3 tKSIm Input data tKSOm SO3 Remark Output data m = 1, 2 n=2 246 User’s Manual U15104EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions Resolution Total conversion MIN. TYP. MAX. Unit 8 8 8 bit ±1.0 %FSR ±1.4 %FSR VDD = 4.5 to 5.5 V errorNotes 1, 2 Conversion time t CONV 21.3 64.0 µs Analog input voltage VIAN 0 VDD V MAX. Unit Notes 1. Excluding quantization error (±0.2%FSR) 2. This value is indicated as a ratio to the full-scale value (%FSR). PLL Characteristics (T A = –40 to +85°C, V DD = 4.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. Operating frequency fIN1 VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P 0.5 3.0 MHz fIN2 VCOL pin, HF mode, sine wave input, V IN = 0.15 VP-P 10 40 MHz fIN3 VCOH pin, VHF mode, sine wave input, V IN = 0.15 V P-P 60 130 MHz fIN4 VCOH pin, VHF mode, sine wave input, V IN = 0.3 V P-P 40 160 MHz MAX. Unit IFC Characteristics (T A = –40 to +85°C, V DD = 4.5 to 5.5 V) Parameter Symbol Conditions Operating frequency fIN5 AMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P 0.4 0.5 MHz fIN6 FMIFC pin, FMIF count mode, sine wave input, VIN = 0.15 VP-P 10 11 MHz fIN7 FMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P 0.4 0.5 MHz User’s Manual U15104EJ2V0UD MIN. TYP. 247 CHAPTER 19 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics (V DD = 3.5 to 5.5 V, TA = 10 to 40°C) (µ PD178F054 only) (1) Write/delete characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current (VDD pin)Note IDDW When VPP = V PP1, f X = 4.5 MHz 20 mA Note I PPW When VPP = V PP1, f X = 4.5 MHz 20 mA Delete current (VDD pin)Note I DDE When VPP = V PP1, f X = 4.5 MHz 20 mA Delete current (VPP pin)Note I PPE When VPP = V PP1 100 mA Unit delete time tER 1 s Total delete time t ERA 20 s 20 times 0.2 VDD V 10.0 10.3 V TYP. MAX. Unit Write current (VPP pin) Number of overwrite VPP power supply voltage Note 0.5 1 Delete and write are counted as one cycle VPP0 In normal mode 0 VPP1 During flash memory programming 9.7 Port current (including current flowing to internal pull-up resistors) is not included. Remark fX: System clock oscillation frequency (2) Serial write operation characteristics Parameter Symbol Conditions MIN. VPP setup time tPSRON VPP high voltage 1.0 µs VPP↑ setup time from V DD↑ t DRPSR VPP high voltage 1.0 µs RESET↑ setup time from V PP↑ t PSRRF VPP high voltage 1.0 µs V PP count start time from RESET↑ t RFCF 1.0 µs Count execution time tCOUNT 2.0 ms VPP counter high-level width t CH 8.0 µs VPP counter low-level width t CL 8.0 µs VPP counter noise elimination width 248 t NFW 40 User’s Manual U15104EJ2V0UD ns CHAPTER 19 ELECTRICAL SPECIFICATIONS Flash Write Mode Setting Timing VDD VDD 0V tDRPSR tRFCF tCH VPPH VPP VPP tCL VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V User’s Manual U15104EJ2V0UD 249 CHAPTER 20 PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G H I M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.20±0.20 B 14.00±0.20 C 14.00±0.20 D 17.20±0.20 F 0.825 G 0.825 H I 0.32±0.06 0.13 J 0.65 (T.P.) K 1.60±0.20 L 0.80±0.20 M 0.17 +0.03 −0.07 N P Q R S 0.10 1.40±0.10 0.125±0.075 3° +7° −3° 1.70 MAX. P80GC-65-8BT-1 250 User’s Manual U15104EJ2V0UD CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS The µ PD178053, 178054, and 178F054 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 21-1. Surface Mounting Type Soldering Conditions µ PD178053GC-×××-8BT: 80-pin plastic QFP (14 × 14) µ PD178054GC-×××-8BT: 80-pin plastic QFP (14 × 14) µ PD178F054GC-8BT: Soldering Method 80-pin plastic QFP (14 × 14) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Twice or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Twice or less VP15-00-2 Wave soldering Soldering bath temperature: 260°C or less, Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C or less, Time: 3 seconds max. (per pin row) Caution – Do not use different soldering methods together (except for partial heating). User’s Manual U15104EJ2V0UD 251 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µPD178054 Subseries. Figure A-1 shows the configuration example of the tools. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT TM compatibles can be used for PC98-NX series computers. When using PC98-NX series computers, refer to the description for IBM PC/AT compatibles. • Windows Unless otherwise specified, “Windows” means the following OSs. • Windows 3.1 • Windows 95 • Windows 98 • Windows 2000 • Windows NTTM Ver. 4.0 252 User’s Manual U15104EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Configuration of Development Tools (1/2) (1) When using the in-circuit emulator IE-78K0-NS Software Package • Software package Debugging Software Language Processing Software • Assembler package • Integrated debugger • C compiler package • System simulator • Device file • C compiler source fileNote 1 Control Software • Project manager (Windows only)Note 2 Embedded Software • Real-time OS • OS Host Machine (PC or EWS) Interface adapter, PC card interface, etc. Power supply unit Flash Memory Write Environment In-Circuit Emulator Emulation board Flash programmer Flash memory write adapter I/O board Performance board Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. The C compiler source file is not included in the software package. 2. The project manager is included in the assembler package. The project manager is only used for Windows. User’s Manual U15104EJ2V0UD 253 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Configuration of Development Tools (2/2) (2) When using the in-circuit emulator IE-78001-R-A Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator • Integrated debugger • Device file Embedded Software • Real-time OS • OS Host Machine (PC or EWS) Interface board Flash Memory Write Environment In-Circuit Emulator Interface adapter Flash programmer Emulation board I/O board Flash memory write adapter Probe board Emulation probe conversion board On-chip flash memory version Emulation probe Conversion socket or conversion adapter Target system Remark Items in broken line boxes differ according to the development environment. Refer to A.5 Debugging Tools (Hardware). 254 User’s Manual U15104EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Software package This package contains various software tools for 78K/0 Series development. The following tools are included. RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files Part Number: µ S××××SP78K0 Remark ×××× in the part number differs depending on the OS used. µS××××SP78K0 ×××× Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software RA78K0 Assembler package This assembler converts programs written in mnemonics into an object codes executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optical device file (DF178054). <Precaution when using RA78K0 in PC environment> This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part Number: µS××××RA78K0 CC78K0 C compiler package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler should be used in combination with an optical assembler package and device file. <Precaution when using CC78K0 in PC environment> This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part Number: µ S××××CC78K0 DF178054 Note 1 Device file This file contains information peculiar to the device. This device file should be used in combination with an optical tool (RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0). Corresponding OS and host machine differ depending on the tool used. Part Number: µS××××DF178054 CC78K0-LNote 2 C library source file This is a source file of functions configuring the object library included in the C compiler package. This file is required to match the object library included in C compiler package to the user’s specifications. It does not depend on the operating environment because it is a source file. Part Number: µS××××CC78K0-L Notes 1. The DF178054 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0. 2. CC78K0-L is not included in the software package (SP78K0). User’s Manual U15104EJ2V0UD 255 APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µS××××RA78K0 µS××××CC78K0 ×××× Host Machine OS AB13 PC-9800 series, Windows (Japanese version) BB13 IBM PC/AT compatibles Windows (English version) AB17 Windows (Japanese version) BB17 Supply Medium 3.5-inch 2HD FD CD-ROM Windows (English version) 700TM 3P17 HP9000 series 3K17 SPARCstationTM HP-UXTM (Rel. 10.10) SunOS TM (Rel. 4.1.1), SolarisTM (Rel. 2.5.1) µS××××DF178054 µS××××CC78K0-L ×××× Host Machine OS Supply Medium AB13 PC-9800 series, Windows (Japanese version) BB13 IBM PC/AT compatibles Windows (English version) 3P16 HP9000 series 700 HP-UX (Rel. 10.10) DAT 3K13 SPARCstation SunOS (Rel. 4.1.1), 3.5-inch 2HD FD Solaris (Rel. 2.5.1) 1/4-inch CGMT 3K15 3.5-inch 2HD FD A.3 Control Software Project manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. <Caution> The project manager is included in the assembler package (RA78K0). It can only be used in Windows. A.4 Flash Memory Writing Tools Flashpro III (Part number: FL-PR3, PG-FP3) Flash programmer Flash programmer dedicated to microcontrollers with on-chip flash memory. FA-80GC Flash memory writing adapter Flash memory writing adapter used connected to the Flashpro III. • FA-80GC: 80-pin plastic QFP (GC-8BT type) Flashpro III controller Control program that runs on a PC. This is supplied with Flashpro III. Remark Flashpro III and FA-80GC are products of Naito Densei Machida Mfg. Co., Ltd. Contact: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 256 User’s Manual U15104EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) (1/2) (1) When using the in-circuit emulator IE-78K0-NS IE-78K0-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0-NS). This emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. IE-78K0-NS-PA Performance board This board is used for extending the IE-78K0-NS functions, and is used connected to the IE-78K0-NS. With the addition of this board, the addition of a coverage function, enhancement of tracer and timer functions, and other such debugging function enhancements are possible. IE-78K0-NS-A In-circuit emulator In-circuit emulator that combines IE-78K0-NS and IE-78K0-NS-PA IE-70000-MC-PS-B Power supply unit This adapter is used for supplying power from a receptacle of 100 to 240 V AC. IE-70000-98-IF-C Interface adapter This adapter is required when using the PC-9800 series computer (except notebook type) as the IE-78K0-NS host machine (C bus compatible). IE-70000-CD-IF-A PC card interface This is PC card and interface cable required when using the notebook-type computer as the IE-78K0-NS host machine (PCMCIA socket compatible). IE-70000-PC-IF-C Interface adapter This adapter is required when using the IBM PC compatible computers as the IE-78K0NS host machine (ISA bus compatible). IE-70000-PCI-IF-A Interface adapter This adapter is required when using a PC with a PCI bus as the IE-78K0-NS host machine. IE-178054-NS-EM1 Emulation board This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. NP-80GC Emulation probe This probe is used to connect the in-circuit emulator to the target system and is designed for 80-pin plastic QFP (GC-8BT type). EV-9200GC-80 Conversion socket (Refer to Figures A-2, A-3) This conversion socket connects the NP-80GC to the target system board designed to mount an 80-pin plastic QFP (GC-8BT type). Remarks 1. NP-80GC is a product of Naito Densei Machida Mfg. Co., Ltd. Contact: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. EV-9200GC-80 is sold in five-unit sets. User’s Manual U15104EJ2V0UD 257 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) (2/2) (2) When using the in-circuit emulator IE-78001-R-A IE-78001-R-A In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0). This emulator should be used in combination with emulation probe and interface adapter, which is required to connect this emulator to the host machine. IE-70000-98-IF-C Interface adapter This adapter is required when using the PC-9800 series computer (except notebook type) as the IE-78001-R-A host machine (C bus compatible). IE-70000-PC-IF-C Interface adapter This adapter is required when using the IBM PC/AT compatible computers as the IE78001-R-A host machine (ISA bus compatible). IE-70000-PCI-IF-A Interface adapter This adapter is required when using a PC with a PCI bus as the IE-78001-R-A host machine. IE-78000-R-SV3 Interface adapter This is adapter and cable required when using an EWS computer as the IE-78001-RA host machine, and is used connected to the board in the IE-78000-R-A. As EthernetTM, 10Base-5 is supported. With the other method, a commercially available conversion adapter is necessary. IE-178054-NS-EM1 Emulation board This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator and emulation conversion board. IE-78K0-R-EX1 Emulation probe conversion board This board is required when using the IE-178054-NS-EM1 on the IE-78001-R-A. This probe is used to connect the in-circuit emulator to the target system and is designed for 80-pin plastic QFP (GC-8BT type). EP-78230GC-R Emulation probe EV-9200GC-80 Conversion socket (Refer to Figures A-2, A-3) This conversion socket connects the EP-78230GC-R to the target system board designed to mount an 80-pin plastic QFP (GC-8BT type). Remark EV-9200GC-80 is sold in five-unit sets. 258 User’s Manual U15104EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 System simulator This is a system simulator for the 78K/0S Series. The SM78K0 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with the device file (DF178054) (sold separately). Part Number: µ S××××SM78K0 ID78K0-NS Integrated debugger (supporting in-circuit emulators IE-78K0-NS and IE-78K0-NS-A) ID78K0 Integrated debugger (supporting in-circuit emulator IE-78001-R-A) This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS and ID78K0 are Windows-based software. ID78K0: Supports in-circuit emulator IE-78001-R-A. ID78K0-NS: Supports in-circuit emulators IE-78K0-NS and IE-78K0-NS-A. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately). Part Number: µS××××ID78K0-NS, µS××××ID78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µS××××SM78K0 µS××××ID78K0-NS µS××××ID78K0 ×××× AB13 Host Machine IBM PC/AT compatibles OS Windows (Japanese version) BB13 Windows (English version) AB17 Windows (Japanese version) BB17 Windows (English version) User’s Manual U15104EJ2V0UD Supply Medium 3.5-inch 2HD FD CD-ROM 259 APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software RX78K0 is a real-time OS conforming to the µ ITRON specifications. Tool (configurator) for generating nucleus of RX78K0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K0) and device file (DF178054). <Precaution when using RX78K0 in PC environment> The real-time OS is a DOS-based application. It should be used in the DOS Prompt when using in Windows. RX78K0 Real-time OS Part number: µS××××RX78013-∆∆∆∆ Caution When purchasing the RX78K0, fill in the purchase application form in advance and sign the user agreement. Remark ×××× and ∆∆∆∆ in the part number differ depending on the host machine and OS used. µ S××××RX78013-∆∆∆∆ ∆∆∆∆ Evaluation object Do not use for mass-produced product. 100K Mass-production object 0.1 million units 001M 1 million units 010M 10 million units Source program Source program for mass-produced object Host Machine OS AA13 PC-9800 series Windows (Japanese version) AB13 IBM PC/AT compatibles Windows (Japanese version) BB13 260 Maximum Number for Use in Mass Production 001 S01 ×××× Product Outline Windows (English version) User’s Manual U15104EJ2V0UD Supply Medium 3.5-inch 2HD FD APPENDIX A DEVELOPMENT TOOLS A.8 System Upgrade from Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A If you already have a former in-circuit emulator for 78K/0 Series microcontrollers (IE-78000-R or IE-78000-R-A), that in-circuit emulator can operate as an equivalent to the IE-78001-R-A by replacing its internal break board with the IE-78001-R-BK. Table A-1. System Upgrade Method from Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A In-circuit Emulator Owned In-circuit Emulator Cabinet System Upgrade Note IE-78000-R Required IE-78000-R-A Not required Board to Be Purchased IE-78001-R-BK Note For upgrading a cabinet, send user’s in-circuit emulator to NEC. User’s Manual U15104EJ2V0UD 261 APPENDIX A DEVELOPMENT TOOLS Drawing for Conversion Socket (EV-9200GC-80) Package and Recommended Board Mounting Pattern Figure A-2. EV-9200GC-80 Package Drawing (for Reference Only) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G1E ITEM 262 MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.7 0.736 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S φ 1.5 φ 0.059 User’s Manual U15104EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200GC-80 Recommended Board Mounting Pattern (for Reference Only) G J H D E F K I L C B A EV-9200GC-80-P1E ITEM MILLIMETERS A 19.7 B 15.0 INCHES 0.776 0.591 C 0.65±0.02 × 19=12.35±0.05 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 × 0.748=0.486 –0.002 0.026+0.001 –0.002 × 0.748=0.486 +0.003 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.003 –0.002 H 6.0 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). User’s Manual U15104EJ2V0UD 263 APPENDIX B REGISTER INDEX B.1 Register Index 8-bit compare register 50 (CR50) ... 100 8-bit compare register 51 (CR51) ... 100 8-bit compare register 52 (CR52) ... 100 8-bit compare register 53 (CR53) ... 100 8-bit timer counter 50 (TM50) ... 99 8-bit timer counter 51 (TM51) ... 99 8-bit timer counter 52 (TM52) ... 99 8-bit timer counter 53 (TM53) ... 99 8-bit timer mode control register 50 (TMC50) ... 102 8-bit timer mode control register 51 (TMC51) ... 102 8-bit timer mode control register 52 (TMC52) ... 102 8-bit timer mode control register 53 (TMC53) ... 104 [A] A/D conversion result register 3 (ADCR3) ... 132, 146 A/D converter mode register 3 (ADM3) ... 133 Analog input channel specification register 3 (ADS3) ... 134 [B] BEEP clock select register 0 (BEEPCL0) ... 128 [C] Clock output select register (CKS) ... 129 [D] DTS system clock select register (DTSCK) ... 88 [E] External interrupt falling edge enable register (EGN) ... 164 External interrupt rising edge enable register (EGP) ... 164 [I] IF counter control register (IFCCR) ... 198 IF counter gate judge register (IFCJG) ... 198 IF counter mode select register (IFCMD) ... 197 IF counter register (IFCR) ... 196 Internal expansion RAM size switching register (IXS) ... 222 Interrupt mask flag register 0H (MK0H) ... 162 Interrupt mask flag register 0L (MK0L) ... 162 Interrupt request flag register 0H (IF0H) ... 161 Interrupt request flag register 0L (IF0L) ... 161 264 User’s Manual U15104EJ2V0UD APPENDIX B REGISTER INDEX [M] Memory size switching register (IMS) ... 221 [O] Oscillation stabilization time select register (OSTS) ... 124, 204 [P] PLL data register (PLLR) ... 190, 191, 192 PLL data register 0 (PLLR0) ... 180 PLL data register H (PLLRH) ... 180 PLL data register L (PLLRL) ... 180 PLL data transfer register (PLLNS) ... 184 PLL mode select register (PLLMD) ... 181 PLL reference mode register (PLLRF) ... 182 PLL unlock F/F judge register (PLLUL) ... 183 POC status register (POCS) ... 218, 219 Port 0 (P0) ... 70 Port 1 (P1) ... 71 Port 3 (P3) ... 72 Port 4 (P4) ... 74 Port 5 (P5) ... 75 Port 6 (P6) ... 76 Port 7 (P7) ... 77 Port 12 (P12) ... 80 Port 13 (P13) ... 82 Port mode register 0 (PM0) ... 83 Port mode register 3 (PM3) ... 83 Port mode register 4 (PM4) ... 83 Port mode register 5 (PM5) ... 83 Port mode register 6 (PM6) ... 83 Port mode register 7 (PM7) ... 83 Port mode register 12 (PM12) ... 83 Power-fail comparison mode register 3 (PFM3) ... 135 Power-fail comparison threshold value register 3 (PFT3) ... 132, 141 Priority specification flag register 0H (PR0H) ... 163 Priority specification flag register 0L (PR0L) ... 163 Processor clock control register (PCC) ... 90 Pull-up resistor option register 4 (PU4) ... 86 [S] Serial I/O shift register 30 (SIO30) ... 149 Serial I/O shift register 31 (SIO31) ... 149 Serial I/O shift register 32 (SIO32) ... 149 Serial operating mode register 30 (CSIM30) ... 150 Serial operating mode register 31 (CSIM31) ... 150 Serial operating mode register 32 (CSIM32) ... 150 Serial port select register 32 (SIO32SEL) ... 151 User’s Manual U15104EJ2V0UD 265 APPENDIX B REGISTER INDEX [T] Timer clock select register 50 (TCL50) ... 101 Timer clock select register 51 (TCL51) ... 101 Timer clock select register 52 (TCL52) ... 101 Timer clock select register 53 (TCL53) ... 102 [W] Watchdog timer clock select register (WDCS) ... 122 Watchdog timer mode register (WDTM) ... 123 266 User’s Manual U15104EJ2V0UD APPENDIX B REGISTER INDEX B.2 Register Index (Symbol) [A] ADCR3: A/D conversion result register 3 ... 132, 146 ADM3: A/D converter mode register 3 ... 133 ADS3: Analog input channel specification register 3 ... 134 [B] BEEPCL0: BEEP clock select register 0 ... 128 [C] CKS: Clock output select register ... 129 CR50: 8-bit compare register 50 ... 100 CR51: 8-bit compare register 51 ... 100 CR52: 8-bit compare register 52 ... 100 CR53: 8-bit compare register 53 ... 100 CSIM30: Serial operating mode register 30 ... 150 CSIM31: Serial operating mode register 31 ... 150 CSIM32: Serial operating mode register 32 ... 150 [D] DTSCK: DTS system clock select register ... 88 [E] EGN: External interrupt falling edge enable register ... 164 EGP: External interrupt rising edge enable register ... 164 [I] IF0H: Interrupt request flag register 0H ... 161 IF0L: Interrupt request flag register 0L ... 161 IFCCR: IF counter control register ... 198 IFCJG: IF counter gate judge register ... 198 IFCMD: IF counter mode select register ... 197 IFCR: IF counter register ... 196 IMS: Memory size switching register ... 221 IXS: Internal expansion RAM size switching register ... 222 [M] MK0H: Interrupt mask flag register 0H ... 162 MK0L: Interrupt mask flag register 0L ... 162 [O] OSTS: Oscillation stabilization time select register ... 124, 204 [P] P0: Port 0 ... 70 P1: Port 1 ... 71 P3: Port 3 ... 72 User’s Manual U15104EJ2V0UD 267 APPENDIX B P4: Port 4 ... 74 P5: Port 5 ... 75 P6: Port 6 ... 76 REGISTER INDEX P7: Port 7 ... 77 P12: Port 12 ... 80 P13: Port 13 ... 82 PCC: Processor clock control register ... 90 PFM3: Power-fail comparison mode register 3 ... 135 PFT3: Power-fail comparison threshold value register 3 ... 132, 141 PLLMD: PLL mode select register ... 181 PLLNS: PLL data transfer register ... 184 PLLR: PLL data register ... 190, 191, 192 PLLR0: PLL data register 0 ... 180 PLLRF: PLL reference mode register ... 182 PLLRH: PLL data register H ... 180 PLLRL: PLL data register L ... 180 PLLUL: PLL unlock F/F judge register ... 183 PM0: Port mode register 0 ... 83 PM3: Port mode register 3 ... 83 PM4: Port mode register 4 ... 83 PM5: Port mode register 5 ... 83 PM6: Port mode register 6 ... 83 PM7: Port mode register 7 ... 83 PM12: Port mode register 12 ... 83 POCS: POC status register ... 218, 219 PR0H: Priority specification flag register 0H ... 163 PR0L: Priority specification flag register 0L ... 163 PU4: Pull-up resistor option register 4 ... 86 [S] SIO30: Serial I/O shift register 30 ... 149 SIO31: Serial I/O shift register 31 ... 149 SIO32: Serial I/O shift register 32 ... 149 SIO32SEL: Serial port select register 32 ... 151 [T] TCL50: Timer clock select register 50 ... 101 TCL51: Timer clock select register 51 ... 101 TCL52: Timer clock select register 52 ... 101 TCL53: Timer clock select register 53 ... 102 TM50: 8-bit timer counter 50 ... 99 TM51: 8-bit timer counter 51 ... 99 TM52: 8-bit timer counter 52 ... 99 TM53: 8-bit timer counter 53 ... 99 TMC50: 8-bit timer mode control register 50 ... 102 TMC51: 8-bit timer mode control register 51 ... 102 TMC52: 8-bit timer mode control register 52 ... 102 TMC53: 8-bit timer mode control register 53 ... 104 268 User’s Manual U15104EJ2V0UD APPENDIX B REGISTER INDEX [W] WDCS: Watchdog timer clock select register ... 122 WDTM: Watchdog timer mode register ... 123 User’s Manual U15104EJ2V0UD 269 APPENDIX C REVISION HISTORY A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the revision was applied. Edition 2nd Description Applied to: Change of µPD178053, 178054, and 178F054 status from under development to development completed Throughout Modification of Related Documents PREFACE Modification of 1.5 Development of 8-Bit DTS Series CHAPTER 1 OUTLINE Modification of bit units for manipulation for OSTS in Table 3-4 Special Function Registers CHAPTER 3 CPU ARCHITECTURE Deletion of pins P10 to P15 from Table 4-3 Port Mode Register and Output Latch CHAPTER 4 Settings When Using Alternate Functions PORT FUNCTIONS Modification of description in (3) Oscillation stabilization time select register (OSTS) in 8.3 Registers Controlling Watchdog Timer CHAPTER 8 WATCHDOG TIMER Addition of electrical specifications CHAPTER 19 ELECTRICAL SPECIFICATIONS Addition of package drawing CHAPTER 20 PACKAGE DRAWING Addition of recommended soldering conditions Modification of Figure A-1 Configuration of Development Tools Addition of A.1 Software Package and A.3 Control Software Addition of Note 2 to A.2 Language Processing Software Addition of description for IE-78K0-NS-A to A.5 Debugging Tools (Hardware) Deletion of MX78K0 from A.7 Embedded Software 270 User’s Manual U15104EJ2V0UD CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS APPENDIX A DEVELOPMENT TOOLS Facsimile Message From: Name Company Tel. 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