ETC UPD780306

User’s Manual
µPD780308, 780308Y SUBSERIES
8-BIT SINGLE-CHIP MICROCONTROLLER
µPD780306
µPD780308
µPD78P0308
µPD780306Y
µPD780308Y
µPD78P0308Y
Document No. U11377EJ2V0UM00 (2nd edition)
Date Published August 1997 N
©
Printed in Japan
1996
[MEMO]
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide
and ultimately degrade the device operation. Steps must be taken to stop generation of
static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Environmental control must be adequate. When it is dry, humidifier should be used. It is
recommended to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static shielding bag or
conductive material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor devices
must not be touched with bare hands. Similar precautions need to be taken for PW boards
with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is
provided to the input pins, it is possible that an internal input level may be generated due
to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or
NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up
or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor,
if it is considered to have a possibility of being an output pin. All handling related to the
unused pins must be judged device by device and related specifications governing the
devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of
MOS does not define the initial operation status of the device. Immediately after the power
source is turned ON, the devices with reset function have not yet been initialized. Hence,
power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is
not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of Xerox Corporation.
NEWS and NEWS-OS are trademarks of Sony Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products
may be prohibited without governmental license. To export or re-export some or all of these products from a country other
than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: µPD78P0308KL-T, 78P0308YKL-T
The customer must judge the need for license:
µPD780306GC-×××-8EU, 780306GF-×××-3BA, 780306YGC-×××-8EU,
µPD780306YGF-×××-3BA, 780308GC-×××-8EU, 780308GF-×××-3BA,
µPD780308YGC-×××-8EU, 780308YGF-×××-3BA, 780306GC(A)-×××-8EU,
µPD780306GF(A)-×××-3BA, 780308GC(A)-×××-8EU, 780308GF(A)-×××-3BA,
µPD78P0308GC-×××-8EU, 78P0308GF-×××-3BA, 78P00308YGF-×××-3BA
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M5 96.5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
Main Revision in This Edition (1/2)
Page
Description
Throughout
Addition of “µ PD780306(A), 780308(A) ... under planning”
Change of package as follows:
• Deletion of 100-pin plastic QFP (GC-7EA type)
• Addition of 100-pin plastic QFP (GC-8EU type)
Change of minimum supply voltage from 1.8 to 2.0 V
PREFACE
Revised document number of related document
p.9
CHAPTER 1 OUTLINE ( µ PD780308 Subseries)
Addition of description on following subseries to 1.6 78K/0 Series Line-up
µ PD78075B, 78075BY, 780018, 780018Y, 780058, 780058Y, 780034, 780034Y, 780024, 780024Y,
78014H, 780964, 780924, 780228, 78044H, 78044F, 78098B, 780973, 78P0914
p.17
CHAPTER 2 OUTLINE ( µ PD780308Y Subseries)
• Addition of connection diagram of 100-pin plastic LQFP (GC-8EU type) to 2.5 Pin Configuration
p.64, 67, 75, Correction of following text in CHAPTER 5 CPU ARCHITECTURE
76, 77, 80,
• 5.1.4 Data memory addressing
85, 86, 87
• 5.2.1 Control registers (a) Interrupt enable flag (IE),
(e) In-service priority flag (ISP)
• 5.3.1 Relative addressing
• 5.3.2 Immediate addressing
• 5.3.3 Table indirect addressing
• 5.4.2 Register addressing
• 5.4.6 Register indirect addressing
• 5.4.7 Based addressing
• 5.4.8 Based indexed addressing
p.118,119
CHAPTER 7 CLOCK GENERATOR
• 7.3 Clock Generator Control Register
Change of Figure 7-3 Processor Clock Control Register Format
Addition of Table 7-2 Relation between CPU Clock and Minimum Instruction Execution Time
p.192, 197
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
• 9.4.1 8-bit timer/event counter mode
Addition of Figure 9-10 Square Wave Output Operation Timing
Correction of text in 9.4.2 16-bit timer/event counter mode
Addition of Figure 9-13 Square Wave Output Operation Timing
p.209
CHAPTER 11 WATCHDOG TIMER
• 11.2 Watchdog Timer Configuration
Change of Figure 11-1 Watchdog Timer Configuration
p.226, 227
CHAPTER 14 A/D CONVERTER
• 14.2 A/D Converter Configuration
Correction of Figure 14-1 A/D Converter Block Diagram
Addition of caution on voltage
p.242, 249,
283
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (µ PD780308 Subseries)
• 15.1 Serial Interface Channel 0 Functions
Addition of caution on operation mode
• 15.3 Serial Interface Channel 0 Control Registers
Addition of caution on operation mode
• 15.4.3 SBI mode operation
Addition of caution on transfer mode
Main Revision in This Edition (2/2)
Page
Description
p.292, 298
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µ PD780308Y Subseries)
• 16.1 Serial Interface Channel 0 Functions
Addition of caution on operation mode
• 16.3 Serial Interface Channel 0 Control Registers
Addition of caution on operation mode
p.372, 373,
380, 381
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
17.4.2 Asynchronous serial interface (UART) mode
Change of Figure 17-11 Receive Error Timing
Correction of note on UART mode
17.4.3 3-wire serial I/O mode
Addition of description on selecting MSB/LSB first
Addition of Figure 17-14 Circuit of Switching in Transfer Bit Order
Addition of 17.4.4 Limitations of UART mode
p.393
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
• 18.4.2 3-wire serial I/O mode
Addition of description on selecting MSB/LSB first
Addition of Figure 18-5 Circuit of Switching in Transfer Bit Order
p.429, 439,
440, 442,
444, 445,
447, 451
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
• 20.3 Interrupt Function Control Registers
Change of Table 20-2 Various Flags Corresponding to Interrupt Request Sources
• 20.4 Interrupt Request Servicing Operations
Correction of Figure 20-11 Non-Maskable Interrupt Acknowledge Timing
Correction of Figure 20-12 Non-Maskable Interrupt Request Acknowledge Operation
Addition of description on flags to Figure 20-13 Interrupt Request Acknowledge Processing
Algorithm
• Correction of text in 20.4.4 Multiple interrupt servicing
Correction of Figure 20-16 Multiple Interrupt Example
• Correction of text in 20.4.5 Interrupt reserve
• 20.5 Test Functions
Correction of text in 20.5.2 Test input signal acknowledge operation
p.494, 496,
499, 502
APPENDIX A DEVELOPMENT TOOLS
• A.1 Language Processing Software
Change of part number of device file from “DF780308” to “DF78064”
• A.3 Debugging Tools
A.3.1 Hardware
Change of conversion adapter name from “EV-9500GC-100” to “TGC-100SDW”
Deletion of 5-inch supply media supporting Windows from A.3.2 Software
p.515
Addition of APPENDIX D Revision History
The mark
shows major revised points.
PREFACE
Readers
This manual has been prepared for user engineers who understand the functions of
the µPD780308 and 780308Y Subseries and design and develop its application
systems and programs.
•
µPD780308 Subseries : µPD780306, 780308, 78P0308, 780306(A), 780308(A)
•
µPD780308Y Subseries : µPD780306Y, 780308Y, 78P0308Y
Of the µPD780308 and 780308Y Subseries, the µPD78P0308KL-T and
Caution
78P0308YKL-T do not have a reliability level intended to be used in massproduced systems. Use these models only for experiments and function
evaluation.
Purpose
This manual is intended for users to understand the functions described in the
Organization below.
Organization
The µPD780308, 780308Y Subseries manual is separated into two parts: this manual
and the instruction edition (common to the 78K/0 Series).
µPD780308, 780308Y
78K/0 Series
Subseries User’s Manual
User’s Manual
(This Manual)
How to Read This Manual
Instruction
•
Pin functions
•
CPU functions
•
Internal block functions
•
Instruction set
•
Interrupt
•
Explanation of each instruction
•
Other on-chip peripheral functions
Before reading this manual, you should have general knowledge of electric and logic
circuits and microcontrollers.
•
To those who use this manual as the manual of the µPD780306(A) and 780308(A):
→ The µPD780306 and 780308, and µPD780306(A) and 780308(A) differ only in
their quality grade. Regarding (A) models read the product name as follows:
µPD780306 → µPD780306(A)
µPD780308 → µPD780308(A)
•
When you want to understand the functions in general:
→ Read this manual in the order of the contents.
•
How to interpret the register format:
→ For the circled bit number, the bit name is defined as a reserved word in the
RA78K/0, and in the CC78K/0, already defined in the header file named sfrbit.h.
•
When you know a register name and want to confirm its details:
→ Read APPENDIX C REGISTER INDEX.
•
To know the µPD780308 and 780308Y Subseries instruction function in detail:
→ Refer to the 78K/0 Series User's Manual: Instructions (U12326E).
Caution The application examples in this manual are for the “standard”
quality grade for general-purpose electronic systems. If the examples
in this manual are to be used for applications where a quality higher
than that of the “standard” quality grade is required, determine the
required quality grade of the respective components and circuits to
be used.
Chapter Organization: This manual divides the descriptions for the µPD780308 and 780308Y Subseries into
different chapters as shown below. Read only the chapters related to the device you use.
Chapter
µ PD780308
µPD780308Y
Subseries
Subseries
Chapter 1
Outline (µ PD780308 Subseries)
√
—
Chapter 2
Outline (µ PD780308Y Subseries)
—
√
Chapter 3
Pin Function ( µ PD780308 Subseries)
√
—
Chapter 4
Pin Function ( µ PD780308Y Subseries)
—
√
Chapter 5
CPU Architecture
√
√
Chapter 6
Port Functions
√
√
Chapter 7
Clock Generator
√
√
Chapter 8
16-Bit Timer/Event Counter
√
√
Chapter 9
8-Bit Timer/Event Counters 1 and 2
√
√
Chapter 10 Watch Timer
√
√
Chapter 11 Watchdog Timer
√
√
Chapter 12 Clock Output Control Circuit
√
√
Chapter 13 Buzzer Output Control Circuit
√
√
Chapter 14 A/D Converter
√
√
Chapter 15 Serial Interface Channel 0 (µ PD780308 Subseries)
√
—
Chapter 16 Serial Interface Channel 0 (µ PD780308Y Subseries)
—
√
Chapter 17 Serial Interface Channel 2
√
√
Chapter 18 Serial Interface Channel 3
√
√
Chapter 19 LCD Controller / Driver
√
√
Chapter 20 Interrupt and Test Functions
√
√
Chapter 21 Standby Function
√
√
Chapter 22 Reset Function
√
√
Chapter 23 µ PD78P0308, µ PD78P0308Y
√
√
Chapter 24 Instruction Set
√
√
Differences between µPD780308 and µPD780308Y Subseries:
The µPD780308 and µPD780308Y Subseries are different in the following functions
of the serial interface channel 0.
Modes of serial interface channel 0
√
µPD780308
µPD780308Y
Subseries
Subseries
3-wire serial I/O mode
√
√
2-wire serial I/O mode
√
√
SBI (serial bus interface) mode
√
—
I2C (Inter IC) bus mode
—
√
: Supported
— : Not supported
Legend
Data representation weight
:
High digits on the left and low digits on the right
Active low representations
:
××× (line over the pin and signal names)
Note
:
Description of note in the text.
Caution
:
Information requiring particular attention
Remarks
:
Additional explanatory material
Numerical notation
:
Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents
The related documents indicated in this publication may include preliminary
versions. However, preliminary versions are not marked as such.
•
Related documents for µPD780308 Subseries
Document name
•
Document No.
Japanese
English
µPD780306, 780308 Data Sheet
U11105J
Planned
µPD780306Y, 780308Y Data Sheet
U12251J
Planned
µPD78P0308 Preliminary Product Information
U11776J
U11776E
µPD78P0308Y Preliminary Product Information
U11832J
U11832E
µPD780308, 780308Y Subseries User’s Manual
U11377J
This manual
78K/0 Series User’s Manual—Instruction
U12326J
U12326E
78K/0 Series Instruction Table
U10903J
—
78K/0 Series Instruction Set
U10904J
—
µPD780308 Subseries Special Function Register Table
Planned
—
Related documents for µPD780308Y Subseries
Document name
Document No.
Japanese
English
µPD780306Y, 780308Y Data Sheet
U12251J
Planned
µPD78P0308Y Preliminary Product Information
U11832J
U11832E
µPD780308, 780308Y Subseries User’s Manual
U11377J
This manual
78K/0 Series User’s Manual—Instruction
IEU-849
IEU-1372
78K/0 Series Instruction Table
U10903J
—
78K/0 Series Instruction Set
U10904J
—
µPD780308Y Subseries Special Function Register Table
Planned
—
Caution The above documents are subject to change without prior notice. Be sure to use the latest version
when starting design.
•
Development Tool Documents (User’s Manuals)
Document Name
RA78K Series Assembler Package
Document No.
Japanese
English
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
EEU-817
EEU-1402
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structure Assembly
Language
U11789J
U11789E
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
Operation
U11517J
U11517E
Language
U11518J
U11518E
Programming Know-How
EEA-618
EEA-1208
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
CC78K Series C Compiler
CC78K0 C Compiler
CC78K C Compiler Application Note
CC78K Series Library Source File
U12322J
PG-1500 PROM Programmer
—
U11940J
EEU-1355
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC DOS ) Base
EEU-5008
U10540E
IE-78000-R
U11376J
U11376E
IE-78000-R-A
U10057J
U10057E
IE-78000-R-BK
EEU-867
EEU-1427
IE-78064-R-EM
U11362J
U11362E
EEU-934
EEU-1469
U10181J
U10181E
SM78K Series System Simulator
External Parts User Open U10092J
Interface Specifications
U10092E
ID78K0 Integrated Debugger EWS Base
Reference
U11151J
ID78K0 Integrated Debugger PC Base
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows Base
Guide
U11649J
U11649E
SD78K/0 Screen Debugger
Introduction
EEU-852
U10539E
PC-9800 Series (MS-DOS) Base
Reference
U10952J
SD78K/0 Screen Debugger
Introduction
EEU-5024
EEU-1414
Reference
U11279J
U11279E
TM
PG-1500 Controller PC-9800 Series (MS-DOS ) Base
TM
EP-78064
SM78K0 System Simulator Windows
IBM PC/AT
TM
TM
Base
(PC DOS) Base
Reference
—
—
Caution The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
•
Documents for Embedded Software (User's Manual)
Document Name
Document No.
Japanese
78K/0 Series Real-Time OS
Basics
U11537J
—
Installation
U11536J
—
Basics
U12257J
—
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-1438
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System—Translator
EEU-862
EEU-1444
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module
EEU-858
EEU-1441
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Debugger
EEU-921
EEU-1458
78K/0 Series OS MX78K0
•
English
Other Documents
Document Name
Document No.
Japanese
English
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Electric Static Discharge (ESD) Test
MEM-539
Guide to Quality Assurance for Semiconductor Devices
C11893J
Microcomputer Product Series Guide
C11416J
—
MEI-1202
—
Caution The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
CONTENTS
CHAPTER 1 OUTLINE (µPD780308 Subseries) ...........................................................................
1.1 Features .............................................................................................................................
1.2 Application Field ..............................................................................................................
1.3 Ordering Information .......................................................................................................
1.4 Quality Grade ....................................................................................................................
1.5 Pin Configuration (Top View) .........................................................................................
1.6 78K/0 Series Line-up .......................................................................................................
1.7 Block Diagram ..................................................................................................................
1.8 Outline of Function ..........................................................................................................
1.9 Mask Options ....................................................................................................................
1
1
2
2
3
4
9
11
12
13
CHAPTER 2 OUTLINE (µPD780308Y Subseries) ........................................................................
2.1 Features .............................................................................................................................
2.2 Application Field ..............................................................................................................
2.3 Ordering Information .......................................................................................................
2.4 Quality Grade ....................................................................................................................
2.5 Pin Configuration (Top View) .........................................................................................
2.6 78K/0 Series Line-up .......................................................................................................
2.7 Block Diagram ..................................................................................................................
2.8 Outline of Function ..........................................................................................................
2.9 Mask Options ....................................................................................................................
15
15
16
16
16
17
22
24
25
26
CHAPTER 3 PIN FUNCTION (µPD780308 Subseries) ................................................................
3.1 Pin Function List ..............................................................................................................
27
27
3.2
3.1.1
Normal operating mode pins ..........................................................................................
3.1.2
27
PROM programming mode pins (µPD78P0308 only) ...................................................
30
Description of Pin Functions .........................................................................................
31
3.2.1
P00 to P05, P07 (Port 0) ...................................................................................................
31
3.2.2
P10 to P17 (Port 1) ...........................................................................................................
32
3.2.3
P25 to P27 (Port 2) ...........................................................................................................
32
3.2.4
P30 to P37 (Port 3) ...........................................................................................................
33
3.2.5
P70 to P72 (Port 7) ...........................................................................................................
34
3.2.6
P80 to P87 (Port 8) ...........................................................................................................
35
3.2.7
P90 to P97 (Port 9) ...........................................................................................................
35
3.2.8
P100 to P103 (Port 10) .....................................................................................................
35
3.2.9
P110 to P117 (Port 11) .....................................................................................................
36
3.2.10
COM0 to COM3 ..................................................................................................................
36
3.2.11
VLC0 to VLC2 ......................................................................................................................................................................................
36
3.2.12
BIAS ....................................................................................................................................
36
3.2.13
AVREF .....................................................................................................................................................................................................
37
3.2.14
AVSS ........................................................................................................................................................................................................
37
3.2.15
RESET .................................................................................................................................
37
3.2.16
X1 and X2 ...........................................................................................................................
37
3.2.17
XT1 and XT2 ......................................................................................................................
37
–i–
3.2.18
VDD0, VDD1 ...........................................................................................................................................................................................
37
3.2.19
VSS0, VSS1 ............................................................................................................................................................................................
37
3.2.20
VPP (µPD78P0308 only) .....................................................................................................
37
3.2.21
IC (Mask ROM version only) ...........................................................................................
37
Input/output Circuits and Recommended Connection of Unused Pins ..................
38
CHAPTER 4 PIN FUNCTION (µPD780308Y Subseries) ..............................................................
4.1 Pin Function List ..............................................................................................................
43
43
3.3
4.2
4.1.1
Normal operating mode pins ..........................................................................................
4.1.2
43
PROM programming mode pins (µPD78P0308Y only) ................................................
46
Description of Pin Functions .........................................................................................
47
4.2.1
P00 to P05, P07 (Port 0) ...................................................................................................
47
4.2.2
P10 to P17 (Port 1) ...........................................................................................................
48
4.2.3
P25 to P27 (Port 2) ...........................................................................................................
48
4.2.4
P30 to P37 (Port 3) ...........................................................................................................
49
4.2.5
P70 to P72 (Port 7) ...........................................................................................................
50
4.2.6
P80 to P87 (Port 8) ...........................................................................................................
51
4.2.7
P90 to P97 (Port 9) ...........................................................................................................
51
4.2.8
P100 to P103 (Port 10) .....................................................................................................
51
4.2.9
P110 to P117 (Port 11) .....................................................................................................
52
4.2.10
COM0 to COM3 ..................................................................................................................
52
4.2.11
VLC0 to VLC2 ......................................................................................................................................................................................
52
4.2.12
BIAS ....................................................................................................................................
52
4.2.13
AVREF .....................................................................................................................................................................................................
53
4.2.14
AVSS ........................................................................................................................................................................................................
53
4.2.15
RESET .................................................................................................................................
53
4.2.16
X1 and X2 ...........................................................................................................................
53
4.2.17
XT1 and XT2 ......................................................................................................................
53
4.2.18
VDD0, VDD1 ...........................................................................................................................................................................................
53
4.2.19
VSS0, VSS1 ............................................................................................................................................................................................
53
4.2.20
VPP (µPD78P0308Y only) ..................................................................................................
53
4.2.21
IC (Mask ROM version only) ...........................................................................................
53
Input/output Circuits and Recommended Connection of Unused Pins ..................
54
CHAPTER 5 CPU ARCHITECTURE ...............................................................................................
5.1 Memory Spaces ................................................................................................................
59
59
4.3
5.2
5.3
5.1.1
Internal program memory space ....................................................................................
62
5.1.2
Internal data memory space ...........................................................................................
63
5.1.3
Special-function register (SFR) area .............................................................................
63
5.1.4
Data memory addressing ................................................................................................
64
Processor Registers ........................................................................................................
67
5.2.1
Control registers ...............................................................................................................
67
5.2.2
General registers ..............................................................................................................
69
5.2.3
Special-function register (SFR) ......................................................................................
71
Instruction Address Addressing ...................................................................................
75
5.3.1
Relative addressing ..........................................................................................................
75
5.3.2
Immediate addressing ......................................................................................................
76
5.3.3
Table indirect addressing ................................................................................................
77
– ii –
5.3.4
Register addressing .........................................................................................................
78
Operand Address Addressing .......................................................................................
79
5.4.1
Implied addressing ...........................................................................................................
79
5.4.2
Register addressing .........................................................................................................
80
5.4.3
Direct addressing .............................................................................................................
81
5.4.4
Short direct addressing ...................................................................................................
82
5.4.5
Special-function register (SFR) addressing .................................................................
84
5.4.6
Register indirect addressing ..........................................................................................
85
5.4.7
Based addressing .............................................................................................................
86
5.4.8
Based indexed addressing ..............................................................................................
87
5.4.9
Stack addressing ..............................................................................................................
87
CHAPTER 6 PORT FUNCTIONS ....................................................................................................
6.1 Port Functions ..................................................................................................................
6.2 Port Configuration ...........................................................................................................
89
89
92
5.4
6.3
6.4
6.2.1
Port 0 ..................................................................................................................................
92
6.2.2
Port 1 ..................................................................................................................................
94
6.2.3
Port 2 (µPD780308 Subseries) ........................................................................................
95
6.2.4
Port 2 (µPD780308Y Subseries) ......................................................................................
97
6.2.5
Port 3 ..................................................................................................................................
99
6.2.6
Port 7 ..................................................................................................................................
100
6.2.7
Port 8 ..................................................................................................................................
102
6.2.8
Port 9 ..................................................................................................................................
103
6.2.9
Port 10 ................................................................................................................................
104
6.2.10
Port 11 ................................................................................................................................
105
Port Function Control Registers ...................................................................................
Port Function Operations ...............................................................................................
108
113
6.4.1
Writing to input/output port ............................................................................................
113
6.4.2
Reading from input/output port ......................................................................................
113
6.4.3
Operations on input/output port ....................................................................................
113
CHAPTER 7 CLOCK GENERATOR ...............................................................................................
7.1 Clock Generator Functions ............................................................................................
7.2 Clock Generator Configuration ......................................................................................
7.3 Clock Generator Control Register .................................................................................
7.4 System Clock Oscillator .................................................................................................
115
115
115
117
121
7.4.1
Main system clock oscillator ..........................................................................................
121
7.4.2
Subsystem clock oscillator .............................................................................................
122
7.4.3
Scaler ..................................................................................................................................
124
7.4.4
When no subsystem clocks are used ...........................................................................
124
Clock Generator Operations ..........................................................................................
125
7.5.1
Main system clock operations ........................................................................................
126
7.5.2
Subsystem clock operations ..........................................................................................
127
Changing System Clock and CPU Clock Settings ......................................................
128
7.6.1
Time required for switchover between system clock and CPU clock ......................
128
7.6.2
System clock and CPU clock switching procedure ....................................................
129
CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................
131
7.5
7.6
– iii –
8.1
8.2
8.3
8.4
8.5
µPD780308 and 780308Y Subseries .............................
Functions .........................................................................
Configuration ...................................................................
Control Registers ............................................................
Operations .......................................................................
131
133
135
140
149
8.5.1
Interval timer operations .................................................................................................
149
8.5.2
PWM output operations ...................................................................................................
151
8.5.3
PPG output operations ....................................................................................................
154
8.5.4
Pulse width measurement operations ...........................................................................
155
8.5.5
External event counter operation ..................................................................................
162
8.5.6
Square-wave output operation .......................................................................................
164
8.5.7
Outline of Internal Timer of
16-Bit Timer/Event Counter
16-Bit Timer/Event Counter
16-Bit Timer/Event Counter
16-Bit Timer/Event Counter
One-shot pulse output operation ...................................................................................
166
16-Bit Timer/Event Counter Operating Precautions ...................................................
170
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 ............................................................
9.1 8-Bit Timer/Event Counters 1 and 2 Functions ...........................................................
173
173
8.6
9.1.1
8-bit timer/event counter mode ......................................................................................
9.1.2
173
16-bit timer/event counter mode ....................................................................................
176
8-Bit Timer/Event Counters 1 and 2 Configurations ..................................................
8-Bit Timer/Event Counters 1 and 2 Control Registers .............................................
8-Bit Timer/Event Counters 1 and 2 Operations .........................................................
178
182
187
9.4.1
8-bit timer/event counter mode ......................................................................................
187
9.4.2
16-bit timer/event counter mode ....................................................................................
193
8-Bit Timer/Event Counters 1 and 2 Precautions .......................................................
198
CHAPTER 10 WATCH TIMER ........................................................................................................
10.1 Watch Timer Functions ...................................................................................................
10.2 Watch Timer Configuration ............................................................................................
10.3 Watch Timer Control Registers .....................................................................................
10.4 Watch Timer Operations .................................................................................................
201
201
202
202
206
9.2
9.3
9.4
9.5
10.4.1
Watch timer operation .....................................................................................................
206
10.4.2
Interval timer operation ...................................................................................................
206
CHAPTER 11 WATCHDOG TIMER ................................................................................................
11.1 Watchdog Timer Functions ............................................................................................
11.2 Watchdog Timer Configuration ......................................................................................
11.3 Watchdog Timer Control Registers ...............................................................................
11.4 Watchdog Timer Operations ..........................................................................................
207
207
209
210
213
11.4.1
Watchdog timer operation ...............................................................................................
213
11.4.2
Interval timer operation ...................................................................................................
214
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ..................................................................
12.1 Clock Output Control Circuit Functions.......................................................................
12.2 Clock Output Control Circuit Configuration ................................................................
12.3 Clock Output Function Control Registers ...................................................................
215
215
216
217
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT ................................................................
13.1 Buzzer Output Control Circuit Functions ....................................................................
221
221
– iv –
13.2 Buzzer Output Control Circuit Configuration ..............................................................
13.3 Buzzer Output Function Control Registers .................................................................
221
222
CHAPTER 14 A/D CONVERTER ....................................................................................................
14.1 A/D Converter Functions ................................................................................................
14.2 A/D Converter Configuration ..........................................................................................
14.3 A/D Converter Control Registers ...................................................................................
14.4 A/D Converter Operations ..............................................................................................
225
225
225
228
232
14.4.1
Basic operations of A/D converter ................................................................................
232
14.4.2
Input voltage and conversion results ............................................................................
234
14.4.3
A/D converter operating mode .......................................................................................
235
14.5 A/D Converter Cautions ..................................................................................................
237
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries) ...............................
15.1 Serial Interface Channel 0 Functions ...........................................................................
15.2 Serial Interface Channel 0 Configuration .....................................................................
15.3 Serial Interface Channel 0 Control Registers ..............................................................
15.4 Serial Interface Channel 0 Operations ..........................................................................
241
242
244
248
254
15.4.1
Operation stop mode .......................................................................................................
254
15.4.2
3-wire serial I/O mode operation ....................................................................................
255
15.4.3
SBI mode operation ..........................................................................................................
259
15.4.4
2-wire serial I/O mode operation ....................................................................................
285
15.4.5
SCK0/P27 pin output manipulation ................................................................................
290
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries) ............................
16.1 Serial Interface Channel 0 Functions ...........................................................................
16.2 Serial Interface Channel 0 Configuration .....................................................................
16.3 Serial Interface Channel 0 Control Registers ..............................................................
16.4 Serial Interface Channel 0 Operations ..........................................................................
291
292
294
298
305
16.4.1
Operation stop mode .......................................................................................................
305
16.4.2
3-wire serial I/O mode operation ....................................................................................
306
16.4.3
2-wire serial I/O mode operation ....................................................................................
310
16.4.4
I2C bus mode operation ...................................................................................................
316
16.4.5
Cautions on use of I2C bus mode ..................................................................................
336
16.4.6
Restrictions when using I2C bus mode ........................................................................
339
16.4.7
SCK0/SCL/P27 pin output manipulation .......................................................................
341
CHAPTER 17 SERIAL INTERFACE CHANNEL 2 .........................................................................
17.1 Serial Interface Channel 2 Functions ...........................................................................
17.2 Serial Interface Channel 2 Configuration .....................................................................
17.3 Serial Interface Channel 2 Control Registers ..............................................................
17.4 Serial Interface Channel 2 Operation ............................................................................
343
343
344
348
358
17.4.1
Operation stop mode .......................................................................................................
358
17.4.2
Asynchronous serial interface (UART) mode ...............................................................
360
17.4.3
3-wire serial I/O mode ......................................................................................................
374
17.4.4
Limitations of UART mode ..............................................................................................
381
CHAPTER 18 SERIAL INTERFACE CHANNEL 3 .........................................................................
385
–v–
18.1
18.2
18.3
18.4
Chapter
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
Serial
Serial
Serial
Serial
Functions ...........................................................................
Configuration .....................................................................
Control Registers ..............................................................
Operation ............................................................................
385
385
387
390
18.4.1
Operation stop mode .......................................................................................................
390
18.4.2
3-wire serial I/O mode ......................................................................................................
391
19 LCD CONTROLLER/DRIVER......................................................................................
LCD Controller/Driver Functions ...................................................................................
LCD Controller/Driver Configuration ............................................................................
LCD Controller/Driver Control Registers .....................................................................
LCD Controller/Driver Settings ......................................................................................
LCD Display Data Memory ..............................................................................................
Common Signals and Segment Signals .......................................................................
Supply of LCD Drive Voltages VLC0, VLC1, VLC2 .....................................................................................
Display Modes ..................................................................................................................
395
395
396
398
402
403
404
408
412
19.8.1
Interface
Interface
Interface
Interface
Channel
Channel
Channel
Channel
3
3
3
3
Static display example .....................................................................................................
412
19.8.2
2-time-division display example .....................................................................................
415
19.8.3
3-time-division display example .....................................................................................
418
19.8.4
4-time-division display example .....................................................................................
422
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS ...................................................................
20.1 Interrupt Function Types ................................................................................................
20.2 Interrupt Sources and Configuration ............................................................................
20.3 Interrupt Function Control Registers ............................................................................
20.4 Interrupt Request Servicing Operations ......................................................................
425
425
426
429
438
20.4.1
Non-maskable interrupt request acknowledge operation ..........................................
438
20.4.2
Maskable interrupt request acknowledge operation ...................................................
441
20.4.3
Software interrupt request acknowledge operation ....................................................
444
20.4.4
Multiple interrupt request servicing ..............................................................................
444
20.4.5
Interrupt request reserve .................................................................................................
447
20.5 Test Functions ..................................................................................................................
448
20.5.1
Registers controlling the test function .........................................................................
448
20.5.2
Test input signal acknowledge operation .....................................................................
451
CHAPTER 21 STANDBY FUNCTION ............................................................................................
21.1 Standby Function and Configuration ...........................................................................
453
453
21.1.1
Standby function ..............................................................................................................
453
21.1.2
Standby function control register ..................................................................................
454
21.2 Standby Function Operations ........................................................................................
455
21.2.1
HALT mode ........................................................................................................................
455
21.2.2
STOP mode ........................................................................................................................
458
CHAPTER 22 RESET FUNCTION ..................................................................................................
22.1 Reset Function .................................................................................................................
461
461
CHAPTER 23 µPD78P0308, 78P0308Y .........................................................................................
23.1 Internal Memory Size Switching Register ....................................................................
465
466
– vi –
23.2 Internal Expansion RAM Size Switching Register ......................................................
23.3 PROM Programming ........................................................................................................
467
468
23.3.1
Operating modes ..............................................................................................................
468
23.3.2
PROM write procedure .....................................................................................................
470
23.3.3
PROM reading procedure ................................................................................................
474
23.4 Erasure Procedure (µPD78P0308KL-T and 78P0308YKL-T Only) .............................
23.5 Opaque Film Masking the Window
(µPD78P0308KL-T and 78P0308YKL-T Only) ...............................................................
23.6 Screening of One-Time PROM Versions ......................................................................
475
CHAPTER 24 INSTRUCTION SET .................................................................................................
24.1 Legends Used in Operation List ....................................................................................
477
478
475
475
24.1.1
Operand identifiers and description methods .............................................................
24.1.2
Description of “operation” column ................................................................................
479
24.1.3
Description of “flag operation” column ........................................................................
479
24.2 Operation List ...................................................................................................................
24.3 Instructions Listed by Addressing Type ......................................................................
480
488
APPENDIX A DEVELOPMENT TOOLS .......................................................................................
A.1 Language Processing Software .....................................................................................
A.2 PROM Writing Tools ........................................................................................................
493
494
495
A.3
478
A.2.1
Hardware ............................................................................................................................
495
A.2.2
Software .............................................................................................................................
495
Debugging Tools ..............................................................................................................
496
A.3.1
Hardware ............................................................................................................................
496
A.3.2
Software .............................................................................................................................
497
Operating Systems for IBM PC ......................................................................................
Upgrading Other In-Circuit Emulators to In-Circuit Emulator for 78K/0 Series .....
500
501
APPENDIX B EMBEDDED SOFTWARE ......................................................................................
B.1 Real-time OS .....................................................................................................................
B.2 Fuzzy Inference Development Support System ..........................................................
505
505
507
APPENDIX C REGISTER INDEX .................................................................................................
C.1 Register Name Index .......................................................................................................
C.2 Register Symbol Index ....................................................................................................
509
509
512
APPENDIX D
515
A.4
A.5
REVISION HISTORY ..............................................................................................
– vii –
LIST OF FIGURES (1/7)
Figure No.
Title
Page
3-1.
Pin Input/Output Circuit of List ..............................................................................................
40
4-1.
Pin Input/Output Circuit Type ................................................................................................
56
5-1.
Memory Map (µPD780306, 780306Y) ..................................................................................
59
5-2.
Memory Map (µPD780308, 780308Y) ..................................................................................
60
5-3.
Memory Map (µPD78P0308, 78P0308Y) ..............................................................................
61
5-4.
Data Memory Addressing (µPD780306, 780306Y) ...............................................................
64
5-5.
Data Memory Addressing (µPD780308, 780308Y) ...............................................................
65
5-6.
Data Memory Addressing (µPD78P0308, 78P0308Y) ..........................................................
66
5-7.
Program Counter Configuration ............................................................................................
67
5-8.
Program Status Word Configuration .....................................................................................
67
5-9.
Stack Pointer Configuration ..................................................................................................
68
5-10.
Data to be Saved to Stack Memory ......................................................................................
68
5-11.
Data to be Reset from Stack Memory ...................................................................................
69
5-12.
General Register Configuration .............................................................................................
70
6-1.
Port Types .............................................................................................................................
89
6-2.
P00 and P07 Block Diagram .................................................................................................
93
6-3.
P01 to P05 Block Diagram ....................................................................................................
93
6-4.
P10 to P17 Block Diagram ....................................................................................................
94
6-5.
P25, P26 Block Diagram (µPD780308 Subseries) ................................................................
95
6-6.
P27 Block Diagram (µPD780308 Subseries) ........................................................................
96
6-7.
P25, P26 Block Diagram (µPD780308Y Subseries) .............................................................
97
6-8.
P27 Block Diagram (µPD780308Y Subseries) ......................................................................
98
6-9.
P30 to P37 Block Diagram ....................................................................................................
99
6-10.
P70 Block Diagram ...............................................................................................................
100
6-11.
P71 and P72 Block Diagram .................................................................................................
101
6-12.
P80 to P87 Block Diagram ....................................................................................................
102
6-13.
P90 to P97 Block Diagram ....................................................................................................
103
6-14.
P100 to P103 Block Diagram ................................................................................................
104
6-15.
P110, P114 to P117 Block Diagram ......................................................................................
105
6-16.
P111 Block Diagram .............................................................................................................
106
6-17.
P112 and P113 Block Diagram .............................................................................................
107
6-18.
Block Diagram of Falling Edge Detection Circuit ..................................................................
107
6-19.
Port Mode Register Format ...................................................................................................
110
6-20.
Pull-Up Resistor Option Register Format ..............................................................................
111
6-21.
Key Return Mode Register Format .......................................................................................
112
7-1.
Clock Generator Block Diagram ............................................................................................
116
7-2.
Subsystem Clock Feedback Resistor ...................................................................................
117
7-3.
Processor Clock Control Register Format .............................................................................
118
7-4.
Oscillation Mode Select Register Format ..............................................................................
120
– viii –
LIST OF FIGURES (2/7)
Figure No.
Title
Page
7-5.
Main System Clock Waveform due to Writing to OSMS .......................................................
120
7-6.
External Circuit of Main System Clock Oscillator ..................................................................
121
7-7.
External Circuit of Subsystem Clock Oscillator .....................................................................
122
7-8.
Examples of Oscillator with Bad Connection ........................................................................
122
7-9.
Main System Clock Stop Function ........................................................................................
126
7-10.
System Clock and CPU Clock Switching ..............................................................................
129
8-1.
16-Bit Timer/Event Counter Block Diagram ..........................................................................
136
8-2.
16-Bit Timer/Event Counter Output Control Circuit Block Diagram .......................................
137
8-3.
Timer Clock Selection Register 0 Format .............................................................................
141
8-4.
16-Bit Timer Mode Control Register Format .........................................................................
143
8-5.
Capture/Compare Control Register 0 Format .......................................................................
144
8-6.
16-Bit Timer Output Control Register Format .......................................................................
145
8-7.
Port Mode Register 3 Format ................................................................................................
146
8-8.
External Interrupt Mode Register 0 Format ...........................................................................
147
8-9.
Sampling Clock Select Register Format ...............................................................................
148
8-10.
Control Register Settings for Interval Timer Operation .........................................................
149
8-11.
Interval Timer Configuration Diagram ...................................................................................
150
8-12.
Interval Timer Operation Timings ..........................................................................................
150
8-13.
Control Register Settings for PWM Output Operation ...........................................................
152
8-14.
Example of D/A Converter Configuration with PWM Output .................................................
153
8-15.
TV Tuner Application Circuit Example ..................................................................................
153
8-16.
Control Register Settings for PPG Output Operation ............................................................
154
8-17.
Control Register Settings for Pulse Width Measurement with ..............................................
155
8-18.
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ................
156
8-19.
Timing of Pulse Width Measurement Operation by Free-Running Counter ..........................
156
8-20.
Control Register Settings for Two Pulse Width Measurements with
Free-Running Counter ..........................................................................................................
157
8-21.
Timing of Pulse Width Measurement Operation with ............................................................
158
8-22.
Control Register Settings for Pulse Width Measurement with ..............................................
159
8-23.
Timing of Pulse Width Measurement Operation by Free-Running ........................................
160
8-24.
Control Register Settings for Pulse Width Measurement by Means of Restart .....................
161
8-25.
Timing of Pulse Width Measurement Operation by ...............................................................
161
8-26.
Control Register Settings in External Event Counter Mode ..................................................
162
8-27.
External Event Counter Configuration Diagram ....................................................................
163
8-28.
External Event Counter Operation Timings (with Rising Edge Specified) .............................
163
8-29.
Control Register Settings in Square-Wave Output Mode ......................................................
164
8-30.
Square-Wave Output Operation Timing ................................................................................
165
8-31.
Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ....
166
8-32.
Timing of One-Shot Pulse Output Operation Using Software Trigger ...................................
167
8-33.
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger .....
168
8-34.
Timing of One-Shot Pulse Output Operation Using ..............................................................
169
8-35.
16-Bit Timer Register Start Timing ........................................................................................
170
– ix –
LIST OF FIGURES (3/7)
Figure No.
Title
Page
8-36.
Timings After Change of Compare Register During Timer Count Operation ........................
170
8-37.
Capture Register Data Retention Timing ..............................................................................
171
8-38.
Operation Timing of OVF0 Flag ............................................................................................
172
9-1.
8-Bit Timer/Event Counters 1 and 2 Block Diagram .............................................................
179
9-2.
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 ..................................
180
9-3.
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 ..................................
180
9-4.
Timer Clock Select Register 1 Format ..................................................................................
183
9-5.
8-Bit Timer Mode Control Register Format ...........................................................................
184
9-6.
8-Bit Timer Output Control Register Format .........................................................................
185
9-7.
Port Mode Register 3 Format ................................................................................................
186
9-8.
Interval Timer Operation Timings ..........................................................................................
187
9-9.
External Event Counter Operation Timings (with Rising Edge Specified) .............................
190
9-10.
Square Wave Output Operation Timing ................................................................................
192
9-11.
Interval Timer Operation Timing ............................................................................................
193
9-12.
External Event Counter Operation Timings (with Rising Edge Specified) .............................
195
9-13.
Square Wave Output Operation Timing ................................................................................
197
9-14.
8-Bit Timer Registers 1 and 2 Start Timing ...........................................................................
198
9-15.
External Event Counter Operation Timing ............................................................................
198
9-16.
Timing after Compare Register Change during Timer Count Operation ...............................
199
10-1.
Watch Timer Block Diagram ..................................................................................................
203
10-2.
Timer Clock Select Register 2 Format ..................................................................................
204
10-3.
Watch Timer Mode Control Register Format ........................................................................
205
11-1.
Watchdog Timer Block Diagram ...........................................................................................
209
11-2.
Timer Clock Select Register 2 Format ..................................................................................
211
11-3.
Watchdog Timer Mode Register Format ...............................................................................
212
12-1.
Remote Controlled Output Application Example ...................................................................
215
12-2.
Clock Output Control Circuit Block Diagram .........................................................................
216
12-3.
Timer Clock Select Register 0 Format ..................................................................................
218
12-4.
Port Mode Register 3 Format ................................................................................................
219
13-1.
Buzzer Output Control Circuit Block Diagram .......................................................................
221
13-2.
Timer Clock Select Register 2 Format ..................................................................................
223
13-3.
Port Mode Register 3 Format ................................................................................................
224
14-1.
A/D Converter Block Diagram ...............................................................................................
226
14-2.
A/D Converter Mode Register Format ...................................................................................
229
14-3.
A/D Converter Input Select Register Format .........................................................................
230
14-4.
External Interrupt Mode Register 1 Format ...........................................................................
231
–x–
LIST OF FIGURES (4/7)
Figure No.
Title
Page
14-5.
A/D Converter Basic Operation .............................................................................................
233
14-6.
Relationships between Analog Input Voltage and A/D Conversion Result ...........................
234
14-7.
A/D Conversion by Hardware Start .......................................................................................
235
14-8.
A/D Conversion by Software Start ........................................................................................
236
14-9.
Example of Method of Reducing Current Consumption in Standby Mode ............................
237
14-10.
Analog Input Pin Disposition .................................................................................................
238
14-11.
A/D Conversion End Interrupt Generation Timing .................................................................
239
15-1.
Serial Bus Interface (SBI) System Configuration Example ...................................................
243
15-2.
Serial Interface Channel 0 Block Diagram ............................................................................
245
15-3.
Timer Clock Select Register 3 Format ..................................................................................
248
15-4.
Serial Operating Mode Register 0 Format ............................................................................
249
15-5.
Serial Bus Interface Control Register Format .......................................................................
251
15-6.
Interrupt Timing Specify Register Format .............................................................................
253
15-7.
3-Wire Serial I/O Mode Timings ............................................................................................
257
15-8.
RELT and CMDT Operations ................................................................................................
257
15-9.
Circuit of Switching in Transfer Bit Order ..............................................................................
258
15-10.
Example of Serial Bus Configuration with SBI ......................................................................
259
15-11.
SBI Transfer Timings .............................................................................................................
261
15-12.
Bus Release Signal ...............................................................................................................
262
15-13.
Command Signal ...................................................................................................................
262
15-14.
Addresses .............................................................................................................................
263
15-15.
Slave Selection with Address ................................................................................................
263
15-16.
Commands ............................................................................................................................
264
15-17.
Data .......................................................................................................................................
264
15-18.
Acknowledge Signal ..............................................................................................................
265
15-19.
BUSY and READY Signals ...................................................................................................
266
15-20.
RELT, CMDT, RELD, and CMDD Operations (Master) ........................................................
271
15-21.
RELD and CMDD Operations (Slave) ...................................................................................
271
15-22.
ACKT Operation ....................................................................................................................
272
15-23.
ACKE Operations ..................................................................................................................
273
15-24.
ACKD Operations ..................................................................................................................
274
15-25.
BSYE Operation ....................................................................................................................
274
15-26.
Pin Configuration ...................................................................................................................
277
15-27.
Address Transmission from Master Device to Slave Device (WUP = 1) ...............................
279
15-28.
Command Transmission from Master Device to Slave Device .............................................
280
15-29.
Data Transmission from Master Device to Slave Device ......................................................
281
15-30.
Data Transmission from Slave Device to Master Device ......................................................
282
15-31.
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .........................................
285
15-32.
2-Wire Serial I/O Mode Timings ............................................................................................
288
15-33.
RELT and CMDT Operations ................................................................................................
289
15-34.
SCK0/P27 Pin Configuration .................................................................................................
290
– xi –
LIST OF FIGURES (5/7)
Figure No.
Title
Page
16-1.
Serial Bus Configuration Example Using I2C Bus .................................................................
16-2.
Serial Interface Channel 0 Block Diagram ............................................................................
295
16-3.
Timer Clock Select Register 3 Format ..................................................................................
298
16-4.
Serial Operating Mode Register 0 Format ............................................................................
299
16-5.
Serial Bus Interface Control Register Format .......................................................................
301
16-6.
Interrupt Timing Specify Register Format .............................................................................
303
16-7.
3-Wire Serial I/O Mode Timings ............................................................................................
308
16-8.
RELT and CMDT Operations ................................................................................................
308
16-9.
Circuit of Switching in Transfer Bit Order ..............................................................................
309
16-10.
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .........................................
310
16-11.
2-Wire Serial I/O Mode Timings ............................................................................................
314
16-12.
RELT and CMDT Operations ................................................................................................
315
16-13.
Example of Serial Bus Configuration Using I2C Bus .............................................................
316
16-14.
I2C Bus Serial Data Transfer Timing .....................................................................................
317
16-15.
Start Condition ......................................................................................................................
318
16-16.
Address .................................................................................................................................
318
16-17.
Transfer Direction Specification ............................................................................................
318
16-18.
Acknowledge Signal ..............................................................................................................
319
16-19.
Stop Condition .......................................................................................................................
319
16-20.
Wait Signal ............................................................................................................................
320
16-21.
Pin Configuration ...................................................................................................................
327
16-22.
Data Transmission from Master to Slave ..............................................................................
329
16-23.
Data Transmission from Slave to Master ..............................................................................
332
16-24.
Start Condition Output ...........................................................................................................
336
16-25.
Slave Wait Release (Transmission) ......................................................................................
337
16-26.
Slave Wait Release (Reception) ...........................................................................................
338
16-27.
SCK0/SCL/P27 Pin Configuration .........................................................................................
341
16-28.
SCK0/SCL/P27 Pin Configuration .........................................................................................
342
16-29.
Logic Circuit of SCL Signal ...................................................................................................
342
17-1.
Serial Interface Channel 2 Block Diagram ............................................................................
345
17-2.
Baud Rate Generator Block Diagram ....................................................................................
346
17-3.
Serial Operating Mode Register 2 Format ............................................................................
348
17-4.
Asynchronous Serial Interface Mode Register Format .........................................................
349
17-5.
Asynchronous Serial Interface Status Register Format ........................................................
352
17-6.
Baud Rate Generator Control Register Format .....................................................................
353
17-7.
Serial Interface Pin Select Register Format ..........................................................................
357
17-8.
Asynchronous Serial Interface Transmit/Receive Data Format ............................................
368
17-9.
Asynchronous Serial Interface Transmit Completion Interrupt Request Timing ...................
370
17-10.
Asynchronous Serial Interface Receive Completion Interrupt Request Timing ....................
371
17-11.
Receive Error Timing .............................................................................................................
372
– xii –
293
LIST OF FIGURES (6/7)
Figure No.
17-12.
Title
Page
Status of Receive Buffer Register (RXB) and Generation of
Interrupt Request (INTSR) When Reception is Stopped .......................................................
373
17-13.
3-Wire Serial I/O Mode Timing ..............................................................................................
379
17-14.
Circuit of Switching in Transfer Bit Order ..............................................................................
380
17-15.
Receive Completion Interrupt Generation Timing (when ISRM = 1) .....................................
381
17-16.
Disabling Reading Receive Buffer Register ..........................................................................
382
18-1.
Serial Interface Channel 3 Block Diagram ............................................................................
386
18-2.
Timer Clock Select Register 4 Format ..................................................................................
388
18-3.
Serial Operating Mode Register 3 Format ............................................................................
389
18-4.
3-Wire Serial I/O Mode Timing ..............................................................................................
392
18-5.
Circuit of Switching in Transfer Bit Order ..............................................................................
393
19-1.
LCD Controller/Driver Block Diagram ...................................................................................
396
19-2.
LCD Clock Select Circuit Block Diagram ..............................................................................
397
19-3.
LCD Display Mode Register Format .....................................................................................
399
19-4.
LCD Display Control Register Format ...................................................................................
401
19-5.
Relationship between LCD Display Data Memory
Contents and Segment/Common Outputs ............................................................................
403
19-6.
Common Signal Waveform ...................................................................................................
406
19-7.
Common Signal and Static Signal Voltages and Phases ......................................................
407
19-8.
LCD Drive Power Supply Connection Examples (with On-Chip Split Resistor) ....................
409
19-9.
LCD Drive Power Supply Connection Examples (with External Split Resistor) ....................
410
19-10.
Example of LCD Drive Voltage Supply from Off-Chip ...........................................................
411
19-11.
Static LCD Display Pattern and Electrode Connections .......................................................
412
19-12.
Static LCD Panel Connection Example .................................................................................
413
19-13.
Static LCD Drive Waveform Examples .................................................................................
414
19-14.
2-Time-Division LCD Display Pattern and Electrode Connections .......................................
415
19-15.
2-Time-Division LCD Panel Connection Example .................................................................
416
19-16.
2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) ...................................
417
19-17.
3-Time-Division LCD Display Pattern and Electrode Connections .......................................
418
19-18.
3-Time-Division LCD Panel Connection Example .................................................................
419
19-19.
3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) ...................................
420
19-20.
3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ....................................
421
19-21.
4-Time-Division LCD Display Pattern and Electrode Connections .......................................
422
19-22.
4-Time-Division LCD Panel Connection Example .................................................................
423
19-23.
4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................................
424
20-1.
Basic Configuration of Interrupt Function ..............................................................................
427
20-2.
Interrupt Request Flag Register Format ................................................................................
430
20-3.
Interrupt Mask Flag Register Format ....................................................................................
431
20-4.
Priority Specify Flag Register Format ...................................................................................
432
– xiii –
LIST OF FIGURES (7/7)
Figure No.
Title
Page
20-5.
External Interrupt Mode Register 0 Format ...........................................................................
433
20-6.
External Interrupt Mode Register 1 Format ...........................................................................
434
20-7.
Sampling Clock Select Register Format ...............................................................................
435
20-8.
Noise Remover Input/Output Timing (during rising edge detection) .....................................
436
20-9.
Program Status Word Format ...............................................................................................
437
20-10.
Non-Maskable Interrupt Request Acknowledge Flowchart ...................................................
439
20-11.
Non-Maskable Interrupt Request Acknowledge Timing ........................................................
439
20-12.
Non-Maskable Interrupt Request Acknowledge Operation ...................................................
440
20-13.
Interrupt Request Acknowledge Processing Algorithm .........................................................
442
20-14.
Interrupt Request Acknowledge Timing (Minimum Time) .....................................................
443
20-15.
Interrupt Request Acknowledge Timing (Maximum Time) ....................................................
443
20-16.
Multiple Interrupt Example ....................................................................................................
445
20-17.
Interrupt Request Hold ..........................................................................................................
447
20-18.
Basic Configuration of Test Function ....................................................................................
448
20-19.
Format of Interrupt Request Flag Register 1L .......................................................................
449
20-20.
Format of Interrupt Mask Flag Register 1L ...........................................................................
449
20-21.
Key Return Mode Register Format .......................................................................................
450
21-1.
Oscillation Stabilization Time Select Register Format ..........................................................
454
21-2.
HALT Mode Clear upon Interrupt Request Generation .........................................................
456
21-3.
HALT Mode Release by RESET Input ..................................................................................
457
21-4.
STOP Mode Release by Interrupt Request Generation ........................................................
459
21-5.
Release by STOP Mode RESET Input .................................................................................
460
22-1.
Block Diagram of Reset Function ..........................................................................................
461
22-2.
Timing of Reset Input by RESET Input .................................................................................
462
22-3.
Timing of Reset due to Watchdog Timer Overflow ................................................................
462
22-4.
Timing of Reset Input in STOP Mode by RESET Input .........................................................
462
23-1.
Internal Memory Size Switching Register Format .................................................................
466
23-2.
Internal Expansion RAM Size Switching Register Format ....................................................
467
23-3.
Page Program Mode Flowchart ............................................................................................
470
23-4.
Page Program Mode Timing .................................................................................................
471
23-5.
Byte Program Mode Flowchart ..............................................................................................
472
23-6.
Byte Program Mode Timing ..................................................................................................
473
23-7.
PROM Read Timing ..............................................................................................................
474
A-1.
Development Tool Configuration ...........................................................................................
493
A-2.
TGC-100SDW Drawing (For Reference Only) (Unit: mm) ....................................................
502
A-3.
EV-9200GF-100 Drawing (For Reference Only) (Unit: mm) .................................................
503
A-4.
EV-9200GF-100 Footprint (For Reference Only) (Unit: mm) ................................................
504
– xiv –
LIST OF TABLES (1/3)
Table No.
Title
Page
1-1.
Mask Options of Mask ROM Versions ..................................................................................
13
2-1.
Mask Options of Mask ROM Versions ..................................................................................
26
3-1.
Pin Input/Output Circuit Types ..............................................................................................
38
4-1.
Pin Input/Output Circuit Types ..............................................................................................
54
5-1.
Internal ROM Capacity ..........................................................................................................
62
5-2.
Vector ....................................................................................................................................
62
5-3.
Special-Function Register List ..............................................................................................
72
6-1.
Port Functions (µPD780308 Subseries) ................................................................................
90
6-2.
Port Functions (µPD780308Y Subseries) .............................................................................
91
6-3.
Port Configuration .................................................................................................................
92
6-4.
Port Mode Register and Output Latch Settings when Using Alternate Functions .................
109
7-1.
Clock Generator Configuration ..............................................................................................
115
7-2.
Relation between CPU Clock and Minimum Instruction Execution Time ..............................
119
7-3.
Maximum Time Required for CPU Clock Switchover ............................................................
128
8-1.
Timer/Event Counter Types and Functions ...........................................................................
132
8-2.
16-Bit Timer/Event Counter Interval Times ...........................................................................
133
8-3.
16-Bit Timer/Event Counter Square-Wave Output Ranges ..................................................
134
8-4.
16-Bit Timer/Event Counter Configuration ............................................................................
135
8-5.
INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge .....................................
138
8-6.
16-Bit Timer/Event Counter Interval Times ...........................................................................
151
8-7.
16-Bit Timer/Event Count Square-Wave Output Ranges ......................................................
165
9-1.
8-Bit Timer/Event Counters 1 and 2 Interval Times ..............................................................
174
9-2.
8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges ......................................
175
9-3.
Interval Times when 8-Bit Timer/Event Counters 1 and 2
are Used as 16-Bit Timer/Event Counters ............................................................................
9-4.
176
Square-Wave Output Ranges when 8-Bit Timer/Event
Counters 1 and 2 are Used as 16-Bit Timer/Event Counters ................................................
177
9-5.
8-Bit Timer/Event Counters 1 and 2 Configurations ..............................................................
178
9-6.
8-Bit Timer/Event Counter 1 Interval Time ............................................................................
188
9-7.
8-Bit Timer/Event Counter 2 Interval Time ............................................................................
189
9-8.
8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges ......................................
191
9-9.
Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2)
9-10.
are Used as 16-Bit Timer/Event Counter ..............................................................................
194
Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters .......................
196
– xv –
LIST OF TABLES (2/3)
Table No.
Title
Page
10-1.
Interval Timer Interval Time ...................................................................................................
201
10-2.
Watch Timer Configuration ...................................................................................................
202
10-3.
Interval Timer Interval Time ...................................................................................................
206
11-1.
Watchdog Timer Inadvertent Program Overrun Detection Times .........................................
207
11-2.
Interval Times ........................................................................................................................
208
11-3.
Watchdog Timer Configuration .............................................................................................
209
11-4.
Watchdog Timer Overrun Detection Time .............................................................................
213
11-5.
Interval Timer Interval Time ...................................................................................................
214
12-1.
Clock Output Control Circuit Configuration ...........................................................................
216
13-1.
Buzzer Output Control Circuit Configuration .........................................................................
221
14-1.
A/D Converter Configuration .................................................................................................
225
15-1.
Differences between Channels 0, 2, and 3 ...........................................................................
241
15-2.
Serial Interface Channel 0 Configuration ..............................................................................
244
15-3.
Various Signals in SBI Mode .................................................................................................
275
16-1.
Differences between Channels 0, 2, and 3 ..........................................................................
291
16-2.
Serial Interface Channel 0 Configuration ..............................................................................
294
16-3.
Serial Interface Channel 0 Interrupt Request Signal Generation ..........................................
297
2
16-4.
Signals in I C Bus Mode ........................................................................................................
326
17-1.
Serial Interface Channel 2 Configuration ..............................................................................
344
17-2.
Serial Interface Channel 2 Operating Mode Settings ............................................................
350
17-3.
Relationships between Main System Clock and Baud Rate .................................................
355
17-4.
Relationships between ASCK Pin Input Frequency and Baud Rate
17-5.
17-6.
(When BRGC is set to 00H) ..................................................................................................
356
Relationships between Main System Clock and Baud Rate .................................................
365
Relationships between ASCK Pin Input Frequency and Baud Rate
(When BRGC is set to 00H) ..................................................................................................
366
17-7.
Receive Error Causes ...........................................................................................................
372
18-1.
Configuration of Serial Interface Channel 3 ..........................................................................
385
19-1.
Maximum Number of Display Pixels .....................................................................................
395
19-2.
LCD Controller/Driver Configuration .....................................................................................
396
19-3.
Frame Frequencies (Hz) .......................................................................................................
400
19-4.
COM Signals .........................................................................................................................
404
– xvi –
LIST OF TABLES (3/3)
Table No.
Title
Page
19-5.
LCD Drive Voltages ...............................................................................................................
405
19-6.
LCD Drive Voltages (with On-Chip Split Resistor) ................................................................
408
19-7.
Selection and Non-Selection Voltages (COM0) ....................................................................
412
19-8.
Selection and Non-Selection Voltages (COM0, COM1) ........................................................
415
19-9.
Selection and Non-Selection Voltages (COM0 to COM2) .....................................................
418
19-10.
Selection and Non-Selection Voltages (COM0 to COM3) .....................................................
422
20-1.
Interrupt Source List ..............................................................................................................
426
20-2.
Various Flags Corresponding to Interrupt Request Sources .................................................
429
20-3.
Times from Maskable Interrupt Request Generation to Interrupt Service .............................
441
20-4.
Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ..........................
444
20-5.
Test Input Factors .................................................................................................................
448
20-6.
Flags Corresponding to Test Input Signals ...........................................................................
448
21-1.
HALT Mode Operating Status ...............................................................................................
455
21-2.
Operation after HALT Mode Release ....................................................................................
457
21-3.
STOP Mode Operating Status ..............................................................................................
458
21-4.
Operation after STOP Mode Release ...................................................................................
460
22-1.
Hardware Status after Reset .................................................................................................
463
23-1.
Differences among µPD78P0308, 78P0308Y, and Mask ROM Versions .............................
465
23-2.
Examples of Internal Memory Size Switching Register Settings ...........................................
466
23-3.
Examples of Internal Expansion RAM Size Switching Register ............................................
467
23-4.
PROM Programming Operating Modes ................................................................................
468
24-1.
Operand Identifiers and Description Methods .......................................................................
478
A-1.
Upgrading Other In-Circuit Emulators to IE-78000-R ............................................................
501
A-2.
Upgrading Other In-Circuit Emulators to IE-78000-R-A ........................................................
501
– xvii –
[MEMO]
– xviii –
CHAPTER 1 OUTLINE (µPD780308 Subseries)
1.1 Features
●
On-chip high-capacity ROM and RAM
Type
Internal High-Speed RAM
Internal Expansion RAM
µPD780306
48 Kbytes
1024 bytes
1024 bytes
µPD780308
60 Kbytes
µPD78P0308
60 Kbytes Note
Part Number
Note
Data Memory
Program Memory
(ROM)
LCD RAM
40 × 4 bits
The capacity of internal PROM can be changed by means of the internal memory size switching register
(IMS).
● Minimum instruction execution time changeable from high speed (0.4 µs: @ 5.0-MHz operation with main system
clock) to ultra-low speed (122 µs: @ 32.768-kHz operation with subsystem clock)
● Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
● Fifty-seven I/O ports (including alternate-function pins for segment signal output)
● LCD Controller / Driver
• Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias:
1/2, 1/3 bias switching possible
• Power supply voltage:
VDD = 2.0 to 5.5 V (can operate in all modes)
● 8-bit resolution A/D converter: 8 channels
● Serial interface: 3 channels
• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel
• 3-wire serial I/O/UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
● Timer: 5 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
● Twenty-one vectored interrupt sources
● Two test inputs
● Two types of on-chip clock oscillators (main system clock and subsystem clock)
● Power supply voltage: VDD = 2.0 to 5.5 V
1
CHAPTER 1
OUTLINE (µPD780308 Subseries)
1.2 Application Field
Cellular phones, pagers, CD players, cameras, meters, etc.
1.3 Ordering Information
Part number
Package
µPD780306GC-×××-8EU Note 1
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Mask ROM
µPD780306GF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD780308GC-×××-8EU Note 1
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Mask ROM
µPD780308GF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD780306GC(A)-×××-8EU Note 2 100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Mask ROM
µPD780306GF(A)-×××-3BA Note 2 100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD780308GC(A)-×××-8EU Note 2 100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Mask ROM
µPD780308GF(A)-×××-3BA Note 2 100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD78P0308GC-8EU Note 1
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
One-time PROM
µPD78P0308GF-3BA
100-pin plastic QFP (14 × 20 mm)
One-time PROM
µPD78P0308KL-T Note 1
100-pin ceramic WQFN
Notes
1. Under development
2. Under planning
Remark
2
Internal ROM
××× indicates ROM code suffix.
EPROM
CHAPTER 1
OUTLINE (µPD780308 Subseries)
1.4 Quality Grade
Part number
Package
Quality grade
µPD780306GC-×××-8EU Note 1
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD780306GF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
µPD780308GC-×××-8EU Note 1
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD780308GF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
µPD780306GC(A)-×××-8EU Note 2 100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD780306GF(A)-×××-3BA Note 2 100-pin plastic QFP (14 × 20 mm)
Standard
µPD780308GC(A)-×××-8EU Note 2 100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD780308GF(A)-×××-3BA Note 2 100-pin plastic QFP (14 × 20 mm)
Standard
µPD78P0308GC-8EU Note 1
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD78P0308GF-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
µPD78P0308KL-T Note 1
100-pin ceramic WQFN
Not applied (for function evaluation)
Notes
1. Under development
2. Under planning
Caution The µPD78P0308KL-T does not have a reliability intended to be used for mass production of your
system. Use this model only for experiment and function evaluation.
Remark
××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to
know the specification of quality grade on the devices and its recommended applications.
3
CHAPTER 1
OUTLINE (µPD780308 Subseries)
1.5 Pin Configuration (Top View)
(1) Normal operating mode
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
µPD780306GC-×××-8EU Note 1, 780308GC-×××-8EU Note 1, 78P0308GC-8EU Note 1,
P10/ANI0
AV SS
P117
P116
P115
P114/RxD
P113/TxD
P112/SCK3
P111/SO3
P110/SI3
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
RESET
XT2
XT1/P07
VDD1
X1
X2
IC (VPP)
P72/SCK2/ASCK
P71/SO2/TxD
µPD780306GC(A)-×××-8EU Note 2, 780308GC(A)-×××-8EU Note 2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P70/SI2/RxD
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
S20
S19
COM3
BIAS
VLC0
VLC1
VLC2
VSS0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
V DD0
AV REF
P100
P101
VSS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
COM0
COM1
COM2
Notes
1. Under development
2. Under planning
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS0 or VSS1 directly.
2. Connect AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the µPD78P0308.
2. When using the µPD780308 Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
4
lines.
CHAPTER 1
OUTLINE (µPD780308 Subseries)
100-pin plastic QFP (14 × 20 mm)
µPD780306GF-×××-3BA, 780308GF-×××-3BA, 78P0308GF-3BA,
µPD780306GF(A)-×××-3BA Note 2, 780308GF(A)-×××-3BA Note 2
100-pin ceramic WQFN
P25/SI0/SB0
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
µPD78P0308KL-T Note 1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
VSS0
VLC2
VLC1
VLC0
BIAS
COM3
COM2
COM1
COM0
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
VDD0
AV REF
P100
P101
VSS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
P26/SO0/SB1
P27/SCK0
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
IC (VPP)
X2
X1
VDD1
XT1/P07
XT2
RESET
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P110/SI3
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115
P116
P117
AV SS
P10/ANI0
P11/ANI1
P12/ANI2
Notes
1. Under development
2. Under planning
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS0 or VSS1 directly.
2. Connect AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the µPD78P0308.
2. When using the µPD780308 Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
5
CHAPTER 1
6
OUTLINE (µPD780308 Subseries)
ANI0 to ANI7
: Analog Input
PCL
: Programmable Clock
ASCK
: Asynchronous Serial Clock
RESET
: Reset
AVREF
: Analog Reference Voltage
RxD
: Receive Data
AVSS
: Analog Ground
S0 to S39
BIAS
: LCD Power Supply Bias Control SB0, SB1
: Segment Output
: Serial Bus
BUZ
: Buzzer Clock
SCK0, SCK2, SCK3 : Serial Clock
COM0 to COM3
: Common Output
SI0, SI2, SI3
: Serial Input
INTP0 to INTP5
: Interrupt from Peripherals
SO0, SO2, SO3
: Serial Output
IC
: Internally Connected
TI00, TI01
: Timer Input
P00 to P05, P07
: Port0
TI1, TI2
: Timer Input
P10 to P17
: Port1
TO0 to TO2
: Timer Output
P25 to P27
: Port2
TxD
: Transmit Data
P30 to P37
: Port3
VDD0, VDD1
: Power Supply
P70 to P72
: Port7
VLC0 to VLC2
: LCD Power Supply
P80 to P87
: Port8
VPP
: Programming Power Supply
P90 to P97
: Port9
VSS0, VSS1
: Ground
P100 to P103
: Port10
X1, X2
: Crystal (Main System Clock)
P110 to P117
: Port11
XT1, XT2
: Crystal (Subsystem Clock)
CHAPTER 1
OUTLINE (µPD780308 Subseries)
(2) PROM programming mode
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
(L)
VDD
VDD
(L)
VSS
(L)
D0
D1
D2
D3
D4
D5
D6
D7
(L)
PGM
(L)
A9
RESET
Open
(L)
VDD
(L)
Open
VPP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(L)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
(L)
(L)
(L)
CE
OE
(L)
µPD78P0308GC-8EU Note
Note
Under development
Cautions 1. (L)
2. VSS
: Connect individually to VSS via a pull-down resistor.
: Connect to the ground.
3. RESET : Set to the low level.
4. Open
: Do not connect anything.
7
CHAPTER 1
OUTLINE (µPD780308 Subseries)
100-pin plastic QFP (14 × 20 mm)
µPD78P0308GF-3BA
100-pin ceramic WQFN
(L)
D0
D1
D2
D3
D4
D5
D6
D7
(L)
(L)
VSS
OE
CE
(L)
(L)
(L)
VPP
Open
(L)
VDD
(L)
Open
RESET
A9
(L)
PGM
VDD
VDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(L)
Note
(L)
(L)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
µPD78P0308KL-T Note
Under development
Cautions 1. (L)
2. VSS
: Connect individually to VSS via a pull-down resistor.
: Connect to the ground.
3. RESET : Set to the low level.
4. Open
8
: Do not connect anything.
A0 to A16
: Address Bus
RESET
: Reset
CE
: Chip Enable
VDD
: Power Supply
D0 to D7
: Data Bus
VPP
: Programming Power Supply
OE
: Output Enable
VSS
: Ground
PGM
: Program
CHAPTER 1
OUTLINE (µPD780308 Subseries)
1.6 78K/0 Series Line-up
The 78K/0 Series product line-up is illustrated below. Part numbers in the boxes indicate subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
µPD78075B
µ PD78075BY
100-pin
µPD78078
µPD78078Y
A timer was added to the µ PD78054, and the external interface function was enhanced.
100-pin
µPD78070A
µPD78070AY
ROM-less versions of the µ PD78078.
100-pin
80-pin
µPD780018Note
µPD780058
µPD780018Y
µPD780058YNote
Serial I/O of the µ PD78078 was enhanced, and only selected functions are provided.
Serial I/O of the µ PD78054 was enhanced, EMI noise reduction version.
80-pin
80-pin
µPD78058F
µPD78054
µPD78058FY
µPD78054Y
EMI noise reduction version of the µ PD78054.
UART and D/A converter were added to the µPD78014, and I/O was enhanced.
64-pin
µPD780034
µPD780034Y
An A/D converter of the µ PD780024 was enhanced.
64-pin
64-pin
µPD780024
µPD78014H
µPD780024Y
64-pin
µPD78018F
µPD78018FY
Low-voltage (1.8 V) operation versions of the µ PD78014 with several ROM and RAM capacities available.
64-pin
64-pin
µPD78014
µPD780001
µPD78014Y
An A/D converter and 16-bit timer were added to the µPD78002.
An A/D converter was added to the µPD78002.
64-pin
µPD78002
µPD78002Y
Basic subseries for control.
42/44-pin
µPD78083
EMI noise reduction version of the µ PD78078.
Serial I/O of the µ PD78018F was enhanced, EMI noise reduction version.
EMI noise reduction version of the µPD78018F.
On-chip UART, capable of operating at a low voltage (1.8 V).
Inverter control
64-pin
µPD780964
An A/D converter of the µPD780924 was enhanced.
64-pin
µPD780924
On-chip inverter control circuit and UART, EMI noise reduction version.
FIPTM drive
78K/0
Series
100-pin
µPD780208
The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53
100-pin
µ PD780228
The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48
80-pin
µPD78044H
N-ch open-drain input/output was added to the µ PD78044F, Display output total: 34
80-pin
µPD78044F
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
µPD780308
100-pin
µPD78064B
100-pin
µPD78064
µPD780308Y
SIO of the µPD78064 was enhanced, and ROM and RAM were expanded.
EMI noise reduction version of the µ PD78064.
µPD78064Y
Basic subseries for driving LCDs, On-chip UART.
IEBusTM supported
80-pin
µPD78098B
EMI noise reduction version of the µPD78098.
80-pin
µPD78098
The IEBus controller was added to the µPD78054.
Meter control
80-pin
µPD780973
Generalize automobile meter driving controller/driver of the µPD780805.
100-pin
µPD780805
On-chip automobile meter driving controller/driver.
LV
64-pin
µPD78P0914
On-chip PWM output, LV digital code decoder, Hsync counter.
9
CHAPTER 1
OUTLINE (µPD780308 Subseries)
Major differences among these subseries are tabulated below.
Function
Subseries Name
µPD78075B
µPD78078
µPD78070A
µPD780018
µPD780058
µPD78058F
µPD78054
µPD780034
µPD780024
µPD78014H
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
Inverter µPD780964
control
µPD780924
FIP
µPD780208
drive
µPD780228
µPD78044H
µPD78044F
LCD
µPD780308
drive
µPD78064B
µPD78064
IEBus
µPD78098B
supported µPD78098
Meter
µPD780973
control
µPD780805
LV
µPD78P0914
Control
Note
10
ROM
Timer
Capacity
8-bit
16-bit
32 K to 40 K
48 K to 60 K
–
48 K to 60 K
24 K to 60 K
48 K to 60 K
16 K to 60 K
8 K to 32 K
4ch
1ch
8-bit 10-bit 8-bit
Watch WDT
1ch
1ch
A/D
8ch
8 K to 60 K
8 K to 32 K
8K
8 K to 16 K
I/O
VDD External
MIN.
Value Expansion
88
1.8 V Available
A/D D/A
–
2ch
–
8ch
Serial Interface
8ch
–
2ch
3ch (UART: 1ch)
–
2ch
61
2ch (time-division 3-wire: 1ch) 88
3ch (time-division UART: 1ch) 68
3ch (UART: 1ch)
69
–
3ch (UART: 1ch,
51
time-division 3-wire: 1ch)
2ch
53
2.7 V
1.8
2.7
2.0
1.8
V
V
V
V
2.7 V
8 K to 32 K
3ch
Note
–
1ch
–
–
32 K to 60 K
48 K to 60 K
32 K to 48 K
16 K to 40 K
48 K to 60 K
32 K
16 K to 32 K
40 K to 60 K
32 K to 60 K
24 K to 32 K
40 K to 60 K
32 K
2ch
3ch
2ch
1ch
–
1ch
1ch
–
1ch
1ch
–
8ch
–
8ch
8ch
2ch
1ch
1ch
1ch
8ch
–
–
2ch
1ch
1ch
1ch
8ch
–
2ch
3ch (UART: 1ch)
69
2.7 V Available
3ch
2ch
6ch
1ch
1ch
1ch
–
–
2ch (UART: 1ch)
–
–
1ch
5ch
8ch
8ch
–
–
2ch
56
39
54
4.5 V
–
2.7 V
4.5 V Available
10-bit timer: 1 channel
–
1ch
1ch
8ch
–
–
–
–
39
53
33
47
–
Available
1.8 V
–
2.7 V Available
74
72
68
2.7 V
4.5 V
2.7 V
–
2ch
3ch (time-division UART: 1ch) 57
2ch (UART: 1ch)
2.0 V
–
1ch (UART: 1ch)
2ch (UART: 2ch)
2ch
1ch
CHAPTER 1
OUTLINE (µPD780308 Subseries)
1.7 Block Diagram
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
16-bit Timer/
Event Counter
Port 0
P07
8-bit Timer/
Event Counter 1
Port 1
P10 to P17
8-bit Timer/
Event Counter 2
Port 2
P25 to P27
Port 3
P30 to P37
Port 7
P70 to P72
Port 8
P80 to P87
Port 9
P90 to P97
Watchdog Timer
Watch Timer
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI2/RxD/P70
SO2/TxD/P71
RxD/P114
TxD/P113
SCK2/ASCK/P72
P00
P01 to P05
Serial
Interface 0
78K/0
CPU Core
ROM
Serial
Interface 2
Port 10
P100 to P103
Port 11
P110 to P117
SI3/P110
SO3/P111
Serial
Interface 3
S0-S23
SCK3/P112
RAM
ANI0/P10 to
ANI7/P17
AVSS
AVREF
INTP0/P00 to
INTP5/P05
LCD
Controller/
Driver
A/D Converter
S24/P97 to
S31/P90
S32/P87 to
S39/P80
COM0 to COM3
VLC0 to VLC2
BIAS
fLCD
Interrupt
Control
BUZ/P36
Buzzer Output
PCL/P35
Clock Output
Control
VDD0,
VDD1
VSS0,
VSS1
IC
(VPP)
System
Control
RESET
X1
X2
XT1/P07
XT2
Remarks 1. The internal ROM capacity differs depending on the product.
2. Pin connection in parentheses is intended for the µPD78P0308.
11
CHAPTER 1
OUTLINE (µPD780308 Subseries)
1.8 Outline of Function
Part Number
µPD780306
Item
Internal
ROM
memory
µPD780308
Mask ROM
PROM
48 Kbytes
High-speed RAM
1024 bytes
Expansion RAM
1024 bytes
LCD RAM
40 × 4 bits
µPD78P0308
60 Kbytes
60 Kbytes Note
General register
8 bits × 8 × 4 banks
Minimum With main system clock selected
instruction
execution With subsystem clock selected
time
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz)
Instruction set
• 16-bit operation
122 µs (@ 32.768 kHz)
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O port (including alternate-function pins
• Total
: 57
for segment signal output)
• CMOS input
• CMOS I/O
:2
: 55
A/D converter
8-bit resolution × 8 channels
LCD controller/driver
• Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible : 1 channel
• 3-wire serial I/O mode / UART mode selection possible
: 1 channel
• 3-wire serial I/O mode
: 1 channel
Timer
•
•
•
•
Timer output
Three outputs: (14-bit PWM output enable: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,
2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)
32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)
Note
12
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
:
:
:
:
1
2
1
1
channel
channels
channel
channel
The capacity of the internal PROM can be changed using the internal memory size switching register (IMS).
CHAPTER 1
Part Number
OUTLINE (µPD780308 Subseries)
µPD780306
Item
Vectored
interrupt
Maskable
Internal: 13
External: 6
source
Non-maskable
Internal: 1
Software
1
µPD780308
Test input
Internal: 1
External: 1
Power supply voltage
VDD = 2.0 to 5.5 V
Operating ambient temperature
TA = –40 to +85 °C
Package
• 100-pin plastic LQFP (Fine pitch) (14 × 14 mm) Note
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin ceramic WQFN (µPD78P0308 only) Note
Note
1.9
µPD78P0308
Under development
Mask Options
The mask ROM versions (µPD780306, 780308) provide split resistor mask options. By specifying this mask options
at the time of ordering, split registers which enable to generate LCD drive voltage suited to each bias method type
can be incorporated. Using this mask option reduces the number of components to add to the device, resulting in
board space saving.
The mask options provided in the µPD780308 Subseries are shown in Table 1-1.
Table 1-1. Mask Options of Mask ROM Versions
Pin names
VLC0 to VLC2
Mask options
Split register can be incorporated.
13
[MEMO]
14
CHAPTER 2 OUTLINE (µPD780308Y Subseries)
2.1 Features
●
On-chip high-capacity ROM and RAM
Type
Internal High-Speed RAM
Internal Expansion RAM
µPD780306Y
48 Kbytes
1024 bytes
1024 bytes
µPD780308Y
60 Kbytes
µPD78P0308Y
60 Kbytes Note
Part Number
Note
Data Memory
Program Memory
(ROM)
LCD RAM
40 × 4 bits
The capacity of internal PROM can be changed by means of the internal memory size switching register
(IMS).
● Minimum instruction execution time changeable from high speed (0.4 µs: @ 5.0-MHz operation with main system
clock) to ultra-low speed (122 µs: @ 32.768-kHz operation with subsystem clock)
● Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
● Fifty-seven I/O ports (including alternate-function pins for segment signal output)
● LCD Controller / Driver
• Segment signal output:
Max. 40
• Common signal output:
Max. 4
• Bias:
1/2, 1/3 bias switching possible
• Power supply voltage:
VDD = 2.0 to 5.5 V (can operate in all modes)
● 8-bit resolution A/D converter: 8 channels
● Serial interface: 3 channels
• 3-wire serial I/O/2-wire serial I/O/I2C bus mode: 1 channel
• 3-wire serial I/O/UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
● Timer: 5 channels
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
● Twenty-one vectored interrupt sources
● Two test inputs
● Two types of on-chip clock oscillators (main system clock and subsystem clock)
● Power supply voltage: VDD = 2.0 to 5.5 V
15
CHAPTER 2
OUTLINE (µPD780308Y Subseries)
2.2 Application Field
Cellular phones, pagers, CD players, cameras, meters, audio equipment, etc.
2.3 Ordering Information
Part number
Package
Internal ROM
µPD780306YGC-×××-8EU Note
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Mask ROM
µPD780306YGF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD780308YGC-×××-8EU Note
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Mask ROM
µPD780308YGF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD78P0308YGC-×××-8EU Note
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
One time PROM
µPD78P0308YGF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
One time PROM
µPD78P0308YKL-T Note
100-pin ceramic WQFN
Note
EPROM
Under development
Remark
××× indicates ROM code suffix.
2.4 Quality Grade
Part number
Package
Quality grade
µPD780306YGC-×××-8EU Note
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD780306YGF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
µPD780308YGC-×××-8EU Note
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD780308YGF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
µPD78P0308YGC-×××-8EU Note
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
Standard
µPD78P0308YGF-×××-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
µPD78P0308YKL-T Note
100-pin ceramic WQFN
Not applied (for function evaluation)
Note
Under development
Caution The µPD78P0308YKL-T does not have a reliability level intended to be used for mass production
of systems. Use this model only for experiment and function evaluation.
Remark
××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to
know the specification of quality grade on the devices and its recommended applications.
16
CHAPTER 2
OUTLINE (µPD78064Y Subseries)
2.5 Pin Configuration (Top View)
(1) Normal operating mode
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
AVREF
P100
9
10
P101
VSS
P102
11
12
13
P103
P30/TO0
14
15
P31/TO1
P32/TO2
16
17
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
18
19
20
21
Note
P72/SCK2/ASCK
X1
X2
IC
XT1/P07
VDD
XT2
P71/SO2/TXD
71
P70/SI2/RXD
P27/SCK0/SCL
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P80/S39
70
69
68
P81/S38
P82/S37
P83/S36
67
66
65
P84/S35
P85/S34
64
63
62
61
60
59
58
57
56
55
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
S20
S19
S18
S13
S14
S15
S16
S17
54
22
53
23
52
24
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM3
BIAS
VLC0
COM0
COM1
COM2
P113
P112
P111
P110
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
RESET
7
8
S6
S7
S8
S9
S10
S11
S12
P17/ANI7
AVDD
5
6
S3
S4
S5
P14/ANI4
P15/ANI5
P16/ANI6
S0
S1
S2
P12/ANI2
P13/ANI3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
2
73
3
72
4
VLC1
VLC2
VSS
P11/ANI1
AVSS
P117
P116
P115
P114
P10/ANI0
µPD780306YGC-×××-8EU Note, 780308YGC-×××-8EU Note, 78P0308YGC-8EU Note
Under development
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS0 or VSS1 directly.
2. Connect AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the µPD78P0308Y.
2. When using the µPD780308Y Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
17
CHAPTER 2
OUTLINE (µPD780308Y Subseries)
100-pin plastic QFP (14 × 20 mm)
µPD780306YGF-×××-3BA, 780308YGF-×××-3BA, 78P0308YGF-3BA
100-pin ceramic WQFN
P25/SI0/SB0/SDA0
P80/S39
P81/S38
P82/S37
P83/S36
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
S22
S21
µPD78P0308YKL-T Note
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
VSS0
VLC2
VLC1
VLC0
BIAS
COM3
COM2
COM1
COM0
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
VDD0
AV REF
P100
P101
VSS1
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
IC (VPP)
X2
X1
VDD1
XT1/P07
XT2
RESET
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P110/SI3
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115
P116
P117
AV SS
P10/ANI0
P11/ANI1
P12/ANI2
Note
Under development
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS0 or VSS1 directly.
2. Connect AVSS pin to VSS0.
Remarks 1. Pin connection in parentheses is intended for the µPD78P0308Y.
2. When using the µPD780308Y Subseries in an application field where the noise generated from
the microcontroller must be reduced, it is recommended to take noise reduction measures by
supplying separate power to VDD0 and VDD1, and connecting VSS0 and VSS1 to separate ground
lines.
18
CHAPTER 2
ANI0 to ANI7
OUTLINE (µPD78064Y Subseries)
: Analog Input
RESET
: Reset
ASCK
: Asynchronous Serial Clock
RxD
: Receive Data
AVREF
: Analog Reference Voltage
S0 to S39
: Segment Output
AVSS
: Analog Ground
SB0, SB1
: Serial Bus
BIAS
: LCD Power Supply Bias Control SCK0, SCK2, SCK3 : Serial Clock
BUZ
: Buzzer Clock
SCL
: Serial Clock
COM0 to COM3
: Common Output
SDA0, SDA1
: Serial Data
INTP0 to INTP5
: Interrupt from Peripherals
SI0, SI2, SI3
: Serial Input
IC
: Internally Connected
SO0, SO2, SO3
: Serial Output
P00 to P05, P07
: Port0
TI00, TI01
: Timer Input
P10 to P17
: Port1
TI1, TI2
: Timer Input
P25 to P27
: Port2
TO0 to TO2
: Timer Output
P30 to P37
: Port3
TxD
: Transmit Data
P70 to P72
: Port7
VDD0, VDD1
: Power Supply
P80 to P87
: Port8
VLC0 to VLC2
: LCD Power Supply
P90 to P97
: Port9
VPP
: Programming Power Supply
P100 to P103
: Port10
VSS0, VSS1
: Ground
P110 to P117
: Port11
X1, X2
: Crystal (Main System Clock)
PCL
: Programmable Clock
XT1, XT2
: Crystal (Subsystem Clock)
19
CHAPTER 2
OUTLINE (µPD780308Y Subseries)
(2) PROM programming mode
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
(L)
VDD
VDD
(L)
VSS
(L)
D0
D1
D2
D3
D4
D5
D6
D7
(L)
PGM
(L)
A9
RESET
Open
(L)
VDD
(L)
Open
VPP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(L)
(L)
(L)
CE
OE
(L)
µPD78P0308YGC-8EU Note
Note
Under development
Cautions 1. (L)
2. VSS
: Connect individually to VSS via a pull-down resistor.
: Connect to the ground.
3. RESET : Set to the low level.
4. Open
20
: Do not connect anything.
(L)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
CHAPTER 2
OUTLINE (µPD78064Y Subseries)
100-pin plastic QFP (14 × 20 mm)
µPD78P0308YGF-3BA
100-pin ceramic WQFN
(L)
D0
D1
D2
D3
D4
D5
D6
D7
(L)
(L)
VSS
OE
CE
(L)
(L)
(L)
VPP
Open
(L)
VDD
(L)
Open
RESET
A9
(L)
PGM
VDD
VDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(L)
Note
(L)
(L)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
µPD78P0308YKL-T Note
Under development
Cautions 1. (L)
2. VSS
: Connect individually to VSS via a pull-down resistor.
: Connect to the ground.
3. RESET : Set to the low level.
4. Open
: Do not connect anything.
A0 to A16
: Address Bus
RESET
: Reset
CE
: Chip Enable
VDD
: Power Supply
D0 to D7
: Data Bus
VPP
: Programming Power Supply
OE
: Output Enable
VSS
: Ground
PGM
: Program
21
CHAPTER 2
OUTLINE (µPD780308Y Subseries)
2.6 78K/0 Series Line-up
The 78K/0 Series product line-up is illustrated below. Part numbers in the boxes indicates subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
µPD78075B
µ PD78075BY
100-pin
µPD78078
µPD78078Y
A timer was added to the µ PD78054, and the external interface function was enhanced.
100-pin
µPD78070A
µPD78070AY
ROM-less versions of the µ PD78078.
100-pin
80-pin
µPD780018Note
µPD780058
µPD780018Y
µPD780058YNote
Serial I/O of the µ PD78078 was enhanced, and only selected functions are provided.
Serial I/O of the µ PD78054 was enhanced, EMI noise reduction version.
80-pin
80-pin
µPD78058F
µPD78054
µPD78058FY
µPD78054Y
EMI noise reduction version of the µ PD78054.
UART and D/A converter were added to the µPD78014, and I/O was enhanced.
64-pin
µPD780034
µPD780034Y
An A/D converter of the µ PD780024 was enhanced.
64-pin
64-pin
µPD780024
µPD78014H
µPD780024Y
64-pin
µPD78018F
µPD78018FY
Low-voltage (1.8 V) operation versions of the µ PD78014 with several ROM and RAM capacities available.
64-pin
64-pin
µPD78014
µPD780001
µPD78014Y
An A/D converter and 16-bit timer were added to the µPD78002.
An A/D converter was added to the µPD78002.
64-pin
µPD78002
µPD78002Y
Basic subseries for control.
42/44-pin
µPD78083
EMI noise reduction version of the µ PD78078.
Serial I/O of the µ PD78018F was enhanced, EMI noise reduction version.
EMI noise reduction version of the µPD78018F.
On-chip UART, capable of operating at a low voltage (1.8 V).
Inverter control
64-pin
µPD780964
An A/D converter of the µPD780924 was enhanced.
64-pin
µPD780924
On-chip inverter control circuit and UART, EMI noise reduction version.
FIP drive
78K/0
Series
100-pin
µPD780208
The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53
100-pin
µ PD780228
The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48
80-pin
µPD78044H
N-ch open-drain input/output was added to the µ PD78044F, Display output total: 34
80-pin
µPD78044F
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
µPD780308
100-pin
µPD78064B
100-pin
µPD78064
µPD780308Y
SIO of the µPD78064 was enhanced, and ROM and RAM were expanded.
EMI noise reduction version of the µ PD78064.
µPD78064Y
Basic subseries for driving LCDs, On-chip UART.
IEBus supported
80-pin
µPD78098B
EMI noise reduction version of the µ PD78098.
80-pin
µPD78098
The IEBus controller was added to the µ PD78054.
Meter control
80-pin
µPD780973
Generalize automobile meter driving controller/driver of the µPD780805.
100-pin
µPD780805
On-chip automobile meter driving controller/driver.
LV
64-pin
22
µPD78P0914
On-chip PWM output, LV digital code decoder, Hsync counter.
CHAPTER 2
OUTLINE (µPD78064Y Subseries)
Major differences among these subseries are tabulated below.
Function
ROM Capacity
Serial Interface
I/O
VDD MIN.
88
1.8 V
61
2.7 V
Subseries
Control
µPD78075BY
32 K to 40 K
µPD78078Y
48 K to 60 K
3-wire/UART
: 1ch
µPD78070AY
—
µPD780018Y
48 K to 60 K
3-wire with automatic transfer/reception function : 1ch
Time-division 3-wire
: 1ch
I2C bus (multi-master supported)
: 1ch
88
µPD780058Y
24 K to 60 K
3-wire/2-wire/I2C
: 1ch
3-wire with automatic transfer/reception function : 1ch
3-wire/time-division UART
: 1ch
68
1.8 V
µPD78058FY
48 K to 60 K
69
2.7 V
µPD78054Y
16 K to 60 K
3-wire/2-wire/I2C
: 1ch
3-wire with automatic transfer/reception function : 1ch
3-wire/UART
µPD780034Y
8 K to 32 K
UART
3-wire
I2C bus (multi-master supported)
: 1ch
: 1ch
: 1ch
51
µPD78018FY
8 K to 60 K
3-wire/2-wire/I2C
: 1ch
3-wire with automatic transfer/reception function : 1ch
53
µPD78014Y
8 K to 32 K
3-wire/2-wire/SBI/I2C
: 1ch
3-wire with automatic transfer/reception function : 1ch
µPD78002Y
8 K to 16 K
3-wire/2-wire/SBI/I2C
: 1ch
µPD780308Y
48 K to 60 K
3-wire/2-wire/I2C
3-wire/time-division UART
3-wire
: 1ch
: 1ch
: 1ch
µPD78064Y
16 K to 32 K
3-wire/2-wire/I2C
3-wire/UART
: 1ch
: 1ch
µPD780024Y
LCD
drive
3-wire/2-wire/I2C
: 1ch
3-wire with automatic transfer/reception function : 1ch
Remark
2.0 V
1.8 V
2.7 V
57
2.0 V
The functions other than the serial interface function are the same as those of the subseries without
Y.
23
CHAPTER 2
OUTLINE (µPD780308Y Subseries)
2.7 Block Diagram
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
16-bit Timer/
Event Counter
Port 0
P07
8-bit Timer/
Event Counter 1
Port 1
P10 to P17
8-bit Timer/
Event Counter 2
Port 2
P25 to P27
Port 3
P30 to P37
Port 7
P70 to P72
Port 8
P80 to P87
Port 9
P90 to P97
Watchdog Timer
Watch Timer
SDA0/SI0/SB0/P25
SDA1/SO0/SB1/P26
SCL/SCK0/P27
SI2/RxD/P70
SO2/TxD/P71
RxD/P114
TxD/P113
SCK2/ASCK/P72
P00
P01 to P05
Serial
Interface 0
78K/0
CPU Core
ROM
Serial
Interface 2
Port 10
P100 to P103
Port 11
P110 to P117
SI3/P110
SO3/P111
Serial
Interface 3
S0 to S23
SCK3/P112
RAM
ANI0/P10 to
ANI7/P17
AV SS
AV REF
INTP0/P00 to
INTP5/P05
LCD
Controller/
Driver
A/D Converter
COM0 to COM3
VLC0 to VLC2
BIAS
fLCD
Interrupt
Control
BUZ/P36
Buzzer Output
PCL/P35
Clock Output
Control
VDD0,
VDD1
VSS0,
VSS1
IC
(VPP)
System
Control
Remarks 1. The internal ROM capacity differs depending on the product.
2. Pin connection in parentheses is intended for the µPD78P0308Y.
24
S24/P97 to
S31/P90
S32/P87 to
S39/P80
RESET
X1
X2
XT1/P07
XT2
CHAPTER 2
OUTLINE (µPD78064Y Subseries)
2.8 Outline of Function
Part Number
µPD780306Y
Item
Internal
memory
ROM
µPD780308Y
Mask ROM
PROM
48 Kbytes
High-speed RAM
1024 bytes
Expansion RAM
1024 bytes
LCD RAM
40 × 4 bits
µPD78P0308Y
60 Kbytes
60 Kbytes Note
General register
8 bits × 8 × 4 banks
Minimum With main system clock selected
instruction
execution With subsystem clock selected
time
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz)
122 µs (@ 32.768 kHz)
Instruction set
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O port (including alternate-function pins
for segment signal output)
A/D converter
LCD controller / driver
• Total
• CMOS input
: 57
:2
• CMOS I/O
: 55
8-bit resolution × 8 channels
• Segment signal output: Max. 40
• Common signal output: Max. 4
• Bias: 1/2, 1/3 bias switching possible
Serial interface
• 3-wire serial I/O/2-wire serial I/O/I2C bus mode selection possible : 1 channel
• 3-wire serial I/O mode/UART mode selection possible
: 1 channel
• 3-wire serial I/O mode
: 1 channel
Timer
•
•
•
•
Timer output
Three outputs: (14-bit PWM output enable: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,
2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)
32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)
Note
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
:
:
:
:
1
2
1
1
channel
channels
channel
channel
The capacity of the internal PROM can be changed using the internal memory switching register (IMS).
25
OUTLINE (µPD780308Y Subseries)
CHAPTER 2
Part Number
µPD780306Y
Item
Vectored
interrupt
source
Maskable
Internal: 13
External: 6
Non-maskable
Internal: 1
Software
1
µPD780308Y
Test input
Internal: 1
External: 1
Power supply voltage
VDD = 2.0 to 5.5 V
Operating ambient temperature
TA = –40 to +85 °C
Package
• 100-pin plastic LQFP (14 × 14 mm) Note
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin ceramic WQFN (µPD78P0308Y only) Note
Note
2.9
µPD78P0308Y
Under development
Mask Options
The mask ROM versions (µPD780306Y, 780308Y) provide split resistor mask options. By specifying this mask
options at the time of ordering, split registers which enable to generate LCD drive voltage suited to each bias method
type can be incorporated. Using this mask option reduces the number of components to add to the device, resulting
in board space saving.
The mask options provided in the µPD780308Y Subseries are shown in Table 2-1.
Table 2-1. Mask Options of Mask ROM Versions
Pin names
VLC0 to VLC2
26
Mask options
Split register can be incorporated.
CHAPTER 3 PIN FUNCTION (µPD780308 Subseries)
3.1 Pin Function List
3.1.1 Normal operating mode pins
(1) Port pins (1/2)
Pin Name Input/Output
Function
After Reset Alternate Function
P00
Input
Port 0.
Input only
Input
INTP0/TI00
P01
Input/
output
7-bit input/output port.
Input/output mode can be specified
bit-wise.
Input
INTP1/TI01
P02
INTP2
If used as an input port, an internal
P03
INTP3
pull-up resistor can be used by
software.
P04
INTP4
P05
INTP5
P07 Note 1
Input
P10 to P17
Input/
output
Input only
Input
XT1
Input
ANI0 to ANI7
Port 2.
3-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Input
SI0/SB0
Input
Port 1.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software Note 2.
P25
Input/
output/
P26
P27
P30
Input/
Port 3.
P31
output
8-bit input/output port.
Input/output mode can be specified bit-wise.
P32
P33
SO0/SB1
SCK0
If used as an input port, an internal pull-up resistor can be used by
software.
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
Notes
1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register
(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).
2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the internal pullup resistor is automatically disabled.
27
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
(1) Port pins (2/2)
Pin Name Input/Output
P70
Input/
output
P71
P72
Function
After Reset Alternate Function
Port 7.
3-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Input
SI2/RxD
SO2/TxD
SCK2/ASCK
P80 to P87
Input/
output
Port 8.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
I/O port / segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
Input
S39 to S32
P90 to P97
Input/
output
Port 9.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Input
S31 to S24
I/O port / segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
P100 to P103
Input/
output
Port 10.
4-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
A resistor can be connected.
LED can be driven directly.
Input
—
P110
Input/
Output
Port 11.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Falling edge can be detected.
Input
SI3
P111
P112
P113
P114
P115 to P117
28
SO3
SCK3
TxD
RxD
—
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
(2) Pins other than port pins (1/2)
Pin Name Input/Output
INTP0
Input
Function
External interrupt request inputs with specifiable valid edges (rising
After Reset Alternate Function
Input
edge, falling edge, both rising and falling edges).
INTP1
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
SI0
Input
Serial interface serial data input.
Input
P25/SB0
SI2
P70/RxD
SI3
P110
SO0
Output
Serial interface serial data output.
Input
P26/SB1
SO2
P71/TxD
SO3
P111
SB0
Input/
SB1
output
SCK0
Input/
SCK2
output
Serial interface serial data input/output.
Input
P25/SI0
P26/SO0
Serial interface serial clock input/output.
Input
P27
P72/ASCK
SCK3
P112
RxD
Input
Asynchronous serial interface serial data input.
Input
P70/SI2, P114
TxD
Output
Asynchronous serial interface serial data output.
Input
P71/SO2, P113
ASCK
Input
Asynchronous serial interface serial clock input.
Input
P72/SCK2
TI00
Input
External count clock input to 16-bit timer (TM0).
Input
P00/INTP0
TI01
Capture trigger signal input to capture register (CR00).
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output
16-bit timer (TM0) output (also used for 14-bit PWM output).
P01/INTP1
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output
Clock output (for main system clock and subsystem clock trimming).
Input
P35
BUZ
Output
Buzzer output.
Input
P36
S0 to S23
Output
Segment signal output of LCD controller/driver.
Output
—
Input
P97 to P90
S24 to S31
S32 to S39
P87 to P80
COM0 to COM3 Output
Common signal output of LCD controller/driver
Output
—
VLC0 to VLC2
—
LCD drive voltage (mask ROM versions can incorporate dividing resistor
(mask option)).
—
—
BIAS
—
Power supply for LCD drive.
—
—
ANI0 to ANI7
Input
A/D converter analog input.
Input
P10 to P17
AVREF
Input
A/D converter reference voltage input (also used for analog power).
—
—
29
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
(2) Pins other than port pins (2/2)
Pin Name Input/Output
AVSS
—
RESET
Function
After Reset Alternate Function
A/D converter ground potential. Same potential as VSS0.
—
—
Input
System reset input.
—
—
X1
Input
Crystal connection for main system clock oscillation.
—
—
X2
—
—
—
XT1
Input
Input
P07
XT2
—
—
—
VDD0
—
Positive power to port.
—
—
VSS0
—
Ground potential of port.
—
—
VDD1
—
Positive power supply (except ports, analogs).
—
—
VSS1
—
Ground potential (except ports, analogs).
—
—
VPP
—
High-voltage application for program write/verify. Connect directly to
VSS0 or VSS1 in normal operating mode.
—
—
IC
—
Internal connection. Connect directly to VSS0 or VSS1.
—
—
Crystal connection for subsystem clock oscillation.
3.1.2 PROM programming mode pins (µPD78P0308 only)
Pin Name Input/Output
Function
RESET
Input
PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.
VPP
Input
High-voltage application for PROM programming mode setting and program write/verify.
A0 to A16
Input
Address bus.
D0 to D7
30
Input/output Data bus.
CE
Input
PROM enable input/program pulse input.
OE
Input
Read strobe input to PROM.
PGM
Input
Program/program inhibit input in PROM programming mode.
VDD
—
Positive power supply.
VSS
—
Ground potential.
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2 Description of Pin Functions
3.2.1 P00 to P05, P07 (Port 0)
These are 7-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for
subsystem clock oscillation.
The following operating modes can be specified bit-wise.
(1) Port mode
P00 and P07 function as input-only ports and P01 to P05 function as input/output ports.
P01 to P05 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they
are used as input ports, internal pull-up resistors can be used to them by defining the pull-up resistor option
register L (PUOL).
(2) Control mode
In this mode, these ports function as an external interrupt request input, an external count clock input to the
timer, and crystal connection for subsystem clock oscillation.
(a) INTP0 to INTP5
INTP0 to INTP5 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.
(b) TI00
Pin for external count clock input to 16-bit timer/event counter.
(c) TI01
Pin for capture trigger signal input to capture register (CR00) of 16-bit timer/event counter.
(d) XT1
Crystal connect pin for subsystem clock oscillation.
31
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2.2 P10 to P17 (Port 1)
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog
input.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports.
They can be specified bit-wise as input or output ports with a port mode register 1 (PM1). If used as input
ports, internal pull-up resistors can be used to these ports by defining the pull-up resistor option register L
(PUOL).
(2) Control mode
These ports function as A/D converter analog input pins (ANI0 to ANI7). The pull-up resistor is automatically
disabled when the pins specified for analog input.
3.2.3 P25 to P27 (Port 2)
These are 3-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/
from the serial interface and clock input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 2 (PM2). When they are used as input ports, internal pull-up resistors can be used to them
by defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data input/output and clock input/output.
(a) SI0, SO0
Serial interface serial data input/output pins.
(b) SCK0
Serial interface serial clock input/output pins.
(c) SB0 and SB1
NEC standard serial bus interface input/output pins.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function the user requires. For the setting, refer to Figure 15-4 “Serial Operating Mode
Register 0 Format”.
32
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2.4 P30 to P37 (Port 3)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock
output and buzzer output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 3 (PM3). When they are used as input ports, internal pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as timer input/output, clock output, and buzzer output.
(a) TI1 and TI2
Pin for external count clock input to the 8-bit timer/event counter.
(b) TO0 to TO2
Timer output pins.
(c) PCL
Clock output pin.
(d) BUZ
Buzzer output pin.
33
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2.5 P70 to P72 (Port 7)
These are 3-bit input/output ports. Beside serving as input/output ports, they function as serial interface data input/
output, clock input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 7 (PM7). When they are used as input ports, internal pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data input/output and clock input/output.
(a) SI2, SO2
Serial interface serial data input/output pins.
(b) SCK2
Serial interface serial clock input/output pin.
(c) RxD, TxD
Asynchronous serial interface serial data input/output pins.
(d) ASCK
Asynchronous serial interface serial clock input pin.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function the user requires. For the setting, refer to Table 17-2 “Serial Interface Channel
2 Operating Mode Settings”.
34
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2.6 P80 to P87 (Port 8)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output
of LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port
mode register 8 (PM8). When they are used as input ports, internal pull-up resistors can be used by defining
the pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S32 to S39) of LCD controller/driver.
3.2.7 P90 to P97 (Port 9)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output
of LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port
mode register 9 (PM9). When they are used as input ports, internal pull-up resistors can be used by defining
the pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal/output pins (S24 to S31) of LCD controller/driver.
3.2.8 P100 to P103 (Port 10)
These are 4-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register
10 (PM10). When they are used as input ports, internal pull-up resistors can be used by defining the pull-up resistor
option register H (PUOH).
LED can be driven directly.
35
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2.9 P110 to P117 (Port 11)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as serial interface data input/
output or clock input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
In this mode, port 11 functions as an 8-bit I/O port. Each bit of the port can be set in the input or output mode
by using port mode register 11 (PM11). When a bit of this port is used in the input mode, internal pull-up resistor
can be used by using pull-up resistor option register H (PUOH).
When the falling edge is detected on a specified bit of this port, test input flag (KRIF) can be set to 1.
(2) Control mode
In this mode, port 11 functions to input/output the data of the serial interface, or to input/output clock.
(a) SI3, SO3
These pins input/output the serial data of the serial interface.
(b) SCK3
This pin inputs/outputs the serial clock of the serial interface.
(c) RxD, TxD
These pins input/output the serial data of the asynchronous serial interface.
Caution When port 11 is used as a serial interface, the I/O and output latches must be set according
to the function used. For how to set these latches, refer to Table 17-2 “Serial Interface
Channel 2 Operating Mode Settings”, and Figure 18-3 “Serial Operating Mode Register 3
Format”.
3.2.10 COM0 to COM3
These are LCD controller/driver common signal output pins. They output common signals under either of the
following conditions:
– when the static mode is selected (COM0 to COM3 outputs)
– when 2-time-division (COM0, COM1 outputs) or 3-time-division (COM0 to COM2 outputs) operation is performed
in 1/2 bias mode
– when 3-time-division (COM0 to COM2 outputs) or 4-time-division (COM0 to COM3 outputs) operation is
performed in 1/3 bias mode
3.2.11
VLC0 to VLC2
These are LCD-driving voltage pins. The mask ROM versions can have split resistors by mask option so that LCD
driving voltage can be supplied inside the VLC0 to VLC2 pins according to the required bias without connecting external
split resistors.
3.2.12
BIAS
These are LCD driving power supply pins. They should be connected to the VLC0 pin to realize user-desired LCD
drive voltages to change resistance division ratios, or should be connected to external resistors together with the VLC0
to VLC2 pins and VSS1 pin to fine-adjust the LCD-driving power voltage.
36
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
3.2.13 AVREF
This pin inputs the reference voltage for the on-chip A/D converter. This pin also functions to supply power to
the internal analog circuit. Supply power to this pin when using the A/D converter.
When not using the A/D converter, connect this pin to the VSS0 line.
3.2.14 AVSS
This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS0 pin even when
A/D converter is not used.
3.2.15 RESET
This is a low-level active system reset input pin.
3.2.16 X1 and X2
Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its
inverted signal to X2.
3.2.17 XT1 and XT2
Crystal resonator connect pins for subsystem clock oscillation.
For external clock supply, input it to XT1 and its inverted signal to XT2.
3.2.18 VDD0, VDD1
VDD0 supplies positive power to the ports.
VDD1 supplies positive power to the circuits other than those of the ports.
3.2.19 VSS0, VSS1
VSS0 is the ground pin of the ports.
VSS1 is the ground pin of the circuits other than those of the ports.
3.2.20 VPP (µPD78P0308 only)
High-voltage apply pin for PROM programming mode setting and program write/verify.
Connect directly to VSS0 or VSS1 in normal operating mode.
3.2.21 IC (Mask ROM version only)
The IC (Internally Connected) pin is provided to set the test mode to check the µPD780308 Subseries at delivery.
Connect it directly to the VSS0 or VSS1 with the shortest possible wire in the normal operating mode.
When a voltage difference is produced between the IC pin and VSS0 or VSS1 pin because the wiring between those
two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.
● Connect IC pins to VSS0 or VSS1 pins directly.
VSS0, 1
IC
As short as possible
VSS0
37
PIN FUNCTION (µPD780308 Subseries)
CHAPTER 3
3.3 Input/output Circuits and Recommended Connection of Unused Pins
Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 3-1 for the configuration of the input/output circuit of each type.
Table 3-1. Pin Input/Output Circuit Types (1/2)
Input/Output
Circuit Type
Input/Output
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-C
Input/Output
16
Input
P10/ANI0 to P17/ANI7
11-B
Input/Output
P25/SI0/SB0
10-B
Pin Name
Recommended Connection of Unused Pins
Connect to VSS0.
Connect independently via a resistor to VSS0.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1
Connect to VDD0.
Connect independently via a resistor to
VDD0 or VSS0.
P26/SO0/SB1
P27/SCK0
P30/TO0
5-H
P31/TO1
P32/TO2
P33/TI1
8-C
P34/TI2
P35/PCL
5-H
P36/BUZ
P37
P70/SI2/RxD
8-C
P71/SO2/TxD
5-H
P72/SCK2/ASCK
8-C
P80/S39 to P87/S32
17-C
P90/S31 to P97/S24
P100 to P103
5-H
P110/SI3
8-C
Connect independently via a resistor to
VDD0.
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115 to P117
S0 to S23
17-B
COM0 to COM3
18-A
VLC0 to VLC2
BIAS
38
—
Output
—
Open
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
Table 3-1. Pin Input/Output Circuit Types (2/2)
Input/Output
Circuit Type
Input/Output
RESET
2
Input
XT2
16
—
Open
AVREF
—
—
Connect to VSS0.
Pin Name
Recommended Connection of Unused Pins
—
AVSS
Connect to VSS0.
IC (Mask ROM version)
Connect directly to VSS0 or VSS1.
VPP (µPD78P0308 version)
39
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
Figure 3-1. Pin Input/Output Circuit of List (1/2)
Type 2
Type 10-B
VDD0
pullup
enable
P-ch
VDD0
data
IN
P-ch
IN/OUT
open drain
output disable
N-ch
VSS0
Schmitt-triggered input with hysteresis characteristics
Type 5-H
pullup
enable
data
pullup
enable
P-ch
P-ch
VDD0
data
VDD0
P-ch
IN/OUT
P-ch
IN/OUT
output
disable
VDD0
Type 11-B
VDD0
N-ch
output
disable
Comparator
N-ch
P-ch
VSS0
+
–
AV SS N-ch
VREF (Threshold voltage)
VSS0
input
enable
input
enable
Type 16
Type 8-C
VDD0
pullup
enable
data
feedback
cut-off
P-ch
VDD0
P-ch
P-ch
IN/OUT
output
disable
40
N-ch
VSS0
XT1
XT2
CHAPTER 3
PIN FUNCTION (µPD780308 Subseries)
Figure 3-1. Pin Input/Output Circuit of List (2/2)
Type 17-C
Type 17-B
VDD0
VLC0
VLC1
P-ch
N-ch
pullup
enable
P-ch
SEG
data
OUT
P-ch
P-ch
VDD0
data
P-ch
IN/OUT
N-ch
VLC2
output
disable
N-ch
N-ch
VSS0
VSS1
input
enable
Type 18-A
VLC0
VLC0
P-ch
VLC1
P-ch
VLC1
N-ch
N-ch
COM
data
P-ch
N-ch
N-ch
P-ch
P-ch
SEG
data
OUT
N-ch
P-ch
P-ch
VLC2
VLC2
N-ch
N-ch
VSS1
VSS1
41
[MEMO]
42
CHAPTER 4 PIN FUNCTION (µPD780308Y Subseries)
4.1 Pin Function List
4.1.1 Normal operating mode pins
(1) Port pins (1/2)
Pin Name Input/Output
Function
After Reset Alternate Function
P00
Input
Port 0.
Input only
Input
INTP0/TI00
P01
Input/
output
7-bit input/output port.
Input/output mode can be specified
bit-wise.
Input
INTP1/TI01
P02
INTP2
If used as an input port, an internal
P03
INTP3
pull-up resistor can be used by
software.
P04
INTP4
P05
INTP5
P07 Note 1
Input
P10 to P17
Input/
output
Input only
Input
XT1
Input
ANI0 to ANI7
Port 2.
3-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Input
SI0/SB0/SDA0
Input
Port 1.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software Note 2.
P25
P26
Input
output/
P27
P30
Input/
Port 3.
P31
output
8-bit input/output port.
Input/output mode can be specified bit-wise.
P32
P33
SO0/SB1/SDA1
SCK0/SCL
If used as an input port, an internal pull-up resistor can be used by
software.
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
Notes
1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register
(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).
2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the internal pullup resistor is automatically disabled.
43
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
(1) Port pins (2/2)
Pin Name Input/Output
P70
P71
Input/
output
P72
Function
After Reset Alternate Function
Port 7.
3-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Input
SI2/RxD
SO2/TxD
SCK2/ASCK
P80 to P87
Input/
output
Port 8.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
I/O port / segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
Input
S39 to S32
P90 to P97
Input/
output
Port 9.
8-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
Input
S31 to S24
I/O port / segment signal output can be specified in 2-bit units by LCD
display control register (LCDC).
P100 to P103
Input/
output
Port 10.
4-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by
software.
LED can be driven directly.
Input
—
P110
Input/
Output
Port 11.
8-bit input/output port.
Input/output mode can be specified bit-wise.
Input
SI3
P111
P112
P113
P114
P115 to P117
44
If used as an input port, an internal pull-up resistor can be used by
software.
Falling edge can be detected.
SO3
SCK3
TxD
RxD
—
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
(2) Pins other than port pins (1/2)
Pin Name Input/Output
INTP0
Input
Function
External interrupt request inputs with specifiable valid edges (rising edge,
After Reset Alternate Function
Input
falling edge, both rising and falling edges).
INTP1
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
SI0
Input
Serial interface serial data input.
Input
P25/SB0/SDA0
SI2
P70/RxD
SI3
P110
SO0
Output
Serial interface serial data output.
Input
P26/SB1/SDA1
SO2
P71/TxD
SO3
P111
SB0
SB1
Input/
output
Serial interface serial data input/output.
Input
P25/SI0/SDA0
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
P26/SO0/SB1
SCK0
SCK2
Input/
output
Serial interface serial clock input/output.
Input
P27/SCL
P72/ASCK
SCK3
P112
SCL
P27/SCK0
RxD
Input
Asynchronous serial interface serial data input.
Input
P70/SI2,P114
TxD
Output
Asynchronous serial interface serial data output.
Input
P71/SO2, P113
ASCK
Input
Asynchronous serial interface serial clock input.
Input
P72/SCK2
TI00
Input
External count clock input to 16-bit timer (TM0).
Input
P00/INTP0
TI01
Capture trigger signal input to capture register (CR00).
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output
16-bit timer (TM0) output (also used for 14-bit PWM output).
P01/INTP1
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output
Clock output (for main system clock and subsystem clock trimming).
Input
P35
BUZ
Output
Buzzer output.
Input
P36
S0 to S23
Output
Segment signal output of LCD controller/driver.
Output
—
Input
P97 to P90
S24 to S31
S32 to S39
P87 to P80
COM0 to COM3 Output
Common signal output of LCD controller/driver.
Output
—
VLC0 to VLC2
—
LCD drive voltage (mask ROM versions can incorporate dividing resistor
(mask option)).
—
—
BIAS
—
Power supply for LCD drive.
—
—
ANI0 to ANI7
Input
A/D converter analog input.
Input
P10 to P17
AVREF
Input
A/D converter reference voltage input (also used for analog power).
—
—
45
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
(2) Pins other than port pins (2/2)
Pin Name Input/Output
AVSS
—
RESET
Function
After Reset Alternate Function
A/D converter ground potential. Same potential as VSS0.
—
—
Input
System reset input.
—
—
X1
Input
Crystal connection for main system clock oscillation.
—
—
X2
—
—
—
XT1
Input
Input
P07
XT2
—
—
—
VDD0
—
Positive power to port.
—
—
VSS0
—
Ground potential of port.
—
—
VDD1
—
Positive power supply (except ports, analogs).
—
—
VSS1
—
Ground potential (except ports, analogs).
—
—
VPP
—
High-voltage application for program write/verify. Connect directly to
VSS0 or VSS1 in normal operating mode.
—
—
IC
—
Internal connection. Connect directly to VSS0 or VSS1.
—
—
Crystal connection for subsystem clock oscillation.
4.1.2 PROM programming mode pins (µPD78P0308Y only)
Pin Name Input/Output
Function
RESET
Input
PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.
VPP
Input
High-voltage application for PROM programming mode setting and program write/verify.
A0 to A16
Input
Address bus.
D0 to D7
46
Input/output Data bus.
CE
Input
PROM enable input/program pulse input.
OE
Input
Read strobe input to PROM.
PGM
Input
Program/program inhibit input in PROM programming mode.
VDD
—
Positive power supply.
VSS
—
Ground potential.
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.2 Description of Pin Functions
4.2.1 P00 to P05, P07 (Port 0)
These are 7-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for
subsystem clock oscillation.
The following operating modes can be specified bit-wise.
(1) Port mode
P00 and P07 function as input-only ports and P01 to P05 function as input/output ports.
P01 to P05 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they
are used as input ports, internal pull-up resistors can be used to them by defining the pull-up resistor option
register L (PUOL).
(2) Control mode
In this mode, these ports function as an external interrupt request input, an external count clock input to the
timer, and crystal connection for subsystem clock oscillation.
(a) INTP0 to INTP5
INTP0 to INTP5 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.
(b) TI00
Pin for external count clock input to 16-bit timer/event counter.
(c) TI01
Pin for capture trigger signal input to capture register (CR00) of 16-bit timer/event counter.
(d) XT1
Crystal connect pin for subsystem clock oscillation.
47
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.2.2 P10 to P17 (Port 1)
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog
input.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports.
They can be specified bit-wise as input or output ports with a port mode register 1 (PM1). If used as input
ports, internal pull-up resistors can be used to these ports by defining the pull-up resistor option register L
(PUOL).
(2) Control mode
These ports function as A/D converter analog input pins (ANI0 to ANI7). The pull-up resistor is automatically
disabled when the pins specified for analog input.
4.2.3 P25 to P27 (Port 2)
These are 3-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/
from the serial interface and clock input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 2 (PM2). When they are used as input ports, internal pull-up resistors can be used to them
by defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data input/output and clock input/output.
(a) SI0, SO0, SB0, SB1, SDA0, SDA1
Serial interface serial data input/output pins.
(b) SCK0, SCL
Serial interface serial clock input/output pins.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function the user requires. For the setting, refer to Figure 16-4 “Serial Operating Mode
Register 0 Format”.
48
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.2.4 P30 to P37 (Port 3)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock
output and buzzer output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 3 (PM3). When they are used as input ports, internal pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as timer input/output, clock output, and buzzer output.
(a) TI1 and TI2
Pin for external clock input to the 8-bit timer/event counter.
(b) TO0 to TO2
Timer output pins.
(c) PCL
Clock output pin.
(d) BUZ
Buzzer output pin.
49
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.2.5 P70 to P72 (Port 7)
These are 3-bit input/output ports. Beside serving as input/output ports, they function as serial interface data input/
output, clock input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 3-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 7 (PM7). When they are used as input ports, internal pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as serial interface data input/output and clock input/output.
(a) SI2, SO2
Serial interface serial data input/output pins.
(b) SCK2
Serial interface serial clock input/output pin.
(c) RxD, TxD
Asynchronous serial interface serial data input/output pins.
(d) ASCK
Asynchronous serial interface serial clock input pin.
Caution When this port is used as a serial interface, the I/O and output latches must be set according
to the function the user requires. For the setting, refer to Table 17-2 “Serial Interface Channel
2 Operating Mode Settings”.
50
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.2.6 P80 to P87 (Port 8)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output
of LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port
mode register 8 (PM8). When they are used as input ports, internal pull-up resistors can be used by defining
the pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S32 to S39) of LCD controller/driver.
4.2.7 P90 to P97 (Port 9)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as segment signal output
of LCD controller/driver.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port
mode register 9 (PM9). When they are used as input ports, internal pull-up resistors can be used by defining
the pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as segment signal output pins (S24 to S31) of LCD controller/driver.
4.2.8 P100 to P103 (Port 10)
These are 4-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register
10 (PM10). When they are used as input ports, internal pull-up resistors can be used by defining the pull-up resistor
option register H (PUOH).
LED can be driven directly.
51
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.2.9 P110 to P117 (Port 11)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as serial interface data input/
output or clock input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
In this mode, port 11 functions as an 8-bit I/O port. Each bit of the port can be set in the input or output mode
by using port mode register 11 (PM11). When a bit of this port is used in the input mode, internal pull-up resistor
can be used by using pull-up resistor option register H (PUOH).
When the falling edge is detected on a specified bit of this port, test input flag (KRIF) can be set to 1.
(2) Control mode
In this mode, port 11 functions to input/output the data of the serial interface, or to input/output clock.
(a) SI3, SO3
These pins input/output the serial data of the serial interface.
(b) SCK3
This pin inputs/outputs the serial clock of the serial interface.
(c) RxD, TxD
These pins input/output the serial data of the asynchronous serial interface.
Caution When port 11 is used as a serial interface, the I/O and output latches must be set according
to the function used. For how to set these latches, refer to Table 17-2 “Serial Interface
Channel 2 Operating Mode Settings”, and Figure 18-3 “Serial Operating Mode Register 3
Format”.
4.2.10 COM0 to COM3
These are LCD controller/driver common signal output pins. They output common signals under either of the
following conditions:
– when the static mode is selected (COM0 to COM3 outputs)
– when 2-time-division (COM0, COM1 outputs) or 3-time-division (COM0 to COM2 outputs) operation is performed
in 1/2 bias mode
– when 3-time-division (COM0 to COM2 outputs) or 4-time-division (COM0 to COM3 outputs) operation is
performed in 1/3 bias mode
4.2.11
VLC0 to VLC2
These are LCD-driving voltage pins. The mask ROM versions can have split resistors by mask option so that LCD
driving voltage can be supplied inside the VLC0 to VLC2 pins according to the required bias without connecting external
split resistors.
4.2.12
BIAS
These are LCD driving power supply pins. They should be connected to the VLC0 pin to realize user-desired LCD
drive voltages to change resistance division ratios, or should be connected to external resistors together with the VLC0
to VLC2 pins and VSS1 pin to fine-adjust the LCD-driving power voltage.
52
CHAPTER 4
4.2.13
PIN FUNCTION (µPD780308Y Subseries)
AVREF
This pin inputs the reference voltage for the on-chip A/D converter. This pin also functions to supply power to
the internal analog circuit. Supply power to this pin when using the A/D converter.
When not using the A/D converter, connect this pin to the VSS0 line.
4.2.14
AVSS
This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS0 pin even when
A/D converter is not used.
4.2.15 RESET
This is a low-level active system reset input pin.
4.2.16 X1 and X2
Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its
inverted signal to X2.
4.2.17 XT1 and XT2
Crystal resonator connect pins for subsystem clock oscillation.
For external clock supply, input it to XT1 and its inverted signal to XT2.
4.2.18 VDD0, VDD1
VDD0 supplies positive power to the ports.
VDD1 supplies positive power to the circuits other than those of the ports.
4.2.19 VSS0, VSS1
VSS0 is the ground pin of the ports.
VSS1 is the ground pin of the circuits other than those of the ports.
4.2.20 VPP (µPD78P0308Y only)
High-voltage apply pin for PROM programming mode setting and program write/verify.
Connect directly to VSS0 or VSS1 in normal operating mode.
4.2.21 IC (Mask ROM version only)
The IC (Internally Connected) pin is provided to set the test mode to check the µPD780308Y Subseries at delivery.
Connect it directly to the VSS0 or VSS1 with the shortest possible wire in the normal operating mode.
When a voltage difference is produced between the IC pin and VSS0 or VSS1 pin because the wiring between those
two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.
● Connect IC pins to VSS0 or VSS1 pins directly.
VSS0, 1 IC
As short as possible
VSS0
53
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
4.3 Input/output Circuits and Recommended Connection of Unused Pins
Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 4-1 for the configuration of the input/output circuit of each type.
Table 4-1. Pin Input/Output Circuit Types (1/2)
Input/Output
Circuit Type
Input/Output
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-C
Input/Output
16
Input
11-B
Input/Output
Pin Name
Recommended Connection of Unused Pins
Connect to VSS0.
Connect independently via a resistor to VSS0.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1
P10/ANI0 to P17/ANI7
P25/SI0/SB0/SDA0
Connect to VDD0.
Connect independently via a resistor
to VDD0 or VSS0.
10-B
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0
5-H
P31/TO1
P32/TO2
P33/TI1
8-C
P34/TI2
P35/PCL
5-H
P36/BUZ
P37
P70/SI2/RxD
8-C
P71/SO2/TxD
5-H
P72/SCK2/ASCK
8-C
P80/S39 to P87/S32
17-C
P90/S31 to P97/S24
P100 to P103
5-H
P110/SI3
8-C
Connect independently via a resistor to
VDD0.
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115 to P117
S0 to S23
17-B
COM0 to COM3
18-A
VLC0 to VLC2
BIAS
54
—
Output
—
Open
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
Table 4-1. Pin Input/Output Circuit Types (2/2)
Input/Output
Circuit Type
Input/Output
RESET
2
Input
XT2
16
—
Open
AVREF
—
—
Connect to VSS0.
Pin Name
Recommended Connection of Unused Pins
—
AVSS
Connect to VSS0.
IC (Mask ROM version)
Connect directly to VSS0 or VSS1.
VPP (µPD78P0308Y version)
55
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
Figure 4-1. Pin Input/Output Circuit Type (1/2)
Type 10-B
Type 2
VDD0
pullup
enable
P-ch
VDD0
data
IN
P-ch
IN/OUT
open drain
output disable
N-ch
VSS0
Schmitt-triggered input with hysteresis characteristics
Type 5-H
pullup
enable
data
pullup
enable
P-ch
P-ch
VDD0
data
VDD0
P-ch
IN/OUT
P-ch
IN/OUT
output
disable
VDD0
Type 11-B
VDD0
N-ch
output
disable
Comparator
N-ch
P-ch
VSS0
+
–
AV SS N-ch
VREF (Threshold voltage)
VSS0
input
enable
input
enable
Type 16
Type 8-C
VDD0
pullup
enable
data
feedback
cut-off
P-ch
VDD0
P-ch
P-ch
IN/OUT
output
disable
56
N-ch
VSS0
XT1
XT2
CHAPTER 4
PIN FUNCTION (µPD780308Y Subseries)
Figure 4-1. Pin Input/Output Circuit Type (2/2)
Type 17-C
Type 17-B
VDD0
VLC0
VLC1
P-ch
N-ch
pullup
enable
P-ch
SEG
data
OUT
P-ch
P-ch
VDD0
data
P-ch
IN/OUT
N-ch
VLC2
output
disable
N-ch
N-ch
VSS0
VSS1
input
enable
Type 18-A
VLC0
VLC0
P-ch
VLC1
P-ch
VLC1
N-ch
N-ch
COM
data
P-ch
N-ch
N-ch
P-ch
P-ch
SEG
data
OUT
N-ch
P-ch
P-ch
VLC2
VLC2
N-ch
N-ch
VSS1
VSS1
57
[MEMO]
58
CHAPTER 5 CPU ARCHITECTURE
5.1 Memory Spaces
The µPD780308 and 780308Y Subseries can access a 64-KB memory space. Figures 5-1 to 5-3 shows memory
maps.
Figure 5-1. Memory Map (µPD780306, 780306Y)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256 × 8 bits
General Registers
32 × 8 bits
Internal High-speed RAM
1024 × 8 bits
FB00H
FAFFH
Reserved
FA80H
FA7FH
LCD RAM
40 × 4 bits
Data memory
space
FA58H
FA57H
Reserved
BFFFH
Program Area
1000H
0FFFH
F800H
F7FFH
CALLF Entry Area
Internal Expansion RAM
1024 × 8 bits
0800H
07FFH
Program Area
F400H
F3FFH
Reserved
C000H
BFFFH
Program
memory
space
0080H
007FH
CALLT Table Area
Internal ROM
49152 × 8 bits
0040H
003FH
Vector Table Area
0000H
0000H
59
CHAPTER 5
CPU ARCHITECTURE
Figure 5-2. Memory Map (µPD780308, 780308Y)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256 × 8 bits
General Registers
32 × 8 bits
Internal High-speed RAM
1024 × 8 bits
FB00H
FAFFH
Reserved
FA80H
FA7FH
LCD RAM
40 × 4 bits
Data memory
space
FA58H
FA57H
Reserved
EFFFH
Program Area
1000H
0FFFH
F800H
F7FFH
CALLF Entry Area
Internal Expansion RAM
1024 × 8 bits
0800H
07FFH
Program Area
F400H
F3FFH
Reserved
F000H
EFFFH
Program
memory
space
0080H
007FH
CALLT Table Area
Internal ROM
61440 × 8 bits
0040H
003FH
Vector Table Area
0000H
60
0000H
CHAPTER 5
CPU ARCHITECTURE
Figure 5-3. Memory Map (µPD78P0308, 78P0308Y)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256 × 8 bits
General Registers
32 × 8 bits
Internal High-speed RAM
1024 × 8 bits
FB00H
FAFFH
Reserved
FA80H
FA7FH
LCD RAM
40 × 4 bits
Data memory
space
FA58H
FA57H
Reserved
EFFFH
Program Area
1000H
0FFFH
F800H
F7FFH
CALLF Entry Area
Internal Expansion RAM
1024 × 8 bits
0800H
07FFH
Program Area
F400H
F3FFH
Reserved
F000H
EFFFH
Program
memory
space
0080H
007FH
CALLT Table Area
Internal ROM
61440 × 8 bits
0040H
003FH
Vector Table Area
0000H
0000H
61
CHAPTER 5
CPU ARCHITECTURE
5.1.1 Internal program memory space
The internal program memory space stores program data and table data. This space is generally accessed with
program counter (PC).
The µPD780308, 780308Y Subseries has on-chip ROM (or PROM) and the capacity of the memory varies
depending on the part number.
Table 5-1. Internal ROM Capacity
Part Number
Internal ROM
Type
µPD780306, 780306Y
Capacity
Mask ROM
µPD780308, 780308Y
µPD78P0308, 78P0308Y
49152 × 8 bits
61440 × 8 bits
PROM
The internal program memory is divided into the following three areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start
addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the
16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.
Table 5-2. Vector Table
Vector Table Address
62
Interrupt Source
0000H
RESET input
0004H
INTWDT
0006H
INTP0
0008H
INTP1
000AH
INTP2
000CH
INTP3
000EH
INTP4
0010H
INTP5
0014H
INTCSI0
0018H
INTSER
001AH
INTSR/INTCSI2
001CH
INTST
001EH
INTTM3
0020H
INTTM00
0022H
INTTM01
0024H
INTTM1
0026H
INTTM2
0028H
INTAD
002AH
INTCSI1
003EH
BRK
CHAPTER 5
CPU ARCHITECTURE
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
5.1.2 Internal data memory space
The µPD780308 and 780308Y Subseries units incorporate the following RAMs.
(1) Internal high-speed RAM
The internal high-speed RAM space consists of 1024 × 8 bits, or addresses FB00H to FEFFH. In this area,
four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area
FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack.
(2) Internal expansion RAM
Internal expansion RAM is allocated to the 1024-byte area of addresses F400H to F7FFH.
(3) LCD display RAM
Addresses FA58H to FA7FH of 40 × 4 bits are allocated for LCD display RAM, However, this area can also
be used as general-purpose RAM.
5.1.3 Special-function register (SFR) area
An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH (Refer
to Table 5-3).
Caution Do not access addresses where the SFR is not assigned.
63
CHAPTER 5
CPU ARCHITECTURE
5.1.4 Data memory addressing
Addressing is to specify the address of the instruction to be executed next or the address of a register or memory
to be manipulated when an instruction is executed.
The address of the instruction to be executed next is specified by the program counter (for details, refer to 5.3
Instruction Address Addressing).
To specify the address of the memory to be manipulated when an instruction is executed, the µPD780308 and
780308Y Subseries are provided with many addressing modes to improve operability. Especially at addresses
corresponding to data memory area (FB00H to FFFFH), particular addressing modes are possible to meet the
functions of the special function registers (SFRs) and general registers. This area is between FB00H and FFFFH.
Figures 5-4 to 5-6 show the data memory addressing modes.
For details of each addressing, refer to 5.4 Operand Address Addressing.
Figure 5-4. Data Memory Addressing (µPD780306, 780306Y)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256 × 8 bits
General Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FA80H
FA7FH
Direct Addressing
LCD RAM
40 × 4 bits
FA58H
FA57H
Reserved
F800H
F7FFH
F400H
F3FFH
Reserved
C000H
BFFFH
Internal ROM
49152 × 8 bits
64
Based Addressing
Based Indexed
Addressing
Internal Expansion RAM
1024 × 8 bits
0000H
Register Indirect
Addressing
CHAPTER 5
CPU ARCHITECTURE
Figure 5-5. Data Memory Addressing (µPD780308, 780308Y)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256 × 8 bits
General Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FA80H
FA7FH
Direct Addressing
LCD RAM
40 × 4 bits
FA58H
FA57H
Reserved
F800H
F7FFH
Register Indirect
Addressing
Based Addressing
Based Indexed
Addressing
Internal Expansion RAM
1024 × 8 bits
F400H
F3FFH
Reserved
F000H
EFFFH
Internal ROM
61440 × 8 bits
0000H
65
CHAPTER 5
CPU ARCHITECTURE
Figure 5-6. Data Memory Addressing (µPD78P0308, 78P0308Y)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256 × 8 bits
General Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FA80H
FA7FH
Direct Addressing
LCD RAM
40 × 4 bits
FA58H
FA57H
Reserved
F800H
F7FFH
F400H
F3FFH
Reserved
F000H
EFFFH
Internal PROM
61440 × 8 bits
66
Based Addressing
Based Indexed
Addressing
Internal Expansion RAM
1024 × 8 bits
0000H
Register Indirect
Addressing
CHAPTER 5
CPU ARCHITECTURE
5.2 Processor Registers
The µPD780308 and 780308Y Subseries units incorporate the following processor registers.
5.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist
of a program counter (PC), a program status word (PSW), and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 5-7. Program Counter Configuration
15
PC
0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 5-8. Program Status Word Configuration
7
PSW
IE
0
Z
RBS1
AC
RBS0
0
ISP
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When IE = 0, interrupt requests are disabled (DI), and all interrupts except the non-maskable interrupt
are disabled.
When IE = 1, the interrupts are enabled. At this time, acknowledging interrupt requests is controlled with
an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
This flag is reset (to 0) upon DI instruction execution or interrupt acknowledgement and is set (to 1) upon
EI instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (to 1). It is reset (to 0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
67
CHAPTER 5
CPU ARCHITECTURE
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (to 1). It is reset (to 0)
in all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupt requests.
When ISP= 0, the vector interrupts assigned a low priority with the priority specify flag registers (PR0L,
PR0H, and PR1L) (refer to 20.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) are
acknowledge disabled. Actual acknowledgement is controlled with the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area (FB00H to FEFFH) can be set as the stack area.
Figure 5-9. Stack Pointer Configuration
15
SP
0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 5-10 and 5-11.
Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before
instruction execution.
Figure 5-10. Data to be Saved to Stack Memory
PUSH rp Instruction
Interrupt and
BRK Instruction
CALL, CALLF, and
CALLT Instruction
SP
SP
SP _ 2
SP _ 2
SP _ 3
PC7 to PC0
SP _ 2
Register Pair Lower
SP _ 2
PC7 to PC0
SP _ 2
PC15 to PC8
SP _ 1
Register Pair Upper
SP _ 1
PC15 to PC8
SP _ 1
PSW
SP
68
SP
SP _ 3
SP
SP
CHAPTER 5
CPU ARCHITECTURE
Figure 5-11. Data to be Reset from Stack Memory
POP rp Instruction
SP
RETI and RETB
Instruction
RET Instruction
SP
Register Pair Lower
SP
PC7 to PC0
SP
PC7 to PC0
SP + 1
Register Pair Upper
SP + 1
PC15 to PC8
SP + 1
PC15 to PC8
SP + 2
PSW
SP + 2
SP
SP + 2
SP
SP + 3
5.2.2 General registers
A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks,
each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H).
Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register
(AX, BC, DE and HL).
They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names
(R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because
of the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interruption for each bank.
69
CHAPTER 5
CPU ARCHITECTURE
Figure 5-12. General Register Configuration
(a) Absolute Name
16-Bit Processing
8-Bit Processing
FEFFH
R7
BANK0
RP3
R6
FEF8H
FEF7H
R5
BANK1
RP2
R4
FEE0H
FEEFH
R3
RP1
BANK2
R2
FEE8H
FEE7H
R1
RP0
BANK3
R0
FEE0H
15
0
7
0
(b) Function Name
16-Bit Processing
8-Bit Processing
FEFFH
H
BANK0
HL
L
FEF8H
FEF7H
D
BANK1
DE
E
FEF0H
FEEFH
B
BC
BANK2
C
FEE8H
FEE7H
A
AX
BANK3
X
FEE0H
15
70
0
7
0
CHAPTER 5
CPU ARCHITECTURE
5.2.3 Special-function register (SFR)
Unlike a general register, each special-function register has special functions.
It is allocated in the FF00H to FFFFH area.
The special-function register can be manipulated like the general register, with the operation, transfer and bit
manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).
When addressing an address, describe an even address.
Table 5-3 gives a list of special-function registers. The meaning of items in the table is as follows.
• Symbol
There are symbols indicating the addresses of the special function registers.
These symbols are reserved words of the RA78K/0 or defined in header file sfrbit.h of CC78K/0, and can be
described as instruction operands when the RA78K/0, ID78K0, and SD78K/0 are used.
• R/W
Indicates whether the corresponding special-function register can be read or written.
R/W : Read/write enable
R
: Read only
W
: Write only
• Manipulatable bit units
“√” indicates the manipulatable bit unit (1, 8, or 16). “—” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon RESET input.
71
CHAPTER 5
CPU ARCHITECTURE
Table 5-3. Special-Function Register List (1/3)
Manipulatable Bit Unit
Address
Special-Function Register (SFR) Name
Symbol
R/W
R/W
After Reset
1 bit
8 bits
16 bits
√
√
—
FF00H
Port0
P0
00H
FF01H
Port1
P1
√
√
—
FF02H
Port2
P2
√
√
—
FF03H
Port3
P3
√
√
—
FF07H
Port7
P7
√
√
—
FF08H
Port8
P8
√
√
—
FF09H
Port9
P9
√
√
—
FF0AH
Port10
P10
√
√
—
FF0BH
Port11
P11
√
√
—
FF10H
Capture/compare register 00
CR00
—
—
√
Capture/compare register 01
CR01
—
—
√
16-bit timer register
TM0
R
—
—
√
0000H
FF16H
Compare register 10
CR10
R/W
—
√
—
Undefined
FF17H
Compare register 20
CR20
—
√
—
FF18H
8-bit timer register 1
—
√
√
0000H
FF19H
8-bit timer register 2
—
√
FF1AH
Serial I/O shift register 0
SIO0
R/W
—
√
—
Undefined
FF1FH
A/D conversion result register
ADCR
R
—
√
—
FF20H
Port mode register 0
PM0
R/W
√
√
—
FF21H
Port mode register 1
PM1
√
√
—
FF22H
Port mode register 2
PM2
√
√
—
FF23H
Port mode register 3
PM3
√
√
—
FF27H
Port mode register 7
PM7
√
√
—
FF28H
Port mode register 8
PM8
√
√
—
FF29H
Port mode register 9
PM9
√
√
—
FF2AH
Port mode register 10
PM10
√
√
—
FF2BH
Port mode register 11
PM11
√
√
—
FF40H
Timer clock select register 0
TCL0
√
√
—
FF41H
Timer clock select register 1
TCL1
—
√
—
FF42H
Timer clock select register 2
TCL2
—
√
—
FF43H
Timer clock select register 3
TCL3
—
√
—
FF44H
Timer clock select register 4
TCL4
—
√
—
FF47H
Sampling clock select register
SCS
—
√
—
FF48H
16-bit timer mode control register
TMC0
√
√
—
Undefined
FF11H
FF12H
FF13H
FF14H
FF15H
72
TMS
TM1
R
TM2
FFH
00H
88H
00H
CHAPTER 5
CPU ARCHITECTURE
Table 5-3. Special-Function Register List (2/3)
Manipulatable Bit Unit
Address
Special-Function Register (SFR) Name
Symbol
R/W
1 bit
8 bits
16 bits
After Reset
√
√
—
TMC2
√
√
—
Capture/compare control register 0
CRC0
√
√
—
04H
FF4EH
16-bit timer output control register
TOC0
√
√
—
00H
FF4FH
8-bit timer output control register
TOC1
√
√
—
FF60H
Serial operating mode register 0
CSIM0
√
√
—
FF61H
Serial bus interface control register
SBIC
√
√
—
FF62H
Slave address register
SVA
—
√
—
Undefined
FF63H
Interrupt timing specify register
SINT
√
√
—
00H
FF6CH
Serial operating mode register 3
CSIM3
√
√
—
FF6DH
Serial I/O shift register 3
SIO3
—
√
—
Undefined
FF70H
Asynchronous serial interface mode register
ASIM
√
√
—
00H
FF71H
Asynchronous serial interface status register
ASIS
R
—
√
—
FF72H
Serial operating mode register 2
CSIM2
R/W
√
√
—
FF73H
Baud rate generator control register
BRGC
—
√
—
FF74H
Transmit shift register
TXS
—
√
—
FFH
Receive buffer register
RXB
√
√
—
00H
FF49H
8-bit timer mode control register
TMC1
FF4AH
Watch timer mode control register
FF4CH
SIO2
R/W
W
00H
R
FF75H
Serial interface pin select register
SIPS
FF80H
A/D converter mode register
ADM
√
√
—
01H
FF84H
A/D converter input select register
ADIS
—
√
—
00H
FFB0H
LCD display mode register
LCDM
√
√
—
FFB2H
LCD display control register
LCDC
√
√
—
FFB8H
Key return mode register
KRM
√
√
—
02H
FFE0H
Interrupt request flag register 0L
IF0L
√
√
√
00H
FFE1H
Interrupt request flag register 0H
IF0H
√
√
FFE2H
Interrupt request flag register 1L
√
√
—
FFE4H
Interrupt mask flag register 0L
MK0L
√
√
√
FFE5H
Interrupt mask flag register 0H
MK0H
√
√
FFE6H
Interrupt mask flag register 1L
√
√
—
FFE8H
Priority order specify flag register 0L
PR0L
√
√
√
FFE9H
Priority order specify flag register 0H
PR0H
√
√
FFEAH
Priority order specify flag register 1L
PR1L
√
√
—
FFECH
External interrupt mode register 0
INTM0
—
√
—
FFEDH
External interrupt mode register 1
INTM1
—
√
—
FFF0H
Internal memory size switching register
IMS
—
√
—
(Note)
FFF2H
Oscillation mode select register
OSMS
W
—
√
—
00H
FFF3H
Pull-up resistor option register H
PUOH
R/W
√
√
—
Note
IF0
R/W
IF1L
MK0
MK1L
PR0
FFH
00H
The value after reset depends on products.
µPD780306, 780306Y: CCH, µPD780308, 780308Y: CFH, µPD78P0308, 78P0308Y: CFH.
73
CHAPTER 5
CPU ARCHITECTURE
Table 5-3. Special-Function Register List (3/3)
Manipulatable Bit Unit
Address
Special-Function Register (SFR) Name
Symbol
R/W
After Reset
1 bit
8 bits
16 bits
IXS
W
—
√
—
0AH
Pull-up resistor option register L
PUOL
R/W
√
√
—
00H
FFF9H
Watchdog timer mode register
WDTM
√
√
—
FFFAH
Oscillation stabilization time select register
OSTS
—
√
—
FFFBH
Processor clock control register
PCC
√
√
—
FFF4H
Internal expansion RAM size switching
register
FFF7H
74
04H
CHAPTER 5
CPU ARCHITECTURE
5.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched
by the following addressing (For details of instructions, refer to 78K/0 Series User’s Manual: Instruction (U12326E).
5.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched.
The
displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists in relative branching from the start address of the following instruction
to the –128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC indicates the start address
of the instruction
after the BR instruction.
PC
+
15
8
α
7
0
6
S
jdisp8
15
0
PC
When S = 0, all bits of α are 0.
When S = 1, all bits of α are 1.
75
CHAPTER 5
CPU ARCHITECTURE
5.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALLF !addr11 instruction
7 6
4
fa10
3
CALLF
to 8
fa7
15
PC
76
0
0
to 0
11 10
0
0
0
1
8 7
0
CHAPTER 5
CPU ARCHITECTURE
5.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
7
Operation Code
6
1
5
1
1
ta4
1
to 0
15
Effective Address
0
7
0
0
0
0
0
Memory (Table)
0
0
8
7
6
0
0
1
5
1 0
0
0
Low Addr.
High Addr.
Effective Address+1
15
8
7
0
PC
77
CHAPTER 5
CPU ARCHITECTURE
5.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
rp
78
7
A
15
PC
0
0
X
8
7
0
CHAPTER 5
CPU ARCHITECTURE
5.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
5.4.1 Implied addressing
[Function]
The register which functions as an accumulator (A and AX) in the general register is automatically (implicity)
addressed.
Of the µPD780308 and 780308Y Subseries instruction words, the following instructions employ
implied
addressing.
Instruction
Register to be Specified by Implied Addressing
MULU
A register for multiplicand and AX register for product storage
DIVUW
AX register for dividend and quotient storage
ADJBA/ADJBS
A register for storage of numeric values which become decimal correction targets
ROR4/ROL4
A register for storage of digit data which undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
79
CHAPTER 5
CPU ARCHITECTURE
5.4.2 Register addressing
[Function]
The general register to be specified is accessed as an operand with the register bank select flag (RBS0 and RBS1)
and with the register specify code (Rn and RPn) in an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute
names (R0 to R7 and RP0 to RP3).
[Description example]
MOV A, C; when selecting C register as r
Operation code
0 1 1 0 0 0 1 0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code
1 0 0 0 0 1 0 0
Register specify code
80
CHAPTER 5
CPU ARCHITECTURE
5.4.3 Direct addressing
[Function]
This addressing is to directly address the memory indicated by the immediate data in the instruction word.
[Operand format]
Identifier
Description
addr16
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; when setting !addr16 to FE00H
Operation code
1 0 0 0 1 1 1 0
OP code
0 0 0 0 0 0 0 0
00H
1 1 1 1 1 1 1 0
FFH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (upper)
Memory
81
CHAPTER 5
CPU ARCHITECTURE
5.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to a fixed 256-byte space of FE20H through FF1FH. An internal high-speed RAM
and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H through FF1FH) to which short direct addressing is applied, is a part of the entire SFR
area. Ports which are frequency accessed in a program, and compare registers capture registers of timers/event
counters are mapped to this area and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] on the next page.
[Operand format]
Identifier
82
Description
saddr
Label of FE20H to FF1FH immediate data
saddrp
Label of FE20H to FF1FH immediate data (even address only)
CHAPTER 5
CPU ARCHITECTURE
[Description example]
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code
0 0 0 1 0 0 0 1
OP code
0 0 1 1 0 0 0 0
30H (saddr-offset)
0 1 0 1 0 0 0 0
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short Direct Memory
15
Effective Address
1
8 7
1
1
1
1
1
1
0
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
83
CHAPTER 5
CPU ARCHITECTURE
5.4.5 Special-function register (SFR) addressing
[Function]
The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
Description
sfr
Special-function register name
sfrp
16-bit manipulatable special-function register name (even address only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1 1 1 1 0 1 1 0
OP code
0 0 1 0 0 0 0 0
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
15
Effective Address
84
1
8 7
1
1
1
1
1
1
1
0
CHAPTER 5
CPU ARCHITECTURE
5.4.6 Register indirect addressing
[Function]
This addressing is to address a memory area to be manipulated by using as an operand address the contents
of a register pair specified by the register bank select flags (RBS0 and RBS1) and the register pair specification
code in the operation code.
[Operand format]
Identifier
—
Description
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1 0 0 0 0 1 0 1
[Illustration]
15
8 7
E
D
DE
0
7
Memroy
0
The memroy address
specified with the
register pair DE
The contents of the
memory addressed
are transferred.
7
0
A
85
CHAPTER 5
CPU ARCHITECTURE
5.4.7 Based addressing
[Function]
This addressing is to address the memory by using the result of adding 8-bit immediate data to the contents of
the HL register pair that is used as a base register. The HL register pair to be accessed is in the register bank
specified with the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset
data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out
for all the memory spaces.
[Operand format]
Identifier
—
Description
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1 0 1 0 1 1 1 0
0 0 0 1 0 0 0 0
86
CHAPTER 5
CPU ARCHITECTURE
5.4.8 Based indexed addressing
[Function]
This addressing is to address the memory by using the result of adding the contents of the B or C register specified
in the instruction word to the contents of the HL register that is used as a base register. The H, B, and C registers
accessed are in the register bank specified by the register bank select registers (RBS0 and RBS1). The addition
is executed with the contents of the B or C register extended to 16 bits as a positive number. A carry from the
16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
—
Description
[HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B]
Operation code
1 0 1 0 1 0 1 1
5.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN
instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing enables to address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Operation code
1 0 1 1 0 1 0 1
87
[MEMO]
88
CHAPTER 6 PORT FUNCTIONS
6.1 Port Functions
The µPD780308 and 780308Y Subseries units incorporate two input ports and 55 input/output ports. Figure 61 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably
varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins.
Figure 6-1. Port Types
P80
P00
Port 0
Port 8
P05
P87
P07
P90
P10
Port 9
Port 1
P97
P17
P100
P25
Port 2
Port 10
P103
P27
P30
P110
Port 3
Port 11
P37
P117
P70
Port 7
P72
89
CHAPTER 6
PORT FUNCTIONS
Table 6-1. Port Functions (µPD780308 Subseries)
Pin Name
P00
P01
P02
Function
Port 0.
7-bit input/output port.
Alternate Function
Input only
INTP0/TI00
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up
resistor can be used by software.
INTP1/TI01
INTP2
P03
INTP3
P04
INTP4
P05
INTP5
P07
Input only
XT1
P10 to P17
Port 1.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
ANI0 to ANI7
P25
Port 2.
3-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
SI0/SB0
P26
P27
P30
P31
SO0/SB1
SCK0
Port 3.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
TO0
TO1
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P70
P71
Port 7.
3-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
P72
SI2/RxD
SO2/TxD
SCK2/ASCK
P80 to P87
Port 8.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
S39 to S32
P90 to P97
Port 9.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
S31 to S24
P100 to P103
Port 10.
4-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
This port can directly drive LEDs.
—
P110
Port 11.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
Falling edge detection is possible.
SI3
P111
P112
SO3
SCK3
P113
TxD
P114
RxD
P115 to P117
—
90
CHAPTER 6
PORT FUNCTIONS
Table 6-2. Port Functions (µPD780308Y Subseries)
Pin Name
P00
P01
P02
Function
Port 0.
7-bit input/output port.
Alternate Function
Input only
INTP0/TI00
Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up
resistor can be used by software.
INTP1/TI01
INTP2
P03
INTP3
P04
INTP4
P05
INTP5
P07
Input only
P10 to P17
Port 1.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
P25
Port 2.
3-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
P26
P27
P30
P31
XT1
ANI0 to ANI7
SI0/SB0/SDA0
SO0/SB1/SDA1
SCK0/SCL
Port 3.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
TO0
TO1
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P70
P71
Port 7.
3-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
P72
SI2/RxD
SO2/TxD
SCK2/ASCK
P80 to P87
Port 8.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
S39 to S32
P90 to P97
Port 9.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
This port can be used as a segment signal output port or an I/O port in 2-bit units
by setting LCD display control register (LCDC).
S31 to S24
P100 to P103
Port 10.
4-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
This port can directly drive LEDs.
P110
Port 11.
8-bit input/output port. Input/output mode can be specified bit-wise.
If used as an input port, an internal pull-up resistor can be used by software.
Falling edge detection is possible.
P111
P112
—
SI3
SO3
SCK3
P113
TxD
P114
RxD
P115 to P117
—
91
CHAPTER 6
PORT FUNCTIONS
6.2 Port Configuration
A port consists of the following hardware:
Table 6-3. Port Configuration
Item
Configuration
Control register
Port mode register (PMm: m = 0 to 3, 7 to 11)
Pull-up resistor option register (PUOH, PUOL)
Key return mode register (KRM)
Port
Total: 57 ports (2 inputs, 55 inputs/outputs)
Pull-up resistor
Total: 55 (software specifiable: 55)
6.2.1 Port 0
Port 0 is an 7-bit input/output port with output latch. P01 to P05 pins can specify the input mode/output mode in
1-bit units with the port mode register 0. P00 and P07 pins are input-only ports. When P01 to P05 pins are used
as input ports, an internal pull-up resistor can be used to them in 5-bit units with a pull-up resistor option register L.
Alternate functions include external interrupt request input, external count clock input to the timer and crystal
connection for subsystem clock oscillation.
RESET input sets port 0 to input mode.
Figures 6-2 and 6-3 show block diagrams of port0.
Caution Because port 0 also serves for external interrupt request input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. Thus, when
the output mode is used, set the interrupt mask flag to 1.
92
CHAPTER 6
PORT FUNCTIONS
Figure 6-2. P00 and P07 Block Diagram
Internal Bus
RD
P00/INTP0/TI00,
P07/XT1
Figure 6-3. P01 to P05 Block Diagram
VDD0
WRPUO
PUO0
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P01 to P05)
P01/INTP1/TI01.
P02/INTP2
P05/INTP5
WRPM
PM01 to PM05
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 0 read signal
WR : Port 0 write signal
93
CHAPTER 6
PORT FUNCTIONS
6.2.2 Port 1
Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with
a port mode register 1. When P10 to P17 pins are used as input ports, an internal pull-up resistor can be used to
them in 8-bit units with a pull-up resistor option register L.
Alternate functions include an A/D converter analog input.
RESET input sets port 1 to input mode.
Figure 6-4 shows a block diagram of port 1.
Caution A pull-up resistor cannot be used for pins used as A/D converter analog input.
Figure 6-4. P10 to P17 Block Diagram
VDD0
WRPUO
PUO1
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P10 to P17)
WRPM
PM10 to PM17
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 1 read signal
WR : Port 1 write signal
94
P10/ANI0,
P17/ANI7
CHAPTER 6
PORT FUNCTIONS
6.2.3 Port 2 (µPD780308 Subseries)
Port 2 is an 3-bit input/output port with output latch. P25 to P27 pins can specify the input mode/output mode in
1-bit units with the port mode register 2. When P25 to P27 pins are used as input ports, an internal pull-up resistor
can be used to them in 3-bit units with a pull-up resistor option register L.
Alternate functions include serial interface data input/output and clock input/output.
RESET input sets port 2 to input mode.
Figures 6-5 and 6-6 show a block diagram of port 2.
Cautions 1.
When used as a serial interface, set the input/output and output latch according to its
functions. For the setting method, refer to Figure 15-4 Serial Operating Mode Register 0
Format.
2.
When reading the pin state in SBI mode, set PM2n to 1 (n = 5, 6) (Refer to the description
of (10) “Identifying busy status of slave” in section 15.4.3 SBI mode operation).
Figure 6-5. P25, P26 Block Diagram (µPD780308 Subseries)
VDD0
WRPUO
PUO2
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P25 and P26)
P25/SI0/SB0,
P26/SO0/SB1
WRPM
PM25 and PM26
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 2 read signal
WR : Port 2 write signal
95
CHAPTER 6
PORT FUNCTIONS
Figure 6-6. P27 Block Diagram (µPD780308 Subseries)
VDD0
WRPUO
PUO2
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P27)
WRPM
PM27
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 2 read signal
WR : Port 2 write signal
96
P27/SCK0
CHAPTER 6
PORT FUNCTIONS
6.2.4 Port 2 (µPD780308Y Subseries)
Port 2 is an 3-bit input/output port with output latch. P25 to P27 pins can specify the input mode/output mode in
1-bit units with the port mode register 2. When P25 to P27 pins are used as input ports, an internal pull-up resistor
can be used to them in 3-bit units with a pull-up resistor option register L.
Alternate functions include serial interface data input/output and clock input/output.
RESET input sets port 2 to input mode.
Figures 6-7 and 6-8 show a block diagram of port 2.
Caution When used as a serial interface, set the input/output and output latch according to its functions.
For the setting method, refer to Figure 16-4 Serial Operating Mode Register 0 Format.
Figure 6-7. P25, P26 Block Diagram (µPD780308Y Subseries)
VDD0
WRPUO
PUO2
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P25 and P26)
P25/SI0/SB0/SDA0,
P26/SO0/SB1/SDA1
WRPM
PM25 and PM26
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 2 read signal
WR : Port 2 write signal
97
CHAPTER 6
PORT FUNCTIONS
Figure 6-8. P27 Block Diagram (µPD780308Y Subseries)
VDD0
WRPUO
PUO2
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P27)
WRPM
PM27
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 2 read signal
WR : Port 2 write signal
98
P27/SCK0/SCL
CHAPTER 6
PORT FUNCTIONS
6.2.5 Port 3
Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in
1-bit units with the port mode register 3. When P30 to P37 pins are used as input ports, an internal pull-up resistor
can be used to them in 8-bit units with a pull-up resistor option register L.
Alternate functions include timer input/output, clock output and buzzer output.
RESET input sets port 3 to input mode.
Figure 6-9 shows a block diagram of port 3.
Figure 6-9. P30 to P37 Block Diagram
VDD0
WRPUO
PUO3
P-ch
RD
Internal Bus
Selector
WRPORT
P30/TO0
Output Latch
(P30 to P37)
WRPM
P32/TO2,
P33/TI1,
P34/TI2,
P35/PCL,
P36/BUZ,
P37
PM30 to PM37
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 3 read signal
WR : Port 3 write signal
99
CHAPTER 6
PORT FUNCTIONS
6.2.6 Port 7
This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means
of port mode register 7. When pins P70 to P72 are used as input port pins, an internal pull-up resistor can be used
as a 3-bit unit by means of pull-up resistor option register L.
Alternate functions include serial interface channel 2 data input/output and clock input/output.
RESET input sets the input mode.
Port 7 block diagrams are shown in Figures 6-10 and 6-11.
Caution When used as a serial interface, set the input/output and output latch according to its functions.
For the setting method, refer to Table 17-2 Serial Interface Channel 2 Operating Mode Settings.
Figure 6-10. P70 Block Diagram
VDD0
WRPUO
PUO7
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P70)
WRPM
PM70
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 7 read signal
WR : Port 7 write signal
100
P70/SI2/RxD
CHAPTER 6
PORT FUNCTIONS
Figure 6-11. P71 and P72 Block Diagram
VDD0
WRPUO
PUO7
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P71 and P72)
P71/SO2/TxD,
P72/SCK2/ASCK
WRPM
PM71 and PM72
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 7 read signal
WR : Port 7 write signal
101
CHAPTER 6
PORT FUNCTIONS
6.2.7 Port 8
This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means
of port mode register 8. When pins P80 to P87 are used as input port pins, an internal pull-up resistor can be used
as an 8-bit unit by means of pull-up resistor option register H.
These pins are alternate-function pins and serve as LCD controller/driver segment signal outputs.
RESET input sets the input mode.
The port 8 block diagram is shown in Figure 6-12.
Figure 6-12. P80 to P87 Block Diagram
VDD0
WRPUO
PUO8
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P80 to P87)
WRPM
PM80 to PM87
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 8 read signal
WR : Port 8 write signal
102
P80/S39
P87/S32
CHAPTER 6
PORT FUNCTIONS
6.2.8 Port 9
This is a 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means
of port mode register 9. When pins P90 and P97 are used as input port pins, an internal pull-up resistor can be used
as a 8-bit unit by means of pull-up resistor option register H.
These pins are alternate-function pins and serve as LCD controller/driver segment signal outputs.
RESET input sets the input mode.
The port 9 block diagram is shown in Figure 6-13.
Figure 6-13. P90 to P97 Block Diagram
VDD0
WRPUO
PUO9
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P90 to P97)
P90/S31
P97/S24
WRPM
PM90 to PM97
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 9 read signal
WR : Port 9 write signal
103
CHAPTER 6
PORT FUNCTIONS
6.2.9 Port 10
This is a 4-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means
of port mode register 10. When pins P100 and P103 are used as input port pins, an internal pull-up resistor can be
used as a 4-bit unit by means of pull-up resistor option register H.
RESET input sets the input mode.
The port 10 block diagram is shown in Figure 6-14.
Figure 6-14. P100 to P103 Block Diagram
VDD0
WRPUO
PUO10
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P100 to P103)
WRPM
PM100 to PM103
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 10 read signal
WR : Port 10 write signal
104
P100 to P103
CHAPTER 6
PORT FUNCTIONS
6.2.10 Port 11
Port 11 is an 8-bit input/output port with output latches. P110 to P117 pins can specify the input mode/output mode
in 8-bit units with the port mode register 11. When they are used as input ports, an internal pull-up resistor can be
connected to them in 8-bit units with pull-up resistor option register H.
This port also has a function to input/output the data and clock of the serial interface.
When this function is not used, the test input flag (KRIF) can be set to 1 when the falling edge is detected on this
port.
Alternate functions include address/data bus function in external memory expansion mode.
RESET input sets port 11 to input mode.
Figures 6-15 to 6-17 show the block diagrams of port 11, and Figure 6-18 shows the falling edge detection circuit,
respectively.
Caution When using this port as the serial interface, the I/O latch and output latch must be set according
to the function to be used. For how to set these latches, refer to Table 17-2 "Serial Interface
Channel 2 Operating Mode Settings" and Figure 18-3 “Serial Operating Mode Register 3 Format.”
Figure 6-15. P110, P114 to P117 Block Diagram
VDD0
WRPUO
PUO11
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P110, P114 to P117)
P110/SI3
P114/RxD
P115 to P117
WRPM
PM110, PM114 to PM117
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 11 read signal
WR : Port 11 write signal
105
CHAPTER 6
PORT FUNCTIONS
Figure 6-16. P111 Block Diagram
VDD0
WRPUO
PUO11
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P111)
WRPM
PM111
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 11 read signal
WR : Port 11 write signal
106
P111/SO3
CHAPTER 6
PORT FUNCTIONS
Figure 6-17. P112 and P113 Block Diagram
VDD0
WRPUO
PUO11
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P112 and P113)
P112/SCK3,
P113/TxD
WRPM
PM112 and PM113
Alternate Function
PUO : Pull-up resistor option register
PM
: Port mode register
RD
: Port 11 read signal
WR : Port 11 write signal
Figure 6-18. Block Diagram of Falling Edge Detection Circuit
Key return mode register (KRM)
P110/SI3
P113/TXD
P114/RXD
P115
P116
P117
Note
Selector Note
P111/SI3
P112/SCK3
Falling Edge
Detection Circuit
KRMK
KRIF setting signal
Standby release signal
Selector that selects a pin used to input the falling edge
107
CHAPTER 6
PORT FUNCTIONS
6.3 Port Function Control Registers
The following three types of registers control the ports.
• Port mode registers (PM0 to PM3, PM7 to PM11)
• Pull-up resistor option register (PUOH, PUOL)
• Key return mode register (KRM)
(1) Port mode registers (PM0 to PM3, PM7 to PM11)
These registers are used to set port input/output in 1-bit units.
PM0 to PM3 and PM7 to PM11 are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets registers to FFH.
When port pins are used as the alternate-function pins, set the port mode register and output latch according
to Table 6-4.
Cautions 1. Pins P00 and P07 are input-only pins.
2. As port 0 has an alternate function as external interrupt request input, when the port
function output mode is specified and the output level is changed, the interrupt
request flag is set. When the output mode is used, therefore, the interrupt mask flag
should be set to 1 beforehand.
3. Port 11 has a falling edge detection function. Do not specify the pin of this port to
input the falling edge in a mode other than port mode. For how to set this port to
falling edge input, refer to Figure 6-21 “Key Return Mode Register Format.”
108
CHAPTER 6
PORT FUNCTIONS
Table 6-4. Port Mode Register and Output Latch Settings when Using Alternate Functions
Alternate Functions
Pin Name
Name
P00
P××
INTP0
Input
1 (Fixed)
None
TI00
Input
1 (Fixed)
None
INTP1
Input
1
×
TI01
Input
1
×
P02 to P05
INTP2 to INTP5
Input
1
×
P07 Note 1
XT1
Input
1 (Fixed)
None
ANI0 to ANI7
Input
1
×
P30 to P32
TO0 to TO2
Output
0
0
P33, P34
TI1, TI2
Input
1
×
P35
PCL
Output
0
0
P36
BUZ
Output
0
0
P80 to P87
S39 to S32
Output
× Note 2
P90 to P97
S31 to S24
Output
× Note 2
P01
P10 to P17
Notes
PM××
Input/Output
Note 1
1. If these ports are read out when these pins are used in the alternate function mode, undefined values
are read.
2. When the P80 to P87 and P90 to P97 pins are used for alternate functions, set the function by the
LCD display control register (LCDC).
Caution When port 2, port 7, and port 11 are used for serial interface, the I/O latch or output latch must
be set according to their function. For the setting methods, see Figure 15-4 “Serial Operating
Mode Register 0 Format,” Figure 16-4 “Serial Operating Mode Register 0 Format,” Table 17-2
“Serial Interface Channel 2 Operating Mode Settings”, and Figure 18-3 “Serial Operating Mode
Register 3 Format.”
Remarks ×
: don’t care
PM×× : port mode register
P××
: port output latch
109
CHAPTER 6
PORT FUNCTIONS
Figure 6-19. Port Mode Register Format
Symbol
7
6
PM0
1
1
4
3
2
1
PM05 PM04 PM03 PM02 PM01
0
Address
After
Reset
R/W
1
FF20H
FFH
R/W
PM1
PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
FF21H
FFH
R/W
PM2
PM27 PM26 PM25
FF22H
FFH
R/W
PM3
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
FF23H
FFH
R/W
PM72 PM71 PM70
FF27H
FFH
R/W
PM8
PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80
FF28H
FFH
R/W
PM9
PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90
FF29H
FFH
R/W
PM103 PM102 PM101 PM100
FF2AH
FFH
R/W
PM11 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110
FF2BH
FFH
R/W
PM7
PM10
1
1
PMmn
110
5
1
1
1
1
1
1
1
1
1
1
1
1
Pmn Pin Input/Output Mode Selection (m = 0 to 3, 7 to 11 : n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
CHAPTER 6
PORT FUNCTIONS
(2) Pull-up resistor option register (PUOH, PUOL)
This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor
is internally used at bits which are set to the input mode at a port where internal pull-up resistor use has been
specified with PUOH, PUOL. No internal pull-up resistors can be used to the bits set to the output mode or
to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.
PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
2. When ports 1, 8, and 9 are used as alternate-function pins, an internal pull-up resistor
cannot be used even if 1 is set in PUOm (m = 1, 8, 9).
Figure 6-20. Pull-Up Resistor Option Register Format
Symbol
7
6
5
4
PUOH
0
0
0
0
7
6
5
4
PUO7
0
0
0
PUOL
PUOm
Caution
3
2
1
0
PUO11 PUO10 PUO9 PUO8
3
2
1
Address
After
Reset
R/W
FFF3H
00H
R/W
FFF7H
00H
R/W
0
PUO3 PUO2 PUO1 PUO0
Pm Internal Pull-up Resistor Selection (m = 0 to 3, 7 to 11)
0
Internal pull-up resistor not used
1
Internal pull-up resistor used
Zeros must be set to bits 4 to 7 of PUOH and bits 4 to 6 of PUOL.
111
CHAPTER 6
PORT FUNCTIONS
(3) Key return mode register (KRM)
This register sets enabling/disabling of standby function release by a key return signal (falling edge detection
of port 11), and selects the port 11 falling edge input.
KRM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM to 02H.
Figure 6-21. Key Return Mode Register Format
Symbol
7
6
5
4
KRM
0
0
0
0
3
2
1
0
KRM3 KRM2 KRMK KRIF
KRM3 KRM2
Address
After
Reset
R/W
FFB8H
02H
R/W
Selection of Port 11 Falling Edge Input
0
0
P117
0
1
P114 to P117
1
0
P112 to P117
1
1
P110 to P117
Standby Mode Control by Key Return Signal
KRMK
0
Standby mode release enabled
1
Standby mode release disabled
Key Return Signal Detection Flag
KRIF
0
Not Detected
1
Detected (Falling edge detection of port 11)
Caution When falling edge detection of port 11 is used, KRIF should be cleared to 0 (not cleared to
0 automatically).
112
CHAPTER 6
PORT FUNCTIONS
6.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
6.4.1 Writing to input/output port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from
the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status
does not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output
pins, the output latch contents for pins specified as input are undefined except for the
manipulated bit.
6.4.2 Reading from input/output port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
6.4.3 Operations on input/output port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output
pins, the output latch contents for pins specified as input are undefined, even for bits other
than the manipulated bit.
113
[MEMO]
114
CHAPTER 7 CLOCK GENERATOR
7.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two
types of system clock oscillators are available.
(1) Main system clock oscillator
This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the processor clock control register (PCC).
(2) Subsystem clock oscillator
The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock
oscillator is not used, not using the internal feedback resistance can be set by the processor clock control
register (PCC). This enables to decrease power consumption in the STOP mode.
7.2 Clock Generator Configuration
The clock generator consists of the following hardware.
Table 7-1. Clock Generator Configuration
Item
Configuration
Control register
Processor clock control register (PCC)
Oscillation mode selection register (OSMS)
Oscillator
Main system clock oscillator
Subsystem clock oscillator
115
CHAPTER 7
CLOCK GENERATOR
Figure 7-1. Clock Generator Block Diagram
FRC
X1
X2
f XT
Main
System
Clock
Oscillator
fX
Watch Timer,
Clock Output
Function
Prescaler
Scaler
fX
2
Clock to
Peripheral
Hardware
1/2
Prescaler
f XX
f XX
2
f XX
f XX 4
f XX 23 2
22
f XT
2
Selector
XT2
Subsystem
Clock
Oscillator
Selector
XT1/P07
Standby
Control
Circuit
3
CPU Clock
(fCPU)
To INTP0
Sampling Clock
STOP
MCS
MCC FRC CLS CSS PCC2 PCC1 PCC0
Processor Clock Control Register
Oscillation Mode
Selection Register
Internal Bus
116
CHAPTER 7
CLOCK GENERATOR
7.3 Clock Generator Control Register
The clock generator is controlled by the following two registers:
• Processor clock control register (PCC)
• Oscillation mode selection register (OSMS)
(1) Processor clock control register (PCC)
The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/
stop and subsystem clock oscillator internal feedback resistor.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Figure 7-2. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback Resistor
XT1
XT2
117
CHAPTER 7
CLOCK GENERATOR
Figure 7-3. Processor Clock Control Register Format
Symbol
7
6
5
4
3
PCC
MCC
FRC
CLS
CSS
0
R/W
MCC
R/W
R
R/W
2
1
0
PCC2 PCC1 PCC0
Address
After
Reset
R/W
FFFBH
04H
R/W
Main System Clock Oscillation Control
0
Oscillation possible
1
Oscillation stopped
Note 2
Subsystem Clock Feedback Resistor Selection
FRC
0
Internal feedback resistor used
1
Internal feedback resistor not used
CPU Clock Status
CLS
0
Main system clock
1
Subsystem clock
CPU CIock (fCPU) Selection
CSS PCC2 PCC1 PCC0
MCS = 1
0
1
Note 1
MCS = 0
0
0
0
fX
fX /2
0
0
1
fX /2
fX /22
0
1
0
fX /2
2
fX /23
0
1
1
fX /23
fX /24
4
fX /25
1
0
0
fX /2
0
0
0
fXT/2
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
Setting prohibited
Notes 1. Bit 5 is Read Only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. A STOP instruction should not be used.
Caution Bit 3 must be set to 0.
Remarks 1. fX
2. fXT
: Main system clock oscillation frequency
: Subsystem clock oscillation frequency
3. MCS : Bit 0 of oscillation mode selection register
118
CHAPTER 7
CLOCK GENERATOR
The fastest instruction of the µPD780308 and 780308Y Subseries is executed with two CPU clocks. Therefore,
the relation between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 7-2.
Table 7-2. Relation between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Minimum Instruction Execution Time: 2/fCPU
fX
0.4 µs
fX/2
0.8 µs
fX/22
1.6 µs
fX/23
3.2 µs
fX/24
6.4 µs
fX/25
12.8 µs
fXT/2
122 µs
fX = 5.0 MHz, fXT = 32.768 kHz
fX
: Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency
119
CHAPTER 7
CLOCK GENERATOR
(2) Oscillation mode select register (OSMS)
This register specifies whether the clock output from the main system clock oscillator without passing through
the scaler is used as the main system clock, or the clock output via the scaler is used as the main system
clock.
OSMS is set with an 8-bit memory manipulation instruction.
RESET input clears OSMS to 00H.
Figure 7-4. Oscillation Mode Select Register Format
Symbol
7
6
5
4
3
2
1
0
Address
After
Reset
R/W
OSMS
0
0
0
0
0
0
0
MCS
FFF2H
00H
W
Main System Clock Scaler Control
MCS
0
Scaler used
1
Scaler not used
Cautions 1. As shown in Figure 7-5 below, writing data (including same data as previous) to OSMS cause
delay of main system clock cycle up to 2/fX during the write operation. Therefore, if this
register is written during the operation, in peripheral hardware which operates with the main
system clock, a temporary error occurs in the count clock cycle of timer, etc. In addition,
because the oscillation mode is changed by this register, the clocks for peripheral hardware
as well as that for the CPU are switched.
Figure 7-5. Main System Clock Waveform due to Writing to OSMS
Write to OSMS
(MCS
0)
Max. 2/fX
fXX
Operating at fXX = fX/2 (MCS = 0)
Operating at fXX = fX/2 (MCS = 0)
2. When writing “1” to MCS, VDD must be 2.7 V or higher before the write execution.
Remark
fXX : Main system clock frequency (fX or fX/2)
fX
120
: Main system clock oscillation frequency
CHAPTER 7
CLOCK GENERATOR
7.4 System Clock Oscillator
7.4.1 Main system clock oscillator
The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz)
connected to the X1 and X2 pins.
External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin
and an antiphase clock signal to the X2 pin.
Figure 7-6 shows an external circuit of the main system clock oscillator.
Figure 7-6. External Circuit of Main System Clock Oscillator
(a) Crystal and ceramic oscillation
(b) External clock
X2
IC
X2
VSS1
X1
Crystal
or
Ceramic Resonator
External
Clock
µ PD74HCU04
X1
Caution Do not execute the STOP instruction and do not set MCC to 1 if an external clock is used. This
is because the X2 pin is connected to VDD1 via a pull-up resistor.
121
CHAPTER 7
CLOCK GENERATOR
7.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1
and XT2 pins.
External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin
and an antiphase clock signal to the XT2 pin.
Figure 7-7 shows an external circuit of the subsystem clock oscillator.
Figure 7-7. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
32.768
kHz
IC
XT1
VSS1
(b) External clock
External
Clock
XT2
XT1
µ PD74HCU04
XT2
Cautions 1. When using a main system clock oscillator and a subsystem clock oscillator, carry out wiring
in the broken line area in Figures 7-6 and 7-7 to prevent any effects from wiring capacities.
●
Minimize the wiring length.
●
Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come
near changing high current.
●
Set the potential of the grounding position of the oscillator capacitor to that of VSS1. Do
not ground to any ground pattern where high current is present.
●
Do not fetch signals from the oscillator.
Take special note of the fact that the subsystem clock oscillator is a circuit with low-level
amplification so that current consumption is maintained at low levels.
Figure 7-8 shows examples of oscillator having bad connection.
Figure 7-8. Examples of Oscillator with Bad Connection (1/2)
(a) Wiring of connection
circuits is too long
(b) Signal conductors intersect
each other
PORTn
(n = 0 to 3, 7 to 11)
IC
X2
X1
VSS1
Remark
X2
X1
VSS1
When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert
resistors in series on the side of XT2.
122
IC
CHAPTER 7
CLOCK GENERATOR
Figure 7-8. Examples of Oscillator with Bad Connection (2/2)
(c) Changing high current is too near a
signal conductor
(d) Current flows through the grounding line
of the oscillator (potential at points A, B,
and C fluctuate)
VDD0
Pnm
IC
X2
X1
IC
X2
X1
High
Current
A
C
High
Current
VSS1
VSS1
(e) Signals are fetched
B
(f) Signal conductors of the main and sub system
clocks are parallel and near each other
IC
X2
X1
VSS1
Remark
IC
X2
X1
XT1
XT2
XT1 and X1 are wiring in parallel
VSS1
When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
Cautions 2. In Figure 7-8 (f), XT1 and X1 are wired in parallel. Thus, the crosstalk noise of X1 may
increase with XT1, resulting in malfunctioning. To prevent that from occurring, it is
recommended to wire XT1 and X1 so that they are not in parallel.
123
CHAPTER 7
CLOCK GENERATOR
7.4.3 Scaler
The scaler divides the main system clock oscillator output (fXX) and generates various clocks.
7.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations,
connect the XT1 and XT2 pins as follows.
XT1 : Connect to VDD0
XT2 : Open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To minimize leakage current, the above internal feedback resistance can be
removed with bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2
pins as described above.
124
CHAPTER 7
CLOCK GENERATOR
7.5 Clock Generator Operations
The clock generator generates the following types of clocks and controls the CPU operating mode including
the standby mode.
• Main system clock
• Subsystem clock
• CPU clock
fXX
fXT
fCPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined with the processor clock control register
(PCC) and the oscillation mode select register (OSMS).
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (12.8 µs when operated
at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while low level is
applied to the RESET pin.
(b) With the main system clock selected, one of the six CPU clock types (0.4 µs. 0.8 µs, 1.6 µs, 3.2 µs, 6.4 µs,
12.8 µs @ 5.0 MHz) can be selected by setting the PCC and OSMS.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. In a
system that does not use the subsystem clock, the power consumption in the STOP mode can be further
reduced by specifying not to use the internal feedback resistor by using bit 6 (FRC) of PCC.
(d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption
(122 µs when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT
mode can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be
stopped.)
(f)
The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied
to the 16-bit timer/event counter, the watch timer, and clock output functions only. Thus, 16-bit timer/event
counter (when selecting watch timer output for count clock operating with subsystem clock), the watch function,
and the clock output function can also be continued in the standby state. However, since all other peripheral
hardware operates with the main system clock, the peripheral hardware also stops if the main system clock
is stopped. (Except external input clock operation)
125
CHAPTER 7
CLOCK GENERATOR
7.5.1 Main system clock operations
When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to
0), the following operations are carried out by PCC setting.
(a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the
minimum instruction execution time can be changed by bit 0 to bit 2 (PCC0 to PCC2) of the PCC.
(b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system clock oscillation
does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation is switched to subsystem clock
operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 7-9).
Figure 7-9. Main System Clock Stop Function (1/2)
(a) Operation when MCC is set after setting CSS with main system clock operation
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
(b) Operation when MCC is set in case of main system clock operation
MCC
CSS
L
CLS
L
Oscillation does not stop.
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
126
CHAPTER 7
CLOCK GENERATOR
Figure 7-9. Main System Clock Stop Function (2/2)
(c) Operation when CSS is set after setting MCC with main system clock operation
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
7.5.2 Subsystem clock operations
When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1),
the following operations are carried out.
(a) The minimum instruction execution time remains constant (122 µs when operated at 32.768 kHz) irrespective
of bit 0 to bit 2 (PCC0 to PCC2) of the PCC.
(b) Watchdog timer counting stops.
Caution Do not execute the STOP instruction while the subsystem clock is in operation.
127
CHAPTER 7
CLOCK GENERATOR
7.6 Changing System Clock and CPU Clock Settings
7.6.1 Time required for switchover between system clock and CPU clock
The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS)
of the processor clock control register (PCC).
The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the
pre-switchover clock for several instructions (see Table 7-3).
Determination as to whether the system is operating on the main system clock or the subsystem clock is performed
by bit 5 (CLS) of the PCC register.
Table 7-3. Maximum Time Required for CPU Clock Switchover
Set Values after Switchover
Set Values before Switchover
MCS CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
×
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
16 instructions
0
1
0
16 instructions 8 instructions
0
1
1
16 instructions 8 instructions 4 instructions
1
0
0
16 instructions 8 instructions 4 instructions 2 instructions
×
×
×
fX/2fXT instruction fX/4fXT instruction fX/8fXT instruction fX/16fXT instruction fX/32fXT instruction
(77 instructions)
0
0
1
×
×
×
8 instructions 4 instructions 2 instructions 1 instruction
1 instruction
4 instructions 2 instructions 1 instruction
1 instruction
2 instructions 1 instruction
1 instruction
1 instruction
1 instruction
(39 instructions)
(20 instructions)
(10 instructions)
1 instruction
(5 instructions)
fX/4fXT instruction fX/8fXT instruction fX/16fXT instruction fX/32fXT instruction fX/64fXT instruction
(39 instructions)
(20 instructions)
(10 instructions)
(5 instructions)
(3 instructions)
Caution Selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the main
system clock to the subsystem clock (changing CSS from 0 to 1) should not be performed
simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle
scaling factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock.
2. Figures in parentheses apply to operation with fX = 5.0 MHz and fXT = 32.768 kHz.
128
CHAPTER 7
CLOCK GENERATOR
7.6.2 System clock and CPU clock switching procedure
This section describes switching procedure between system clock and CPU clock.
Figure 7-10. System Clock and CPU Clock Switching
VDD
RESET
Interrupt
Request
Signal
System Clock
CPU Clock
fXX
fXX
Minimum Maximum Speed
Operation
Speed
Operation
Wait (26.2 ms : 5.0 MHz)
fXT
Subsystem Clock
Operation
fXX
High-Speed
Operation
Internal Reset Operation
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation
stabilization time (217/fX) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 µs when
operated at 5.0 MHz).
(2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds,
the processor clock control register (PCC) and oscillation mode select register (OSMS) are rewritten and the
maximum-speed operation is carried out.
(3) Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock
is switched to the subsystem clock (which must be in an oscillation stable state).
(4) Upon detection of VDD voltage reset due to an interrupt request signal, 0 is set to the bit 7 of PCC (MCC) and
oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation,
the PCC and OSMS are rewritten and the maximum-speed operation is resumed.
Caution When subsystem clock is being operated while main system clock was stopped, if switching to
the main system clock is made again, be sure to switch after securing oscillation stable time by
software.
129
[MEMO]
130
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
8.1 Outline of Internal Timer of µPD780308 and 780308Y Subseries
This chapter explains the 16-bit timer/event counter. Before that, the internal timer of the µPD780308 and 780308Y
Subseries and related functions are briefly explained below.
(1) 16-bit timer/event counter (TM0)
The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control
receive function), external event counter, square wave output of any frequency or one-shot pulse output.
(2) 8-bit timers/event counters 1 and 2 (TM1 and TM2)
TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square
waves with any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/event
counter (See CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2).
(3) Watch timer (TM3)
This timer can set a flag every 0.5 sec. and simultaneously generates interrupt requests at the preset time
intervals (See CHAPTER 10 WATCH TIMER).
(4) Watchdog timer (WDTM)
WDTM can perform the watchdog timer function or generate non-maskable interrupt requests, maskable
interrupt requests and RESET at the preset time intervals (See CHAPTER 11 WATCHDOG TIMER).
(5) Clock output control circuit
This circuit supplies other devices with the divided main system clock and the subsystem clock (See CHAPTER
12 CLOCK OUTPUT CONTROL CIRCUIT).
(6) Buzzer output control circuit
This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 13
BUZZER OUTPUT CONTROL CIRCUIT).
131
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
Table 8-1. Timer/Event Counter Types and Functions
16-bit Timer/
event Counter
Type
Function
8-bit Timer/event
Counters 1 and 2
Watch Timer
Watchdog Timer
2 channels Note 1
2 channels
1 channel Note 2
1 channel Note 3
External event counter
√
√
—
—
Timer output
√
√
—
—
PWM output
√
—
—
—
Pulse width measurement
√
—
—
—
Square-wave output
√
√
—
—
One-shot pulse output
√
—
—
—
Interrupt request
√
√
√
√
Test input
—
—
√
—
Interval timer
Notes 1. When capture/compare registers (CR00, CR01) are specified as compare registers.
2. Watch timer can perform both watch timer and interval timer functions at the same time.
3. Watchdog timer can perform either the watchdog timer function or the interval timer function.
132
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
8.2 16-Bit Timer/Event Counter Functions
The 16-bit timer/event counter (TM0) has the following functions.
• Interval timer
• PWM output
• Pulse width measurement
• External event counter
• Square-wave output
• One-shot pulse output
(1) Interval timer
TM0 generates interrupt requests at the preset time interval.
Table 8-2. 16-Bit Timer/Event Counter Interval Times
Minimum Interval Time
MCS = 1
MCS = 0
2 × TI00 input cycle
2 × 1/fX
—
Maximum Interval Time
MCS = 1
216
MCS = 0
× TI00 input cycle
Resolution
MCS = 1
MCS = 0
TI00 input edge cycle
—
× 1/fX
(13.1 ms)
—
1/fX
(200 ns)
(400 ns)
216
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
1/fX
(200 ns)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
2 × watch timer output cycle
216 × watch timer output cycle
Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz
(2) PWM output
TM0 can generate 14-bit resolution PWM output.
(3) Pulse width measurement
TM0 can measure the pulse width of an externally input signal.
(4) External event counter
TM0 can measure the number of pulses of an externally input signal.
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16-BIT TIMER/EVENT COUNTER
(5) Square-wave output
TM0 can output a square wave with any selected frequency.
Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width
MCS = 1
MCS = 0
2 × TI00 input cycle
Maximum Pulse Width
MCS = 1
MCS = 0
216 × TI00 input cycle
Resolution
MCS = 1
TI00 input edge cycle
—
2 × 1/fX
(400 ns)
—
216 × 1/fX
(13.1 ms)
—
1/fX
(200 ns)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
1/fX
(200 ns)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
2 × watch timer output cycle
216 × watch timer output cycle
Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz
(6) One-shot pulse output
TM0 is able to output one-shot pulse which can set any width of output pulse.
134
MCS = 0
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
8.3 16-Bit Timer/Event Counter Configuration
The 16-bit timer/event counter consists of the following hardware.
Table 8-4. 16-Bit Timer/Event Counter Configuration
Item
Configuration
Timer register
16 bits × 1 (TM0)
Register
Capture/compare register: 16 bits × 2 (CR00, CR01)
Timer output
1 (TO0)
Control register
Timer clock select register 0 (TCL0)
16-bit timer mode control register (TMC0)
Capture/compare control register 0 (CRC0)
16-bit timer output control register (TOC0)
Port mode register 3 (PM3)
External interrupt mode register 0 (INTM0)
Sampling clock select register (SCS) Note
Note
For details, refer to Figure 20-1 Basic Configuration of Interrupt Function.
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16-BIT TIMER/EVENT COUNTER
Figure 8-1. 16-Bit Timer/Event Counter Block Diagram
Internal Bus
Capture/Compare
Control Register 0
CRC02 CRC01 CRC00
Selector
INTP1
TI01/
P01/INTP1
16-Bit Capture/Compare
Control Register (CR00)
Match
Selector
INTTM3
2f XX
f XX
f XX/2
f XX/22
TI00/P00/
INTP0
INTTM00
PWM Pulse
Output
Controller
Note 2
TMC01 to TMC03
16-Bit Timer Register (TM0)
Clear
Note 1
Clear Circuit
TMC01 to TMC03
Match
3
16-Bit Capture/Compare
Control Register (CR01)
TO0/P30
2
INTTM01
3
TCL06 TCL05 TCL04
Timer Clock
Selection
Register 0
16-Bit Timer/Event
Counter Output
Control Circuit
INTP0
TMC03 TMC02 TMC01 OVF0
OSPT OSPE TOC04 LVS0 LVR0 TOC01TOE0
16-Bit Timer Mode
Control Register
CRC02
16-Bit Timer Output
Control Register
Internal Bus
Notes 1. Edge detection circuit
2. The configuration of the 16-bit timer/event counter output control circuit is shown in Figure 8-2.
Remark
136
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram
PWM Pulse
Output Control
Circuit
Level
Inversion
Selector
CRC00
INTTM00
Edge
Detection
Circuit
TI00/P00/
INTP0
INV
S
One-Shot Pulse
Output Control
Circuit
Selector
CRC02
INTTM01
Q
TO0/P30
R
3
2
ES11 ES10
External Interrupt
Mode Register 0
OSPT OSPE TOC04 LVS0
LVR0 TOC01 TOE0
16-Bit Timer Output
Control Register
TMC03 TMC02 TMC01
16-Bit Timer Mode
Control Register
P30 Output
Latch
PM30
Port Mode
Register 3
Internal Bus
Remark
The circuitry enclosed by the dotted line is the output control circuit.
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16-BIT TIMER/EVENT COUNTER
(1) Capture/compare register 00 (CR00)
CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control
register 0.
When CR00 is used as a compare register, the value set in the CR00 is constantly compared with the 16bit timer register (TM0) count value, and an interrupt request (INTTM00) is generated if they match. When
TM0 is set to interval timer operation, this register is used to hold the interval time. When the PWM output
operation is specified, it is used as a register that specifies a pulse width.
When CR00 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin or the
INTP1/TI01 pin as the capture trigger. Setting of the INTP0/TI00 or INTP1/TI01 valid edge is performed by
means of external interrupt mode register 0.
If CR00 is specified as a capture register and capture trigger is specified to be the valid edge of the INTP0/
TI00 pin, the situation is as shown in the following table.
Table 8-5. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
ES11
ES10
INTP0/TI00 Pin Valid Edge
CR00 Capture Trigger Valid Edge
0
0
Falling edge
Rising edge
0
1
Rising edge
Falling edge
1
0
Setting prohibited
1
1
Both rising and falling edges
No capture operation
CR00 is set by a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Cautions 1. Set the data of PWM (14 bits) to the high-order 4 bits of CR00. At this time, clear the loworder 2 bits to 00.
2. Set a value other than 0000H to CR00. Therefore, when the 16-bit timer/event counter
is used as an event counter, the 1-pulse count operation cannot be performed.
3. If the new value of CR00 is less than the value of the 16-bit timer register (TM0), TM0
continues counting. When an overflow occurs, it counts again from 0. Therefore, if the
new value (M) of CR00 is less than the old value (N), the timer must be restarted after
changing the value of CR00.
(2) Capture/compare register 01 (CR01)
CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register
0.
When CR01 is used as a compare register, the value set in the CR01 is constantly compared with the 16bit timer register (TM0) count value, and an interrupt request (INTTM01) is generated if they match.
When CR01 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin as the
capture trigger. Setting of the INTP0/TI00 valid edge is performed by means of external interrupt mode register
0 (INTM0).
CR01 is set with a 16-bit memory manipulation instruction.
After RESET input, the value of CR01 is undefined.
Caution If the valid edge of the TI00/P00 pin is input while CR01 is read, CR01 does not perform the
capture operation, but retains data. However, the interrupt request flag (PIF0) is set when
the valid edge is detected.
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CHAPTER 8
16-BIT TIMER/EVENT COUNTER
(3) 16-bit timer register (TM0)
TM0 is a 16-bit register which counts the count pulses.
TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01)
should first be set as a capture register.
RESET input clears TM0 to 0000H.
Caution Because reading of the value of TM0 is performed via CR01, the previously set value of CR01
is lost.
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16-BIT TIMER/EVENT COUNTER
8.4 16-Bit Timer/Event Counter Control Registers
The following seven types of registers are used to control the 16-bit timer/event counter.
• Timer clock select register 0 (TCL0)
• 16-bit timer mode control register (TMC0)
• Capture/compare control register 0 (CRC0)
• 16-bit timer output control register (TOC0)
• Port mode register 3 (PM3)
• External interrupt mode register 0 (INTM0)
• Sampling clock select register (SCS)
(1) Timer clock select register 0 (TCL0)
This register is used to set the count clock of the 16-bit timer register (TM0).
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TCL0 value to 00H.
Remark
TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock
of the 16-bit timer register.
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16-BIT TIMER/EVENT COUNTER
Figure 8-3. Timer Clock Selection Register 0 Format
Symbol
7
6
5
4
3
2
1
0
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
Address
After Reset
R/W
FF40H
00H
R/W
PCL Output Control
CLOE
0
Output disabled
1
Output enabled
16-Bit Timer Register Count Clock Selection
TCL06 TCL05 TCL04
MCS = 0
MCS = 1
0
0
0
TI00 (Valid edge specifiable)
0
0
1
Setting prohibited
fX
0
1
0
fX
fX/2
0
1
1
(5.0 MHz)
fX/2
2
(2.5 MHz)
(2.5 MHz)
2
(1.25 MHz)
3
(625 kHz)
fX/2
1
0
0
fX/2
1
1
1
Watch timer output (INTTM 3)
Other than above
(5.0 MHz)
(1.25 MHz)
fX/2
Setting prohibited
PCL Output Clock Selection
TCL03 TCL02 TCL01 TCL00
MCS = 0
MCS = 1
0
0
0
0
fXT (32.768 kHz)
0
1
0
1
fX
(5.0 MHz)
fX/2
0
1
1
0
fX/2
(2.5 MHz)
fX/2
0
1
1
1
2
fX/2
5
(156 kHz)
6
(78.1 kHz)
7
(39.1 kHz)
8
(19.5 kHz)
(313 kHz)
fX/2
fX/2
1
0
0
1
fX/2
5
fX/2
(156 kHz)
fX/2
6
(78.1 kHz)
fX/2
7
(39.1 kHz)
fX/2
1
0
1
1
fX/2
1
1
0
0
fX/2
Other than above
(313 kHz)
4
0
0
(625 kHz)
4
fX/2
fX/2
0
1
(1.25 MHz)
3
(625 kHz)
0
0
2
3
1
1
(1.25 MHz)
(2.5 MHz)
Setting prohibited
Cautions 1. Setting of the TI00/INTP0 pin valid edge is performed by external interrupt mode register
0, and selection of the sampling clock frequency is performed by the sampling clock
selection register.
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the timer operation beforehand.
141
CHAPTER 8
Remarks
16-BIT TIMER/EVENT COUNTER
1. fX
: Main system clock oscillation frequency
2. fXT
: Subsystem clock oscillation frequency
3. TI00 : 16-bit timer/event counter input pin
4. TM0 : 16-bit timer register
5. MCS : Bit 0 of oscillation mode select register
6. Figures in parentheses apply to operation with fX = 5.0 MHz of fXT = 32.768 kHz.
(2) 16-bit timer mode control register (TMC0)
This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and
detects an overflow.
TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC0 value to 00H.
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation
stop mode) is set in TMC01 to TMC03, respectively. Set 0, 0, 0 in TMC01 to TMC03 to stop
the operation.
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16-BIT TIMER/EVENT COUNTER
Figure 8-4. 16-Bit Timer Mode Control Register Format
Symbol
7
6
5
4
TMC0
0
0
0
0
3
2
1
TMC03 TMC02 TMC01 OVF0
Operating Mode
Clear Mode Selection
TMC03 TMC02 TMC01
0
Address
After Reset
R/W
FF48H
00H
R/W
TO0 Output Timing Selection
Interrupt Generation
0
0
0
Operation stop
(TM0 cleared to 0)
No change
Not Generated
0
0
1
PWM mode
(free running)
PWM pulse output
0
1
0
Free running mode
Match between TM0 and
CR00 or match between
TM0 and CR01
Generated on match
between TM0 and CR00,
and match between TM0
and CR01
0
1
1
1
0
0
1
0
1
1
1
0
1
1
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Clear & start on TI00
valid edge
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Clear & start on match
between TM0 and CR00
1
OVF0
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
16-Bit Timer Register Overflow Detection
0
Overflow not detected
1
Overflow detected
Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation
(by setting TMC01 to TMC03 to 0, 0, 0).
2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0
and select the sampling clock frequency with a sampling clock select register.
3. When using the PWM mode, set the PWM mode and then set data to CR00.
4. If clear & start mode on match between TM0 and CR00 is selected, when the set value
of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set to
1.
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CHAPTER 8
Remark TO0
16-BIT TIMER/EVENT COUNTER
: 16-bit timer/event counter output pin
TI00
: 16-bit timer/event counter input pin
TM0
: 16-bit timer register
CR00 : Capture/compare register 00
CR01 : Capture/compare register 01
(3) Capture/compare control register 0 (CRC0)
This register controls the operation of the capture/compare registers (CR00, CR01).
CRC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CRC0 value to 04H.
Figure 8-5. Capture/Compare Control Register 0 Format
Symbol
7
6
5
4
3
CRC0
0
0
0
0
0
2
1
0
CRC02 CRC01 CRC00
CRC02
Address
After Reset
R/W
FF4CH
04H
R/W
CR01 Operating Mode Selection
0
Operates as compare register
1
Operates as capture register
CRC01
CR00 Capture Trigger Selection
0
Captures on valid edge of TI01
1
Captures on valid edge of TI00
CRC00
CR00 Operating Mode Selection
0
Operates as compare register
1
Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC0.
2. When clear & start mode on a match between TM0 and CR00 is selected with the 16bit timer mode control register, CR00 should not be specified as a capture register.
144
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
(4) 16-bit timer output control register (TOC0)
This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type
flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other
than PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation
enabling/disabling, and output trigger for a one-shop pulse by software. TOC0 is set with a 1-bit or 8-bit memory
manipulation instruction. RESET input clears TOC0 value to 00H.
Figure 8-6. 16-Bit Timer Output Control Register Format
Symbol
7
TOC0
0
6
5
4
3
2
1
0
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
OSPT
Address
After Reset
R/W
FF4EH
00H
R/W
Control of One-Shot Pulse Output Trigger by Software
0
One-shot pulse trigger not used
1
One -shot pulse trigger used
OSPE
One-Shot Pulse Output Control
0
Continuous pulse output
1
One-shot pulse output
TOC04
Timer Output F/F Control by Match of CR01 and TM0
0
Inversion operation disabled
1
Inversion operation enabled
LVS0 LVR0
16-Bit Timer/Event Counter Timer Output F/F Status Setting
0
0
No change
0
1
Timer output F/F reset (0)
1
0
Timer output F/F set (1)
1
1
Setting prohibited
TOC04
In PWM Mode
In Other Modes
Active Level Selection
Timer Output F/F Control by Match of CR00 and TM0
0
Active high
Inversion operation disabled
1
Active low
Inversion operation enabled
TOE0
16-Bit Timer/Event Counter Output Control
0
Output disabled (Port mode)
1
Output enabled
Cautions 1. Timer operation must be stopped before setting TOC0 (except OSPT).
2. If LVS0 and LVR0 are read after data is set, they will be 0.
3. OSPT is cleared automatically after data setting, and will therefore be 0 if read.
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CHAPTER 8
16-BIT TIMER/EVENT COUNTER
(5) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 value to FFH.
Figure 8-7. Port Mode Register 3 Format
Symbol
7
6
5
4
3
2
1
0
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
146
Address
After Reset
R/W
FF23H
FFH
R/W
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
(6) External interrupt mode register 0 (INTM0)
This register is used to set INTP0 to INTP2 valid edges.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 value to 00H.
Figure 8-8. External Interrupt Mode Register 0 Format
Symbol
7
6
5
4
3
INTM0 ES31 ES30 ES21 ES20 ES11
2
1
0
Address
After Reset
R/W
ES10
0
0
FFECH
00H
R/W
ES31 ES30
INTP2 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES21 ES20
INTP1 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES11 ES10
INTP0 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
Caution Be sure to set bit 1 to 3 (TMC01 to TMC03) to 0, 0, 0, and stop the timer operation before setting
the valid edge of the INTP0/TI00 pin.
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16-BIT TIMER/EVENT COUNTER
(7) Sampling clock select registers (SCS)
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS value to 00H.
Figure 8-9. Sampling Clock Select Register Format
Symbol
7
6
5
4
3
2
SCS
0
0
0
0
0
0
1
0
SCS1 SCS0
Address
After Reset
R/W
FF47H
00H
R/W
INTP0 Sampling Clock Selection
SCS1 SCS0
MCS = 1
MCS = 0
N
0
0
fXX/2
0
1
fX/2 (39.1 kHz)
1
0
fX/2 (156.3 kHz)
1
1
fX/2 (78.1 kHz)
8
7
fX/2 (19.5 kHz)
5
fX/2 (78.1 kHz)
6
fX/2 (39.1 kHz)
6
7
Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are clocks supplied to
peripheral hardware. fXX/2N is stopped in HALT mode.
Remarks
1. N
: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
2. fXX
: Main system clock frequency (fX or fX/2)
3. fX
: Main system clock oscillation frequency
(N= 0 to 4)
4. MCS : Bit 0 of oscillation mode select register
5. Figures in parentheses apply to operation with fX = 5.0 MHz.
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16-BIT TIMER/EVENT COUNTER
8.5 16-Bit Timer/Event Counter Operations
8.5.1 Interval timer operations
Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown
in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value
set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with
the TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated.
Count clock of the 16-bit timer/event counter can be selected with bits 4 to 6 (TCL04 to TCL06) of the timer clock
select register 0 (TCL0).
For the operation to be performed when the value of the compare register is changed during timer count operation,
refer to 8.6 16-Bit Timer/Event Counter Operating Precautions (3).
Figure 8-10. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clear & start on match TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See
the description of the respective control registers for details.
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CHAPTER 8
16-BIT TIMER/EVENT COUNTER
Figure 8-11. Interval Timer Configuration Diagram
16-Bit Capture/Compare Register 00 (CR00)
INTTM00
2fXX
fXX
fXX/2
2
fXX/2
TI00/P00/INTP0
Selector
INTTM3
OVF0
16-Bit Timer Register (TM0)
Clear Circuit
Figure 8-12. Interval Timer Operation Timings
t
Count Clock
TM0 Count Value
0000
0001
Count Start
CR00
N
N
0000 0001
Clear
N
0000 0001
Clear
N
N
N
INTTM00
Interrupt Request
Acknowledge
Interrupt Request
Acknowledge
TO0
Interval Time
Remark
150
N
Interval Time
Interval time = (N + 1) × t : N = 0001H to FFFFH.
Interval Time
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
Table 8-6. 16-Bit Timer/Event Counter Interval Times
Minimum Interval Time
TCL06
TCL05
TCL04
0
0
0
MCS = 1
MCS = 0
2 × TI00 input cycle
Maximum Interval Time
MCS = 1
MCS = 0
216 × TI00 input cycle
Resolution
MCS = 1
MCS = 0
TI00 input edge cycle
0
0
1
Setting
prohibited
2 × 1/fX
(400 ns)
Setting
prohibited
× 1/fX
(13.1 ms)
Setting
prohibited
1/fX
(200 ns)
0
1
0
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
1/fX
(200 ns)
2 × 1/fX
(400 ns)
0
1
1
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
1
0
0
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
1
1
1
Other than above
Remarks 1. fX
2 × watch timer output cycle
216
216 × watch timer output cycle
Watch timer output edge cycle
Setting prohibited
: Main system clock oscillation frequency
2. MCS : Bit 0 of oscillation mode select register
3. Figures in parentheses apply to operation with fX = 5.0 MHz
8.5.2 PWM output operations
Setting the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit
timer output control register (TOC0) as shown in Figure 8-13 allows operation as PWM output. Pulses with the duty
rate determined by the value set in 16-bit capture/compare register 00 (CR00) beforehand are output from the TO0/
P30 pin.
Set the active level width of the PWM pulse to the high-order 14 bits of CR00. Select the active level with bit 1
(TOC01) of the TOC0.
This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with
an external low-pass filter (LPF). The PWM pulse is formed by a combination of the basic cycle determined by 28/
Φ and the sub-cycle determined by 214/Φ so that the time constant of the external LPF can be shortened. Count clock
Φ can be selected with bits 4 to 6 (TCL04 to TCL06) of the timer clock select register 0 (TCL0).
PWM output enable/disable can be selected with bit 0 (TOE0) of TOC0.
Cautions 1. PWM operation mode should be selected before setting CR00.
2. Be sure to write 0 to bits 0 and 1 of CR00.
3. Do not select PWM operation mode for external clock input from the TI00/P00 pin.
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Figure 8-13. Control Register Settings for PWM Output Operation
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
0
1
0
PWM mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
×
×
×
×
LVR0 TOC01 TOE0
×
0/1
1
TO0 Output Enabled
Specifies Active Level
Remarks 1. 0/1 : Setting 0 or 1 allows another function to be used simultaneously with PWM output.
See the description of the respective control registers for details.
2. ×
152
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By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog
voltage and used for electronic tuning and D/A converter applications, etc.
The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows.
VAN = VREF ×
Capture/compare register 00 (CR00) value
216
VREF: External switching circuit reference voltage
Figure 8-14. Example of D/A Converter Configuration with PWM Output
µ PD780308, 780308Y
VREF
TO0/P30
PWM
signal
Switching Circuit
Low-Pass Filter
Analog Output (VAN)
Figure 8-15 shows an example in which PWM output is converted to an analog voltage and used in a voltage
synthesizer type TV tuner.
Figure 8-15. TV Tuner Application Circuit Example
+110 V
µ PD780308, 780308Y
22 kΩ
47 kΩ
47 kΩ
47 kΩ
100 pF
TO0/P30
2SC
2352
8.2 kΩ
0.22 µ F
µ PC574J
0.22 µ F
0.22 µ F
Electronic
Tuner
8.2 kΩ
VSS0
GND
VSS0
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8.5.3 PPG output operations
Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown
in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output.
In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle
that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/
compare register 00 (CR00), respectively.
Figure 8-16. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0
0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
×
0
CR00 set as compare register
CR01 set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
0
0
1
0/1
LVR0 TOC01 TOE0
0/1
1
1
TO0 Output Enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output disabled
Caution Values in the following range should be set in CR00 and CR01:
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark
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8.5.4 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the
16-bit timer register (TM0).
There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
(1) Pulse width measurement with free-running counter and one capture register
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-17),
and the edge specified by external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value
of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0)
is set.
Any of three edge specifications can be selected—rising, falling, or both edges—by means of bits 2 and 3
(ES10 and ES11) of INTM0.
For valid edge detection, sampling is performed at the interval selected by means of the sampling clock
selection register (SCS), and a capture operation is only performed when a valid level is detected twice, thus
eliminating noise with a short pulse width.
Figure 8-17. Control Register Settings for Pulse Width Measurement with
Free-Running Counter and One Capture Register
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-Running Mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
0/1
0
CR00 set as compare register
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
INTTM3
Selector
2fXX
fXX
fXX/2
16-Bit Timer Register (TM0)
OVF0
2
fXX/2
16-Bit Capture/Compare
Register 01 (CR01)
TI00/P00/INTP00
INTP0
Internal Bus
Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count Clock
TM0 Count Value
0000
0001
D0
D1
FFFF 0000
D2
D3
TI00 Pin Input
CR01 Captured Value
D0
D1
D2
INTP0
OVF0
(D1 – D0) × t
156
(10000H – D1 + D2) × t
(D3 – D2) × t
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(2) Measurement of two pulse widths with free-running counter
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20),
it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the
TI01/P01 pin.
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an
external interrupt request signal (INTP0) is set.
Also, when the edge specified by bits 4 and 5 (ES20 and ES21) of INTM0 is input to the TI01/P01 pin, the
value of TM0 is taken into 16-bit capture/compare register 00 (CR00) and an external interrupt request signal
(INTP1) is set.
Any of three edge specifications can be selected—rising, falling, or both edges—as the valid edges for the
TI00/P00 pin and the TI01/P01 pin by means of bits 2 and 3 (ES10 and ES11) and bits 4 and 5 (ES20 and
ES21) of INTM0, respectively.
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling
clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice,
thus eliminating noise with a short pulse width.
Figure 8-20. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-Running Mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
0
1
CR00 set as capture register
Captured in CR00 on valid edge of TI01/P01 Pin
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
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Figure 8-21. Timing of Pulse Width Measurement Operation with
Free-Running Counter (with Both Edges Specified)
t
Count Clock
TM0 Count Value
0000 0001
D0
D1
FFFF 0000
D2
D3
TI00 Pin Input
CR01 Captured Value
D0
D1
D2
INTP0
TI01 Pin Input
CR00 Captured Value
D1
INTP1
OVF0
(D1 – D0) × t
(10000H – D1 + D2) × t
(D3 – D2) × t
(10000H – D1 + (D2 + 1)) × t
158
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(3) Pulse width measurement with free-running counter and two capture registers
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22),
it is possible to measure the pulse width of the signal input to the TI00/P00 pin.
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an
external interrupt request signal (INTP0) is set.
Also, on the inverse edge input of that of the capture operation into CR01, the value of TM0 is taken into 16bit capture/compare register 00 (CR00).
Either of two edge specifications can be selected—rising or falling—as the valid edges for the TI00/P00 pin
by means of bits 2 and 3 (ES10 and ES11) of INTM0.
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling
clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice,
thus eliminating noise with a short pulse width.
Caution If the valid edge of TI00/P00 is specified to be both rising and falling edge, capture/compare
register 00 (CR00) cannot perform the capture operation.
Figure 8-22. Control Register Settings for Pulse Width Measurement with
Free-Running Counter and Two Capture Registers
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-Running Mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
1
1
CR00 set as capture register
Captured in CR00 on invalid edge of
TI00/P00 Pin
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified)
t
Count Clock
TM0 Count Value
0000
0001
D0
D1
FFFF 0000
D2
D3
TI00 Pin Input
CR01 Captured Value
D0
CR00 Captured Value
D2
D1
D3
INTP0
OVF0
(D1 - D0) × t
160
(10000H - D1 + D2) × t
(D3 - D2) × t
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16-BIT TIMER/EVENT COUNTER
(4) Pulse width measurement by means of restart
When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0)
is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the
TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).
The edge specification can be selected from two types, rising and falling edges by INTM0 bits 2 and 3 (ES10
and ES11).
In a valid edge detection, the sampling is performed by a cycle selected by the sampling clock selection register
(SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise
with a short pulse width.
Caution If the valid edge of TI00/P00 is specified to be both rising and falling edge, the 16-bit capture/
compare register 00 (CR00) cannot perform the capture operation.
Figure 8-24. Control Register Settings for Pulse Width Measurement by Means of Restart
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
0
0/1
0
Clear & start with valid edge of TI00/P00 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
1
1
CR00 set as capture register
Captured in CR00 on invalid
edge of TI00/P00 Pin
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
Figure 8-25. Timing of Pulse Width Measurement Operation by
Means of Restart (with Rising Edge Specified)
t
Count Clock
TM0 Count Value
0000
0001
D0
0000
0001
D1
D2
0000
0001
TI00 Pin Input
CR01 Captured Value
D0
CR00 Captured Value
D2
D1
INTP0
D1 × t
D2 × t
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8.5.5 External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the
16-bit timer register (TM0).
TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input.
When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to
0 and the interrupt request signal (INTTM00) is generated.
Set a value other than 0000H to CR00 (the 1-pulse count operation cannot be performed).
The rising edge, the falling edge or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0.
Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected
with the sampling clock select register (SCS), noise with short pulse widths can be removed.
Figure 8-26. Control Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clear & start with match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event
counter. See the description of the respective control registers for details.
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Figure 8-27. External Event Counter Configuration Diagram
16-Bit Capture/Compare
Register 00 (CR00)
INTTM00
Clear
OVF0
16-Bit Timer Register (TM0)
TI00 Valid Edge
INTP0
16-Bit Capture/Compare
Register 01 (CR01)
Internal Bus
Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified)
TI00 Pin Input
TM0 Count Value
CR00
0000
0001 0002 0003
0004
0005
N–1
N
0000 0001 0002 0003
N
INTTM0
Caution When reading the external event counter count value, TM0 should be read.
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8.5.6 Square-wave output operation
A square wave of any frequency is output at the interval specified by the count value set in advance to the 16bit capture/compare register 00 (CR00).
The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0)
and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected
frequency to be output.
Figure 8-29. Control Register Settings in Square-Wave Output Mode
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
0
0
0
0/1
LVR0 TOC01 TOE0
0/1
1
1
TO0 Output Enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
No inversion of output on match of TM0 and CR01
One-shot pulse output disabled
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output.
See the description of the respective control registers for details.
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Figure 8-30. Square-Wave Output Operation Timing
TI00 Pin Input
TM0 Count Value
0000
0001
CR00
0002
N–1
N
0000
0001
0002
N–1
N
0000
N
INTTM0
TO0 Pin Output
Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges
Minimum Pulse Width
MCS = 1
MCS = 0
2 × TI00 input cycle
Maximum Pulse Width
MCS = 1
216
MCS = 0
× TI00 input cycle
Resolution
MCS = 1
MCS = 0
TI00 input edge cycle
—
2 × 1/fX
(400 ns)
—
× 1/fX
(13.1 ms)
—
1/fX
(200 ns)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
1/fX
(200 ns)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
2 × watch timer output cycle
Remarks 1. fX
216
216 × watch timer output cycle
Watch timer output edge cycle
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz
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8.5.7 One-shot pulse output operation
It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin
input).
(1) One-shot pulse output using software trigger
If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit
timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0
by software, a one-shot pulse is output from the TO0/P30 pin.
By setting 1 in OSPT, the 16-bit timer/event counter is cleared and started, and output is activated by the count
value set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivated by the
count value set beforehand in 16-bit capture/compare register 00 (CR00).
TM0 continues to operate after one-shot pulse is output. To stop TM0, 00H must be set to TMC0.
Caution When outputting one-shot pulse, do not set 1 in OSPT. When outputting one-shot pulse
again, execute after the INTTM00, or interrupt match signal with CR00, is generated.
Figure 8-31. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0
0
Clear & start with match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
0/1
0
CR00 set as compare register
CR01 set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
0
1
1
0/1
LVR0 TOC01 TOE0
0/1
1
1
TO0 Output Enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output mode
Set 1 in case of output
Caution Values in the following range should be set in CR00 and CR01.
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.
See the description of the respective control registers for details.
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Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger
Set 0CH to TMC0
(TM0 count start)
Count Clock
TM0 Count Value
0000
0001
N
N+1
0000
N–1
N
M–1
M
0000 0001 0002
CR01 Set Value
N
N
N
N
CR00 Set Value
M
M
M
M
OSPT
INTTM01
INTTM00
TO0 Pin Output
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation
stop mode) is set to TMC01 to TMC03, respectively.
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(2) One-shot pulse output using external trigger
If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit
timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/
P30 pin with a TI00/P00 valid edge as an external trigger.
Any of three edge specifications can be selected—rising, falling, or both edges — as the valid edges for the
TI00/P00 pin by means of bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0).
When a valid edge is input to the TI00/P00 pin, the 16-bit timer/event counter is cleared and started, and output
is activated by the count values set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter,
output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (CR00).
Caution When outputting one-shot pulses, external trigger is ignored if generated again.
Figure 8-33. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
(a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
0
0
0
Clear & start with valid edge of TI00/P00 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
0/1
0
CR00 set as compare register
CR01 set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
0
1
1
0/1
LVR0 TOC01 TOE0
0/1
1
1
TO0 Output Enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output mode
Caution Values in the following range should be set in CR00 and CR01.
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.
See the description of the respective control registers for details.
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Figure 8-34. Timing of One-Shot Pulse Output Operation Using
External Trigger (with Rising Edge Specified)
Set 08H to TMC0
(TM0 count start)
Count Clock
TM0 Count Value
0000
0001
0000
N
N+1 N+2
M–2 M–1
M
M+1 M+2
CR01 Set Value
N
N
N
N
CR00 Set Value
M
M
M
M
M+3
TI00 Pin Input
INTTM01
INTTM00
TO0 Pin Output
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation
stop mode) is set to TMC01 to TMC03, respectively.
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8.6 16-Bit Timer/Event Counter Operating Precautions
(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be
generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the
count pulse.
Figure 8-35. 16-Bit Timer Register Start Timing
Count Pulse
TM0 Count Value
0000H
0001H
0002H
0003H
0004H
Timer Start
(2) 16-bit compare register setting
Set a value other than 0000H to the 16-bit capture/compare register 00 (CR00).
Thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot
be carried out.
(3) Operation after compare register change during timer count operation
If the value after the 16-bit capture/compare register (CR00) is changed is smaller than that of the 16-bit timer
register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M)
after CR00 change is smaller than that (N) before change, it is necessary to restart the timer after changing
CR00.
Figure 8-36. Timings After Change of Compare Register During Timer Count Operation
Count Pulse
CR00
TM0 Count Value
Remark
170
N
X–1
N>X>M
M
X
FFFFH
0000H
0001H
0002H
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
(4) Capture register data retention timings
If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01
holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon
detection of the valid edge.
Figure 8-37. Capture Register Data Retention Timing
Count Pulse
TM0 Count
Value
N
N+1
N+2
M
M+1
M+2
Edge Input
Interrupt
Request Flag
Capture
Read Signal
CR01
Captured
Value
X
N+1
Capture Operation
Ignored
(5) Valid edge setting
Set the valid edge of the TI00/INTP0 pin after setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode
control register to 0, 0 and 0, respectively, and then stopping timer operation. Valid edge setting is carried
out with bits 2 and 3 (ES10 and ES11) of the external interrupt mode register 0.
(6) Re-trigger of one-shot pulse
(a) One-shot pulse output using software
When outputting one-shot pulse, do not set 1 in bit 6 (OSPT) of 16-bit timer output control register (TOC0).
When outputting one-shot pulse again, execute it after the INTTM00, or interrupt match signal with 16bit capture/compare register 00 (CR00), is generated.
(b) One-shot pulse output using external trigger
When outputting one-shot pulses, external trigger is ignored if generated again.
171
CHAPTER 8
16-BIT TIMER/EVENT COUNTER
(7) Operation of OVF0 flag
OFV0 flag is set to 1 in the following case.
The clear & start mode on match between TM0 and CR00 is selected.
↓
CR00 is set to FFFFH.
↓
When TM0 is counted up from FFFFH to 0000H.
Figure 8-38. Operation Timing of OVF0 Flag
Count Pulse
CR00
FFFFH
TM0
FFFEH
OVF0
INTTM00
172
FFFFH
0000H
0001H
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.1 8-Bit Timer/Event Counters 1 and 2 Functions
For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/
event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/
event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode).
9.1.1 8-bit timer/event counter mode
The 8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions.
• Interval timer
• External event counter
• Square-wave output
173
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(1) 8-bit interval timer
Interrupt requests are generated at the preset time intervals.
Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times
Minimum Interval Time
Maximum Interval Time
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
212 × 1/fX
(819.2 µs)
213 × 1/fX
(1.64 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
213 × 1/fX
(1.64 ms)
214 × 1/fX
(3.28 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
26 × 1/fX
(12.8 µs)
27 × 1/fX
214 × 1/fX
215 × 1/fX
26 × 1/fX
27 × 1/fX
(25.6 µs)
(3.28 ms)
(6.55 ms)
(12.8 µs)
(25.6 µs)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
215 × 1/fX
(6.55 ms)
216 × 1/fX
(13.1 ms)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
212 × 1/fX
219 × 1/fX
220 × 1/fX
211 × 1/fX
212 × 1/fX
(409.6 µs)
(819.2 µs)
(104.9 ms)
(209.7 ms)
(409.6 µs)
(819.2 µs)
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
174
Resolution
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave with any selected frequency can be output.
Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
Minimum Pulse Width
Maximum Pulse Width
Resolution
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
212 × 1/fX
(819.2 µs)
213 × 1/fX
(1.64 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
213 × 1/fX
(1.64 ms)
214 × 1/fX
(3.28 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
214 × 1/fX
(3.28 ms)
215 × 1/fX
(6.55 ms)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
215 × 1/fX
(6.55 ms)
216 × 1/fX
(13.1 ms)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
212 × 1/fX
219 × 1/fX
220 × 1/fX
211 × 1/fX
212 × 1/fX
(409.6 µs)
(819.2 µs)
(104.9 ms)
(209.7 ms)
(409.6 µs)
(819.2 µs)
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
175
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.1.2 16-bit timer/event counter mode
(1) 16-bit interval timer
Interrupt requests can be generated at the preset time intervals.
Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2
are Used as 16-Bit Timer/Event Counters
Minimum Interval Time
Maximum Interval Time
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
220 × 1/fX
(209.7 ms)
221 × 1/fX
(419.4 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
221 × 1/fX
(419.4 ms)
222 × 1/fX
(838.9 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
222 × 1/fX
(838.9 ms)
223 × 1/fX
(1.7 s)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
223 × 1/fX
(1.7 s)
224 × 1/fX
(3.4 s)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
224 × 1/fX
(3.4 s)
225 × 1/fX
(6.7 s)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
225 × 1/fX
(6.7 s)
226 × 1/fX
(13.4 s)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
212 × 1/fX
227 × 1/fX
228 × 1/fX
211 × 1/fX
212 × 1/fX
(409.6 µs)
(819.2 µs)
(26.8 s)
(53.7 s)
(409.6 µs)
(819.2 µs)
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
176
Resolution
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave with any selected frequency can be output.
Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event
Counters 1 and 2 are Used as 16-Bit Timer/Event Counters
Minimum Pulse Width
Maximum Pulse Width
Resolution
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
2 × 1/fX
(400 ns)
22
× 1/fX
(800 ns)
217
× 1/fX
(26.2 ms)
× 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
220 × 1/fX
(209.7 ms)
221 × 1/fX
(419.4 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
221 × 1/fX
(419.4 ms)
222 × 1/fX
(838.9 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
222 × 1/fX
(838.9 ms)
223 × 1/fX
(1.7 s)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
223 × 1/fX
(1.7 s)
224 × 1/fX
(3.4 s)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
224 × 1/fX
(3.4 s)
225 × 1/fX
(6.7 s)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
225 × 1/fX
(6.7 s)
226 × 1/fX
(13.4 s)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
212 × 1/fX
227 × 1/fX
228 × 1/fX
211 × 1/fX
212 × 1/fX
(409.6 µs)
(819.2 µs)
(26.8 s)
(53.7 s)
(409.6 µs)
(819.2 µs)
Remarks 1. fX
218
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
177
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.2 8-Bit Timer/Event Counters 1 and 2 Configurations
The 8-bit timer/event counters 1 and 2 consist of the following hardware.
Table 9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations
Item
Timer register
8 bits × 2 (TM1, TM2)
Register
Compare register: 8 bits × 2 (CR10, CR20)
Timer output
2 (TO1, TO2)
Control register
Timer clock select register 1 (TCL1)
8-bit timer mode control register 1 (TMC1)
8-bit timer output control register (TOC1)
Port mode register 3 (PM3) Note
Note
178
Configuration
For details, refer to Figure 6-9 P30 to P37 Block Diagram.
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Figure 9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register 10
(CR10)
8-Bit Compare
Register 20
(CR20)
Selector
Note
Match
Match
Selector
11
f XX/2
8-Bit Timer
Register 1
(TM1)
8-Bit Timer
Register 2
(TM2)
INTTM2
Clear
Clear
TI1/P33
4
TO2/P32
4
Selector
9
f XX/2 to fXX/2
8-Bit Timer/
Event Counter
Output Control
Circuit 2
Selector
9
Selector
f XX/2 to f XX/2
11
f XX/2
TI2/P34
8-Bit Timer/
Event Counter
Output Control
Circuit 1
4
Note
TO1/P31
4
TCL TCL TCL TCL TCL TCL TCL TCL
17 16 15 14 13 12 11 10
TMC TCE2 TCE1
12
8-Bit Timer Mode
Control Register
Timer Clock
Select Register 1
LVS2 LVR2 TOC TOE2 LVS1 LVR1 TOC TOE1
15
11
8-Bit Timer Output
Control Register
Internal Bus
Note
Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counter output control circuits 1 and 2,
respectively.
Remark
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
179
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
Level F/F
(LV1)
LVR1
R
Q
TO1/P31
S
LVS1
TOC11
P31
Output Latch
INV
PM31
INTTM1
TOE1
Remark
The section in the broken line is an output control circuit.
Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2
Level F/F
(LV2)
fSCK
LVR2
R
Q
LVS2
TOC15
TO2/P32
S
P32
Output Latch
INV
INTTM2
TOE2
Remarks 1. The section in the broken line is an output control circuit.
2. fSCK : Serial clock frequency
180
PM32
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(1) Compare registers 10 and 20 (CR10, CR20)
These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value,
and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an
interrupt request (INTTM1 and INTTM2, respectively).
When TM1 and TM2 are set to interval timer operation, these registers are used to hold the interval time. When
the PWM output operation is specified, they are used as registers that specify a pulse width.
CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit
memory manipulation instruction. When the compare register is used as an 8-bit timer/event counter, the 00H
to FFH values can be set. When the compare register is used as a 16-bit timer/event counter, the 0000H to
FFFFH values can be set.
RESET input makes CR10 and CR20 undefined.
Caution When using the compare register as 16-bit timer/event counter, be sure to set data after
stopping timer operation.
(2) 8-bit timer registers 1, 2 (TM1, TM2)
These are 8-bit registers to count count pulses.
When TM1 and TM2 are used in the 8-bit timer × 2-channel mode, they are read with an 8-bit memory
manipulation instruction. When TM1 and TM2 are used in 16-bit timer × 1-channel mode, the 16-bit timer (TMS)
is read with a 16-bit memory manipulation instruction.
RESET input clears TM1 and TM2 to 00H.
181
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers
The following four types of registers are used to control the 8-bit timer/event counter.
• Timer clock select register 1 (TCL1)
• 8-bit timer mode control register 1 (TMC1)
• 8-bit timer output control register (TOC1)
• Port mode register 3 (PM3)
(1) Timer clock select register 1 (TCL1)
This register sets count clocks of 8-bit timer registers 1 and 2.
TCL1 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL1 to 00H.
182
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Figure 9-4. Timer Clock Select Register 1 Format
Symbol
7
6
5
4
3
2
1
0
TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
Address
After Reset
R/W
FF41H
00H
R/W
8-Bit Timer Register 2 Count Clock Selection
TCL17 TCL16 TCL15 TCL14
MCS = 1
0
0
0
0
TI2 falling edge
0
0
0
1
TI2 rising edge
0
1
1
0
fX/2
0
1
1
1
fX/2
1
1
0
0
0
0
0
1
2
3
fX/2
4
fX/2
0
1
1
fX/2
1
1
1
1
0
1
1
1
0
1
Other than above
(313 kHz)
5
(156 kHz)
6
(78.1 kHz)
7
(39.1 kHz)
8
(19.5 kHz)
9
(9.8 kHz)
10
(4.9 kHz)
12
(1.2 kHz)
fX/2
(313 kHz)
fX/2
fX/2
1
1
(625 kHz)
(78.1 kHz)
fX/2
1
(625 kHz)
4
fX/2
6
0
0
3
(1.25 MHz)
fX/2
1
0
(1.25 MHz)
fX/2
(156 kHz)
0
1
2
(2.5 MHz)
5
1
1
MCS = 0
7
fX/2
8
fX/2
9
fX/2
11
fX/2
(39.1 kHz)
fX/2
(19.5 kHz)
fX/2
(9.8 kHz)
fX/2
(2.4 kHz)
fX/2
Setting prohibited
8-Bit Timer Register 1 Count Clock Selection
TCL13 TCL12 TCL11 TCL10
MCS = 1
0
0
0
0
TI1 falling edge
0
0
0
1
TI1 rising edge
0
1
1
0
fX/2
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
Other than above
1
0
1
0
1
0
1
0
1
2
fX/2
3
fX/2
4
fX/2
5
fX/2
6
fX/2
7
fX/2
8
fX/2
9
fX/2
11
fX/2
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(2.4 kHz)
MCS = 0
2
(1.25 MHz)
3
(625 kHz)
4
(313 kHz)
5
(156 kHz)
6
(78.1 kHz)
7
(39.1 kHz)
8
(19.5 kHz)
9
(9.8 kHz)
10
(4.9 kHz)
12
(1.2 kHz)
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
fX/2
Setting prohibited
Caution When rewriting TCL1 to other data, stop the timer operation beforehand.
Remarks 1.
2.
3.
4.
5.
fX
:
TI1 :
TI2 :
MCS :
Figures
Main system clock oscillation frequency
8-bit timer register 1 input pin
8-bit timer register 2 input pin
Oscillation mode select register bit 0
in parentheses apply to operation with fX = 5.0 MHz
183
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(2) 8-bit timer mode control register (TMC1)
This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer
register 2.
TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC1 to 00H.
Figure 9-5. 8-Bit Timer Mode Control Register Format
Symbol
7
6
5
4
3
TMC1
0
0
0
0
0
2
1
0
TMC12 TCE2 TCE1
TMC12
Address
After Reset
R/W
FF49H
00H
R/W
Operating Mode Selection
0
8-Bit timer register × 2 channel mode (TM1, TM2)
1
16-Bit timer register × 1 channel mode (TMS)
TCE2
8-Bit Timer Register 2 Operation Control
0
Operation stop (TM2 clear to 0)
1
Operation enable
TCE1
8-Bit Timer Register 1 Operation Control
0
Operation stop (TM1 clear to 0)
1
Operation enable
Cautions 1. Switch the operating mode after stopping timer operation.
2. When used as 16-bit timer register, TCE1 should be used for operation enable/stop.
184
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) 8-bit timer output control register (TOC1)
This register controls operation of 8-bit timer/event counter output control circuits 1 and 2.
It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit
timer registers 1 and 2.
TOC1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC1 to 00H.
Figure 9-6. 8-Bit Timer Output Control Register Format
Symbol
7
6
5
4
3
2
1
0
TOC1 LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1
LVS2 LVR2
Address
After Reset
R/W
FF4FH
00H
R/W
8-Bit Timer/Event Counter 2 Timer Output F/F Status Set
0
0
Unchanged
0
1
Timer output F/F reset (to 0)
1
0
Timer output F/F set (to 1)
1
1
Setting prohibited
TOC15
8-Bit Timer/Event Counter 2 Timer Output F/F Control
0
Inverted operation disable
1
Inverted operation enable
TOE2
8-Bit Timer/Event Counter 2 Output Control
0
Output disable (port mode)
1
Output enable
LVS1 LVR1
8-Bit Timer/Event Counter 1 Timer Output F/F Status Set
0
0
Unchanged
0
1
Timer output F/F reset (to 0)
1
0
Timer output F/F set (to 1)
1
1
Setting prohibited
TOC11
8-Bit Timer/Event Counter 1 Timer Output F/F Control
0
Inverted operation disable
1
Inverted operation enable
TOE1
8-Bit Timer/Event Counter 1 Outptut Control
0
Output disable (port mode)
1
Output enable
Cautions 1. Be sure to set TOC1 after stopping timer operation.
2. LVS1, LVS2, LVR1 and LVR2 are 0 when read after data setting to them.
185
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(4) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and
P32 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 9-7. Port Mode Register 3 Format
Symbol
7
6
5
4
3
2
1
0
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
186
Address
After Reset
R/W
FF23H
FFH
R/W
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.4 8-Bit Timer/Event Counters 1 and 2 Operations
9.4.1 8-bit timer/event counter mode
(1) Interval timer operations
The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly
at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).
When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and
CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1
and INTTM2) are generated.
Count clock of the TM1 can be selected with bits 0 to 3 (TCL10 to TCL13) of the timer clock select register
1 (TCL1). Count clock of the TM2 can be selected with bits 4 to 7 (TCL14 to TCL17) of the timer clock select
register 1 (TCL1).
For the operation to be performed when the value of the compare register is changed during timer count
operation, refer to 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions (3).
Figure 9-8. Interval Timer Operation Timings
t
Count Clock
TM1 Count Value
00
01
Count Start
CR10
N
N
00
01
Clear
N
00
01
N
Clear
N
N
N
INTTM1
Interrupt Request
Acknowledge
Interrupt Request
Acknowledge
TO1
Interval Time
Remark
Interval Time
Interval Time
Interval time = (N + 1) × t : N = 00H to FFH
187
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time
Minimum Interval Time
Maximum Interval Time
Resolution
TCL13 TCL12 TCL11 TCL10
MCS = 1
0
0
0
0
0
0
0
1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
TI1 input cycle
28
× TI1 input cycle
TI1 input edge cycle
TI1 input cycle
28
× TI1 input cycle
TI1 input edge cycle
0
1
1
0
2 × 1/fX
(400 ns)
22
× 1/fX
(800 ns)
× 1/fX
(102.4 µs)
× 1/fX
(204.8 µs)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
0
1
1
1
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
1
0
0
0
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
1
0
0
1
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
212 × 1/fX
(819.2 µs)
213 × 1/fX
(1.64 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
1
0
1
0
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
213 × 1/fX
(1.64 ms)
214 × 1/fX
(3.28 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
1
0
1
1
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
214 × 1/fX
(3.28 ms)
215 × 1/fX
(6.55 ms)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
1
1
0
0
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
215 × 1/fX
(6.55 ms)
216 × 1/fX
(13.1 ms)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
1
1
0
1
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
1
1
1
0
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
1
1
1
1
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
Other than above
Remarks 1. fX
29
210
Setting prohibited
: Main system clock oscillation frequency
2. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register 1 (TCL1)
3. MCS
: Oscillation mode select register bit 0
4. Values in parentheses when operated at fX = 5.0 MHz.
188
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time
Minimum Interval Time
Maximum Interval Time
Resolution
TCL17 TCL16 TCL15 TCL14
MCS = 1
0
0
0
0
0
0
0
1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
TI2 input cycle
28
× TI2 input cycle
TI2 input edge cycle
TI2 input cycle
28
× TI2 input cycle
TI2 input edge cycle
0
1
1
0
2 × 1/fX
(400 ns)
22
× 1/fX
(800 ns)
× 1/fX
(102.4 µs)
× 1/fX
(204.8 µs)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
0
1
1
1
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
1
0
0
0
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
1
0
0
1
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
212 × 1/fX
(819.2 µs)
213 × 1/fX
(1.64 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
1
0
1
0
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
213 × 1/fX
(1.64 ms)
214 × 1/fX
(3.28 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
1
0
1
1
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
214 × 1/fX
(3.28 ms)
215 × 1/fX
(6.55 ms)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
1
1
0
0
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
215 × 1/fX
(6.55 ms)
216 × 1/fX
(13.1 ms)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
1
1
0
1
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
1
1
1
0
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
1
1
1
1
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
Other than above
Remarks 1. fX
29
210
Setting prohibited
: Main system clock oscillation frequency
2. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register 1 (TCL1)
3. MCS
: Oscillation mode select register bit 0
4. Values in parentheses when operated at fX = 5.0 MHz
189
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(2) External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/
P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2).
TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1)
is input. Either the rising or falling edge can be selected.
When the TM1 and TM2 counted values match the values of 8-bit compare registers (CR10 and CR20), TM1
and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Figure 9-9. External Event Counter Operation Timings (with Rising Edge Specified)
TI1 Pin Input
TM1 Count Value
00
01
CR10
INTTM1
Remark
190
N = 00H to FFH
02
03
04
05
N
N–1
N
00
01
02
03
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Square-wave output operation
A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers
10 and 20 (CR10 and CR20).
The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20
by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables
a square wave with any selected frequency to be output.
Table 9-8. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
Minimum Pulse Width
Maximum Pulse Width
Resolution
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
2 × 1/fX
(400 ns)
22
× 1/fX
(800 ns)
× 1/fX
(102.4 µs)
210
× 1/fX
(204.8 µs)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
212 × 1/fX
(819.2 µs)
213 × 1/fX
(1.64 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
213 × 1/fX
(1.64 ms)
214 × 1/fX
(3.28 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
214 × 1/fX
(3.28 ms)
215 × 1/fX
(6.55 ms)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
215 × 1/fX
(6.55 ms)
216 × 1/fX
(13.1 ms)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
216 × 1/fX
(13.1 ms)
217 × 1/fX
(26.2 ms)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
Remarks 1. fX
29
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
191
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Figure 9-10. Square Wave Output Operation Timing
Count Clock
TM1 Count Value
00
01
CR10
02
N–1
N
00
01
02
N–1
N
00
N
TO1 Pin Output Note
Note
The initial value of TO1 output can be set by using bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output
control register (TOC1).
192
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.4.2 16-bit timer/event counter mode
When bit 2 (TMC12) of 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode
is set.
In this mode, the count clock is selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The overflow signal of 8-bit timer/event counter 1 (TM1) is used as the count clock to 8-bit timer/event counter 2 (TM2).
In this mode, the count operation enable/disable is selected with bit 0 (TCE1) of TMC1.
(1) Interval timer operation
The 16-bit timer/event counter can operate as an interval timer which generates interrupt requests repeatedly
at intervals of the count value preset to 2-channel 8-bit compare registers (CR10 and CR20). To set a count
value, set the value of the high-order 8 bits to CR20, and the value of the low-order 8 bits to CR10. For the
count value that can be set (interval time), refer to Table 9-7.
When the 8-bit timer register 1 (TM1) and CR10 values match and the 8-bit timer register 2 (TM2) and CR20
values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal
(INTTM2) is generated. For the operation timing of the interval timer, refer to Figure 9-11.
The count clock can be selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The overflow signal of TM1 is used as the count clock to TM2.
Figure 9-11. Interval Timer Operation Timing
t
Count Clock
TMS (TM1, TM2) Count Value
0000
0001
Count Start
CR10, CR20
N
N
0000 0001
N
0000 0001
Clear
Clear
N
N
N
N
INTTM2
Interrupt Request
Acknowledge
Interrupt Request
Acknowledge
TO2
Interval Time
Remark
Interval Time
Interval Time
Interval time = (N + 1) × t : N = 0000H to FFFFH
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the
CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter
output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit
interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading the 16-bit timer (TMS) count value, use the 16-bit memory manipulation
instruction.
193
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters
(TM1 and TM2) are Used as 16-Bit Timer/Event Counter
Minimum Interval Time
Maximum Interval Time
Resolution
TCL13 TCL12 TCL11 TCL10
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
0
0
0
0
TI1 input cycle
28 × TI1 input cycle
TI1 input edge cycle
0
0
0
1
TI1 input cycle
28 × TI1 input cycle
TI1 input edge cycle
0
1
1
0
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
0
1
1
1
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
1
0
0
0
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
1
0
0
1
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
220 × 1/fX
(209.7 ms)
221 × 1/fX
(419.4 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
1
0
1
0
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
221 × 1/fX
(419.4 ms)
222 × 1/fX
(838.9 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
1
0
1
1
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
222 × 1/fX
(838.9 ms)
223 × 1/fX
(1.7 s)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
1
1
0
0
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
223 × 1/fX
(1.7 s)
224 × 1/fX
(3.4 s)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
1
1
0
1
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
224 × 1/fX
(3.4 s)
225 × 1/fX
(6.7 s)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
1
1
1
0
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
225 × 1/fX
(6.7 s)
226 × 1/fX
(13.4 s)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
1
1
1
1
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
227 × 1/fX
(26.8 s)
228 × 1/fX
(53.7 s)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
Other than above
Remarks 1. fX
Setting prohibited
: Main system clock oscillation frequency
2. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register 1 (TCL1)
3. MCS
: Oscillation mode select register bit 0
4. Values in parentheses when operated at fX = 5.0 MHz.
194
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
(2) External event counter operations
The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2channel 8-bit timer registers 1 and 2 (TM1 and TM2).
TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input.
When TM1 overflows as a result, TM2 is incremented with the overflow signal used as its count clock.
When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and
CR20), TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated.
Figure 9-12. External Event Counter Operation Timings (with Rising Edge Specified)
TI1 Pin Input
TM1, TM2 Count Value
0000 0001 0002 0003 0004 0005
CR10, CR20
N–1
N
0000 0001 0002 0003
N
INTTM2
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the
CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter
output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit
interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading the 16-bit timer (TMS) count value, use the 16-bit memory manipulation
instruction.
195
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Square-wave output operation
A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers
10 and 20 (CR10 and CR20).
The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting
bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected
frequency to be output.
Table 9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters
(TM1 and TM2) are Used as 16-Bit Timer/Event Counter
Minimum Pulse Width
Maximum Pulse Width
MCS = 1
MCS = 0
MCS = 1
MCS = 0
MCS = 1
MCS = 0
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
217 × 1/fX
(26.2 ms)
218 × 1/fX
(52.4 ms)
2 × 1/fX
(400 ns)
22 × 1/fX
(800 ns)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
218 × 1/fX
(52.4 ms)
219 × 1/fX
(104.9 ms)
22 × 1/fX
(800 ns)
23 × 1/fX
(1.6 µs)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
219 × 1/fX
(104.9 ms)
220 × 1/fX
(209.7 ms)
23 × 1/fX
(1.6 µs)
24 × 1/fX
(3.2 µs)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
220 × 1/fX
(209.7 ms)
221 × 1/fX
(419.4 ms)
24 × 1/fX
(3.2 µs)
25 × 1/fX
(6.4 µs)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
221 × 1/fX
(419.4 ms)
222 × 1/fX
(838.9 ms)
25 × 1/fX
(6.4 µs)
26 × 1/fX
(12.8 µs)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
222 × 1/fX
(838.9 ms)
223 × 1/fX
(1.7 s)
26 × 1/fX
(12.8 µs)
27 × 1/fX
(25.6 µs)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
223 × 1/fX
(1.7 s)
224 × 1/fX
(3.4 s)
27 × 1/fX
(25.6 µs)
28 × 1/fX
(51.2 µs)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
224 × 1/fX
(3.4 s)
225 × 1/fX
(6.7 s)
28 × 1/fX
(51.2 µs)
29 × 1/fX
(102.4 µs)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
225 × 1/fX
(6.7 s)
226 × 1/fX
(13.4 s)
29 × 1/fX
(102.4 µs)
210 × 1/fX
(204.8 µs)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
227 × 1/fX
(26.8 s)
228 × 1/fX
(53.7 s)
211 × 1/fX
(409.6 µs)
212 × 1/fX
(819.2 µs)
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses when operated at fX = 5.0 MHz.
196
Resolution
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
Figure 9-13. Square Wave Output Operation Timing
Count clock
TM1
00H
TM2
00H
01H
N N+1
CR10
N
CR20
M
FFH 00H
FFH 00H
01H
02H
FFH 00H 01H
M–1 M
N 00H 00H
00H
Interval Time
TO20
Count Starts
Level Inverted
Counter Cleared
197
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
9.5 8-Bit Timer/Event Counters 1 and 2 Precautions
(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be
generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started
asynchronously with the count pulse.
Figure 9-14. 8-Bit Timer Registers 1 and 2 Start Timing
Count Pulse
TM1, TM2 Count Value
00H
01H
02H
03H
04H
Timer Start
(2) 8-bit compare register 10 and 20 setting
The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H.
Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be
carried out.
When the 8-bit compare register is used as 16-bit timer/event counter, write data to CR10 and CR20 after
setting bit 0 (TCE1) of the 8-bit timer mode control register 1 to 0 and stopping timer operation.
Figure 9-15. External Event Counter Operation Timing
TI1, TI2, Input
CR10, CR20
TM1, TM2 Count Value
TO1, TO2
Interrupt Request Flag
198
00H
00H
00H
00H
00H
CHAPTER 9
8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Operation after compare register change during timer count operation
If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those
of 8-bit timer registers 1 and 2 (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart
counting from 0. Thus, if the value (M) after CR10 and CR20 change is smaller than value (N) before the
change, it is necessary to restart the timer after changing CR10 and CR20.
Figure 9-16. Timing after Compare Register Change during Timer Count Operation
Count Pulse
CR10, CR20
N
TM1, TM2 Count Value
X–1
Remark
M
X
FFH
00H
01H
02H
N>X>M
199
[MEMO]
200
CHAPTER 10 WATCH TIMER
10.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch timer and the interval timer can be used simultaneously.
(1) Watch timer
When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.
When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second
or 0.25 second intervals.
Caution 0.5-second intervals cannot be generated with the 5.0-MHz main system clock. You should
switch to the 32.768 kHz subsystem clock to generate 0.5-second intervals.
(2) Interval timer
Interrupt requests (INTTM3) are generated at the preset time interval.
Table 10-1. Interval Timer Interval Time
Interval Time
When operated at
fXX = 5.0 MHz
When operated at
fXX = 4.19 MHz
When operated at
fXT = 32.768 kHz
24 × 1/fW
410 µs
488 µs
488 µs
25
× 1/fW
819 µs
977 µs
977 µs
26
× 1/fW
1.64 ms
1.95 ms
1.95 ms
27
× 1/fW
3.28 ms
3.91 ms
3.91 ms
28
× 1/fW
6.55 ms
7.81 ms
7.81 ms
29
× 1/fW
13.1 ms
15.6 ms
15.6 ms
Remark
fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency
fW : Watch timer clock frequency (fXX/27 or fXT)
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WATCH TIMER
10.2 Watch Timer Configuration
The watch timer consists of the following hardware.
Table 10-2. Watch Timer Configuration
Item
Configuration
Counter
5 bits × 1
Control register
Timer clock select register 2 (TCL2)
Watch timer mode control register (TMC2)
10.3 Watch Timer Control Registers
The following two types of registers are used to control the watch timer.
• Timer clock select register 2 (TCL2)
• Watch timer mode control register (TMC2)
(1) Timer clock select register 2 (TCL2)
This register sets the watch timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark
Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer
output frequency.
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WATCH TIMER
Figure 10-1. Watch Timer Block Diagram
fW fW fW
24 25 26
fW fW
27 28
fW
29
fW
213
INTWT
INTTM3
To 16-Bit Timer/
Event Counter
3
TCL24
Selector
Prescaler
fW
214
Selector
f XT
fW
5-Bit
Counter
Clear
f XX /2
Clear
Selector
7
Selector
TMC21
To LCD
Controller/Driver
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
Watch Timer Mode
Control Register
Timer Clock
Select Register 2
Internal Bus
Remark
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
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WATCH TIMER
Figure 10-2. Timer Clock Select Register 2 Format
Symbol
7
5
6
4
TCL2 TCL27 TCL26 TCL25 TCL24
3
0
2
1
0
TCL22 TCL21 TCL20
Address
FF42H
After
Reset
00H
R/W
R/W
Buzzer Output Frequency Selection
TCL27 TCL26 TCL25
MCS = 0
MCS = 1
0
×
×
Buzzer output disable
1
0
0
9
fX /2 (9.8 kHz)
fX /210 (4.9 kHz)
1
0
1
f X /210 (4.9 kHz)
f X /211 (2.4 kHz)
1
1
0
f X /211 (2.4 kHz)
f X /212 (1.2 kHz)
1
1
1
Setting prohibited
Watch Timer Count Clock Selection
TCL24
MCS = 0
MCS = 1
7
0
fX /2 (39.1 kHz)
1
f XT (32.768 kHz)
8
fX /2 (19.5 kHz)
Watchdog Timer Count Clock Selection
TCL22 TCL21 TCL20
MCS = 0
MCS = 1
0
0
0
3
fX /2 (625 kHz)
fX /24 (313 kHz)
0
0
1
f X /24 (313 kHz)
f X /25 (156 kHz)
0
1
0
f X /25 (156 kHz)
f X /26 (78.1 kHz)
0
1
1
f X /26 (78.1 kHz)
f X /27 (39.1 kHz)
1
0
0
f X /27 (39.1 kHz)
f X /28 (19.5 kHz)
1
0
1
f X /28 (19.5 kHz)
f X /29 (9.8 kHz)
1
1
0
f X /29 (9.8 kHz)
f X /210 (4.9 kHz)
1
1
1
f X /211 (2.4 kHz)
f X /212 (1.2 kHz)
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.
Remarks 1. fX
: Main system clock oscillation frequency
2. fXT
: Subsystem clock oscillation frequency
3. ×
: don't care
4. MCS : Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
204
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WATCH TIMER
(2) Watch timer mode control register (TMC2)
This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/
disables prescaler and 5-bit counter operations.
TMC2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC2 to 00H.
Figure 10-3. Watch Timer Mode Control Register Format
Symbol
7
TMC2
0
6
5
4
3
2
1
0
Address
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
FF4AH
After
Reset
00H
R/W
R/W
Prescaler Interval Time Selection
TMC26 TMC25 TMC24
fXX = 4.19-MHz Operation
fXX = 5.0-MHz Operation
0
0
fXT = 32.768-kHz Operation
0
2 /f W (410 µ s)
2 /f W (488 µ s)
2 /f W (488 µ s)
4
4
4
0
0
1
2 /f W (819 µ s)
2 /f W (977 µ s)
25/f W (977 µ s)
0
1
0
26/f W (1.64 ms)
26/f W (1.95 ms)
26/f W (1.95 ms)
0
1
1
27/f W (3.28 ms)
27/f W (3.91 ms)
27/f W (3.91 ms)
1
0
0
28/f W (6.55 ms)
28/f W (7.81 ms)
28/f W (7.81 ms)
1
0
1
29/f W (13.1 ms)
29/f W (15.6 ms)
29/f W (15.6 ms)
Other than above
5
5
Setting prohibited
Watch Flag Set Time Selection
TMC23
fXX = 5.0-MHz Operation
fXX = 4.19-MHz Operation
fXT = 32.768-kHz Operation
0
214/f W (0.4 sec)
214/f W (0.5 sec)
214/f W (0.5 sec)
1
213/f W (0.2 sec)
213/f W (0.25 sec)
213/f W (0.25 sec)
TMC22
5-Bit Counter Operation Control
0
Clear after operation stop
1
Operation enable
TMC21
Prescaler Operation Control
0
Clear after operation stop
1
Operation enable
Watch Operating Mode Selection
TMC20
0
Normal operating mode (flag set at f W /2 14 )
1
Fast feed operating mode (flag set at f W /25)
Caution When the watch timer is used, the prescaler should not be cleared frequently.
Remark
fW : Watch timer clock frequency (fXX/27 or fXT)
fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency
205
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WATCH TIMER
10.4 Watch Timer Operations
10.4.1 Watch timer operation
When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch
timer with a 0.5-second or 0.25-second interval.
The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/
HALT mode) can be cleared by setting WTIF to 1.
When bit 2 (TIMC22) of the watch timer mode control register is set to 0, the 5-bit counter is cleared and the count
operation stops.
For simultaneous operation of the interval timer, zero-second start can be achieved by setting TMC22 to 0
(maximum error: 26.2 ms when operated at fXX = 5.0 MHz).
10.4.2 Interval timer operation
The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the
preset count value.
The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register.
Table 10-3. Interval Timer Interval Time
TMC26
TMC25
TMC24
Interval Time
When operated at
fXX = 5.0 MHz
When operated at
fXX = 4.19 MHz
When operated at
fXT = 32.768 kHz
0
0
0
24 × 1/fW
410 µs
488 µs
488 µs
0
0
1
25 × 1/fW
819 µs
977 µs
977 µs
0
1
0
26 × 1/fW
1.64 ms
1.95 ms
1.95 ms
0
1
1
27 × 1/fW
3.28 ms
3.91 ms
3.91 ms
1
0
0
28 × 1/fW
6.55 ms
7.81 ms
7.81 ms
1
0
1
29 × 1/fW
13.1 ms
15.6 ms
15.6 ms
Other than above
Remark
Setting prohibited
fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency
fW : Watch timer clock frequency (fXX/27 or fXT)
206
CHAPTER 11 WATCHDOG TIMER
11.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register
(WDTM).
(1) Watchdog timer mode
An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable
interrupt request or RESET can be generated.
Table 11-1. Watchdog Timer Inadvertent Program Overrun Detection Times
Runaway Detection Time
MCS = 1
MCS = 0
211 × 1/fXX
211 × 1/fX (410 µs)
212 × 1/fX (819 µs)
212 × 1/fXX
212 × 1/fX (819 µs)
213 × 1/fX (1.64 ms)
213 × 1/fXX
213 × 1/fX (1.64 ms)
214 × 1/fX (3.28 ms)
214 × 1/fXX
214 × 1/fX (3.28 ms)
215 × 1/fX (6.55 ms)
215 × 1/fXX
215 × 1/fX (6.55 ms)
216 × 1/fX (13.1 ms)
216 × 1/fXX
216 × 1/fX (13.1 ms)
217 × 1/fX (26.2 ms)
217 × 1/fXX
217 × 1/fX (26.2 ms)
218 × 1/fX (52.4 ms)
219 × 1/fXX
219 × 1/fX (104.9 ms)
220 × 1/fX (209.7 ms)
Remarks 1. fXX
2. fX
: Main system clock frequency (fX or fX/2)
: Main system clock oscillation frequency
3. MCS : Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
207
CHAPTER 11
WATCHDOG TIMER
(2) Interval timer mode
Interrupt requests are generated at the preset time intervals.
Table 11-2. Interval Times
Interval Time
211
212
213
214
215
216
217
219
MCS = 1
× 1/fXX
211
× 1/fXX
212
× 1/fXX
213
× 1/fXX
214
× 1/fXX
215
× 1/fXX
216
× 1/fXX
217
× 1/fXX
219
Remarks 1. fXX
2. fX
CS = 0
× 1/fX (410 µs)
212
× 1/fX (819 µs)
× 1/fX (819 µs)
213
× 1/fX (1.64 ms)
× 1/fX (1.64 ms)
214
× 1/fX (3.28 ms)
× 1/fX (3.28 ms)
215
× 1/fX (6.55 ms)
× 1/fX (6.55 ms)
216
× 1/fX (13.1 ms)
× 1/fX (13.1 ms)
217
× 1/fX (26.2 ms)
× 1/fX (26.2 ms)
218
× 1/fX (52.4 ms)
× 1/fX (104.9 ms)
220
× 1/fX (209.7 ms)
: Main system clock frequency (fX or fX/2)
: Main system clock oscillation frequency
3. MCS : Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
208
CHAPTER 11
WATCHDOG TIMER
11.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware.
Table 11-3. Watchdog Timer Configuration
Item
Configuration
Control register
Timer clock select register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 11-1. Watchdog Timer Block Diagram
Internal Bus
f XX /23
Prescaler
TMMK4
f XX f XX f XX f XX f XX f XX f XX
24 25 26 27 28 29 211
Selector
RUN
TMIF4
8-Bit Counter
Control
Circuit
INTWDT
Maskable
Interrupt
Request
RESET
INTWDT
Non-Maskable
Interrupt
Request
3
TCL22 TCL21 TCL20
RUN WDTM4 WDTM3
Timer Clock Select Register 2
Watchdog Timer Mode Register
Internal Bus
Remark
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
209
CHAPTER 11
WATCHDOG TIMER
11.3 Watchdog Timer Control Registers
The following two types of registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark
Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer
output frequency.
210
CHAPTER 11
WATCHDOG TIMER
Figure 11-2. Timer Clock Select Register 2 Format
Symbol
7
5
6
4
3
TCL2 TCL27 TCL26 TCL25 TCL24
0
2
1
0
TCL22 TCL21 TCL20
After
Reset
00H
Address
FF42H
R/W
R/W
Buzzer Output Frequency Selection
TCL27 TCL26 TCL25
MCS = 0
MCS = 1
0
×
×
Buzzer output disable
1
0
0
9
fX /2 (9.8 kHz)
fX /210 (4.9 kHz)
1
0
1
f X /210 (4.9 kHz)
f X /211 (2.4 kHz)
1
1
0
f X /211 (2.4 kHz)
f X /212 (1.2 kHz)
1
1
1
Setting prohibited
Watch Timer Count Clock Selection
TCL24
MCS = 1
MCS = 0
7
8
0
fX/2 (39.1 kHz)
1
f XT (32.768 kHz)
fX/2 (19.5 kHz)
Watchdog Timer Count Clock Selection
TCL22 TCL21 TCL20
MCS = 0
MCS = 1
0
0
0
3
fX /2 (625 kHz)
4
4
(313 kHz)
5
(156 kHz)
fX /2
0
0
1
f X /2 (313 kHz)
f X /2
0
1
0
f X /25 (156 kHz)
f X /26 (78.1 kHz)
0
1
1
f X /26 (78.1 kHz)
f X /27 (39.1 kHz)
1
0
0
f X /27 (39.1 kHz)
f X /28 (19.5 kHz)
1
0
1
f X /28 (19.5 kHz)
f X /29 (9.8 kHz)
1
1
0
f X /29 (9.8 kHz)
f X /210 (4.9 kHz)
1
1
1
f X /211 (2.4 kHz)
f X /212 (1.2 kHz)
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.
Remarks 1. fX
: Main system clock oscillation frequency
2. fXT
: Subsystem clock oscillation frequency
3. ×
: don't care
4. MCS : Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
211
CHAPTER 11
WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 11-3. Watchdog Timer Mode Register Format
Symbol
7
WDTM RUN
6
5
0
0
4
3
WDTM4 WDTM3
RUN
2
1
0
Address
0
0
0
FFF9H
After
Reset
00H
R/W
R/W
Watchdog Timer Operation Mode Selection Note 1
0
Count stop
1
Counter is cleared and counting starts.
WDTM4WDTM3
Watchdog Timer Operation Mode Selection Note 2
0
×
Interval timer mode (Maskable interrupt occurs upon generation of an overflow.) Note 3
1
0
Watchdog timer mode 1 (Non-maskable interrupt occurs upon generation of an overflow.)
1
0
Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.)
Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
2. Once set to 1, RUN cannot be cleared to 0 by software.
Thus, once counting starts, it can only be stopped by RESET input.
3. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1.
Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is
up to 0.5 % shorter than the time set by timer clock select register 2.
2. To use the watchdog timer modes 1 and 2, confirm that the interrupt request flag (TMIF4)
is 0 and then set the WDTM4 to 1.
If WDTM4 is set while TMIF4 is 1, the non-maskable interrupt request occurs regardless
of the content of WDTM3.
Remark
212
×: don't care
CHAPTER 11
WATCHDOG TIMER
11.4 Watchdog Timer Operations
11.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated
to detect any inadvertent program loop.
The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to
2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1
within the set overrun detection time interval. The watchdog timer can be cleared and counting is started by setting
RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable
interrupt request is generated according to the WDTM bit 3 (WDTM3) value.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual overrun detection time may be shorter than the set time by a maximum of
0.5 %.
2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
stopped.
Table 11-4. Watchdog Timer Overrun Detection Time
TCL22
0
0
0
0
1
1
1
1
TCL21
0
0
1
1
0
0
1
1
TCL20
Runaway Detection Time
0
211
1
212
0
213
1
214
0
215
1
216
0
217
1
219
Remarks 1. fXX
2. fX
MCS = 1
× 1/fXX
211
× 1/fXX
212
× 1/fXX
213
× 1/fXX
214
× 1/fXX
215
× 1/fXX
216
× 1/fXX
217
× 1/fXX
219
MCS = 0
× 1/fX (410 µs)
212
× 1/fX (819 µs)
× 1/fX (819 µs)
213
× 1/fX (1.64 ms)
× 1/fX (1.64 ms)
214
× 1/fX (3.28 ms)
× 1/fX (3.28 ms)
215
× 1/fX (6.55 ms)
× 1/fX (6.55 ms)
216
× 1/fX (13.1 ms)
× 1/fX (13.1 ms)
217
× 1/fX (26.2 ms)
× 1/fX (26.2 ms)
218
× 1/fX (52.4 ms)
× 1/fX (104.9 ms)
220
× 1/fX (209.7 ms)
: Main system clock frequency (fX or fX/2)
: Main system clock oscillation frequency
3. MCS : Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
213
CHAPTER 11
WATCHDOG TIMER
11.4.2 Interval timer operation
The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of
the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
The count clock (interval timer) can be selected by bits 0 to 2 (TCL20 to TCL22) of the timer clock select register
2 (TCL2). The watchdog timer starts operating as an interval timer when bit 7 (RUN) of WDTM is set to 1.
When the watchdog timer is operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag
(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt
requests, the INTWDT default has the highest priority.
The interval timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set bit 7 of WDTM
(RUN) to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval
timer mode is not set unless RESET input is applied.
2. The interval time just after setting with WDTM may be shorter than the set time by a maximum
of 0.5 %.
3. When the subsystem clock is selected as the CPU clock, watchdog timer count operation is
stopped.
Table 11-5. Interval Timer Interval Time
TCL22
TCL21
TCL20
Interval Time
0
0
0
211 × 1/fXX
211 × 1/fX (410 µs)
212 × 1/fX (819 µs)
0
0
1
212 × 1/fXX
212 × 1/fX (819 µs)
213 × 1/fX (1.64 ms)
0
1
0
213 × 1/fXX
213 × 1/fX (1.64 ms)
214 × 1/fX (3.28 ms)
0
1
1
214 × 1/fXX
214 × 1/fX (3.28 ms)
215 × 1/fX (6.55 ms)
1
0
0
215 × 1/fXX
215 × 1/fX (6.55 ms)
216 × 1/fX (13.1 ms)
1
0
1
216 × 1/fXX
216 × 1/fX (13.1 ms)
217 × 1/fX (26.2 ms)
1
1
0
217 × 1/fXX
217 × 1/fX (26.2 ms)
218 × 1/fX (52.4 ms)
1
1
1
219 × 1/fXX
219 × 1/fX (104.9 ms)
220 × 1/fX (209.7 ms)
Remarks 1. fXX
2. fX
MCS = 1
: Main system clock frequency (fX or fX/2)
: Main system clock oscillation frequency
3. MCS : Oscillation mode select register bit 0
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
214
MCS = 0
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
12.1 Clock Output Control Circuit Functions
The clock output control circuit is intended for carrier output during remote controlled transmission and clock output
for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/
P35 pin.
Follow the procedure below to output clock pulses.
(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03)
of TCL0.
(2) Set the P35 output latch to 0.
(3) Set bit 5 (PM35) of port mode register 3 to 0 (set to output mode).
(4) Set bit 7 (CLOE) of TCL0 to 1.
Caution Clock output cannot be used when setting P35 output latch to 1.
Remark
When clock output enable/disable is switched, the clock output control circuit does not output pulses
with small widths (See the portions marked with * in Figure 12-1).
Figure 12-1. Remote Controlled Output Application Example
CLOE
*
*
PCL/P35 Pin Output
215
CHAPTER 12
CLOCK OUTPUT CONTROL CIRCUIT
12.2 Clock Output Control Circuit Configuration
The clock output control circuit consists of the following hardware.
Table 12-1. Clock Output Control Circuit Configuration
Item
Control register
Configuration
Timer clock select register 0 (TCL0)
Port mode register 3 (PM3)
Figure 12-2. Clock Output Control Circuit Block Diagram
f XX
f XX /2
f XX /23
f XX /24
f XX /25
Selector
f XX /22
Synchronizing
Circuit
PCL /P35
f XX /26
f XX /27
f XT
4
CLOE TCL03 TCL02 TCL01 TCL00
P35
Output Latch
Port Mode Register 3
Timer Clock Select Register 0
Internal Bus
Remark
216
PM35
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
CHAPTER 12
CLOCK OUTPUT CONTROL CIRCUIT
12.3 Clock Output Function Control Registers
The following two types of registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TCL0 to 00H.
Remark
Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock.
217
CHAPTER 12
CLOCK OUTPUT CONTROL CIRCUIT
Figure 12-3. Timer Clock Select Register 0 Format
Symbol
7
6
5
4
3
2
1
0
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
CLOE
After
Reset
00H
Address
FF40H
R/W
R/W
PCL Output Control
0
Output disable
1
Output enable
16-Bit Timer Register Count Clock Selection
TCL06 TCL05 TCL04
MCS = 0
MCS = 1
0
0
0
TI00 (Valid edge specifiable)
0
0
1
Setting prohibited
fX
0
1
0
fX
f X /2 (2.5 MHz)
0
1
1
f X /2 (2.5 MHz)
f X /22 (1.25 MHz)
1
0
0
f X /22 (1.25 MHz)
f X /23 (625 kHz)
1
1
1
Watch Timer Output (INTTM3)
Other than above
(5.0 MHz)
(5.0 MHz)
Setting prohibited
PCL Output Clock Selection
TCL03 TCL02 TCL01 TCL00
MCS = 0
MCS = 1
0
0
0
0
f XT (32.768 kHz)
0
1
0
1
fX
0
1
1
0
f X /2 (2.5 MHz)
f X /22 (1.25 MHz)
0
1
1
1
f X /22 (1.25 MHz)
f X /23 (625 kHz)
1
0
0
0
f X /23 (625 kHz)
f X /24 (313 kHz)
1
0
0
1
f X /24 (313 kHz)
f X /25 (156 kHz)
1
0
1
0
f X /25 (156 kHz)
f X /26 (78.1 kHz)
1
0
1
1
f X /26 (78.1 kHz)
f X /27 (39.1 kHz)
1
1
0
0
f X /27 (39.1 kHz)
f X /28 (19.5 kHz)
Other than above
(5.0 MHz)
f X /2 (2.5 MHz)
Setting prohibited
Cautions 1. Setting of the TI00/INTP0 pin valid edge is performed by external interrupt mode register
0, and selection of the sampling clock frequency is performed by the sampling clock
selection register.
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the timer operation beforehand.
218
CHAPTER 12
Remarks 1. fX
CLOCK OUTPUT CONTROL CIRCUIT
: Main system clock oscillation frequency
2. fXT
: Subsystem clock oscillation frequency
3. TI00 : 16-bit timer/event counter input pin
4. TM0 : 16-bit timer register
5. MCS : Oscillation mode select register bit 0
6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
(2) Port mode register 3 (PM3)
This register set port 3 input/output in 1-bit units.
When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 12-4. Port Mode Register 3 Format
Symbol
PM3
7
6
5
4
3
2
1
0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
Address
FF23H
After
Reset
FFH
R/W
R/W
PM3 Pin Input/Output Mode Selection (n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
219
[MEMO]
220
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
13.1 Buzzer Output Control Circuit Functions
The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer
frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin.
Follow the procedure below to output the buzzer frequency.
(1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2.
(2) Set the P36 output latch to 0.
(3) Set bit 6 (PM36) of port mode register 3 to 0 (Set to output mode).
Caution Buzzer output cannot be used when setting P36 output latch to 1.
13.2 Buzzer Output Control Circuit Configuration
The buzzer output control circuit consists of the following hardware.
Table 13-1. Buzzer Output Control Circuit Configuration
Item
Configuration
Control register
Timer clock select register 2 (TCL2)
Port mode register 3 (PM3)
Figure 13-1. Buzzer Output Control Circuit Block Diagram
Selector
f XX /29
f XX /210
f XX /211
BUZ/P36
3
TCL27 TCL26 TCL25
P36
Output Latch
PM36
Port Mode Register 3
Timer Clock Select Register 2
Internal Bus
Remark
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
221
CHAPTER 13
BUZZER OUTPUT CONTROL CIRCUIT
13.3 Buzzer Output Function Control Registers
The following two types of registers are used to control the buzzer output function.
• Timer clock select register 2 (TCL2)
• Port mode register 3 (PM3)
(1) Timer clock select register 2 (TCL2)
This register sets the buzzer output frequency.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark
Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the
watchdog timer count clock.
222
CHAPTER 13
BUZZER OUTPUT CONTROL CIRCUIT
Figure 13-2. Timer Clock Select Register 2 Format
Symbol
7
5
6
4
3
TCL2 TCL27 TCL26 TCL25 TCL24
0
2
1
0
TCL22 TCL21 TCL20
After
Reset
00H
Address
FF42H
R/W
R/W
Buzzer Output Frequency Selection
TCL27 TCL26 TCL25
MCS = 0
MCS = 1
0
×
×
Buzzer output disable
1
0
0
9
fX /2 (9.8 kHz)
fX /210 (4.9 kHz)
1
0
1
f X /210 (4.9 kHz)
f X /211 (2.4 kHz)
1
1
0
f X /211 (2.4 kHz)
f X /212 (1.2 kHz)
1
1
1
Setting prohibited
Watch Timer Count Clock Selection
TCL24
MCS = 1
MCS = 0
7
0
fX/2 (39.1 kHz)
1
f XT (32.768 kHz)
8
fX/2 (19.5 kHz)
Watchdog Timer Count Clock Selection
TCL22 TCL21 TCL20
MCS = 0
MCS = 1
0
0
0
3
fX /2 (625 kHz)
4
4
(313 kHz)
5
(156 kHz)
fX /2
0
0
1
f X /2 (313 kHz)
f X /2
0
1
0
f X /25 (156 kHz)
f X /26 (78.1 kHz)
0
1
1
f X /26 (78.1 kHz)
f X /27 (39.1 kHz)
1
0
0
f X /27 (39.1 kHz)
f X /28 (19.5 kHz)
1
0
1
f X /28 (19.5 kHz)
f X /29 (9.8 kHz)
1
1
0
f X /29 (9.8 kHz)
f X /210 (4.9 kHz)
1
1
1
f X /211 (2.4 kHz)
f X /212 (1.2 kHz)
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.
Remarks 1. fX
: Main system clock oscillation frequency
2. fXT
: Subsystem clock oscillation frequency
3. ×
: don't care
4. MCS : Oscillation mode select register bit 0
5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
223
CHAPTER 13
BUZZER OUTPUT CONTROL CIRCUIT
(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 13-3. Port Mode Register 3 Format
Symbol
PM3
7
5
4
3
2
1
0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
224
6
Address
FF23H
After
Reset
FFH
PM3 Pin Input/Output Mode Selection (n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
R/W
R/W
CHAPTER 14 A/D CONVERTER
14.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an
8-bit resolution.
The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D
conversion result register (ADCR).
The following two ways are available to start A/D conversion.
(1) Hardware start
Conversion is started by trigger input (INTP3).
(2) Software start
Conversion is started by setting the A/D converter mode register.
Select one channel of analog input from ANI0 to ANI7 to execute A/D conversion. In the case of hardware start,
A/D conversion operation stops and an interrupt request (INTAD) is generated when the conversion operation ends.
In the case of software start, the conversion operation is repeated. Each time the conversion operation ends, INTAD
is generated.
14.2 A/D Converter Configuration
The A/D converter consists of the following hardware.
Table 14-1. A/D Converter Configuration
Item
Configuration
Analog input
8 Channels (ANI0 to ANI7)
Control register
A/D converter mode register (ADM)
A/D converter input select register (ADIS)
External interrupt mode register 1 (INTM1)
Register
Successive approximation register (SAR)
A/D conversion result register (ADCR)
225
CHAPTER 14
A/D CONVERTER
Figure 14-1. A/D Converter Block Diagram
Internal Bus
A/D Converter Input
Select Register
ADIS3 ADIS2 ADIS1 ADIS0
4
Note 2
Sample & Hold Circuit
AV SS
Voltage
Comparator
Tap Selector
Note 1
Selector
Series Resistor String
Selector
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
Successive
Approximation
Register (SAR)
AVREF
AVSS
3
ADM1 to ADM3
Edge
Detector
INTP3/P03
Control
Circuit
INTAD
INTP3
ES40, ES41 Note 3
Trigger Enable
3
CS TRG FR1 FR0 ADM3 ADM2 ADM1
A / D Conversion
Result Register
(ADCR)
A /D Converter Mode Register
Internal Bus
Notes 1. Selector to select the number of channels to be used for analog input.
2. Selector to select the channel for A/D conversion.
3. Bits 0 and 1 of external interrupt mode register 1 (INTM1)
226
CHAPTER 14
A/D CONVERTER
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is set (termination of A/D conversion), the SAR contents are
transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR)
This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result
is loaded from the successive approximation register.
ADCR is read with an 8-bit memory manipulation instruction.
RESET input makes ADCR undefined.
(3) Sample & hold circuit
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and
sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D
conversion.
(4) Voltage comparator
The voltage comparator compares the analog input to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected between AVREF and AVSS and generates a voltage to be compared with
the analog input.
(6) ANI0 to ANI7 pins
These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter.
Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used
as input/output ports.
Caution Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AVREF
or lower than AVSS is applied (even if within the absolute maximum ratings), the converted
value of the corresponding channel becomes indeterminate and may adversely affect the
converted values of other channels.
(7) AVREF pin
This pin inputs the A/D converter reference voltage.
It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF
and AVSS.
The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF
pin to AVSS level in standby mode.
The AVREF pin also functions to supply analog power to the A/D converter. When using the A/D converter,
be sure to supply power to the AVREF pin.
Caution When making the voltage applied to the AVREF pin the same level as that of AVSS, be sure
to clear bit 7 (CS) of the A/D converter mode register (ADM) to 0.
(8) AVSS pin
This is a GND potential pin of the A/D converter. Keep it at the same potential as the VSS0 pin when not using
the A/D converter.
227
CHAPTER 14
A/D CONVERTER
14.3 A/D Converter Control Registers
The following three types of registers are used to control the A/D converter.
• A/D converter mode register (ADM)
• A/D converter input select register (ADIS)
• External interrupt mode register 1 (INTM1)
(1) A/D converter mode register (ADM)
This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and
external trigger.
ADM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADM to 01H.
228
CHAPTER 14
A/D CONVERTER
Figure 14-2. A/D Converter Mode Register Format
Symbol
7
6
5
ADM
CS
TRG
FR1
4
3
2
1
0
FR0 ADM3 ADM2 ADM1 HSC
CS
After
Reset
01H
Address
FF80H
Operation stop
1
Operation start
TRG
External Trigger Selection
0
No external trigger (software starts)
1
Conversion started by external trigger (hardware starts)
A/D Conversion Time Selection
FR0
HSC
0
80/f X (Setting prohibited
1
MCS = 0
Note 2
0
1
1
40/f X (Setting prohibited
1
0
0
50/f X (Setting prohibited Note 2) 100/f X (20.0 µ s)
1
0
1
100/f X (20.0 µ s)
Other than above
MCS = 1
) 80/f X (Setting prohibited
MCS = 0
80/f X (19.1 µs)
) 160/f X (32.0 µ s)
Note 2
Note 1
fX = 4.19-MHz Operation
fX = 5.0-MHz Operation
MCS = 1
0
R/W
A/D Conversion Operation Control
0
FR1
R/W
Note 2
200/f X (40.0 µ s)
) 40/f X (Setting prohibited
160/f X (38.1 µ s)
) 80/f X (19.1 µ s)
Note 2
50/f X (Setting prohibited Note 2) 100/f X (23.8 µs)
100/f X (23.8 µs)
200/f X (47.7 µ s)
Setting prohibited
ADM3 ADM2 ADM1
Analog Input Channel Selection
0
0
0
ANI0
0
0
1
ANI1
0
1
0
ANI2
0
1
1
ANI3
1
0
0
ANI4
1
0
1
ANI5
1
1
0
ANI6
1
1
1
ANI7
Notes 1. Set so that the A/D conversion time is 19.1 µs or more.
2. Setting prohibited because A/D conversion time is less than 19.1 µs.
Cautions 1. The following sequence is recommended for power consumption reduction of A/D
converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the
A/D conversion operation, and then execute the HALT or STOP instruction.
2. When restarting the stopped A/D conversion operation, start the A/D conversion
operation after clearing the interrupt request flag (ADIF) to 0.
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
229
CHAPTER 14
A/D CONVERTER
(2) A/D converter input select register (ADIS)
This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels
or ports. Pins other than those selected as analog input can be used as input/output ports.
ADIS is set with an 8-bit memory manipulation instruction.
RESET input clears ADIS to 00H.
Cautions 1. Set the analog input channel in the following order.
(1) Set the number of analog input channels with ADIS.
(2) Using A/D converter mode register (ADM), select one channel to undergo A/D
conversion from among the channels set for analog input with ADIS.
2. No internal pull-up resistor can be used to the channels set for analog input with ADIS,
irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register L.
Figure 14-3. A/D Converter Input Select Register Format
Symbol
7
6
5
4
ADIS
0
0
0
0
3
2
1
0
ADIS3 ADIS2 ADIS1 ADIS0
After
Reset
R/W
FF84H
00H
R/W
Number of Analog Input Channel Selection
ADIS3 ADIS2 ADIS1 ADIS0
0
0
0
0
No analog input channel (P10 to P17)
0
0
0
1
1 channel (ANI0, P11 to P17)
0
0
1
0
2 channel (ANI0, ANI1, P12 to P17)
0
0
1
1
3 channel (ANI0 to ANI2, P13 to P17)
0
1
0
0
4 channel (ANI0 to ANI3, P14 to P17)
0
1
0
1
5 channel (ANI0 to ANI4, P15 to P17)
0
1
1
0
6 channel (ANI0 to ANI5, P16, P17)
0
1
1
1
7 channel (ANI0 to ANI6, P17)
1
0
0
0
8 channel (ANI0 to ANI7)
Other than above
230
Address
Setting prohibited
CHAPTER 14
A/D CONVERTER
(3) External interrupt mode register 1 (INTM1)
This register sets the valid edge for INTP3 to INTP5.
INTM1 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM1 to 00H.
Figure 14-4. External Interrupt Mode Register 1 Format
Symbol
7
6
INTM1
0
0
5
4
3
2
1
0
ES61 ES60 ES51 ES50 ES41 ES40
ES61 ES60
Address
After
Reset
R/W
FFEDH
00H
R/W
INTP5 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES51 ES50
INTP4 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES41 ES40
INTP3 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
231
CHAPTER 14
A/D CONVERTER
14.4 A/D Converter Operations
14.4.1 Basic operations of A/D converter
(1) Set the number of analog input channels with A/D converter input select register (ADIS).
(2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter
mode register (ADM).
(3) The sample & hold circuit samples the voltage input to the selected analog input channel.
(4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit
holds the input analog voltage until termination of A/D conversion.
(5) Set bit 7 of the successive approximation register (SAR). The series resistor string voltage tap is set to (1/
2) AVREF by the tap selector.
(6) The voltage difference between the series resistor string voltage tap and analog input is compared with a
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set. If the input
is smaller than (1/2) AVREF, the MSB is reset.
(7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the
series resistor string voltage tap is selected according to the preset value of bit 7 as described below.
• Bit 7 = 1 : (3/4) AVREF
• Bit 7 = 0 : (1/4) AVREF
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as
follows.
• Analog input voltage ≥ Voltage tap : Bit 6 = 1
• Analog input voltage ≤ Voltage tap : Bit 6 = 0
(8) Comparison of this sort continues up to bit 0 of SAR.
(9) Upon completion of the comparison of 8 bits, any effective digital resultant value remains in SAR and the
resultant value is transferred to and latched in the A/D conversion result register (ADCR).
At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.
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A/D CONVERTER
Figure 14-5. A/D Converter Basic Operation
Conversion
Time
Sampling Time
A/D Converter
Operation
Sampling
SAR
Undefined
A/D Conversion
80H
C0H
or
40H
ADCR
Conversion
Result
Conversion
Result
INTAD
A/D conversion operations are performed continuously until the bit 7 (CS) of ADM is reset (to 0) by software.
If a write to the ADM register is performed during an A/D conversion operation, the conversion operation is
initialized, and if the CS bit is set (to 1), conversion starts again from the beginning.
After RESET input, the value of ADCR is undefined.
233
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A/D CONVERTER
14.4.2 Input voltage and conversion results
The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion
result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression.
ADCR = INT (
VIN
× 256 + 0.5)
AVREF
or
(ADCR – 0.5) ×
AVREF
≤ VIN < (ADCR + 0.5) × AVREF
256
256
INT( ) : Function which returns integer parts of value in parentheses.
VIN
: Analog input voltage
AVREF : AVREF pin voltage
ADCR : A/D conversion result register (ADCR) value
Figure 14-6 shows the relation between the analog input voltage and the A/D conversion result.
Figure 14-6. Relationships between Analog Input Voltage and A/D Conversion Result
255
254
A/D Conversion
Results
(ADCR)
253
3
2
1
0
1
1
3
2
5
3
512 256 512 256 512 256
507 254 509 255 511
512 256 512 256 512
Input Voltage/AV REF
234
1
CHAPTER 14
A/D CONVERTER
14.4.3 A/D converter operating mode
One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS)
and A/D converter mode register (ADM) and starts A/D conversion.
The following two ways are available to start A/D conversion.
• Hardware start: Conversion is started by trigger input (INTP3).
• Software start: Conversion is started by setting ADM.
The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal
(INTAD) is simultaneously generated.
(1) A/D conversion by hardware start
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 1, the A/D conversion standby
state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied
to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started
and terminated, another operation is not started until a new external trigger signal is input.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D
conversion operation and waits for a new external trigger signal to be input. When the external trigger input
signal is reinput, A/D conversion is carried out from the beginning.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops
immediately.
Figure 14-7. A/D Conversion by Hardware Start
INTP3
ADM Rewrite
CS = 1, TRG = 1
ADM Rewrite
CS = 1, TRG = 1
A /D Conversion
Standby
State
ADCR
ANIn
ANIn
ANIn
Standby
State
ANIn
ANIn
Standby
State
ANIn
ANIm
ANIm
ANIm
ANIm
ANIm
INTAD
Remarks 1. n = 0, 1, ... , 7
2. m = 0, 1, ... , 7
235
CHAPTER 14
A/D CONVERTER
(2) A/D conversion operation in software start
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the
A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to
ADM3) of ADM.
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started
and terminated, the next A/D conversion operation starts immediately.
The A/D conversion operation
continues repeatedly until new data is written to ADM.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D
conversion operation and starts A/D conversion on the newly written data.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops
immediately.
Figure 14-8. A/D Conversion by Software Start
Conversion Start
CS = 1, TRG = 0
A /D Conversion
ANIn
ADM Rewrite
CS = 1, TRG = 0
ANIn
ANIn
ANIm
ADM Rewrite
CS = 0, TRG = 0
ANIm
Conversion suspended
Conversion results are
not stored
ADCR
ANIn
INTAD
Remarks 1. n = 0, 1, ... , 7
2. m = 0, 1, ... , 7
236
ANIn
Stop
ANIm
CHAPTER 14
A/D CONVERTER
14.5 A/D Converter Cautions
(1) Current consumption in standby mode
The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in
HALT mode with the subsystem clock. As a current still flows in the AVREF pin at this time, this current must
be cut in order to minimize the overall system power dissipation. In Figure 14-9, the power dissipation can
be reduced by outputting a low-level signal to the output port in standby mode. However, there is no precision
to the actual AVREF voltage, and therefore the conversion values themselves lack precision and can only be
used for relative comparison.
Figure 14-9. Example of Method of Reducing Current Consumption in Standby Mode
VDD0
Output Port
VSS0 µ PD780308, 780308Y
AVREF
AVREF .=. V DD0
Series Resistor String
AVSS
VSS0
(2) Input range of ANI0 to ANI7
The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above
AVREF or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that
channel will be indeterminate. The conversion values of the other channels may also be affected.
237
CHAPTER 14
A/D CONVERTER
(3) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF and ANI0 to ANI7. Since
the effect increases in proportion to the output impedance of the analog input source, it is recommended that
a capacitor be connected externally as shown in Figure 14-10 in order to reduce noise.
Figure 14-10. Analog Input Pin Disposition
If there is possibility that noise whose
level is AV REF or higher or AV SS or lower may enter,
clamp with a diode with a small VF (0.3 V or less).
Reference
Voltage Input
AV REF
ANI0 to ANI7
C = 100 to 1000 pF
AV SS
(4) Pins ANI0/P10 to ANI7/P17
The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins. When A/D conversion
is performed with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while
conversion is in progress, as this may reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected
A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins
adjacent to the pin undergoing A/D conversion.
(5) AVREF pin input impedance
A series resistor string of approximately 10 kΩ is connected between the AVREF pin and the AVSS pin.
Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection
to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage
error.
238
CHAPTER 14
A/D CONVERTER
(6) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed.
Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the
A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set
just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite
the fact that the A/D conversion for the post-change analog input has not ended.
When the A/D conversion is stopped and then resumed, clear the ADIF before it is resumed.
Figure 14-11. A/D Conversion End Interrupt Generation Timing
ADM Rewrite
(Start of ANIn Conversion)
A /D Conversion
ADCR
ANIn
ADM Rewrite
(Start of ANIm Conversion)
ANIn
ANIn
ANIm
ANIn
ADIF is set but ANIm
conversion has not ended
ANIm
ANIm
ANIm
INTAD
239
[MEMO]
240
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
The µPD780308 Subseries incorporates three channels of serial interfaces. Differences between channels 0,
2, and 3 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 2 for details of serial interface
channel 2, and CHAPTER 18 SERIAL INTERFACE CHANNEL 3 for details of serial interface channel 3,
respectively).
Table 15-1. Differences between Channels 0, 2, and 3
Serial Transfer Mode
3-wire serial I/O
Channel 0
Channel 2
Channel 3
Clock selection
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock, TO2 output
External clock, baud
rate generator output
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock
Transfer method
MSB/LSB switchable as
the start bit
MSB/LSB switchable as
the start bit
MSB/LSB switchable as
the start bit
Transfer end flag
Serial transfer end
interrupt request flag
(CSIIF0)
Serial transfer end
interrupt request flag
(SRIF)
Serial transfer end
interrupt request flag
(CSIIF3)
Use possible
None
None
None
Use possible
None
SBI (serial bus interface)
2-wire serial I/O
UART
(Asynchronous serial interface)
241
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.1 Serial Interface Channel 0 Functions
Serial interface channel 0 employs the following four modes.
• Operation stop mode
• 3-wire serial I/O mode
• SBI (serial bus interface) mode
• 2-wire serial I/O mode
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface
channel 0 is enabled. To change the operating mode, stop the serial operation once.
(1) Operation stop mode
This mode is used when serial transfer is not carried out. Power consumption can be reduced.
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)
This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0)
and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data
transfer processing time.
The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected
regardless of their start bit recognition.
This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.
(3) SBI (serial bus interface) mode (MSB-first)
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and
serial data bus (SB0 or SB1).
The SBI mode conforms to the NEC serial bus format, and transfers or receives three types of data:
“addresses”, “commands”, and “data”.
• Address:
Data to select the target device for serial communication
• Command: Data to give an instruction to the target device
• Data:
Data actually transferred
Actually, the master device outputs an “address” to the serial bus to select one of the slave devices with which
the master device is to communicate. After that, “commands” and “data” are transferred or received between
the master and slave devices. The receiver can automatically identify the received data as an “address”,
“command”, or “data” by hardware.
This function enables the input/output ports to be used effectively and the application program serial interface
control portions to be simplified.
In this mode, the wake-up function for handshake and the output function of acknowledge and busy signals
can also be used.
242
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(4) 2-wire serial I/O mode (MSB-first)
This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or
SB1).
This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level
and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or
more devices can be removed, resulting in the increased number of available input/output ports.
Figure 15-1. Serial Bus Interface (SBI) System Configuration Example
VDD0
Master CPU
Slave CPU1
SCK0
SB0
SCK0
SB0
Slave CPU2
SCK0
SB0
Slave CPUn
SCK0
SB0
243
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.2 Serial Interface Channel 0 Configuration
Serial interface channel 0 consists of the following hardware.
Table 15-2. Serial Interface Channel 0 Configuration
Item
Configuration
Register
Serial I/O shift register 0 (SIO0)
Slave address register (SVA)
Control register
Timer clock select register 3 (TCL3)
Serial operating mode register 0 (CSIM0)
Serial bus interface control register (SBIC)
Interrupt timing specify register (SINT)
Port mode register 2 (PM2) Note
Note
Refer to Figure 6-5 P25, P26 Block Diagram (µPD780308 Subseries)
and Figure 6-6 P27 Block Diagram (µPD780308 Subseries).
244
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Figure 15-2. Serial Interface Channel 0 Block Diagram
Internal Bus
Serial Operating
Mode Register 0
CSIE0 COI WUP
Serial Bus Interface
Control Register
Slave Address
Register (SVA)
CSIM CSIM CSIM CSIM CSIM
04
03
02
01
00
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
SVAM
Match
Control
Circuit
SI0/SB0/
P25
PM25
P25
Output
Latch
Output
Control
Busy/
Acknowledge
Output Circuit
Selector
SO0/SB1/
P26
Bus Release/
Command/
Acknowledge
Detector
PM26
Output
Control
SCK0/
P27
CLR SET
D
Q
Serial I/O Shift
Register 0 (SIO0)
Selector
P26 Output
Latch
CLD
ACKD
CMDD
RELD
WUP
Interrupt
Request
Signal
Generator
Serial Clock
Counter
INTCSI0
PM27
Output
Control
Serial Clock
Control Circuit
TO2
Selector
Selector
CSIM00
CSIM01
CSIM00
CSIM01
f xx/2 to f xx/28
4
P27
Output Latch
CLD
Interrupt Timing
Specify Register
SIC
SVAM
TCL33 TCL32 TCL31 TCL30
Timer Clock
Select
Register 3
Internal Bus
Remarks 1. Output Control performs selection between CMOS output and N-ch open drain output.
2. fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
245
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception
(shift operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
Note that, if a bus is driven in the SBI mode or 2-wire serial I/O mode, the bus pin must serve for both input
and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address
reception is carried out by setting bit 5 (WUP) of CSIM0 to 1).
In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial
bus interface control register (SBIC) is not cleared to 0.
RESET input makes SIO0 undefined.
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O
mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave
device. These two data (the slave address output from the master device and the SVA value) are compared
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of
serial operating mode register 0 (CSIM0) becomes 1.
By setting bit 4 (SVAM) of the interrupt timing specification register (SINT) to 1, the address can be compared
by the data of the LSB-masked high-order 7 bits.
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0.
In the SBI mode, the wake-up function can be used by setting bit 5 (WUP) of CSIM0 to 1.
In this case, an interrupt request signal (INTCSI0) is generated only when the slave address output by the
master coincides with the value of SVA. This interrupt request indicates that the master has requested for
communication. If bit 5 (SIC) of the interrupt timing specify register (SINT) is set to 1, the wake-up function
cannot be used even if WUP is set to 1 (the interrupt request signal is generated when bus release is detected).
When using the wake-up function, clear SIC to 0.
When the device is used as the master or slave in the SBI or 2-wire serial I/O mode, detect an error by using
SVA.
RESET input makes SVA undefined.
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CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(3) SO0 latch
This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the
SBI mode, this latch is set upon termination of the 8th serial clock.
(4) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception and to check whether
8-bit data has been transmitted/received.
(5) Serial clock control circuit
This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock
is used, the circuit also controls clock output to the SCK0/P27 pin.
(6) Interrupt request signal generator
This circuit controls interrupt request signal generation. It generates the interrupt request signal in the following
cases.
• In the 3-wire serial I/O mode and 2-wire serial I/O mode
This circuit generates an interrupt request signal every eight serial clocks.
• In the SBI mode
When WUP Note is 0 .... Generates an interrupt request signal every eight serial clocks.
When WUP Note is 1 .... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0)
value matches the slave address register (SVA) value after address reception.
Note
WUP is wake-up function specify bit. It is bit 5 of serial operating mode register 0 (CSIM0). Clear
bit 5 (SIC) of the interrupt timing specification register to 0 when using the wake-up function (WUP
= 1).
(7) Busy/acknowledge output circuit and bus release/command/acknowledge detector
These two circuits output and detect various control signals in the SBI mode.
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
247
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.3 Serial Interface Channel 0 Control Registers
The following four types of registers are used to control serial interface channel 0.
• Timer clock select register 3 (TCL3)
• Serial operating mode register 0 (CSIM0)
• Serial bus interface control register (SBIC)
• Interrupt timing specify register (SINT)
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 0.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Figure 15-3. Timer Clock Select Register 3 Format
Symbol
7
6
5
4
TCL3
1
0
0
0
3
2
1
0
TCL33 TCL32 TCL31 TCL30
Address
After Reset
FF43H
88H
R/W
R/W
Serial Interface Channel 0 Serial Clock Selection
TCL33 TCL32 TCL31 TCL30
MCS = 1
MCS = 0
0
1
1
0
Setting prohibited
fX/22
0
1
1
1
fX/22 (1.25 MHz)
fX/23 (625 kHz)
1
0
0
0
fX/23 (625 kHz)
fX/24 (313 kHz)
1
0
0
1
fX/24 (313 kHz)
fX/25 (156 kHz)
1
0
1
0
fX/25 (156 kHz)
fX/26 (78.1 kHz)
1
0
1
1
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
1
1
0
0
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
1
1
0
1
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
Other than above
(1.25 MHz)
Setting prohibited
Cautions 1. Set bit 4 to bit 6 to 0, and bit 7 to 1.
2. When rewriting other data to TCL3, stop the serial transfer operation beforehand.
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Figures in parentheses apply to operation with fX = 5.0 MHz.
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CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(2) Serial operating mode register 0 (CSIM0)
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up
function and displays the address comparator match signal.
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial
interface channel 0 is enabled. To change the operating mode, once stop the serial operation.
Figure 15-4. Serial Operating Mode Register 0 Format (1/2)
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
Address
After Reset
FF60H
R/W
00H
R/W Note 1
Serial Interface Channel 0 Operation Control
CSIE0
0
Operation stopped
1
Operation enable
Slave Address Comparison Result Flag Note 2
COI
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
Wake-up Function Control Note 3
WUP
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register data in SBI mode
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0 when using the wakeup function (WUP = 1).
249
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
CHAPTER 15
Figure 15-4. Serial Operating Mode Register 0 Format (2/2)
R/W
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
04
03
×
0
Operation
Mode
02
Note 1 Note 1
0
1
1
×
0
0
0
1
3-wire serial
l/O mode
Start Bit
MSB
LSB
SIO/SB0/P25
SO0/SB1/P26
SCK0/P27
Pin Function
Pin Function
Pin Function
SO0
(CMOS output)
SCK0 (CMOS
input/output)
SI0 Note 1
(Input)
Note 2 Note 2
×
0
1
×
0
0
0
P25 (CMOS
input/output)
1
SBI mode
0
0
0
SCK0 (CMOS
input/output)
MSB
Note 2 Note 2
1
×
×
0
1
SB0 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
0
0
0
1
P25 (CMOS
input/output)
SB1 (N-ch
open-drain
input/output)
Note 2 Note 2
×
0
1
×
2-wire serial
l/O mode
1
Note 2 Note 2
1
R/W
0
0
SB1 (N-ch
open-drain
input/output)
×
×
0
MSB
SB0 (N-ch
open-drain
input/output)
1
SCK0 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input Clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Can be used as P25 (CMOS input/output) when used only for transmission.
2. Can be used freely as port function.
Remark
×:
don’t care
PM××: Port mode register
P××:
250
Port output latch
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(3) Serial bus interface control register (SBIC)
This register sets serial bus interface operation and displays statuses.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Figure 15-5. Serial Bus Interface Control Register Format (1/2)
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
FF61H
00H
R/W
R/W
Note 1
Synchronizing Busy Signal Output Control
0
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
execution of the instruction to be cleared to 0.
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
ACKD
Acknowledge Detection
Set Conditions (ACKD = 1)
Clear Conditions (ACKD = 0)
• Falling edge of the SCK0 immediately after the busy
mode is released while executing the transfer
start instruction
• When CSIE0 = 0
• When RESET input is applied
R/W
After Reset
Note 2
BSYE
R
Address
ACKE
0
1
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
Acknowledge Signal Output Control
Acknowledge signal automatic output disable (output with ACKT enable)
Before completion of
transfer
Acknowledge signal is output in synchronization with the 9th clock
falling edge of SCK0 (automatically output when ACKE = 1).
After completion of
transfer
Acknowledge signal is output in synchronization with the falling edge of
SCK0 just after execution of the instruction to be set to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cancelled by start of serial interface transfer. However, the BSYE flag
is not cleared to 0.
Remark
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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Figure 15-5. Serial Bus Interface Control Register Format (2/2)
R/W
ACKT
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution
of the instruction to be set to 1, and after acknowledge signal output, is automatically cleared to 0.
Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
R CMDD
Command Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
Set Conditions (CMDD = 1)
• When command signal (CMD) is detected
• When RESET input is applied
R
RELD
Bus Release Detection
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in
address reception
• When CSIE0 = 0
Set Conditions (RELD =1)
• When bus release signal (REL) is detected
• When RESET input is applied
R/W
CMDT
Used for command signal output.
When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
Used for bus release signal output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
Remarks 1.
Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are 0 when they are read after data has been
set.
2.
252
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(4) Interrupt timing specify register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Figure 15-6. Interrupt Timing Specify Register Format
Symbol
7
6
SINT
0
CLD
R
R/W
R/W
5
4
SIC SVAM
3
2
1
0
Address
0
0
0
0
FF63H
After Reset
00H
R/W
R/W Note 1
SCK0 Pin Level Note 2
CLD
0
Low level
1
High level
SIC
INTCSI0 Interrupt Cause Selection Note 3
0
CSIIF0 is set upon termination of serial interface
channel 0 transfer
1
CSIIF0 is set upon bus release detection or
termination of serial interface channel 0 transfer
SVA Bit to be Used as Slave Address
SVAM
0
Bits 0 to 7
1
Bits 1 to 7
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using the wake-up function in the SBI mode, set SIC to 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark
SVA:
Slave address register
CSIIF0:
Interrupt request flag corresponding to INTCSI0
CSIE0:
Bit 7 of serial operating mode register 0 (CSIM0)
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.4 Serial Interface Channel 0 Operations
The following four operating modes are available to the serial interface channel 0.
• Operation stop mode
• 3-wire serial I/O mode
• SBI mode
• 2-wire serial I/O mode
15.4.1 Operation stop mode
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial
I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as an ordinary 8-bit register.
In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1 and P27/SCK0 pins can be used as ordinary input/
output ports.
(1) Register setting
The operation stop mode is set with the serial operating mode register 0 (CSIM0).
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
CSIM0 CSIE0 COI
R/W
254
5
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
FF60H
After Reset
00H
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
R/W
R/W
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.4.2 3-wire serial I/O mode operation
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
(1) Register setting
The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface
control register (SBIC).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R/W
R/W
4
WUP
3
2
1
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
FF60H
After Reset
00H
R/W
R/W Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
Wake-up Function Control Note 2
WUP
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register data in SBI mode
CSIM CSIM CSIM
Operation
Mode
PM25 P25 PM26 P26 PM27 P27
04
0
R/W
0
03
×
02
0
Note 3 Note 3
1
1
×
0
0
0
1
3-wire serial
l/O mode
Start Bit
MSB
LSB
SIO/SB0/P25
Pin Function
Note 3
SI0
(Input)
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
SO0
(CMOS output)
SCK0 (CMOS
input/output)
1
0
SBI mode (See Section 15.4.3 SBI mode operation)
1
1
2-wire serial I/O mode (See Section 15.4.4 2-wire serial I/O mode operation)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input Clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
3. Can be used as P25 (CMOS input/output) when used only for transmission.
Remark
×:
don’t care
PM××: Port mode register
P××:
Port output latch
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CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
R/W
Address
FF61H
00H
R/W
R/W
CMDT
When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
256
After Reset
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/
reception is carried out in synchronization with the serial clock.
Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the
SI0 pin is latched in SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 15-7. 3-Wire Serial I/O Mode Timings
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0
End of Transfer
Transfer Start at the Falling Edge of SCK0
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status
can be manipulated by setting the bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 15.4.5 SCK0/P27 pin output manipulation).
(3) Other signals
Figure 15-8 shows RELT and CMDT operations.
Figure 15-8. RELT and CMDT Operations
SO0 latch
RELT
CMDT
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(4) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 15-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the
figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register
0 (CSIM0).
Figure 15-9. Circuit of Switching in Transfer Bit Order
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO0 Latch
SI0
Shift Register 0 (SIO0)
D
Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(5) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1.
• Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer.
Caution If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
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15.4.3 SBI mode operation
SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format.
SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration
function. This function enables devices to communicate using only two lines. Thus, when making up a serial bus
with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on
the board can be decreased.
The master device outputs three kinds of data to slave devices on the serial data bus: “addresses” to select a device
to be communicated with, “commands” to instruct the selected device, and “data” which is actually required.
The slave device can identify the received data into “address”, “command”, or “data”, by hardware. An application
program that controls serial interface channel 0 can be simplified by using this function.
The SBI function is incorporated into various devices including 75X/XL Series and 78K Series.
Figure 15-10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI
and peripheral ICs are used.
In SBI, the SB0 (SB1) serial data bus is an open-drain output pin and therefore the serial data bus line behaves
in the same way as the wired-OR configuration. In addition, a pull-up resistor must be connected to the serial data
bus line.
When the SBI mode is used, refer to (10) SBI mode precautions (d) described later.
Figure 15-10. Example of Serial Bus Configuration with SBI
VDD0
Serial Clock
SCK0
SCK0
Slave CPU
SB0 (SB1)
Address 1
SCK0
Slave CPU
SB0 (SB1)
Address 2
Master CPU
Serial Data Bus
SB0 (SB1)
•
•
•
•
•
•
SCK0
Slave IC
SB0 (SB1)
Address N
Caution When exchanging the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock
line (SCK0) as well because serial clock line (SKC0) input/output switching is carried out
asynchronously between the master and slave CPUs.
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(1) SBI functions
In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many
ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the
busy state, because only the data transfer function is available. If these operations are to be controlled by
software, the software must be heavily loaded.
In SBI, a serial bus can be configured with two signal lines of serial clock SCK0 and serial data bus SB0 (SB1).
Thus, use of SBI leads to reduction in the number of microcontroller ports and that of wirings and routings
on the board.
The SBI functions are described below.
(a) Address/command/data identify function
Serial data is distinguished into addresses, commands, and data.
(b) Chip select function by address transmission
The master executes slave chip selection by address transmission.
(c) Wake-up function
The slave can easily judge address reception (chip select judgment) with the wake-up function (which
can be set/reset by software).
When the wake-up function is set, the interrupt request signal (INTCSI0) is generated upon reception of
a match address.
Thus, when communication is executed with two or more devices, the CPU except the selected slave
devices can operate regardless of under way serial communications.
(d) Acknowledge signal (ACK) control function
The acknowledge signal to check serial data reception is controlled.
(e) Busy signal (BUSY) control function
The busy signal to report the slave busy state is controlled.
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(2) SBI definition
The SBI serial data format and the signals to be used are defined as follows.
Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”.
Figure 15-11 shows the address, command, and data transfer timings.
Figure 15-11. SBI Transfer Timings
Address Transfer
8
SCK0
A7
SB0 (SB1)
Command Transfer
Bus Release
Signal
9
A0
ACK
BUSY
Address
Command Signal
9
SCK0
SB0 (SB1)
C7
C0 ACK
BUSY
READY
BUSY
READY
Command
Data Transfer
SCK0
SB0 (SB1)
8
D7
9
D0 ACK
Data
Remark
The dotted line indicates the READY status.
The bus release signal and the command signal are output by the master device. BUSY is output by the slave
signal. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs).
Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(a) Bus release signal (REL)
The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the
high level when the SCK0 line is at the high level (without serial clock output).
This signal is output by the master device.
Figure 15-12. Bus Release Signal
SCK0
H
SB0 (SB1)
The bus release signal indicates that the master device is going to transmit an address to the slave device.
The slave device incorporates hardware to detect the bus release signal.
(b) Command signal (CMD)
The command signal is a signal with the SB0 (SB1) line which has changed from the high level to the
low level when the SCK0 line is at the high level (without serial clock output). This signal is output by
the master device.
Figure 15-13. Command Signal
SCK0
H
SB0 (SB1)
The command signal indicates that the master is to transmit a command to the slave (however, the
command signal following the bus release signal indicates that an address is transmitted).
The slave device incorporates hardware to detect the command signal.
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(c) Address
An address is 8-bit data which the master device outputs to the slave device connected to the bus line
in order to select a particular slave device.
Figure 15-14. Addresses
1
SCK0
A7
SB0 (SB1)
2
A6
3
A5
4
A4
5
A3
6
7
A2
A1
8
A0
Address
Bus Release
Signal
Command Signal
8-bit data following bus release and command signals is defined as an “address”. In the slave device,
this condition is detected by hardware and whether or not 8-bit data matches the own specification number
(slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device
has been selected. After that, communication with the master device continues until a release instruction
is received from the master device.
Figure 15-15. Slave Selection with Address
Master
Slave 2
Address Transmission
Slave 1
Not Selected
Slave 2
Selected
Slave 3
Not Selected
Slave 4
Not Selected
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(d) Command and data
The master device transmits commands to, and transmits/receives data to/from the slave device selected
by address transmission.
Figure 15-16. Commands
1
SCK0
SB0 (SB1)
C7
2
C6
3
C5
4
5
C4
C3
6
C2
7
C1
8
C0
Command
Command Signal
Figure 15-17. Data
SCK0
SB0 (SB1)
1
D7
2
D6
3
D5
4
5
D4
D3
6
D2
7
D1
8
D0
Data
8-bit data following a command signal is defined as “command” data. 8-bit data without command signal
is defined as “data”. Command and data operation procedures are allowed to determine by user according
to communications specifications.
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(e) Acknowledge signal (ACK)
The acknowledge signal is used to check serial data reception between transmitter and receiver.
Figure 15-18. Acknowledge Signal
[When output in synchronization with 11th clock SCK0]
SCK0
8
9
10
SB0 (SB1)
11
ACK
[When output in synchronization with 9th clock SCK0]
SCK0
SB0 (SB1)
Remark
8
9
ACK
The dotted line indicates the READY status.
The acknowledge signal is one-shot pulse to be generated at the falling edge of SCK0 after 8-bit data
transfer. It can be positioned anywhere and can be synchronized with any clock SCK0.
After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge
signal. If the acknowledge signal is not returned for the preset period of time after data transmission,
it can be judged that data reception has not been carried out correctly.
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(f) Busy signal (BUSY) and ready signal (READY)
The BUSY signal is intended to report to the master device that the slave device is preparing for data
transmission/reception.
The READY signal is intended to report to the master device that the slave device is ready for data
transmission/reception.
Figure 15-19. BUSY and READY Signals
SCK0
SB0 (SB1)
Remark
8
9
ACK
BUSY
READY
The dotted line indicates the READY status.
In SBI, the slave device notifies the master device of the busy state by setting SB0 (SB1) line to the low
level.
The BUSY signal output follows the acknowledge signal output from the master or slave device. It is set/
reset at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically
terminates the output of SCK0 serial clock.
When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer.
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(3) Register setting
The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register
(SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
R/W
4
WUP
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
R/W
R/W Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
COI
Slave Address Comparison Result Flag Note 2
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
Wake-up Function Control
WUP
Note 3
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register data in SBI mode
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
Operation
Mode
Start Bit
SI0/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
04
03
02
0
×
3-wire serial I/O mode (See Section 15.4.2 3-wire serial I/O mode operation)
Note 4 Note 4
0
1
×
×
0
0
0
P25 (CMOS
input/output)
1
SBI mode
0
SB1 (N-ch
open-drain
input/output)
MSB
Note 4 Note 4
1
1
R/W
1
0
0
×
×
0
SB0 (N-ch
open-drain
input/output)
1
SCK0/P27
Pin Function
SCK0 (CMOS
input/output)
P26 (CMOS
input/output)
2-wire serial I/O mode (See Section 15.4.4 2-wire serial I/O mode operation)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input Clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. COI is 0 when CSIE0 = 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up
function (WUP = 1).
4. These pins can be used freely as port pins.
Remark
×:
don’t care
PM××: Port mode register
P××:
Port output latch
267
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
FF61H
00H
R/W
R/W
Note 1
Synchronizing Busy Signal Output Control
0
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
execution of the instruction to be cleared (to 0).
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
ACKD
Acknowledge Detection
Set Conditions (ACKD = 1)
Clear Conditions (ACKD = 0)
• SCK0 fall immediately after the busy mode is
released during the transfer start instruction execution.
• When CSIE0 = 0
• When RESET input is applied
R/W
After Reset
Note2
BSYE
R
Address
ACKE
0
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
Acknowledge Signal Output Control
Acknowledge signal automatic output disable (output with ACKT enable)
Before completion of
transfer
Acknowledge signal is output in synchronization with the 9th clock falling edge of
SCK0 (automatically output when ACKE = 1).
After completion of
transfer
Acknowledge signal is output in synchronization with falling edge clock
of SCK0 just after execution of the instruction to be set to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
1
(continued)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cleared by start of serial interface transfer. However, the BSYE flag
is not cleared to 0.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
268
CHAPTER 15
R/W
ACKT
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution
of the instruction to be set (to 1) and, after acknowledge signal output, is automatically cleared (to 0).
Used as ACKE = 0. Also cleared (to 0) upon start of serial interface transfer or when CSIE0 = 0.
R CMDD
Command Detection
Set Conditions (CMDD = 1)
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When command signal (CMD) is detected
• When RESET input is applied
R
RELD
Bus Release Detection
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
R/W
Set Conditions (RELD = 1)
• When bus release signal (REL) is detected
CMDT
Used for command signal output.
When CMDT = 1, SO Iatch is cleared (to 0). After SO latch clearance, automatically cleared (to 0).
Also cleared to 0 when CSIE0 = 0.
RELT
Used for bus release signal output.
When RELT = 1, SO Iatch is set (to 1). After SO latch setting, automatically cleared (to 0).
Also cleared to 0 when CSIE0 = 0.
R/W
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
269
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Symbol
7
6
SINT
0
CLD
R
R/W
R/W
5
4
SIC SVAM
3
2
1
0
Address
0
0
0
0
FF63H
After Reset
00H
R/W Note 1
SCK0 Pin Level Note 2
CLD
0
Low level
1
High level
SIC
INTCSI0 Interrupt Cause Selection Note 3
0
CSIIF0 is set upon termination of serial interface channel 0 transfer
1
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
SVA Bit to be Used as Slave Address
SVAM
0
Bits 0 to 7
1
Bits 1 to 7
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using wake-up function in the SBI mode, set SIC to 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark
SVA:
Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
270
R/W
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(4) Various signals
Figures 15-20 to 15-25 show various signals and serial bus interface control register (SBIC) flag operations
in SBI. Table 15-3 lists various signals in SBI.
Figure 15-20. RELT, CMDT, RELD, and CMDD Operations (Master)
Slave address write to SIO0
(Transfer start instruction)
SIO0
SCK0
SB0 (SB1)
RELT
CMDT
RELD
CMDD
Figure 15-21. RELD and CMDD Operations (Slave)
Write FFH to SIO0
(Transfer start instruction)
SIO0
SCK0
Transfer start instruction
A7
A6
1
2
A7
A6
A1
7
A0
8
9
READY
SB0 (SB1)
A1
Slave Address
A0
ACK
When addresses match
RELD
When addresses do not match
CMDD
271
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Figure 15-22. ACKT Operation
SCK0
SB0 (SB1)
6
7
D2
8
D1
9
D0
ACK
ACKT
When set during
this period
Caution Do not set ACKT before termination of transfer.
272
ACK signal is output for
a period of one clock
just after setting
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Figure 15-23. ACKE Operations
(a) When ACKE = 1 upon completion of transfer
2
1
SCK0
D7
SB0 (SB1)
7
D6
D2
8
D1
9
D0
ACK
ACK signal is output
at 9th clock
ACKE
When ACKE = 1 at this point
(b) When set after completion of transfer
SCK0
SB0 (SB1)
7
6
D2
8
D1
9
D0
ACK
ACK signal is output for
a period of one clock
just after setting
ACKE
If set during this period and ACKE = 1
at the falling edge of the next SCK0
(c) When ACKE = 0 upon completion of transfer
1
SCK0
2
D7
SB0 (SB1)
7
D6
D2
8
D1
9
ACK signal is not output
D0
ACKE
When ACKE = 0 at this point
(d) When “ACKE = 1” period is short
SCK0
SB0 (SB1)
D2
D1
D0
ACK signal is not output
ACKE
If set and cleared during this period
and ACKE = 0 at the falling edge of SCK0
273
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Figure 15-24. ACKD Operations
(a) When ACK signal is output at 9th clock of SCK0
Transfer Start
Instruction
SIO0
Transfer Start
SCK0
6
7
D2
SB0 (SB1)
8
D1
9
D0
ACK
ACKD
(b) When ACK signal is output after 9th clock of SCK0
Transfer Start
Instruction
SIO0
Transfer Start
SCK0
6
7
D2
SB0 (SB1)
8
9
ACK
D0
D1
ACKD
(c) Clear timing when transfer start is instructed in BUSY
Transfer Start
Instruction
SIO0
SCK0
6
7
D2
SB0 (SB1)
8
D1
9
D0
ACK
BUSY
D7
D6
ACKD
Figure 15-25. BSYE Operation
SCK0
SB0 (SB1)
7
6
D2
8
D1
9
D0
ACK
BUSY
BSYE
When BSYE = 1 at this point
274
If reset during this period and
BSYE = 0 at the falling edge of SCK0
Table 15-3. Various Signals in SBI Mode (1/2)
Signal Name
Acknowledge
signal
(ACK)
Busy signal
(BUSY)
Ready signal
(READY)
SB0 (SB1) rising edge
when SCK0 = 1
Output
Condition
Timing Chart
SCK0
CMD signal is output
to indicate that
transmit data is an
address.
• CMDT set
• CMDD set
i) Transmit data is an
address after REL
signal output.
ii) REL signal is not
output and transmit
data is an command.
1 ACKE = 1
2 ACKT set
• ACKD set
Completion of
reception
• RELT set
Master
Master/
slave
Slave
Slave
Low-level signal to be
output to SB0 (SB1) during
one-clock period of SCK0
after completion of serial
reception
SCK0
Meaning of Signal
• RELD set
• CMDD clear
"H"
SB0 (SB1)
SB0 (SB1) falling edge
when SCK0 = 1
Effects on Flag
"H"
SB0 (SB1)
[Synchronous BUSY output]
[Synchronous BUSY signal]
Low-level signal to be
output to SB0 (SB1)
SCK0
following Acknowledge
signal
SB0 (SB1)
High-level signal to be
SB0 (SB1)
output to SB0 (SB1) before
serial transfer start and
after completion of serial
transfer
9
ACK
• BSYE = 1
Serial receive disable
because of processing
—
Serial receive enable
BUSY
D0
READY
ACK
D0
—
BUSY
READY
1 BSYE = 0
2 Execution of
instruction for
data write to
SIO0
(transfer start
instruction)
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Command
signal
(CMD)
Master
Definition
CHAPTER 15
Bus release
signal
(REL)
Output
Device
275
276
Table 15-3. Various Signals in SBI Mode (2/2)
Signal Name
Master
Synchronous clock to
output address/command/
data, ACK signal, synchroSCK0
nous BUSY signal, etc.
Address/command/data are
SB0 (SB1)
transferred with the first
eight synchronous clocks.
Master
8-bit data to be transferred
SCK0
in synchronization with
SCK0 after output of REL
SB0 (SB1)
and CMD signals
1
REL
Commands
(C7 to C0)
Data
(D7 to D0)
Master
Master/
slave
8-bit data to be transferred
SCK0
in synchronization with
SCK0 after output of only
CMD signal without REL
SB0 (SB1)
signal output
Output
Condition
Timing Chart
2
7
8
9
10
1
2
7
8
1
2
7
8
1
2
7
8
CMD
Effects on Flag
Meaning of Signal
Timing of signal
output to serial data
bus
Address value of
When CSIE0 = 1,
slave device on the
execution of
instruction for
CSIIF0 set (rising serial bus
data write to
edge of 9th clock
SIO0 (serial
of SCK0) Note 1
transfer start
instruction) Note 2
Instructions and
messages to the
slave device
CMD
8-bit data to be transferred
SCK0
in synchronization with
SCK0 without output of
REL and CMD signals
SB0 (SB1)
Numeric values to be
processed with slave
or master device
Notes 1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0.
When WUP = 1, an address is received. Only when the address matches the slave address register (SVA) value, CSIIF0 is set.
2. In BUSY state, transfer starts after the READY state is set.
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Address
(A7 to A0)
Definition
CHAPTER 15
Serial clock
(SCK0)
Output
Device
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(5) Pin configuration
The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations.
(a) SCK0 ............ Serial clock input/output pin
<1> Master ... CMOS and push-pull output
<2> Slave ...... Schmitt input
(b) SB0 (SB1) .... Serial data input/output dual-function pin
Both master and slave devices have an N-ch open drain output and a Schmitt input.
Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary.
Figure 15-26. Pin Configuration
Slave Device
Master Device
(Clock Output)
SCK0
SCK0
Clock Output
Clock Input
Serial Clock
(Clock Input)
VDD0
N-ch Open Drain
SB0 (SB1)
RL
SB0 (SB1)
N-ch Open Drain
Serial Data Bus
SO0
VSS0
SI0
SO0
VSS0
SI0
Caution Because the N-ch open-drain output pin must go into a high-impedance state at time of data
reception, write FFH to serial I/O shift register 0 (SIO0) in advance. The N-ch open-drain can
go into a high-impedance state at any time of transfer. However, when the wake-up function
specify bit (WUP) = 1, the N-ch transistor always goes into a high-impedance state. Thus,
it is not necessary to write FFH to SIO0 before reception.
277
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(6) Address match detection method
In the SBI mode, the master transmits a slave address to select a specific slave device.
Address coincidence is automatically detected by hardware. If the slave address transmitted by the master
coincides with the address set to the slave address register (SVA) when the wake-up function specify bit (WUP)
= 1, CSIIF0 is set.
If bit 5 (SIC) of the interrupt timing specify register (SINT) is set to 1, the wake-up function cannot be used
even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected). To use the
wake-up function, therefore, clear SIC to 0.
Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after
bus release (RELD = 1).
For this match detection, match interrupt (INTCSI0) of the address to be generated with
WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave
address when WUP = 1.
2. When detecting selection/non-selection without the use of interrupt with WUP = 0, do so
by means of transmission/reception of the command preset by program instead of using
the address match detection method.
(7) Error detection
In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that
is, the serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged
to have occurred.
(8) Communication operation
In the SBI mode, the master device selects normally one slave device as communication target from among
two or more devices by outputting an “address” to the serial bus.
After the communication target device has been determined, commands and data are transmitted/received
and serial communication is realized between the master and slave devices.
Figures 15-27 to 15-30 show data communication timing charts.
Shift operation of the shift register is carried out at the falling edge of serial clock (SCK0). Transmit data is
latched into the SO0 latch and is output with MSB set as the first bit from the SB0/P25 or SB1/P26 pin. Receive
data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into the shift register.
278
Figure 15-27. Address Transmission from Master Device to Slave Device (WUP = 1)
Master Device Processing (Transmitter)
Program Processing
CMDT
Set
RELT
Set
CMDT
Set
Write
to SIO0
Interrupt Servicing
(Preparation for the Next Serial Transfer)
Serial Transmission
INTCSI0
ACKD
SCK0
Generation
Set
Stop
SCK0 Pin
1
SB0 (SB1) Pin
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
ACK
READY
BUSY
Address
Slave Device Processing (Receiver)
ACKT
Set
BUSY
INTCSI0
ACK BUSY
BUSY
Generation
Output Output
Clear
Program Processing
Hardware Operation
WUP←0
CMDD CMDD CMDD
Set
Clear
Set
RELD
Set
Serial Reception
(When SVA = SIO0)
Clear
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Transfer Line
CHAPTER 15
Hardware Operation
279
280
Figure 15-28. Command Transmission from Master Device to Slave Device
Master Device Processing (Transmitter)
Program Processing
CMDT
Set
Write
to SIO0
Interrupt Servicing
(Preparation for the Next Serial Transfer)
Serial Transmission
INTCSI0
ACKD
SCK0
Generation
Set
Stop
SCK0 Pin
1
SB0 (SB1) Pin
2
C7
3
C6
4
C5
5
C4
6
C3
7
C2
8
C1
9
C0
ACK
BUSY
Command
Slave Device Processing (Receiver)
SIO0
Read
Program Processing
Hardware Operation
CMDD
Set
Serial Reception
Command ACKT
analysis
Set
BUSY
Clear
INTCSI0
ACK BUSY
Generation
Output
Output
BUSY
Clear
READY
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Transfer Line
CHAPTER 15
Hardware Operation
Figure 15-29. Data Transmission from Master Device to Slave Device
Master Device Processing (Transmitter)
Program Processing
Write
to SIO0
Interrupt Servicing
(Preparation for the Next Serial Transfer)
Serial Transmission
INTCSI0
ACKD
SCK0
Generation
Set
Stop
SCK0 Pin
SB0 (SB1) Pin
1
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
9
D0
ACK
BUSY
Data
Slave Device Processing (Receiver)
SIO0
Read
Program Processing
Hardware Operation
Serial Reception
ACKT
Set
BUSY
Clear
INTCSI0
ACK BUSY
Generation
Output
Output
BUSY
Clear
READY
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Transfer Line
CHAPTER 15
Hardware Operation
281
282
Figure 15-30. Data Transmission from Slave Device to Master Device
Master Device Processing (Receiver)
SIO0
Read
FFH Write
to SIO0
Program Processing
Serial Reception
Stop
Set
INTCSI0
ACK
Generation
Output
to SIO0
Receive data processing
Serial
Reception
SCK0 Pin
SB0 (SB1) Pin
1
BUSY
READY
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
9
1
D0
ACK
BUSY
READY
Data
Slave Device processing (Transmitter)
Program Processing
Write
to SIO0
Hardware Operation
BUSY
Clear
Write
to SIO0
Serial Transmission
INTCSI0
ACKD
Generation
Set
BUSY
Output
BUSY
Clear
2
D7
D6
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
Transfer Line
CHAPTER 15
SCK0
Hardware Operation
ACKT FFH Write
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(9) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch transistor output pin must go into a high-impedance state for data
reception, write FFH to SIO0 in advance.
However, when the wake-up function specify bit (WUP) = 1, the N-ch transistor always
goes into a high-impedance state. Thus, it is not necessary to write FFH to SIO0 before
reception.
3. If data is written to SIO0 when the slave is busy, the data is not lost.
When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY)
state, transfer starts.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
For pins (SB0 or SB1) which are to be used for data input/output, be sure to carry out the following settings
before serial transfer of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
283
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(10) Identifying busy status of slave
When device is in the master mode, follow the procedure below to judge whether slave device is in the busy
state or not.
<1> Detect acknowledge signal (ACK) or interrupt request signal generation.
<2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode.
<3> Read out the pin state (when the pin level is high, the READY state is set).
After the detection of the READY state, set the port mode register to 0 and return to the output mode.
(11) SBI mode precautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is
normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) If WUP is set to 1 during BUSY signal output, BUSY is not cleared. In SBI, the BUSY signal continues
to be output after BUSY clear instruction generation to the falling edge of the next serial clock (SCK0).
Before setting WUP to 1, be sure to clear BUSY and then check that the SB0 (SB1) has become highlevel.
(d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial
transfer of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
284
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.4.4 2-wire serial I/O mode operation
The 2-wire serial I/O mode can cope with any communication format by program.
Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or
SB1).
Figure 15-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
AV DD0
AV DD0
Master
Slave
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
285
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
CHAPTER 15
(1) Register setting
The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface
control register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
R/W
4
WUP
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
0
Operation stopped
1
Operation enabled
COI
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
Wake-up Function Control Note 3
WUP
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register data in SBI mode
CSIM CSIM CSIM
Operation
Mode
02
Start Bit
SIO/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
04
03
0
×
3-wire Serial I/O mode (See Section 15.4.2 3-wire serial I/O mode operation)
1
0
SBI mode (See Section 15.4.3 SBI mode operation)
Note 4 Note 4
1
Note 1
Slave Address Comparison Result Flag Note 2
0
×
×
1
0
0
0
1
2-wire serial
l/O mode
Note 4 Note 4
1
0
0
×
×
0
1
P25 (CMOS
input/output
SB1 (N-ch
open-drain
input/output)
SB0 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
MSB
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input Clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.
4. Can be used freely as port function.
Remark
×:
don’t care
PM××: Port mode register
P××:
286
R/W
Serial Interface Channel 0 Operation Control
PM25 P25 PM26 P26 PM27 P27
R/W
R/W
Port output latch
SCK0/P27
Pin Function
SCK0 (N-ch
open-drain
input/output)
CHAPTER 15
SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
Address
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
R/W
After Reset
FF61H
00H
R/W
R/W
CMDT
When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Symbol
7
6
SINT
0
CLD
R
R/W
5
4
SIC SVAM
3
2
1
0
Address
0
0
0
0
FF63H
SCK0 Pin Level
CLD
0
Low level
1
High level
SIC
After Reset
00H
R/W
R/W
Note 1
Note 2
INTCSI0 Interrupt Factor Selection
0
CSIIF0 is set upon termination of serial interface
channel 0 transfer
1
CSIIF0 is set upon bus release detection or
termination of serial interface channel 0 transfer
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception
is carried out bit-wise in synchronization with the serial clock.
Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge
of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/
P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the shift register
at the rising edge of SCK0.
Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request
flag (CSIIF0) is set.
Figure 15-32. 2-Wire Serial I/O Mode Timings
SCK0
SB0 (SB1)
1
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
D0
CSIIF0
End of Transfer
Transfer start at the falling edge of SCK0
The SB0 (SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be
externally connected to a pull-up resistor. Because the N-ch transistor output pin must go into a highimpedance state for data reception, write FFH to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be
manipulated by setting the bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 15.4.5 SCK0/P27 pin output manipulation).
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
(3) Other signals
Figure 15-33 shows RELT and CMDT operations.
Figure 15-33. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch transistor output pin must go into a high-impedance state for data
reception, write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged
to have occurred.
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SERIAL INTERFACE CHANNEL 0 (µPD780308 Subseries)
15.4.5 SCK0/P27 pin output manipulation
Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to
normal serial clock output.
P27 output latch manipulation enables any value of SCK0 to be set by software (SI0/SB0 and SO0/SB1 pin to be
controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)).
SCK0/P27 pin output manipulating procedure is described below.
<1> Set the serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation
is enabled). While serial transfer is suspended, SCK0 is set to 1.
<2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction.
Figure 15-34. SCK0/P27 Pin Configuration
Set by bit
manipulation instruction
SCK0/P27
To Internal
Circuit
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
290
P27 Output
Latch
SCK0 (1 when transfer stops)
From Serial Clock
Control Circuit
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
The µPD780308Y Subseries incorporates three channels of serial interfaces. Differences between channels
0, 2, and 3 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 2 for details of serial interface
channel 2, and CHAPTER 18 SERIAL INTERFACE CHANNEL 3 for details of serial interface channel 3,
respectively).
Table 16-1. Differences between Channels 0, 2, and 3
Serial Transfer Mode
3-wire serial I/O
Channel 0
Channel 3
Channel 2
Clock selection
fXX/2,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock, TO2 output
External clock, baud
rate generator output
fXX/2, fXX/22, fXX/23,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock
Transfer method
MSB/LSB switchable as
the start bit
MSB/LSB switchable as
the start bit
MSB/LSB switchable as
the start bit
Transfer end flag
Serial transfer end
interrupt request flag
(CSIIF0)
Serial transfer end
interrupt request flag
(SRIF)
Serial transfer end
interrupt request flag
(CSIIF3)
Use possible
None
None
None
Use possible
None
I2C bus (Inter IC Bus)
fXX/22,
fXX/23,
2-wire serial I/O
UART
(Asynchronous serial interface)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.1 Serial Interface Channel 0 Functions
Serial interface channel 0 employs the following four modes.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• I2C (Inter IC) bus mode
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or I2C bus) while serial
interface channel 0 is enabled. To change the operating mode, stop the serial operation once.
(1) Operation stop mode
This mode is used when serial transfer is not carried out. Power consumption can be reduced.
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)
This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0)
and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data
transfer processing time.
The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected
regardless of their start bit recognition.
This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
(3) 2-wire serial I/O mode (MSB-first)
This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or
SB1).
This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level
and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or
more devices can be removed, resulting in the increased number of available input/output ports.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(4) I2C (Inter IC) bus mode (MSB-first)
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and
serial data bus (SDA0 or SDA1).
This mode is in compliance with the I2C bus format. In this mode, the transmitter outputs three kinds of data
onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received. The
receiver automatically distinguishes the received data into “start condition”, “data”, or “stop condition”, by
hardware.
Figure 16-1. Serial Bus Configuration Example Using I2C Bus
VDD0
VDD0
Master CPU
Slave CPU1
SCL
SDA0 (SDA1)
SCL
SDA0 (SDA1)
Slave CPU2
SCL
SDA0 (SDA1)
Slave CPUn
SCL
SDA0 (SDA1)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.2 Serial Interface Channel 0 Configuration
Serial interface channel 0 consists of the following hardware.
Table 16-2. Serial Interface Channel 0 Configuration
Item
Configuration
Register
Serial I/O shift register 0 (SIO0)
Slave address register (SVA)
Control register
Timer clock select register 3 (TCL3)
Serial operating mode register 0 (CSIM0)
Serial bus interface control register (SBIC)
Interrupt timing specify register (SINT)
Port mode register 2 (PM2)
Note
Refer to Figure 6-7 P25, P26 Block Diagram (µPD780308Y
Subseries) and Figure 6-8 P27 Block Diagram (µPD780308Y
Subseries).
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CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
Figure 16-2. Serial Interface Channel 0 Block Diagram
Internal Bus
Serial Bus Interface
Control Register
Serial Operating Mode Register 0
CSIE0 COI WUP
Slave Address
Register (SVA)
CSIM CSIM CSIM CSIM CSIM
04
03
02
01
00
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
SVAM
Match
BSYE
Control
Circuit
SI0/SB0/
SDA0/P25
Selector
P25
Output
Latch
PM25
Output
Control
Acknowledge
Output Circuit
Selector
SO0/SB1/
SDA1/P26
Stop Condition/
Start Condition/
Acknowledge
Detector
PM26
Output
Control
SCK0/
SCL/P27
CLR SET
D
Q
Serial I/O Shift
Register 0 (SIO0)
CLD
P26 Output Latch
ACKD
CMDD
RELD
WUP
Interrupt
Request
Signal
Generator
Serial Clock
Counter
PM27
INTCSI0
TO2
Output
Control
Serial Clock
Control Circuit
CSIM00
CSIM01
Selector
1/16
Divider
CSIM00
CSIM01
2
Selector
f xx/2 to f xx/28
4
P27
Output Latch
CLD
SIC
SVAM CLC WREL WAT1 WAT0
TCL33 TCL32 TCL31 TCL30
Interrupt Timing
Specify Register
Timer Clock
Select
Register 3
Internal Bus
Remarks 1. Output Control performs selection between CMOS output and N-ch open drain output.
2. fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception
(shift operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
Note that, if a bus is driven in the I2C bus mode or 2-wire serial I/O mode, the bus pin must serve for both
input and output. Therefore, the transmission N-ch transistor of the device which will start reception of data
must be turned off beforehand. Consequently, write FFH to SIO0 in advance.
In the I2C bus mode, set SIO0 to FFH with bit 7 (BSYE) of the serial bus interface control register (SBIC) set
to 0.
RESET input makes SIO0 undefined.
Caution Do not execute an instruction that writes SIO0 while WUP (bit 5 of the serial operating mode
register 0 (CSIM0)) is 1 in the I2C bus mode. Even if this instruction is not executed, data
can be received when the wake-up function is used (WUP = 1). For the details of the wakeup function, refer to 16.4.4 (1) (c) Wake-up function.
(2) Slave address register (SVA)
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O
mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave
device. These two data (the slave address output from the master device and the SVA value) are compared
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of
serial operating mode register 0 (CSIM0) becomes 1.
By setting bit 4 (SVAM) of the interrupt timing specify register (SINT) to 1, the address can be compared using
the data of the LSB-masked high-order 7 bits.
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0.
In the I2C bus mode, the wake-up function can be used by setting bit 5 (WUP) of the CSIM0 register. In this
case, an interrupt request signal (INTCSI0) is generated when the slave address output by the master
coincides with the value of SVA (the interrupt request signal is also generated when the stop condition is
detected). This interrupt request indicates that the master has requested for communication. Note that SIC
must be set to 1 when the wake-up function is used.
When the device is used as the master or slave in the 2-wire serial I/O or I2C bus mode, detect an error by
using slave address register (SVA).
RESET input makes SVA undefined.
(3) SO0 latch
This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by
software.
(4) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception and to check whether
8-bit data has been transmitted/received.
(5) Serial clock control circuit
This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock
is used, the circuit also controls clock output to the SCK0/SCL/P27 pin.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(6) Interrupt request signal generator
This circuit controls interrupt request signal generation. It generates interrupt request signals according to
the settings of interrupt timing specify register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operating mode
register 0 (CSIM0) bit 5 (WUP), as shown in Table 16-3.
(7) Acknowledge output circuit and stop condition/start condition/acknowledge detector
These two circuits output and detect various control signals in the I2C mode.
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
Table 16-3. Serial Interface Channel 0 Interrupt Request Signal Generation
Serial Transfer Mode
3-wire or 2-wire serial I/O mode
BSYE
WUP
0
0
WAT1 WAT0 ACKE
0
0
0
Other than above
I 2C
bus mode (transmit)
0
0
Setting prohibited
1
0
0
An interrupt request signal is generated each time 8
serial clocks are counted (8-clock wait).
Normally, during transmission the settings WAT21,
WAT0 = 1, 0, are not used. They are used only when
wanting to coordinate receive time and processing
systematically using software. ACK information is
generated by the receiving side, thus ACKE should be
set to 0 (disable).
1
1
0
An interrupt request signal is generated each time 9
serial clocks are counted (9-clock wait).
ACK information is generated by the receiving side,
thus ACKE should be set to 0 (disable).
Other than above
I 2C
bus mode (receive)
1
1
0
1
Description
An interrupt request signal is generated each time 8
serial clocks are counted.
Setting prohibited
1
0
0
An interrupt request signal is generated each time 8
serial clocks are counted (8-clock wait).
ACK information is output by manipulating ACKT by
software after an interrupt request is generated.
1
1
0/1
An interrupt request signal is generated each time 9
serial clocks are counted (9-clock wait).
To automatically generate ACK information, preset
ACKE to 1 before transfer start. However, in the case
of the master, set ACKE to 0 (disable) before receiving
the last data.
1
1
1
Generates an interrupt request signal when the
values of the serial I/O shift register 0 (SIO0) and
slave address register (SVA) coincide, or when the
stop condition is detected, after an address has been
received.
To automatically generate ACK information, preset
ACKE to 1 (enable) before transfer start.
Other than above
Setting prohibited
BSYE: Bit 7 of serial bus interface control register (SBIC)
ACKE: Bit 5 of serial bus interface control register (SBIC)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.3 Serial Interface Channel 0 Control Registers
The following four types of registers are used to control serial interface channel 0.
• Timer clock select register 3 (TCL3)
• Serial operating mode register 0 (CSIM0)
• Serial bus interface control register (SBIC)
• Interrupt timing specify register (SINT)
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 0.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Figure 16-3. Timer Clock Select Register 3 Format
Symbol
7
6
5
4
TCL3
1
0
0
0
3
2
1
0
TCL33 TCL32 TCL31 TCL30
Address
After Reset
FF43H
88H
R/W
R/W
Serial Interface Channel 0 Serial Clock Selection
TCL33 TCL32 TCL31 TCL30
2
Serial Clock in I C Bus Mode
MCS = 1
MCS = 0
Serial Clock in 2-Wire or 3-Wire
Serial I/O Mode
MCS = 1
MCS = 0
0
1
1
0
Setting prohibited
f X/26 (78.1 kHz)
Setting prohibited
f X/22 (1.25 MHz)
0
1
1
1
f X/26 (78.1 kHz)
f X/27 (39.1 kHz)
f X/22 (1.25 MHz)
f X/23 (625 kHz)
1
0
0
0
f X/27 (39.1 kHz)
f X/28 (19.5 kHz)
f X/23 (625 kHz)
f X/24 (313 kHz)
1
0
0
1
f X/28 (19.5 kHz)
f X/29 (9.77 kHz)
f X/24 (313 kHz)
f X/25 (156 kHz)
1
0
1
0
f X/29 (9.77 kHz)
f X/210 (4.88 kHz)
f X/25 (156 kHz)
f X/26 (78.1 kHz)
1
0
1
1
f X/210 (4.88 kHz)
f X/211 (2.44 kHz)
f X/26 (78.1 kHz)
f X/27 (39.1 kHz)
1
1
0
0
f X/211 (2.44 kHz)
f X/212 (1.22 kHz)
f X/27 (39.1 kHz)
f X/28 (19.5 kHz)
1
1
0
1
f X/212 (1.22 kHz)
f X/213 (0.61 kHz)
f X/28 (19.5 kHz)
f X/29 (9.8 kHz)
Other than above
Setting prohibited
Cautions 1. Set bit 4 to bit 6 to 0, and bit 7 to 1.
2. When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Figures in parentheses apply to operation with fX = 5.0 MHz.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(2) Serial operating mode register 0 (CSIM0)
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up
function and displays the address comparator match signal.
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or I2C bus) while serial
interface channel 0 is enabled. To change the operating mode, stop the serial operation once.
Figure 16-4. Serial Operating Mode Register 0 Format (1/2)
Symbol
7
6
CSIM0 CSIE0 COI
R/W
R
R/W
5
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
Address
After Reset
FF60H
00H
R/W
R/W Note 1
Serial Interface Channel 0 Operation Control
CSIE0
0
Operation stopped
1
Operation enabled
Slave Address Comparison Result Flag Note 2
COI
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
Wake-up Function Control Note 3
WUP
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after detecting start condition
(when CMDD = 1) matches the slave address register data in I2C bus mode
Notes 1. Bit 6 (COI) is a read-only bit.
2. COI is 0 when CSIE0 = 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up
function (WUP = 1). Do not execute an instruction that writes the serial I/O shift register 0
(SIO0) while WUP = 1.
Remark
×:
don’t care
PM××: Port mode register
P××: Port output latch
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
Figure 16-4. Serial Operating Mode Register 0 Format (2/2)
R/W
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
04
03
0
×
02
0
Note 2 Note 2
1
1
×
0
0
0
1
Operation
Mode
Start Bit
3-wire serial
l/O mode
MSB
LSB
SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27
P25 Pin Function P26 Pin Function Pin Function
SI0 Note 1
(Input)
Note 3 Note 3
0
1
×
×
0
0
0
1
Note 3 Note 3
1
R/W
CSIM01 CSIM00
0
0
×
×
0
1
2-wire serial
l/O mode
or
2
1 I C Bus Mode
SO0
(CMOS output)
P25 (CMOS
input/output)
SB1/SDA1
(N-ch open-drain
input/output)
SB0/SDA0
(N-ch open-drain
input/output)
P26 (CMOS
input/output)
MSB
SCK0 (CMOS
input/output)
SCK0/SCL
(N-ch open-drain
input/output)
Serial Interface Channel 0 Clock Selection
0
×
Input Clock to SCK0/SCL pin from off-chip
1
0
8-bit timer register 2 (TM2) output Note 4
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up
function (WUP = 1). Do not execute an instruction that writes the serial I/O shift register 0
(SIO0) while WUP = 1.
2. This pin can be used as P25 (CMOS I/O) only to transmit data.
3. These pins can be used freely as port pins.
4. I2C bus mode, the clock frequency becomes 1/16 of that output from TO2.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(3) Serial bus interface control register (SBIC)
This register sets serial bus interface operation and displays statuses.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Figure 16-5. Serial Bus Interface Control Register Format (1/2)
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
Address
FF61H
R
1
Output disabled (reception)
ACKD
Acknowledge Detection
Set Conditions (ACKD = 1)
Clear Conditions (ACKD = 0)
• While executing the transfer start instruction
• When CSIE0 = 0
• When RESET input is applied
ACKT
• When acknowledge signal (ACK) is detected at the
rising edge of SCL clock after completion of
transfer
Acknowledge Signal Output Control Note 4
ACKE
R/W
Note 1
2
Output enabled (transmission)
1
R/W
Control of N-ch Open-Drain Output for Transmission in I C Bus Mode Note 3
0
0
R/W
00H
Note 2
BSYE
R/W
After Reset
Disables acknowledge signal automatic output. (However, output with ACKT is enabled)
Used for reception when 8-clock wait mode is selected or for transmission. Note 5
Enables acknowledge signal automatic output.
Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Used in reception with 9-clock wait mode selected.
Used to generate the ACK signal by software when 8-clock wait mode is selected.
Keeps SDA0 (SDA1) low from set instruction (ACKT=1) execution to the next falling edge of SCL.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
R CMDD
Start Condition Detection
Clear Conditions (CMDD = 0)
Set Conditions (CMDD = 1)
• When transfer start instruction is executed
• When stop condition signal is detected
• When CSIE0 = 0
• When RESET input is applied
• When start condition signal is detected
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cancelled by start of serial interface transfer or reception of address signal.
However, the BSYE flag is not cleared to 0.
3. When using the wake-up function, be sure to set BSYE to 1.
4. Setting should be performed before transfer.
5. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using
ACKT.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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Figure 16-5. Serial Bus Interface Control Register Format (2/2)
R
RELD
Stop Condition Detection
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in
address reception
• When CSIE0 = 0
• When RESET input is applied
R/W
Set Conditions (RELD =1)
• When stop condition signal is detected
CMDT
Used for start condition signal output.
When CMDT = 1, SO Iatch is cleared (to 0). After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
Used for stop condition signal output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(4) Interrupt timing specify register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level
status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Figure 16-6. Interrupt Timing Specify Register Format (1/2)
Symbol
7
6
SINT
0
CLD
R
R/W
R/W
R/W
5
4
3
2
1
0
SIC SVAM CLC WREL WAT1 WAT0
CLD
Address
After Reset
FF63H
00H
R/W
R/W Note 1
SCK0/SCL Pin Level Note 2
0
Low level
1
High level
SIC
INTCSI0 Interrupt Cause Selection
Note 3
0
CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer
1
CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer
SVA Bit to be Used as Slave Address
SVAM
0
Bits 0 to 7
1
Bits 1 to 7
Clock Level Control Note 4
CLC
2
0
Used in I C bus mode.
Make output level of SCL pin low unless serial transfer is being performed.
1
Used in I2C bus mode.
Make SCL pin enter high-impedance state unless serial transfer is being performed.
(except for clock line which is kept high)
Used to enable master device to generate start condition and stop condition signals.
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using wake-up function in the I2C mode, set SIC to 1.
4. When not using the I2C mode, set CLC to 0.
Remark
SVA:
Slave address register
CSIIF0:
Interrupt request flag corresponding to INTCSI0
CSIE0:
Bit 7 of serial operating mode register 0 (CSIM0)
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Figure 16-6. Interrupt Timing Specify Register Format (2/2)
R/W
R/W
WREL
Wait Sate Cancellation Control
0
Wait state has been cancelled.
1
Cancels wait state. Automatically cleared to 0 when the state is cancelled.
(Used to cancel wait state by means of WAT0 and WAT1.)
Wait and Interrupt Control
WAT1 WAT0
0
0
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
(keeping clock output in high impedance)
0
1
Setting prohibited
1
0
Used in I2C bus mode. (8-clock wait)
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 8 clock
pulses are input.)
1
1
Used in I2C bus mode. (9-clock wait)
Generates interrupt service request at rising edge of 9th SCK0 clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 9 clock
pulses are input.)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.4 Serial Interface Channel 0 Operations
The following four operating modes are available to the serial interface channel 0.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• I2C (Inter IC) bus mode
16.4.1 Operation stop mode
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial
I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register.
In the operation stop mode, the P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 and P27/SCK0/SCL pins can be used
as general input/output ports.
(1) Register setting
The operation stop mode is set with the serial operating mode register 0 (CSIM0).
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
CSIM0 CSIE0 COI
R/W
5
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
FF60H
After Reset
00H
R/W
R/W
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.4.2 3-wire serial I/O mode operation
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
(1) Register setting
The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface
control register (SBIC).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R/W
R/W
4
WUP
3
2
1
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
R/W
R/W Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
Wake-up Function Control
WUP
Note 2
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after detecting start condition
(when CMDD = 1) matches the slave address register data in I 2C bus mode
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
04
03
0
×
1
R/W
0
1
02
0
Operation
Mode
Note 3 Note 3
1
1
×
0
0
0
1
3-wire serial
l/O mode
Start Bit
MSB
LSB
SIO/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL/P27
/P25 Pin Function /P26 Pin Function Pin Function
SI0 Note 3
(Input)
SO0
(CMOS output)
2-wire serial I/O mode (See Section 16.4.3 2-wire serial I/O mode operation)
or
I2C bus mode (See Section 16.4.4 I2C bus mode operation)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input Clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
3. Can be used as P25 (CMOS input/output) when used only for transmission.
Remark
×:
don’t care
PM××: Port mode register
P××:
306
Port output latch
SCK0 (CMOS
input/output)
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
R/W
Address
FF61H
After Reset
00H
R/W
R/W
CMDT
When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/
reception is carried out in synchronization with the serial clock.
Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the
SI0 pin is latched in SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 16-7. 3-Wire Serial I/O Mode Timings
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0
End of Transfer
Transfer Start at the Falling Edge of SCK0
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status
can be manipulated by setting the bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 16.4.7 SCK0/SCL/P27 pin output manipulation).
(3) Other signals
Figure 16-8 shows RELT and CMDT operations.
Figure 16-8. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(4) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the
figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register
0 (CSIM0).
Figure 16-9. Circuit of Switching in Transfer Bit Order
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO0 Latch
SI0
Shift Register 0 (SIO0)
D
Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(5) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1.
• Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer.
Caution If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
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CHAPTER 16
16.4.3
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
2-wire serial I/O mode operation
The 2-wire serial I/O mode can cope with any communication format by program.
Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or
SB1).
Figure 16-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
VDD0
VDD0
Master
Slave
SCK0
SB0 (SB1)
SCK0
SB0 (SB1)
(1) Register setting
The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface
control register (SBIC), and the interrupt timing specify register (SINT).
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(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
R/W
4
WUP
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
R/W
Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
COI
Slave Address Comparison Result Flag
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
Wake-up Function Control
WUP
Note 2
Note 3
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after detecting start condition
(when CMDD = 1) matches the slave address register data in I 2C bus mode
CSIM CSIM CSIM
Operation
Mode
PM25 P25 PM26 P26 PM27 P27
04
03
0
×
02
Start Bit
SIO/SB0/SDA0
SO0/SB1/SDA1 SCK0/SCL/P27
/P25 Pin Function /P26 Pin Function Pin Function
3-wire Serial I/O mode (See Section 16.4.2 3-wire serial I/O mode operation)
Note 4 Note 4
0
1
×
×
0
0
0
1
1
Note 4 Note 4
1
R/W
R/W
0
0
×
×
0
2-wire serial
l/O mode
or
I2C bus mode
1
P25 (CMOS
input/output
SB1/SDA1
(N-ch open-drain
input/output)
MSB
SB0/SDA0
(N-ch open-drain
input/output)
SCK0/SCL
(N-ch open-drain
input/output)
P26 (CMOS
input/output)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input Clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.
4. Can be used freely as port function.
Remark
×:
don’t care
PM××: Port mode register
P××:
Port output latch
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
R/W
312
Address
FF61H
After Reset
00H
R/W
R/W
CMDT
When CMDT = 1, SO Iatch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
When RELT = 1, SO Iatch is set to 1. After SO Iatch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Symbol
7
6
SINT
0
CLD
R
R/W
5
4
3
2
1
0
SIC SVAM CLC WREL WAT1 WAT0
CLD
Address
FF63H
SCK0 Pin Level
0
Low level
1
High level
SIC
After Reset
00H
R/W
R/W
Note 1
Note 2
INTCSI0 Interrupt Factor Selection
0
CSIIF0 is set upon termination of serial interface channel 0 transfer
1
CSIIF0 is set upon stop condition detection or termination of serial interface channel 0 transfer
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bit 0 to bit 3 to 0 when 2-wire serial I/O mode is used.
Remark
CSIIF0: Interrupt request flag corresponding to INTCSI0
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(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception
is carried out bit-wise in synchronization with the serial clock.
Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge
of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/SDA0/P25
(or SB1/SDA1/P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched
into the shift register at the rising edge of SCK0.
Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request
flag (CSIIF0) is set.
Figure 16-11. 2-Wire Serial I/O Mode Timings
SCK0
SB0 (SB1)
1
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
D0
CSIIF0
End of Transfer
Transfer start at the falling edge of SCK0
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be
externally connected to a pull-up resistor. Because the N-ch transistor output pin must go into a highimpedance state for data reception, write FFH to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be
manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial
transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 16.4.7 SCK0/SCL/P27 pin output manipulation).
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(3) Other signals
Figure 16-12 shows RELT and CMDT operations.
Figure 16-12. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch transistor output pin must go into a high-impedance state for data
reception, write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged
to have occurred.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
16.4.4
The
I2C bus mode operation
I2 C
bus mode is provided for when communication operations are performed between a single master device
and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is
based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master
device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data
bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple
microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port
pins and on-board wires.
In the I2C bus specification, the master sends start condition, data, and stop condition signals to slave devices
through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the
signal detection function incorporated as hardware. This simplifies I2C bus control sections in the application program.
An example of a serial bus configuration is shown in Figure 16-13. This system below is composed of CPUs and
peripheral ICs having serial interface hardware that complies with the I2C bus specification.
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because opendrain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I2C bus.
The signals used in the I2C bus mode are described in Table 16-4.
Figure 16-13. Example of Serial Bus Configuration Using I2C Bus
VDD0 VDD0
Master CPU
Slave CPU1
SCL
SDA0 (SDA1)
Serial Clock
Serial Data Bus
SCL
SDA0 (SDA1)
Slave CPU2
SCL
SDA0 (SDA1)
Slave IC
SCL
SDA
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(1) I2C bus mode functions
In the I2C bus mode, the following functions are available.
(a) Automatic identification of serial data
Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in
series through the serial data bus.
(b) Chip selection by specifying device addresses
The master device can select a specific slave device connected to the I2C bus and communicate with it by
sending in advance the address data corresponding to the destination device.
(c) Wake-up function
When address data is sent from the master device, slave devices compare it with the value registered in
their internal slave address registers. If the values in one of the slave devices match, the slave device
internally generates an interrupt request signal to terminate the current processing and communicates
with the master device (The interrupt request is also generated when the stop condition is detected).
Therefore, CPUs other than the selected slave device on the I2C bus can perform independent operations
during the serial communication.
(d) Acknowledge signal (ACK) control function
The master device and a slave device send and receive acknowledge signals to confirm that the serial
communication has been executed normally.
(e) Wait signal (WAIT) control function
When a slave device is preparing for data transmission or reception and requires more waiting time, the
slave device outputs a wait signal on the bus to inform the master device of the wait status.
(2) I2C bus definition
This section describes the format of serial data communications and functions of the signals used in the
I2C bus mode.
First, the transfer timings of the start condition, data, and stop condition signals, which are output onto the
signal data bus of the I2C bus, are shown in Figure 16-14.
Figure 16-14. I2C Bus Serial Data Transfer Timing
SCL
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDA0 (SDA1)
Start
Address
Condition
R/W ACK
Data
ACK
Data
ACK
Stop
Condition
The start condition, slave address, and stop condition signals are output by the master. The acknowledge
signal (ACK) is output by either the master or the slave device (normally by the device which has received
the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(a) Start condition
When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is
recognized as the start condition signal. This start condition signal, which is created using the SCL and
SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See
section 16.4.5, "Cautions on Use of I2C Bus Mode," for details of the start condition output.
The start condition signal is detected by hardware incorporated in slave devices.
Figure 16-15. Start Condition
H
SCL
SDA0 (SDA1)
(b) Address
The 7 bits following the start condition signal are defined as an address.
The 7-bit address data is output by the master device to specify a specific slave from among those connected
to the bus line. Each slave device on the bus line must therefore have a different address.
Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and
the data of the slave address register (SVA). After the comparison, only the slave device in which the
data are a match becomes the communication partner, and subsequently performs communication with
the master device until the master device sends a start condition or stop condition signal.
Figure 16-16. Address
SCL
1
2
A6
SDA0 (SDA1)
3
A5
4
A4
5
A3
6
A2
7
A1
A0
R/W
Address
(c) Transfer direction specification
The 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the
transfer direction specification bit. If this bit is 0, it is the master device which will send data to the slave.
If it is 1, it is the slave device which will send data to the master.
Figure 16-17. Transfer Direction Specification
SCL
SDA0 (SDA1)
1
2
A6
3
A5
4
A4
5
A3
6
A2
8
7
A1
A0
R/W
Transfer Direction
Specification
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(d) Acknowledge signal (ACK)
The acknowledge signal indicates that the transferred serial data has definitely been received. This signal
is used between the sending side and receiving side devices for confirmation of correct data transfer. In
principle, the receiving side device returns an acknowledge signal to the sending device each time it
receives 8-bit data. The only exception is when the receiving side is the master device and the 8-bit data
is the last transfer data; the master device outputs no acknowledge signal in this case.
The sending side that has transferred 8-bit data waits for the acknowledge signal which will be sent from
the receiving side. If the sending side device receives the acknowledge signal, which means a successful
data transfer, it proceeds to the next processing. If this signal is not sent back from the slave device, this
means that the data sent has not been received by the slave device, and therefore the master device
outputs a stop condition signal to terminate subsequent transmissions.
Figure 16-18. Acknowledge Signal
SCL
1
2
A6
SDA0 (SDA1)
3
A5
4
A4
5
A3
6
A2
7
A1
8
A0
9
R/W
ACK
(e) Stop condition
If the SDA0 (SDA1) pin level changes from low to high while the SCL pin is high, this transition is defined
as a stop condition signal.
The stop condition signal is output from the master to the slave device to terminate a serial transfer.
The stop condition signal is detected by hardware incorporated in the slave device.
Figure 16-19. Stop Condition
H
SCL
SDA0 (SDA1)
319
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
(f) Wait signal (WAIT)
The wait signal is output by a slave device to inform the master device that the slave device is in wait state
due to preparing for transmitting or receiving data.
During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to
delay subsequent transfers. When the wait state is released, the master device can start the next transfer.
For the releasing operation of slave devices, see Section 16.4.5 Cautions on use of I2C bus mode.
Figure 16-20. Wait Signal
(a) Wait of 8 Clock Cycles
Set low because slave device drives low,
though master device returns to Hi-Z state.
No wait is inserted after 9th clock cycle.
(and before master device starts next transfer.)
SCL of
Master Device
6
7
8
9
1
2
3
4
SCL of
Slave Device
SCL
D2
SDA0 (SDA1)
D1
D0
D7
ACK
D6
D5
D4
Output by manipulating ACKT
(b) Wait of 9 Clock Cycles
Set low because slave device drives low,
though master device returns to Hi-Z state.
SCL of
Master Device
6
7
8
9
1
2
3
SCL of
Slave Device
SCL
SDA0 (SDA1)
D2
D1
D0
ACK
D7
D6
D5
Output based on the value set in ACKE in advance
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(3) Register setting
The I2C mode setting is performed by the serial operating mode register 0 (CSIM0), the serial bus interface
control register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
R/W
4
WUP
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
R/W
Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
COI
Slave Address Comparison Result Flag
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
Wake-up Function Control
WUP
Note 2
Note 3
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after start condition detection
(when CMDD = 1) matches the slave address register data in I2C bus mode
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
Operation
Mode
Start Bit
SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27
P25 Pin Function P26 Pin Function Pin Function
04
03
02
0
×
3-wire serial I/O mode (See Section 16.4.2 3-wire serial I/O mode operation)
Note 4 Note 4
×
0
1
×
0
0
0
0
Note 4 Note 4
1
R/W
R/W
0
0
×
×
0
P25 (CMOS
input/output)
1
Two-wire
serial I/O
or
2
1 I C bus mode
SB1/SDA1
(N-ch open-drain
input/output)
MSB
SB0/SDA0
(N-ch open-drain
input/output)
P26 (CMOS
input/output)
SCK0/SCL
(N-ch open-drain
input/output)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input clock from off-chip to SCL pin
1
0
8-bit timer register 2 (TM2) output Note 5
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. COI is 0 when CSIE0 = 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wake-up function
(WUP = 1). Do not execute an instruction that writes the serial I/O shift register 0 (SIO0) while WUP
= 1.
4. These pins can be used freely as port pins.
5. In the I2C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2.
Remark ×:
don’t care
PM××: Port mode register
P××:
Port output latch
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
R
Note 2
BSYE
FF61H
R/W
00H
R/W
Note 1
2
0
Output enabled (transmission)
1
Output disabled (reception)
ACKD
Note 3
Acknowledge Detection
Set Conditions (ACKD = 1)
• When transfer start instruction is executed
• When CSIE0 = 0
• When RESET input is applied
ACKE
0
After Reset
Control of N-ch Open-Drain Output for Transmission in I C Bus Mode
Clear Conditions (ACKD = 0)
R/W
Address
• When acknowledge signal is detected at the
rising edge of SCL clock after completion of
transfer
Acknowledge Signal Automatic Output Control Note 4
Disabled (with ACKT enabled).
Used when receiving data in the 8-clock wait mode or when transmitting data
Note 5
Enabled.
After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of SCL
clock (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge
signal output. Used for reception when the 9-clock wait mode is selected.
1
R/W
ACKT
SDA0 (SDA1) is set to low after the Set instruction execution (ACKT = 1) before the next SCL falling edge.
Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared to 0 if CSIE0
= 0 when a transfer by the serial interface is started.
R CMDD
Start Condition Detection
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When stop condition is detected
• When CSIE0 = 0
• When RESET input is applied
Set Conditions (CMDD = 1)
• When start condition is detected
(continued)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only bits.
2. The busy mode can be released by the start of a serial interface transfer or reception of an address
signal. However, the BSYE flag is not cleared.
3. When using the wake-up function, be sure to set BSYE to 1.
4. This setting must be performed prior to transfer start.
5. In the 8-clock wait mode, use ACKT for output of the acknowledge signal after normal data reception.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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R
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
RELD
Stop Condition Detection
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
Set Conditions (RELD = 1)
• When stop condition is detected
• When RESET input is applied
R/W
CMDT
Use for start condition output.
When CMDT = 1, SO latch is cleared to 0. After clearing SO latch, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
Used for stop condition output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(c) Interrupt timing specification register (SINT)
SINT is set with the 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Symbol
7
6
SINT
0
CLD
R
R/W
R/W
R/W
R/W
5
4
3
2
1
0
Address
SIC SVAM CLC WREL WAT1 WAT0
CLD
FF63H
SCL Pin Level
0
Low level
1
High level
SIC
After Reset
00H
R/W
R/W
Note 1
Note 2
INTCSI0 Interrupt Cause Selection
Note 3
0
CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer
1
CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer
SVA Bit to be Used as Slave Address
SVAM
0
Bits 0 to 7
1
Bits 1 to 7
Clock Level Control
CLC
2
0
Used in I C bus mode.
Make output level of SCL pin low unless serial transfer is being performed.
1
Used in I2C bus mode.
Make SCL pin enter high-impedance state unless serial transfer is being performed.
(except for clock line which is kept high)
Used to enable master device to generate start condition and stop condition signals.
Wait Sate Cancellation Control
WREL
0
Wait state has been cancelled.
1
Cancels wait state. Automatically cleared to 0 when the state is cancelled.
(Used to cancel wait state by means of WAT0 and WAT1.)
(continued)
Notes 1. Bit 6 (CLD) is read-only.
2. When CSIE0 = 0, CLD is 0.
3. When using the wake-up function in I2C mode, be sure to set SIC to 1.
Remark SVA:
Slave address register
CSIIF0:Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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CHAPTER 16
R/W
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
Wait and Interrupt Control
WAT1 WAT0
Note
0
0
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
(keeping clock output in high impedance)
0
1
Setting prohibited
1
0
Used in I2C bus mode. (8-clock wait)
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 8 clock
pulses are input.)
1
1
Used in I2C bus mode. (9-clock wait)
Generates interrupt service request at rising edge of 9th SCK0 clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 9 clock
pulses are input.)
Note
When the I2C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT0 and WAT1, respectively.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(4) Various signals
A list of signals in the I2C bus mode is given in Table 16-4.
Table 16-4. Signals in I2C Bus Mode
Signal name
Description
Start condition
Definition :
SDA0 (SDA1) falling edge when SCL is high Note 1
Function :
Indicates that serial communication starts and subsequent data are address data.
Signalled by :
Master
Signalled when : CMDT is set.
Affected flag(s) : CMDD (is set.)
Stop condition
Definition :
SDA0 (SDA1) rising edge when SCL is high Note 1
Function :
Indicates end of serial transmission.
Signalled by :
Master
Signalled when : RELT is set.
Affected flag(s) : RELD (is set) and CMDD (is cleared)
Acknowledge signal (ACK)
Definition :
Low level of SDA0(SDA1) pin during one SCL clock cycle after serial reception
Function :
Indicates completion of reception of 1 byte.
Signalled by :
Master or slave
Signalled when : ACKT is set with ACKE = 1.
Affected flag(s) : ACKD (is set.)
Definition :
Low-level signal output to SCL
Wait (WAIT)
Function :
Indicates state in which serial reception is not possible.
Signalled by :
Slave
Signalled when : WAT1, WAT0 = 1x.
Affected flag(s) : None
Serial Clock (SCL)
Definition :
Function :
Synchronization clock for output of various signals
Serial communication synchronization signal.
Signalled by :
Master
Signalled when : See Note 2 below.
Affected flag(s) : CSIIF0. Also see Note 3 below.
Address (A6 to A0)
Definition :
7-bit data synchronized with SCL immediately after start condition signal
Function :
Signalled by :
Indicates address value for specification of slave on serial bus.
Master
Signalled when : See Note 2 below.
Affected flag(s) : CSIIF0. Also see Note 3 below.
Transfer direction (R/W)
Definition :
1-bit data output in synchronization with SCL after address output
Function :
Indicates whether data transmission or reception is to be performed.
Signalled by :
Master
Signalled when : See Note 2 below.
Affected flag(s) : CSIIF0. Also see Note 3 below.
Data (D7 to D0))
Definition :
8-bit data synchronized with SCL, not immediately after start condition
Function :
Contains data actually to be sent.
Signalled by :
Master or slave
Signalled when : See Note 2 below.
Affected flag(s) : CSIIF0. Also see Note 3 below.
Notes 1. The level of the serial clock can be controlled by CLC of interrupt timing specify register (SINT).
2. Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start directive). In the
wait state, the serial transfer operation will be started after the wait state is released.
3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle
of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock
cycle of SCL. If WUP = 1, CSIIF0 is set when an address is received and the address matches the
slave address register (SVA) value, or when the stop condition is detected.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(5) Pin configurations
The configurations of the serial clock pin (SCL) and the serial data bus pins (SDA0, SDA1) are shown
below.
(a) SCL
Pin for serial clock input/output dual-function pin.
<1> Master ..... N-ch open-drain output
<2> Slave ....... Schmitt input
(b) SDA0 (SDA1)
Serial data input/output dual-function pin.
Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices.
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because
open-drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on
the I2C bus.
Figure 16-21. Pin Configuration
Slave Devices
VDD0
Master Device
SCL
Clock Output
SCL
(Clock Output)
VDD0
VSS0
VSS0
(Clock Input)
Clock Input
SDA0 (SDA1)
SDA0 (SDA1)
Data Output
VSS0
Data Input
Data Output
VSS0
Data Input
Caution When data is received, the N-ch open-drain output pin must go into a high-impedance
state. Therefore, set bit 7 (BSYE) of the serial bus interface control register (SBIC) to 1,
and write FFH to the serial I/O shift register 0 (SIO0).
However, do not write FFH to SIO0 before reception when the wake-up function is used
(when bit 5 (WUP) of the serial operating mode register 0 (CSIM0) is set). Even if FFH is
not written to SIO0, the N-ch open-drain output pin always goes into a high-impedance
state.
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(6) Address match detection method
In the I2C mode, the master can select a specific slave device by sending slave address data.
Address match detection is performed automatically by the slave device hardware. A slave device address
has a slave register (SVA), and compares its contents and the slave address sent from the master device.
If they match and the wake-up function specify (WUP) bit is then 1, interrupt request flag (CSIIF0) is set
(CSIIF0 is also set when the stop condition is detected).
Set SIC to 1 when using the wake-up function.
Caution Status detection of slave selection/non-selection is performed by a match detection of
reception data (address) after the start condition. This address match signal interrupt
generated during WUP = 1 is used as a match signal. Thus, perform the slave selection/
non-selection detection during WUP = 1.
(7) Error detection
In the I2C bus mode, transmission error detection can be performed by the following methods because the
serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0)
of the transmitting device.
(a) Comparison of SIO0 data before and after transmission
In this case, a transmission error is judged to have occurred if the two data values are different.
(b) Using the slave address register (SVA)
Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit
(match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1"
indicates normal transmission, and "0" indicates a transmission error.
(8) Communication operation
In the I 2C bus mode, the master selects the slave device to be communicated with from among multiple
devices by outputting address data onto the serial bus.
After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and
starts serial communication with the selected slave device.
Data communication timing charts are shown in Figures 16-22 and 16-23.
In the transmitting device, the serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in
synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSBfirst basis from the SDA0 or SDA1 pin to the receiving device.
In the receiving device, the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchronization
with the rising edge of SCL.
328
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
Figure 16-22.
Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (1 of 3)
(a) Start Condition to Address
Master Device Operation
SIO0
Address
SCL
1
3
SDA0
A6 A5 A4 A3 A2 A1 A0 W ACK
Write SIO0
SIO0
Data
COI
ACKD
CMDD
RELD
L
CLD
P27
WUP
H
L
BSYE
L
ACKE
L
CMDT
RELT
L
CLC
WREL
L
SIC
L
INTCSI0
Transfer Line
2
4
5
6
7
8
9
1
D7
2
3
4
5
D6 D5 D4 D3
Slave Device Operation
SIO0
Write SIO0
FFH
COI
ACKD
CMDD
RELD
L
CLD
P27
WUP
BSYE
H
ACKE
CMDT
H
L
RELT
L
CLC
L
WREL
L
SIC
H
INTCSI0
CSIE0
H
P25
L
PM25
L
PM27
L
329
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
Figure 16-22.
Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (2 of 3)
(b) Data
Master Device Operation
SIO0
Write SIO0
Data
SIO0
Data
COI
ACKD
CMDD
RELD
L
CLD
P27
H
WUP
L
BSYE
L
ACKE
L
CMDT
L
RELT
L
CLC
L
WREL
L
SIC
L
INTCSI0
Transfer Line
SCL
1
SDA0 (SDA1)
D7
2
3
4
5
6
7
8
9
D6 D5 D4 D3 D2 D1 D0 ACK
1
D7
2
3
4
D6 D5 D4 D3
Slave Device Operation
SIO0
Write SIO0
COI
ACKD
CMDD
RELD
L
CLD
P27
WUP
L
BSYE
H
ACKE
CMDT
H
L
RELT
L
CLC
L
WREL
L
SIC
H
INTCSI0
330
CSIE0
H
P25
L
PM25
L
PM27
L
FFH
5
SIO0
FFH
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
Figure 16-22.
Data Transmission from Master to Slave
(Both Master and Slave Selected 9-Clock Wait) (3 of 3)
(c) Stop Condition
Master Device Operation
SIO0
Write SIO0
Data
SIO0
Address
COI
ACKD
CMDD
RELD
CLD
P27
WUP
H
L
BSYE
L
ACKE
L
CMDT
RELT
CLC
WREL
L
SIC
L
INTCSI0
Transfer Line
SCL
1
SDA0
D7
2
3
4
5
6
7
8
9
1
2
3
4
A6 A5 A4 A3
D6 D5 D4 D3 D2 D1 D0 ACK
Slave Device Operation
SIO0
Write SIO0
FFH
SIO0
FFH
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
H
ACKE
CMDT
H
L
RELT
L
CLC
L
WREL
L
SIC
H
INTCSI0
CSIE0
P25
PM25
PM27
331
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
CHAPTER 16
Figure 16-23.
Data Transmission from Slave to Master
(Both Master and Slave Selected 9-Clock Wait) (1 of 3)
(a) Start Condition to Address
Master Device Operation
Write SIO0
SIO0
Address
1
3
SIO0
FFH
COI
ACKD
CMDD
RELD
L
CLD
P27
H
WUP
L
BSYE
ACKE
CMDT
RELT
L
CLC
WREL
L
SIC
L
INTCSI0
Transfer Line
SCL
2
4
5
6
7
8
9
A6 A5 A4 A3 A2 A1 A0 R ACK
SDA0
1
2
3
4
D7 D6 D5 D4 D3
Slave Device Operation
SIO0
Write SIO0
COI
ACKD
CMDD
RELD
L
CLD
P27
WUP
BSYE
ACKE
CMDT
L
RELT
L
CLC
L
WREL
L
SIC
H
INTCSI0
CSIE0
332
H
P25
L
PM25
L
PM27
L
5
Data
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
Figure 16-23.
Data Transmission from Slave to Master
(Both Master and Slave Selected 9-Clock Wait) (2 of 3)
(b) Data
Master Device Operation
SIO0
Write SIO0
FFH
SIO0
FFH
COI
ACKD
CMDD
RELD
L
CLD
P27
WUP
H
L
BSYE
H
ACKE
H
CMDT
L
RELT
L
CLC
L
WREL
L
SIC
L
INTCSI0
Transfer Line
SCL
1
2
3
4
5
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
SDA0
1
2
3
4
5
D7 D6 D5 D4 D3
Slave Device Operation
SIO0
Write SIO0
Data
SIO0
Data
COI
ACKD
CMDD
RELD
L
CLD
P27
WUP
L
BSYE
L
ACKE
L
CMDT
L
RELT
L
CLC
L
WREL
L
SIC
H
INTCSI0
CSIE0
H
P25
L
PM25
L
PM27
L
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CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
Figure 16-23.
Data Transmission from Slave to Master
(Both Master and Slave Selected 9-Clock Wait) (3 of 3)
(c) Stop Condition
Master Device Operation
SIO0
Write SIO0
FFH
SIO0
Address
COI
ACKD
CMDD
RELD
CLD
P27
WUP
H
L
BSYE
ACKE
CMDT
RELT
CLC
WREL
L
SIC
L
INTCSI0
Transfer Line
SCL
1
SDA0
2
D7
3
4
SIO0
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
L
RELT
L
CLC
L
WREL
SIC
H
INTCSI0
334
CSIE0
H
P25
L
PM25
L
PM27
L
6
7
8
9
D6 D5 D4 D3 D2 D1 D0 NAK
Slave Device Operation
Write SIO0
5
Data
1
2
3
4
A6 A5 A4 A3
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(9) Start of transfer
A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two
conditions have been satisfied:
• The serial interface channel 0 operation control bit (CSIE0) = 1.
• After an 8-bit serial transfer, the internal serial clock is stopped or SCL is low.
Cautions 1. Be sure to set CSIE0 to 1 before writing data in SIO0. Setting CSIE0 to 1 after writing data
in SIO0 does not initiate transfer operation.
2. When data is received, the N-ch open-drain output pin must go into a high-impedance
state. Therefore, set BSYE of the serial bus interface control register (SBIC) to 1, and write
FFH to SIO0.
However, do not write FFH to SIO0 before reception when the wake-up function is used
(when bit 5 (WUP) of the serial operating mode register 0 (CSIM0) is set). Even if FFH is
not written to SIO0, the N-ch open-drain output pin always goes into a high-impedance
state.
3. If data is written to SIO0 while the slave is in the wait state, that data is held. Transfer
is started when SCL is output after the wait state is cleared.
When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag
(CSIIF0) is set.
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CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.4.5 Cautions on use of I2C bus mode
(1) Start condition output (master)
The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change
the SCL pin to high in order to output a start condition signal. Set 1 in CLC of interrupt timing specify
register (SINT) to drive the SCL pin high.
After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.
If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is
set to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state).
Figure 16-24. Start Condition Output
SCL
SDA0 (SDA1)
CLC
CMDT
CLD
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CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(2) Slave wait release (slave transmission)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the
clock rises without the start transmission bit being output in the data line. Therefore, manipulate the P27
output latch through the program as shown in Figure 16-25 to transmit data correctly. At this time, control
the low-level width ("a" in Figure 16-25) of the first serial clock at the timing used for setting the P27 output
latch to 1 after execution of an SIO0 write instruction.
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is
completed), set 1 in the WREL flag of SINT and release the wait.
For these timings, see Figure 16-23.
Figure 16-25. Slave Wait Release (Transmission)
Master Device Operation
Writing
FFH
to SIO0
Software Operation
Setting Setting
ACKD CSIIF0
Hardware Operation
Serial Reception
Transfer Line
SCL
SDA0 (SDA1)
9
A0
R
a 1
ACK
D7
2
3
D6
D5
Slave Device Operation
P27
Write
Output Data
Latch 0 to SIO0
Software Operation
Hardware Operation
ACK Setting
Output CSIIF0
Wait
Release
P27
Output
Latch 1
Serial Transmission
337
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(3) Slave wait release (slave reception)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to
SIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannot
start operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0
(until the next instruction execution is started). Therefore, manipulate the P27 output latch through the
program as shown in Figure 16-26 to receive data correctly.
For these timings, see Figure 16-22.
Figure 16-26. Slave Wait Release (Reception)
Master Device Operation
Writing
Data
to SIO0
Software Operation
Setting Setting
ACKD CSIIF0
Hardware Operation
Serial Transmission
Transfer Line
SCL
SDA0 (SDA1)
9
A0
W
1
ACK
D7
2
3
D6
D5
Slave Device Operation
P27
Write
Output
FFH
Latch 0 to SIO0
Software Operation
Hardware Operation
ACK Setting
Output CSIIF0
Wait
Release
P27
Output
Latch 1
Serial Reception
(4) Reception completion of slave
During processing of reception completion by a slave device, confirm the statuses of bit 3 (CMDD) of the
serial bus interface control register (SBIC) and bit 6 (COI) of serial operating mode register 0 (CSIM0) (if
CMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount of
data is sent from the master device, the slave device cannot determine whether the start condition signal
or the data will be sent from the master. This may disable use of the wake-up function.
338
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.4.6 Restrictions when using I2C bus mode
The following restrictions are applied to the µPD780308Y Subseries.
• Restrictions when µPD780308Y Subseries is used as slave device in I2C bus mode
Subject:
µPD780306Y, 780308Y, 78P0308Y, IE-780308-R-EM
Description:
If the wake-up function is executed in the serial transfer status Note (by setting the
WUP flag (bit 5 of the serial operating mode register 0 (CSIM0)) to 1), the data
between the other slave devices and the master device is identified as an address.
If that data coincides with the slave address of the µPD780308Y Subseries, therefore,
the µPD780308Y participates in communication, destroying the communication data.
Note The serial transfer status is the status where the interrupt request flag (CSIIF0)
is set to 1 on completion of serial transfer after data has been written to the
serial I/O shift register 0 (SIO0).
Preventive measures: The above problem can be avoided by modifying the program.
Before executing the wake-up function, execute the program shown below that
releases the serial transfer status. When executing the wake-up function, do not
execute the instruction that writes data to SIO0. Even if this instruction is not
executed, data can be received while the wake-up function is executed.
The program shown below is to release the serial transfer status. To release the
serial transfer status, it is necessary to stop serial interface channel 0 once (by
clearing the CSIE0 flag (bit 7 of the serial operating mode register (CSIM0)) to 0).
If the serial interface channel 0 is stopped in the I2C bus mode, however, the SCL
pin outputs the high level and the SDA0 (SDA1) pin outputs the low level, affecting
communication of the I2C bus. To prevent the I2C bus from being influenced,
therefore, this program makes the SCL and SDA0 (SDA1) pins go into a highimpedance state.
In this example, SDA0 (/P25) is used as a serial data input/output pin. To use
SDA1 (/P26) as the serial data input/output pin, change P2.5 and PM2.5 in the
program below to P2.6 and PM2.6, respectively.
For the timing of each signal when this program is executed, refer to Figure 16-22.
339
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
• Example of program to release serial transfer status
SET1
P2.5;
<1>
SET1
PM2.5;
<2>
SET1
PM2.7;
<3>
CLR1
CSIE0;
<4>
SET1
CSIE0;
<5>
SET1
RELT;
<6>
CLR1
PM2.7;
<7>
CLR1
P2.5;
<8>
CLR1
PM2.5;
<9>
<1>
Prevents the SDA0 pin from outputting the low level when the I2C bus mode is restored by instruction
<5>. The SDA0 pin goes into a high-impedance state.
<2>
Sets the P25(/SDA0) pin in the input mode to prevent the SDA0 line from being affected when the port
mode is set by instruction <4>. The input mode is set when instruction <2> is executed.
<3>
Sets the P27(/SCL) pin in the input mode to prevent the SCL line from being affected when the port
mode is set by instruction <4>. The input mode is set when instruction <3> is executed.
<4>
Changes the mode from the I2C bus mode to the port mode.
<5>
Restores the I2C bus mode from the port mode.
<6>
Prevents instruction <8> from causing the SDA0 pin to output the low level.
<7>
Because the P27 pin must be set in the output mode in the I2C bus mode, sets the P27 pin in the
output mode.
<8>
Because the output latch of the P25 pin must be cleared to 0 in the I2C bus mode, clears the output
latch of the P25 pin to 0.
<9>
Because, in the I2C bus mode, the P25 pin must be set in the output mode, sets the P25 pin in the
output mode.
Remark RELT: bit 0 of serial bus interface control register (SBIC)
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SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
16.4.7 SCK0/SCL/P27 pin output manipulation
The SCK0/SCL/P27 pin enables static output by manipulating software in addition to normal serial clock output.
The value of serial clocks can be set by software (SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the
RELT and CMDT bits of serial bus interface control register (SBIC)).
The SCK0/SCL/P27 pin output should be manipulated as described below.
(1) In 3-wire serial I/O mode and 2-wire serial I/O mode
The SCK0/SCL/P27 pin output level is manipulated by the P27 output latch.
<1> Set serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation
is enabled). While serial transfer is suspended, SCK0 is set to 1.
<2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction.
Figure 16-27. SCK0/SCL/P27 Pin Configuration
Set by bit
manipulation instruction
SCK0/SCL/P27
To Internal
Circuit
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
P27 Output
Latch
SCK0 (1 when transfer stops)
From Serial Clock
Control Circuit
341
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (µPD780308Y Subseries)
(2) In I2C bus mode
The SCK0/SCL/P27 pin output level is manipulated by the CLC bit of interrupt timing specify register
(SINT).
<1> Set serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation
is enabled). Set 1 to the P27 output latch. While serial transfer is suspended, SCL is set to 0.
<2> Manipulate the content of the CLC bit of SINT by executing the bit manipulation instruction.
Figure 16-28. SCK0/SCL/P27 Pin Configuration
Set 1
SCK0/SCL/P27
To Internal
Circuit
P27 Output
Latch
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
Note
SCL Note
From Serial Clock
Control Circuit
The level of SCL signal follows the contents of logic circuit shown in Figure 16-29.
Figure 16-29. Logic Circuit of SCL Signal
CLC (Set by bit manipulation instruction)
SCL
Wait Request Signal
Serial Clock
(Low level when transfer stops)
Remarks 1. This figure shows the relationship of each signal, and does not show the internal circuit.
2. CLC : Bit 3 of interrupt timing specify register (SINT)
342
CHAPTER 17 SERIAL INTERFACE CHANNEL 2
17.1 Serial Interface Channel 2 Functions
Serial interface channel 2 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out to reduce power consumption.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is
possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud
rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
Serial interface channel 2 has two data I/O pins (RxD and TxD) which can be selected by software. Note that
only one data I/O pin can be used at one time.
Caution When it is not necessary to change the data I/O pin, using the RxD/SI2/P70 and TxD/SO2/
P71 is recommended. If only port 11 (RxD/P114 and TxD/P113) is used as data I/O pin, the
function of port 7 is limited.
(3) 3-wire serial I/O mode (MSB-first/LSB-first switchable)
In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines
(SI2, SO2).
In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer
processing speed.
Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection
to devices using either as the start bit.
The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which
incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K
Series, etc.
343
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
17.2 Serial Interface Channel 2 Configuration
Serial interface channel 2 consists of the following hardware.
Table 17-1. Serial Interface Channel 2 Configuration
Item
Configuration
Register
Transmit shift register (TXS)
Receive shift register (RXS)
Receive buffer register (RXB)
Control register
Serial operating mode register 2 (CSIM2)
Asynchronous serial interface mode register (ASIM)
Asynchronous serial interface status register (ASIS)
Baud rate generator control register (BRGC)
Serial interface pin select register (SIPS)
Port mode register 7 (PM7) Note
Note
Refer to Figure 6-10 P70 Block Diagram and Figure 6-11 P71 and P72
Block Diagram.
344
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
Figure 17-1. Serial Interface Channel 2 Block Diagram
Internal Bus
Serial interface
pin select
register
SIPS21SIPS20
Receive Buffer
Register
(RXB/SIO2)
PE
FE
Direction
Control Circuit
OVE
Selector
RxD/P114
SL ISRM SCK
Receive Shift
Register (RXS)
Selector
TxD/SO2/P71
PM71
TXE RXE PS1 PS0 CL
Transmit Shift
Register
(TXS/SIO2)
Direction
Control Circuit
RxD/SI2/P70
Asynchronous
Serial Interface
Mode Register
Asynchronous
Serial Interface
Status Register
TxD/P113
PM113
Reception
Control
Circuit
PM72
INTSER
INTSR/INTCSI2
Transmission
Control
Circuit
SCK Output
Control Circuit
INTST
ISRM
ASCK/
SCK2/P72
Baud Rate Generator
CSIE2
TXE
RXE
CSIE2
CSIM CSCK
22
4
4
Note
f xx to f xx/210
SCK
CSCK
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0
Serial Operating
Mode Register 2
Baud Rate Generator
Control Register
Internal Bus
Note
See Figure 17-2 for the baud rate generator configuration.
Remark
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
345
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
Figure 17-2. Baud Rate Generator Block Diagram
CSIE2
TXE
1/2
Selector
5-Bit
Counter
Selector
Transmit
Clock
Selector
Start Bit
Sampling Clock
Match
ASCK/SCK2/P72
Selector
4
MDL0 to MDL3
f xx to f xx/210
TPS0 to TPS3
SCK
CSCK
Receive
Clock
Selector
Decoder
4
Match
1/2
5-Bit
Counter
4
RXE
Start Bit Detection
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Baud Rate Generator
Control Register
Internal Bus
346
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(1) Transmit shift register (TXS)
This register is used to set the transmit data. The data written in TXS is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.
Writing data to TXS starts the transmit operation.
TXS is written to with an 8-bit memory manipulation instruction. It cannot be read.
TXS value is FFH after RESET input.
Caution TXS must not be written to during a transmit operation. TXS and the receive buffer register
(RXB) are allocated to the same address, and when a read is performed, the value of RXB
is read.
(2) Receive shift register (RXS)
This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is
received, the receive data is transferred to the receive buffer register (RXB).
RXS cannot be directly manipulated by a program.
(3) Receive buffer register (RXB)
This register holds receive data. Each time one byte of data is received, new receive data is transferred from
the receive shift register (RXS).
If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of
RXB is always set to 0.
RXB is read with an 8-bit memory manipulation instruction. It cannot be written to.
RXB value is FFH after RESET input.
Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write
is performed, the value is written to TXS.
(4) Transmission control circuit
This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data
written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial
interface mode register (ASIM).
(5) Reception control circuit
This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface
mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an
error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with
the error contents.
347
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
17.3 Serial Interface Channel 2 Control Registers
Serial interface channel 2 is controlled by the following five registers.
• Serial Operating Mode Register 2 (CSIM2)
• Asynchronous Serial Interface Mode Register (ASIM)
• Asynchronous Serial Interface Status Register (ASIS)
• Baud Rate Generator Control Register (BRGC)
• Serial Interface Pin Select Register (SIPS)
(1) Serial operating mode register 2 (CSIM2)
This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Figure 17-3. Serial Operating Mode Register 2 Format
Symbol
7
CSIM2 CSIE2
6
0
5
0
4
0
3
0
2
1
CSIM CSCK
22
Address
0
FF72H
After Reset
R/W
00H
Operation Control in 3-wire Serial I/O Mode
CSIE2
0
Operation stopped
1
Operation enabled
First Bit Specification
CSIM22
0
MSB
1
LSB
CSCK
0
Clock Selection in 3-wire Serial I/O Mode
0
Input clock from off-chip to SCK2 pin
1
Dedicated baud rate generator output
Cautions 1. Ensure that bit 0 and bit 3 to bit 6 are set to 0.
2. When UART mode is selected, CSIM2 should be set to 00H.
348
R/W
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(2) Asynchronous serial interface mode register (ASIM)
This register is set when serial interface channel 2 is used in the asynchronous serial interface mode.
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Figure 17-4. Asynchronous Serial Interface Mode Register Format
Symbol
ASIM
7
6
5
4
3
2
1
TXE
RXE
PS1
PS0
CL
SL
0
Address
ISRM SCK
TXE
After Reset
FF70H
00H
R/W
Transmit Operation Control
0
Transmit operation stopped
1
Transmit operation enabled
RXE
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
PS1
PS0
0
0
No Parity
0
1
0 parity always added in transmission
No parity test in reception (parity error not generated)
1
0
Odd parity
1
1
Even parity
Parity Bit Specification
CL
Character Length Specification
0
7 bits
1
8 bits
SL
Transmit Data Stop Bit Length Specification
0
1 bit
1
2 bits
ISRM
Control of Reception Completion Interrupt in Case of Error Generation
0
Reception completion interrupt generated in case of error generation
1
Reception completion interrupt not generated in case of error generation
SCK
Clock Selection in Asynchronous Serial Interface Mode
0
Input clock from off-chip to ASCK pin
1
Dedicated baud rate generator output
Note
R/W
Note
When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as
an input/output port.
Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
2. The serial transmit/receive operation must be stopped before changing the operating
mode.
349
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
Table 17-2. Serial Interface Channel 2 Operating Mode Settings
(1) Operation Stop Mode
ASIM
PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72 Start Shift P70/SI2 P71/SO2 P113/TxD P114/RxD P72/SCK2
Bit Clock /RxD Pin /TxD Pin Pin
/ASCK Pin
Pin
TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20
Functions Functions Functions Functions Functions
0
0
CSIM2
x
×
0
SIPS
×
×
× ×
Note 1
×
Note 1
×
Note 1
×
Note 1
×
Note 1
×
Note 1
×
Note 1
×
×
Note 1 Note1
×
Note 1
—
—
P70
Other than above
P71
P113
P114
P72
Setting prohibited
(2) 3-wire Serial I/O Mode
ASIM
PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72 Start Shift P70/SI2 P71/SO2 P113/TxD P114/RxD P72/SCK2
Bit Clock /RxD Pin /TxD Pin Pin
/ASCK Pin
Pin
TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20
Functions Functions Functions Functions Functions
0
0
CSIM2
0
1
1
0
1
SIPS
×
× ×
×
×
Note 1
×
Note 1
×
Note 1
×
Note 1
1
×
MSB External SI2
clock
1
0
1
Internal
clock
0
1
×
1
0
1
0
Note 2
Note 2
0
1
Other than above
Note 2
SO2
(CMOS
output)
LSB External SI2 Note 2 SO2
(CMOS
clock
output)
Internal
clock
350
SCK2 input
SCK2 input
SCK2 output
Setting prohibited
2. Can be used as P70 (CMOS input/output) when only transmitter is used.
×: don't care
P114
SCK2 output
Notes 1. Can be used freely as port function.
Remark
P113
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(3) Asynchronous Serial Interface Mode
ASIM
CSIM2
SIPS
PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72 Start Shift P70/SI2 P71/SO2 P113/TxD P114/RxD P72/SCK2
Bit Clock /RxD Pin /TxD Pin Pin
/ASCK Pin
Pin
TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20
Functions Functions Functions Functions Functions
1
0
0
0
0
0
0
0 ×
Note
×
Note
1
0
×
Note
×
Note
×
Note
×
Note
1
0
1
×
0
0
0
0
0
0
×
1
×
Note
×
Note
×
Note
×
Note
×
Note
×
1
1
0
0
0
0
0
×
1
1
0
×
Note
×
Note
×
Note
×
1
0
0
0
0
1
×
0
Note
×
Note
1
0
0
1
×
Note
×
0
1
0
0
0
0
1
1
×
×
Note
×
Note
×
Note
×
Note
1
1
1
1
×
0
0
0
0
1
1
1
×
0
1
1
0
1
1
×
Note
1
×
Other than above
Note
Note
×
1
×
1
×
0
Note
Note
1
×
1
×
0
Note
Note
1
×
1
×
0
Note
Note
1
×
1
Note
×
LSB External
clock
Note
Internal
clock
×
External
clock
Note
Internal
clock
×
External
clock
Note
Internal
clock
×
External
clock
Note
Internal
clock
×
External
clock
Note
Internal
clock
×
External
clock
×
×
Note
P70
TxD
(CMOS
output)
P113
P114
ASCK input
P72
RxD
ASCK input
P71
P72
TxD
(CMOS
output)
ASCK input
P72
P70
High
output
TxD
P114
ASCK input
P72
P70
(Input)
P71
P113
RxD
ASCK input
P72
P70
(Input)
High
output
TxD
Internal
clock
RxD
ASCK input
P72
Setting prohibited
Can be used freely as port function.
Remark
×:
don't care
PM××: Port mode register
P××:
Port output latch
351
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(3) Asynchronous serial interface status register (ASIS)
This is a register which displays the type of error when a receive error is generated in the asynchronous serial
interface mode.
ASIS is read with an 8-bit memory manipulation instruction.
In 3-wire serial I/O mode, the contents of the ASIS are undefined.
RESET input clears ASIS to 00H.
Figure 17-5. Asynchronous Serial Interface Status Register Format
Symbol
7
6
5
4
3
2
1
0
ASIS
0
0
0
0
0
PE
FE
OVE
Address
After Reset
FF71H
00H
R/W
R
Parity Error Flag
PE
0
Parity error not generated
1
Parity error generated (When transmit data parity does not match)
FE
Framing Error Flag
0
Framing error not generated
1
Framing error generated Note 1 (When stop bit is not detected)
Overrun Error Flag
OVE
0
Overrun error not generated
1
Overrun error generated Note 2
(When next receive operation is completed before data from receive buffer register is read)
Notes 1. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface
mode register (ASIM), only single stop bit detection is performed during reception.
2. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors
will continue to be generated until RXB is read.
352
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(4) Baud rate generator control register (BRGC)
This register sets the serial clock for serial interface channel 2.
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Figure 17-6. Baud Rate Generator Control Register Format (1/2)
Symbol
BRGC
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Address
FF73H
After Reset
00H
R/W
R/W
Selects Source Clock of 5-bit Counter
n
TPS3 TPS2 TPS1 TPS0
MCS = 1
MCS = 0
0
0
0
0
fX/210 (4.9 kHz)
fX/211 (2.4 kHz)
11
0
1
0
1
fX (5.0 MHz)
fX/2 (2.5 MHz)
1
0
1
1
0
fX/2 (2.5 MHz)
fX/2 (1.25 MHz)
2
0
1
1
1
fX/22 (1.25 MHz)
fX/23 (625 kHz)
3
1
0
0
0
fX/23 (625 kHz)
fX/24 (313 kHz)
4
1
0
0
1
fX/24 (313 kHz)
fX/25 (156 kHz)
5
1
0
1
0
fX/25 (156 kHz)
fX/26 (78.1 kHz)
6
1
0
1
1
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
7
1
1
0
0
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
8
1
1
0
1
fX/2 (19.5 kHz)
fX/2 (9.8 kHz)
9
1
1
1
0
fX/29 (9.8 kHz)
fX/210 (4.9 kHz)
10
Other than above
Remarks 1. fX
:
8
9
Setting prohibited
Main system clock oscillation frequency
2. MCS :
Oscillation mode select register bit 0
3. n
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
:
2
4. Figures in parentheses apply to operation with fX = 5.0 MHz
353
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
Figure 17-6. Baud Rate Generator Control Register Format (2/2)
MDL3 MDL2 MDL1 MDL0
Baud Rate Generator Input Clock Selection
k
0
0
0
0
fSCK/16
0
0
0
0
1
fSCK/17
1
0
0
1
0
fSCK/18
2
0
0
1
1
fSCK/19
3
0
1
0
0
fSCK/20
4
0
1
0
1
fSCK/21
5
0
1
1
0
fSCK/22
6
0
1
1
1
fSCK/23
7
1
0
0
0
fSCK/24
8
1
0
0
1
fSCK/25
9
1
0
1
0
fSCK/26
10
1
0
1
1
fSCK/27
11
1
1
0
0
fSCK/28
12
1
1
0
1
fSCK/29
13
1
1
1
0
fSCK/30
14
1
1
1
1
fSCK
Note
Note
—
Can only be used in 3-wire serial I/O mode.
Caution When a write is performed to BRGC during a communication operation, baud rate generator
output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remarks 1. fSCK:
2. k:
354
5-bit counter source clock
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal
scaled from the clock input from the ASCK pin.
(a) Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from
the main system clock is found from the following expression.
fXX
[Baud rate] =
2n
× (k + 16)
[Hz]
fX
: Main system clock oscillation frequency
fXX
: Main system clock frequency (fx or fx/2)
n
: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k
: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 17-3. Relationships between Main System Clock and Baud Rate
fx = 5.0 MHz
Baud
Rate
(bps)
MCS = 1
fx = 4.19 MHz
MCS = 0
MCS = 1
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value
75
–
MCS = 0
Error (%) BRGC Set Value Error (%)
00H
1.73
0BH
1.14
EBH
1.14
110
06H
0.88
E6H
0.88
03H
–2.01
E3H
–2.01
150
00H
1.73
E0H
1.73
EBH
1.14
DBH
1.14
300
E0H
1.73
D0H
1.73
DBH
1.14
CBH
1.14
600
D0H
1.73
C0H
1.73
CBH
1.14
BBH
1.14
1200
C0H
1.73
B0H
1.73
BBH
1.14
ABH
1.14
2400
B0H
1.73
A0H
1.73
ABH
1.14
9BH
1.14
4800
A0H
1.73
90H
1.73
9BH
1.14
8BH
1.14
9600
90H
1.73
80H
1.73
8BH
1.14
7BH
1.14
19200
80H
1.73
70H
1.73
7BH
1.14
6BH
1.14
31250
74H
0
64H
0
71H
–1.31
61H
–1.31
38400
70H
1.73
60H
1.73
6BH
1.14
5BH
1.14
76800
60H
1.73
50H
1.73
5BH
1.14
—
—
MCS: Oscillation mode selection register (CSMS) bit 0
355
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is obtained with the following expression.
fASCK
[Baud rate] =
2 × (k + 16)
[Hz]
fASCK
:
Frequency of clock input to ASCK pin
k
:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 17-4. Relationships between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
356
Baud Rate (bps)
ASCK Pin Input Frequency
75
2.4 kHz
110
3.52 kHz
150
4.8 kHz
300
9.6 kHz
600
19.2 kHz
1200
38.4 kHz
2400
76.8 kHz
4800
153.6 kHz
9600
307.2 kHz
19200
614.4 kHz
31250
1000.0 kHz
38400
1228.8 kHz
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(5) Serial interface pin select register (SIPS)
This register selects input/output pins when the serial interface channel 2 is used in the asynchronous serial
interface mode.
SIPS is set with a 1-bit or 8-bit memory manipulation instruction.
The contents of this register are reset to 00H at RESET.
To select input/output pins, the port mode register and the output latch of the port must be set. For details,
refer to Table 17-2 Serial Interface Channel 2 Operating Mode Settings.
Figure 17-7. Serial Interface Pin Select Register Format
Symbol
7
6
SIPS
0
0
5
4
SIPS21 SIPS20
3
2
1
0
Address
0
0
0
0
FF75H
SIPS21 SIPS20
After Reset
00H
R/W
R/W
Selects Input/Output Pin of Asynchronous Serial Interface
0
0
Input pin: RxD/SI2/P70
Output pin: TxD/SO2/P71
0
1
Input pin: RxD/P114
Output pin: TxD/SO2/P71
1
0
Input pin: RxD/SI2/P70
Output pin: TxD/P113
1
1
Input pin: RxD/P114
Output pin: TxD/P113
Cautions 1. Select input/output pins after stopping serial transmission/reception.
2. Port 11 has a falling edge detection function. Do not specify the pin of this port used
in a mode other than port mode to input the falling edge. For how to set to input the falling
edge, refer to Figure 6-21 Key Return Mode Register Format.
357
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
17.4 Serial Interface Channel 2 Operation
The operating mode of serial interface channel 2 has the following three types.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
17.4.1 Operation stop mode
In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK, P113/TxD, P114/RxD pins can
be used as normal input/output ports.
(1) Register setting
Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the
asynchronous serial interface mode register (ASIM).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Symbol
7
CSIM2 CSIE2
6
0
5
0
4
0
3
0
2
1
CSIM
CSCK
22
0
Address
0
FF72H
After Reset
Operation Control in 3-wire Serial I/O Mode
CSIE2
0
Operation stopped
1
Operation enabled
Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0.
358
00H
R/W
R/W
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Symbol
ASIM
7
6
5
4
3
2
TXE
RXE
PS1
PS0
CL
SL
1
0
ISRM SCK
Address
After Reset
FF70H
00H
R/W
R/W
Transmit Operation Control
TXE
0
Transmit operation stopped
1
Transmit operation enabled
Receive Operation Control
RXE
0
Receive operation stopped
1
Receive operation enabled
359
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
17.4.2 Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.
In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
Serial interface channel 2 has two data I/O pins (RxD and TxD) which can be selected by software. Note that only
one data I/O pin can be used at one time.
(1) Register setting
UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial
interface mode register (ASIM), the asynchronous serial interface status register (ASIS), the baud rate
generator control register (BRGC), and the serial interface pin select register (SIPS).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
When the UART mode is selected, 00H should be set in CSIM2.
Symbol
7
CSIM2 CSIE2
6
5
4
3
0
0
0
0
2
1
CSIM CSCK
22
Address
0
FF72H
0
Operation stopped
1
Operation enabled
00H
First Bit Specification
CSIM22
0
MSB
1
LSB
Clock Selection in 3-wire Serial I/O Mode
0
Input clock from off-chip to SCK2 pin
1
Dedicated baud rate generator output
Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0.
360
After Reset
Operation Control in 3-wire Serial I/O Mode
CSIE2
CSCK
0
R/W
R/W
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Symbol
ASIM
7
6
5
4
3
2
TXE
RXE
PS1
PS0
CL
SL
1
0
Address
ISRM SCK
TXE
FF70H
After Reset
00H
R/W
Transmit Operation Control
0
Transmit operation stopped
1
Transmit operation enabled
RXE
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
PS1
PS0
0
0
No Parity
0
1
0 parity always added in transmission
No parity test in reception (parity error not generated)
1
0
Odd parity
1
1
Even parity
Parity Bit Specification
CL
Character Length Specification
0
7 bits
1
8 bits
SL
Transmit Data Stop Bit Length Specification
0
1 bit
1
2 bits
ISRM
Control of Reception Completion Interrupt in Case of Error Generation
0
Reception completion interrupt generated in case of error generation
1
Reception completion interrupt not generated in case of error generation
Clock Selection in Asynchronous Serial InterfaceMode
SCK
0
Input clock from off-chip to ASCK pin
1
Dedicated baud rate generator output
Note
R/W
Note
When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used
as an input/output port.
Caution The serial transmit/receive operation must be stopped before changing the operating
mode.
361
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(c) Asynchronous serial interface status register (ASIS)
ASIS is set with an 8-bit memory manipulation instruction.
RESET input clears ASIS to 00H.
Symbol
7
6
5
4
3
2
1
0
ASIS
0
0
0
0
0
PE
FE
OVE
PE
Address
After Reset
FF71H
00H
R/W
R
Parity Error Flag
0
Parity error not generated
1
Parity error generated (When transmit data parity does not match)
Framing Error Flag
FE
0
Framing error not generated
1
Framing error generated Note 1
(When stop bit is not detected)
Overrun Error Flag
OVE
0
Overrun error not generated
1
Overrun error generated Note 2
(When next receive operation is completed before data from receive buffer register is read)
Notes 1. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial
interface mode register (ASIM), only single stop bit detection is performed during reception.
2. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun
errors will continue to be generated until RXB is read.
362
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(d) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Symbol
BRGC
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Address
After Reset
FF73H
00H
R/W
R/W
Selects Source Clock of 5-bit Counter
n
TPS3 TPS2 TPS1 TPS0
MCS = 1
MCS = 0
0
0
0
0
fX/210 (4.9 kHz)
fX/211 (2.4 kHz)
11
0
1
0
1
fX (5.0 MHz)
fX/2 (2.5 MHz)
1
0
1
1
0
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
2
0
1
1
1
fX/22 (1.25 MHz)
fX/23 (625 kHz)
3
1
0
0
0
fX/23 (625 kHz)
fX/24 (313 kHz)
4
1
0
0
1
fX/24 (313 kHz)
fX/25 (156 kHz)
5
1
0
1
0
fX/25 (156 kHz)
fX/26 (78.1 kHz)
6
1
0
1
1
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
7
1
1
0
0
fX/27 (39.1 kHz)
fX/2 (19.5 kHz)
8
1
1
0
1
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
9
1
1
1
0
fX/29 (9.8 kHz)
fX/210 (4.9 kHz)
10
Other than above
8
Setting prohibited
(continued)
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. n
: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
363
CHAPTER 17
MDL3 MDL2 MDL1 MDL0
SERIAL INTERFACE CHANNEL 2
Baud Rate Generator Input Clock Selection
k
0
0
0
0
fSCK/16
0
0
0
0
1
fSCK/17
1
0
0
1
0
fSCK/18
2
0
0
1
1
fSCK/19
3
0
1
0
0
fSCK/20
4
0
1
0
1
fSCK/21
5
0
1
1
0
fSCK/22
6
0
1
1
1
fSCK/23
7
1
0
0
0
fSCK/24
8
1
0
0
1
fSCK/25
9
1
0
1
0
fSCK/26
10
1
0
1
1
fSCK/27
11
1
1
0
0
fSCK/28
12
1
1
0
1
fSCK/29
13
1
1
1
0
fSCK/30
14
Caution When a write is performed to BRGC during a communication operation, baud rate
generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remark
364
fSCK:
5-bit counter source clock
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or
a signal scaled from the clock input from the ASCK pin.
(i)
Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated
from the main system clock is obtained with the following expression.
fXX
[Baud rate] =
2n × (k + 16)
[Hz]
fX
: Main system clock oscillation frequency
fXX
: Main system clock frequency (fx or fx/2)
n
: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k
: Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 17-5. Relationships between Main System Clock and Baud Rate
Baud
Rate
(bps)
fx = 5.0 MHz
MCS = 1
fx = 4.19 MHz
MCS = 0
MCS = 1
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value
75
—
MCS = 0
Error (%) BRGC Set Value Error (%)
00H
1.73
0BH
1.14
EBH
1.14
110
06H
0.88
E6H
0.88
03H
–2.01
E3H
–2.01
150
00H
1.73
E0H
1.73
EBH
1.14
DBH
1.14
300
E0H
1.73
D0H
1.73
DBH
1.14
CBH
1.14
600
D0H
1.73
C0H
1.73
CBH
1.14
BBH
1.14
1200
C0H
1.73
B0H
1.73
BBH
1.14
ABH
1.14
2400
B0H
1.73
A0H
1.73
ABH
1.14
9BH
1.14
4800
A0H
1.73
90H
1.73
9BH
1.14
8BH
1.14
9600
90H
1.73
80H
1.73
8BH
1.14
7BH
1.14
19200
80H
1.73
70H
1.73
7BH
1.14
6BH
1.14
31250
74H
0
64H
0
71H
–1.31
61H
–1.31
38400
70H
1.73
60H
1.73
6BH
1.14
5BH
1.14
76800
60H
1.73
50H
1.73
5BH
1.14
—
—
MCS: Oscillation mode select register (OSMS) bit 0
365
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is obtained with the following expression.
[Baud rate] =
fASCK
2 × (k + 16)
[Hz]
fASCK :
Frequency of clock input to ASCK pin
k
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
:
Table 17-6. Relationships between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
366
Baud Rate (bps)
ASCK Pin Input Frequency
75
2.4 kHz
110
3.52 kHz
150
4.8 kHz
300
9.6 kHz
600
19.2 kHz
1200
38.4 kHz
2400
76.8 kHz
4800
153.6 kHz
9600
307.2 kHz
19200
614.4 kHz
31250
1000.0 kHz
38400
1228.8 kHz
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(e) Serial interface pin select register (SIPS)
SIPS is set with a 1-bit or 8-bit memory manipulation instruction.
The contents of this register are reset to 00H at RESET.
To select input/output pins, the port mode register and the output latch of the port must be set. For details,
refer to Table 17-2 Serial Interface Channel 2 Operating Mode Settings.
Symbol
7
6
SIPS
0
0
5
4
SIPS21 SIPS20
SIPS21 SIPS20
3
2
1
0
Address
0
0
0
0
FF75H
After Reset
00H
R/W
R/W
Selects Input/Output Pin of Asynchronous Serial Interface
0
0
Input pin: RxD/SI2/P70
Output pin: TxD/SO2/P71
0
1
Input pin: RxD/P114
Output pin: TxD/SO2/P71
1
0
Input pin: RxD/SI2/P70
Output pin: TxD/P113
1
1
Input pin: RxD/P114
Output pin: TxD/P113
Cautions 1. Select input/output pins after stopping serial transmission/reception.
2. Port 11 has a function to detect the falling edge. To use the TxD/P113 or RxD/P114 pin
as the input/output pin of the serial interface channel 2, the falling edge detection function
must be disabled by using the key return mode register (KRM). For details, refer to Figure
6-21 Key Return Mode Register Format.
367
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(2) Communication operation
(a) Data format
Figure 17-8 shows the format of the transmit/receive data.
Figure 17-8. Asynchronous Serial Interface Transmit/Receive Data Format
One Data Frame
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop Bit
Character Bit
One data frame consists of the following bits:
• Start bits ..................
1 bit
• Character bits .........
7 bits/8 bits
• Parity bits ................
Even parity/odd parity/0 parity/no parity
• Stop bit(s) ...............
1 bit/2 bits
The specification of character bit length, parity selection, and specification of stop bit length for each data
frame is carried out with asynchronous serial interface mode register (ASIM).
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always "0".
The serial transfer rate is selected by means of the ASIM and the baud rate generator control register
(BRGC).
If a serial data receive error is generated, the receive error contents can be determined by reading the
status of the asynchronous serial interface status register (ASIS).
368
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i)
Even parity
• At transmission
Control is executed so that the number of bits with a value of "1" contained in the transmit data including
parity bit is an even number. The parity bit value should be as follows.
The number of bits with a value of "1" is an odd number in transmit data : 1
The number of bits with a value of "1" is an even number in transmit data : 0
• At reception
The number of bits with a value of "1" contained in the receive data including parity bit are counted,
and if this is an odd number, a parity error is generated.
(ii) Odd parity
• At transmission
Conversely to the situation with even parity, control is executed so that the number of bits with a value
of "1" contained in the transmit data including parity bit is an odd number. The parity bit value should
be as follows.
The number of bits with a value of "1" is an odd number in transmit data : 0
The number of bits with a value of "1" is an even number in transmit data : 1
• At reception
The number of bits with a value of "1" contained in the receive data including parity bit are counted,
and if this is an even number, a parity error is generated.
(iii) 0 Parity
When transmitting, the parity bit is set to "0" irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective
of whether the parity bit is set to "0" or "1".
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is no
parity bit. Since there is no parity bit, a parity error is not generated.
369
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(c) Transmission
A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit,
parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in the TXS is shifted out, and when the TXS is empty, a
transmit completion interrupt request (INTST) is generated.
Figure 17-9. Asynchronous Serial Interface Transmit Completion Interrupt Request Timing
(a) Stop bit length: 1
STOP
TxD (Output)
D0
D1
D2
D6
D7
Parity
D7
Parity
START
INTST
(b) Stop bit length: 2
TxD (Output)
D0
D1
D2
D6
STOP
START
INTST
Caution Rewriting of the asynchronous serial interface mode register (ASIM) should not be
performed during a transmit operation. If rewriting of the ASIM register is performed
during transmission, subsequent transmit operations may not be possible (the normal
state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmit completion interrupt request (INTST) or the interrupt request flag (STIF) set by
the INTST.
370
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(d) Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), a receive
operation is enabled and sampling of the RxD pin input is performed.
RxD pin input sampling is performed using the serial clock specified by ASIM.
When the RxD pin goes low, the 5-bit counter of the baud rate generator (refer to Figure 17-2) starts
counting. When the time half the set baud rate has elapsed, a signal to start data sampling is output.
If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start
bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. When character
data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to the receive
buffer register (RXB), and a receive completion interrupt request (INTSR) is generated.
Even if an error occurs, the receive data responsible for the error is transferred to RXB. If bit 1 (ISRM)
of ASIM is cleared to 0 on occurrence of the error, INTSR is generated.
If the ISRM bit is set to 1, INTSR is not generated.
If the RXE bit is reset (to 0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB and asynchronous serial interface status register (ASIS) are not changed,
and INTSR and INTSER are not generated.
Figure 17-10. Asynchronous Serial Interface Receive Completion Interrupt Request Timing
STOP
RxD (Input)
D0
D1
D2
D6
D7
Parity
START
INTSR
Caution The receive buffer register (RXB) must be read even if a receive error is generated. If
RXB is not read, an overrun error will be generated when the next data is received, and
the receive error state will continue indefinitely.
371
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(e) Receive errors
Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.
The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and
a receive error interrupt (INTSER) is generated. The receive error interrupt occurs earlier than the receive
completion interrupt (INTSR). Receive error causes are shown in Table 17-7.
It is possible to determine what kind of error was generated during reception by reading the contents of
the ASIS in the receive error interrupt servicing (INTSER) (see Figures 17-10 and 17-11).
The contents of ASIS are reset (to 0) by reading the receive buffer register (RXB) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 17-7. Receive Error Causes
Receive Errors
Cause
Parity error
Transmission-time parity specification and reception data parity do not match
Framing error
Stop bit not detected
Overrun error
Reception of next data is completed before data is read from receive register buffer
Figure 17-11. Receive Error Timing
RxD (Input)
D0
D1
D2
D6
D7
Parity
STOP
START
INTSR
Note
INTSER
(When framing/overrun
error occurs)
INTSER
(When parity error occurs)
Note
INTSR does not occur if a receive error occurs while bit 1 (ISRM) of the asynchronous serial
interface mode register (ASIM) is set to 1.
Cautions 1. The contents of the asynchronous serial interface status register (ASIS) reset (to 0)
by reading the receive buffer register (RXB) or receiving the next data. To ascertain
the error contents, ASIS must be read before reading RXB.
2. The receive buffer register (RXB) must be read even if a receive error is generated.
If RXB is not read, an overrun error will be generated when the next data is received,
and the receive error state will continue indefinitely.
372
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(3) UART mode cautions
(a) If the transmission under execution has been stopped by clearing bit 7 of the asynchronous serial interface
mode register (ASIM) to 0, be sure to set the transmit shift register (TXS) to FFH and TXE to 1 before
executing the next transmission.
(b) If the reception under execution has been stopped by clearing bit 6 (REX) of the asynchronous serial
interface mode register (ASIM) to 0, the status of the receive buffer register (RXB) and whether the receive
completion interrupt request (INTSR) occurs differ depending on the reception stop timing.
Figure 17-12. Status of Receive Buffer Register (RXB) and Generation of
Interrupt Request (INTSR) When Reception is Stopped
RxD Pin
Parity
RXB
INTSR
<1>
<3>
<2>
When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.
373
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
17.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate
a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc.
Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
In the 3-wire serial I/O mode, the P113/TxD and P114/RxD pins can be used as ordinary I/O port pins.
(1) Register setting
3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), and the baud rate generator control register (BRGC).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Symbol
7
CSIM2 CSIE2
6
5
4
3
0
0
0
0
2
1
CSIM CSCK
22
Address
0
FF72H
0
Operation stopped
1
Operation enabled
00H
First Bit Specification
CSIM22
0
MSB
1
LSB
Clock Selection in 3-wire Serial I/O Mode
0
Input clock from off-chip to SCK2 pin
1
Dedicated baud rate generator output
Caution Ensure that bit 0 and bit 3 to bit 6 are set to 0.
374
After Reset
Operation Control in 3-wire Serial I/O Mode
CSIE2
CSCK
0
R/W
R/W
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
Symbol
ASIM
7
6
5
4
3
2
TXE
RXE
PS1
PS0
CL
SL
1
0
Address
ISRM SCK
TXE
FF70H
00H
Transmit operation stopped
1
Transmit operation enabled
RXE
R/W
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
PS1
PS0
0
0
No Parity
0
1
0 parity always added in transmission
No parity test in reception (parity error not generated)
1
0
Odd parity
1
1
Even parity
Parity Bit Specification
CL
Character Length Specification
0
7 bits
1
8 bits
SL
Transmit Data Stop Bit Length Specification
0
1 bit
1
2 bits
Control of Receive Completion Interrupt in Case of Error Generation
0
Receive completion interrupt generated in case of error generation
1
Receive completion interrupt not generated in case of error generation
SCK
R/W
Transmit Operation Control
0
ISRM
After Reset
Clock Selection in Asynchronous Serial Interface Mode
0
Input clock from off-chip to ASCK pin
1
Dedicated baud rate generator output
375
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(c) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Symbol
BRGC
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Address
After Reset
FF73H
00H
R/W
R/W
Selects Source Clock of 5-bit Counter
n
TPS3 TPS2 TPS1 TPS0
MCS = 1
MCS = 0
0
0
0
0
fX/210 (4.9 kHz)
fX/211 (2.4 kHz)
11
0
1
0
1
fX (5.0 MHz)
fX/2 (2.5 MHz)
1
0
1
1
0
fX/2 (2.5 MHz)
fX/2 (1.25 MHz)
2
0
1
1
1
fX/22 (1.25 MHz)
fX/23 (625 kHz)
3
1
0
0
0
fX/23 (625 kHz)
fX/24 (313 kHz)
4
1
0
0
1
fX/2 (313 kHz)
fX/2 (156 kHz)
5
1
0
1
0
fX/25 (156 kHz)
fX/26 (78.1 kHz)
6
1
0
1
1
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
7
1
1
0
0
fX/2 (39.1 kHz)
fX/2 (19.5 kHz)
8
1
1
0
1
fX/28 (19.5 kHz)
fX/29 (9.8 kHz)
9
1
1
1
0
fX/29 (9.8 kHz)
fX/210 (4.9 kHz)
10
Other than above
4
7
2
5
8
Setting prohibited
(continued)
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. n
: Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
4. Figures in parentheses apply to operation with fX = 5.0 MHz.
376
CHAPTER 17
MDL3 MDL2 MDL1 MDL0
SERIAL INTERFACE CHANNEL 2
Baud Rate Generator Input Clock Selection
k
0
0
0
0
fSCK/16
0
0
0
0
1
fSCK/17
1
0
0
1
0
fSCK/18
2
0
0
1
1
fSCK/19
3
0
1
0
0
fSCK/20
4
0
1
0
1
fSCK/21
5
0
1
1
0
fSCK/22
6
0
1
1
1
fSCK/23
7
1
0
0
0
fSCK/24
8
1
0
0
1
fSCK/25
9
1
0
1
0
fSCK/26
10
1
0
1
1
fSCK/27
11
1
1
0
0
fSCK/28
12
1
1
0
1
fSCK/29
13
1
1
1
0
fSCK/30
14
1
1
1
1
fSCK
—
Caution When a write is performed to BRGC during a communication operation, baud rate
generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remark
fSCK: 5-bit counter source clock
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
377
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below.
BRGC Setting is not required if an external serial clock is used.
(i) When the baud rate generator is not used:
Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
The serial clock frequency is half the source clock frequency of the 5-bit counter.
(ii) When the baud rate generator is used:
Select a serial clock frequency with MDL0 to MDL3 and TPS0 to TPS3. Be sure then to set MDL0 to MDL3
to a value other than 1,1,1,1.
The serial clock frequency is calculated by the following formula:
fXX
Serial clock frequency=
[Hz]
2n × (k + 16)
378
fX :
Main system clock oscillation frequency
fXX :
Main system clock frequency (fX or fX/2)
n
:
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k
:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/
received bit by bit in synchronization with the serial clock.
Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in
synchronization with the fall of the serial clock (SCK2). Then transmit data is held in the SO2 latch and output
from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2)
on the rise of SCK2.
At the end of an 8-bit transfer, the operation of the transmit shift register (TXS/SIO2) or receive shift register
(RXS) stops automatically, and the interrupt request flag (SRIF) is set.
Figure 17-13. 3-Wire Serial I/O Mode Timing
SCK2
SI2
SO2
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SRIF
End of Transfer
Transfer Start at the Falling Edge of SCK2
379
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
(3) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 17-14 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown
in the figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of the serial operating mode register
2 (CSIM2).
Figure 17-14. Circuit of Switching in Transfer Bit Order
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO2 Latch
SI2
Transmit Shift Register (TXS/SIO2)
D
Q
SO2
SCK2
Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to the transmit shift register (TXS/SIO2) when the following
two conditions are satisfied.
• Serial interface channel 2 operation control bit (CSIE2) = 1
• Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer.
Caution If CSIE2 is set to "1" after data write to TXS/SIO2, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is
set.
380
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
17.4.4 Limitations of UART mode
In the UART mode, the receive completion interrupt (INTSR) occurs a certain time after the receive error interrupt
(INTSER) occurred and cleared. Consequently, the following phenomenon may take place.
• Description
If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the receive completion
interrupt (INTSR) does not occur when a receive error occurs. If the receive buffer register (RXB) is read at
certain timing (a in Figure 17-15) while the receive error interrupt (INTSER) is serviced, the internal error flag
is cleared to 0. Therefore, it is judged that the receive error does not occur, and INTSR, which must not occur,
occurs. This is illustrated in Figure 17-15.
Figure 17-15. Receive Completion Interrupt Generation Timing (when ISRM = 1)
fSCK
INTSER (When Framing/
Overrun Error Occurs)
a
Error Flag
(Internal Flag)
INTSR
Cleared when
RXB is read
Interrupt Processing
Routine of CPU
RXB is read
Remark
It is judged that receive error does not
occur, and INTSR occurs.
ISRM: Bit 1 of asynchronous serial interface mode register (ASIM)
fSCK:
Source clock of 5-bit counter of baud rate generator
RXB:
Receive buffer register
To prevent this phenomenon, take the following measures:
• Preventive measures
• In case of framing error or overrun error
Disable reading the receive buffer register (RXB) for a certain time (T2 in Figure 17-16) after the receive error
interrupt (INTSER) has occurred.
• In case of parity error
Disable reading the receive buffer register (RXB) for a certain time (T1 + T2 in Figure 17-16) after the receive
error interrupt (INTSER) has occurred.
381
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
Figure 17-16. Disabling Reading Receive Buffer Register
RxD (Input)
D0
D1
D2
D6
D7
Parity
STOP
START
INTSR
INTSER
(When framing/overrun
error occurs)
INTSER
(When parity error occurs)
T1
T2
T1: Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate)
T2: Time of two clocks of source clock (fSCK) of 5-bit counter selected by BRGC
• Example of preventive measures
Here is an example of preventive measures.
[Condition]
fX = 5.0 MHz
Processor clock control register (PCC) = 00H
Oscillation mode select register (OSMS) = 01H
Baud rate generator control register (BRGC) = B0H (baud rate: 2400 bps)
TCY = 0.4 µs (tCY = 0.2 µs)
1
T1 =
= 416.7 µs
2400
T2 = 12.8 × 2 = 25.6 µs
T1 + T2
= 2212 (clock)
tCY
382
CHAPTER 17
SERIAL INTERFACE CHANNEL 2
[Example]
Main Processing
UART Receive Error
Interrupt (INTSER) Processing
EI
INTSER occurs
Seven CPU Clocks (Time from
generation of interrupt request to
processing)
Instructions of
4288 CPU clocks
(MIN.) are
necessary.
MOV A,RXB
RETI
383
[MEMO]
384
CHAPTER 18 SERIAL INTERFACE CHANNEL 3
18.1 Serial Interface Channel 3 Functions
Serial interface channel 3 operates in the following two modes:
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial interface channel 3 does not perform serial transfer, to reduce the power
consumption.
(2) 3-wire serial I/O mode (MSB/LSB first selectable)
In this mode, 8-bit data are transferred by using three lines: serial clock (SCK3), serial output (SO3), and serial
input (SI3).
Because transmission and reception can be carried out simultaneously in this mode, the data transfer time
can be shortened.
Because whether the 8-bit data to be transferred is transferred starting from its MSB or LSB can be selected
in this mode, serial interface channel 3 can be connected to any device.
The 3-wire serial I/O mode is effective for connecting peripheral I/Os and display controllers that have the
conventional clocked serial interface, such as the 75X/XL Series, 78K Series, and 17K Series.
18.2 Serial Interface Channel 3 Configuration
Serial interface channel 3 consists of the following hardware:
Table 18-1. Configuration of Serial Interface Channel 3
Item
Configuration
Register
Serial I/O shift register 3 (SIO3)
Control register
Control register
Timer clock select register 4 (TCL4)
Serial operating mode register 3 (CSIM3)
Port mode register 11 (PM11) Note
Note
Refer to Figure 6-15 P110, P114 to P117 Block Diagram and Figure 616 P111 Block Diagram.
385
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
Figure 18-1. Serial Interface Channel 3 Block Diagram
Internal Bus
Serial Operating
Mode Register 3
DIR
SIO3 write
SI3/P110
Serial I/O Shift
Register (SIO3)
CSIE3 DIR3 CSIM31 CSIM30
PM111
SO3/P111
P111 Output Latch
Serial Clock
Counter
INTCSI3
Clear
Selector
Selector
SCK3/P112
Selector
f xx/2 to f xx/28
R
Q
4
S
PM112
P112 Output Latch
TCL47 TCL46 TCL45 TCL44
Timer Clock
Select
Register 4
Internal Bus
Remark
386
fXX = fX/2 (MCS = 0), fXX = fX (MCS = 1)
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
(1) Serial I/O shift register 3 (SIO3)
This is an 8-bit register that performs parallel-to-serial conversion and serial transmission/reception (shift
operation) in synchronization with the serial clock.
SIO3 is set with an 8-bit memory manipulation instruction.
Serial operation is started by writing data to SIO3 when bit 7 (CSIE3) of the serial operating mode register
3 (CSIM3) is 1.
During transmission, the data written to SIO3 is output to the serial output line (SO3). During reception, data
is read from the serial input line (SI3) to SIO3.
RESET input makes SIO3 undefined.
(2) Serial clock counter
This counter counts the serial clock output or input during transmission or reception to check whether 8-bit
data has been transmitted or received.
18.3 Serial Interface Channel 3 Control Registers
Serial interface channel 3 is controlled by the following two registers:
• Timer clock select register 4 (TCL4)
• Serial operating mode register 3 (CSIM3)
(1) Timer clock select register 4 (TCL4)
This register sets the serial clock of serial interface channel 3.
TCL4 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL4 to 88H.
387
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
Figure 18-2. Timer Clock Select Register 4 Format
Symbol
7
6
5
4
TCL4 TCL47 TCL46 TCL45 TCL44
3
2
1
0
Address
After Reset
R/W
1
0
0
0
FF44H
88H
R/W
Selects Serial Clock of Serial Interface Channel 3
TCL47 TCL466 TCL45 TCL44
MCS = 1
0
1
1
0
Setting prohibited
fX/2 (1.25 MHz)
2
fX/2 (625 kHz)
3
fX/2 (313 kHz)
4
fX/2 (156 kHz)
5
fX/2 (78.1 kHz)
6
fX/2 (39.1 kHz)
7
fX/2 (19.5 kHz)
8
fX/2 (9.8 kHz)
0
1
1
1
fX/2 (1.25 MHz)
1
0
0
0
fX/2 (625 kHz)
1
0
0
1
fX/2 (313 kHz)
1
0
1
0
fX/2 (156 kHz)
1
0
1
1
fX/2 (78.1 kHz)
1
1
0
0
fX/2 (39.1 kHz)
1
1
0
1
fX/2 (19.5 kHz)
Other than above
MCS = 0
2
3
4
5
6
7
8
9
Setting prohibited
Cautions 1. Set bit 0 to bit 2 to 0, and bit 3 to 1.
2. When rewriting TCL4 to other data, stop the serial transfer operation beforehand.
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Figures in parentheses apply to operation with fX = 5.0 MHz.
388
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
(2) Serial operating mode register 3 (CSIM3)
This register sets the serial clock of serial interface channel 3, and enables or disables the operation of the
interface channel.
CSIM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM3 to 00H.
Figure 18-3. Serial Operating Mode Register 3 Format
Symbol
7
6
5
CSIM3 CSIE3 DIR3
Note 1
0
4
3
2
0
0
0
CSIM
CSIE3
PM110 P110 PM111 P111 PM112 P112
31
1
0
CSIM31 CSIM30
×
×
×
×
0
×
×
1
×
1
×
0
0
0
1
0
MSB
1
LSB
R/W
00H
R/W
P110
P111
P112
(CMOS I/O)
(CMOS I/O)
(CMOS I/O)
SCK3 (Input)
Count
operation
Note 3
SI3
(Input)
SO3
(CMOS output)
SCK3
(CMOS output)
1
SI3/P110 Pin Functions
First Bit
DIR3
FF6CH
Clear
Stops
operation
Enables
operation
Note 2 Note 2
1
After Reset
Controls Operation Controls Operation
SI3/P110
SO3/P111
SCK3/P112
of Serial Interface
of Serial Clock
Pin
Functions
Pin
Functions
Pin
Functions
Channel 3
Counter
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
×
0
Address
SI3
Note 3
(input)
SO3/P111 Pin Functions
SO3 (CMOS output)
Selects Clock of Serial Interface Channel 3
CSIM31 CSIM30
0
×
Input Clock to SCK3 pin from off-chip
1
1
Clock specified by bits 0 through 3 of timer clock select register 4 (TCL4)
Other than above
Setting prohibited
Notes 1. Be sure to clear bit 5 to 0.
2. These pins can be used freely as port pins.
3. This pin can be used as P110 (CMOS I/O) when only transmitting data.
Caution Port 11 has a function to detect the falling edge. To use the SI3/P110, SO3/P111, and SCK3/
P112 pins as the input/output pins of the serial interface channel 3, the falling edge detection
function must be disabled by using the key return mode register (KRM). For details, refer
to Figure 6-21 Key Return Mode Register Format.
Remark
×:
don’t care
PM××: Port mode register
P××:
Port output latch
389
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
18.4 Serial Interface Channel 3 Operation
The operating mode of serial interface channel 3 has the following two types:
• Operation stop mode
• 3-wire serial I/O mode
18.4.1 Operation stop mode
In the operation stop mode, serial transfer is not perform, and therefore current consumption can be reduced.
In addition, the serial I/O shift register 3 (SIO3) does not perform the shift operation, and therefore, this register
can be used as an ordinary 8-bit register.
In the operation stop mode, the P110/SI3, P111/SO3, and P112/SCK3 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode settings are performed using serial operating mode register 3 (CSIM3).
CSIM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM3 to 00H.
Symbol
7
6
5
CSIM3 CSIE3 DIR3
Note 1
0
4
3
2
0
0
0
CSIM
CSIE3
PM110 P110 PM111 P111 PM112 P112
31
1
×
×
×
×
×
0
×
×
1
×
1
×
0
0
0
1
FF6CH
After Reset
00H
R/W
R/W
Controls Operation Controls Operation
SI3/P110
SO3/P111
SCK3/P112
of Serial Interface
of Serial Clock
Pin
Functions
Pin
Functions
Pin
Functions
Channel 3
Counter
Stops
operation
Clear
P110
(CMOS I/O)
P111
(CMOS I/O)
P112
(CMOS I/O)
SCK3 (Input)
Enables
operation
Note 3 Note 3
1
Address
CSIM31 CSIM30
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
0
0
Count
operation
Note 3
SI3
(Input)
SO3
(CMOS output)
1
SCK3
(CMOS output)
Notes 1. Be sure to clear bit 5 to 0.
2. These pins can be used freely as port pins.
3. This pin can be used as P110 (CMOS I/O) when only transmitting data.
Caution Port 11 has a function to detect the falling edge. To use the SI3/P110, SO3/P111, and SCK3/
P112 pins as the input/output pins of the serial interface channel 3, the falling edge detection
function must be disabled by using the key return mode register (KRM). For details, refer
to Figure 6-21 Key Return Mode Register Format.
Remark
×:
don’t care
PM××: Port mode register
P××:
390
Port output latch
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
18.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate
a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, and 17K Series, etc.
In this mode, communication is performed by using three lines: serial clock (SCK3), serial output (SO3), and serial
input (SI3).
(1) Register setting
The 3-wire serial I/O mode is set by using the serial operating mode register 3 (CSIM3).
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM3 to 00H.
Symbol
7
6
5
CSIM3 CSIE3 DIR3
Note 1
0
4
3
2
0
0
0
CSIM
CSIE3
PM110 P110 PM111 P111 PM112 P112
31
1
0
CSIM31 CSIM30
×
×
×
×
0
×
×
1
×
1
×
0
0
0
1
0
MSB
1
LSB
R/W
00H
R/W
P110
(CMOS I/O)
P111
(CMOS I/O)
Count
operation
Note 3
SI3
(Input)
SO3
(CMOS output)
SCK3
(CMOS output)
SI3/P110 Pin Functions
SI3
Note 3
(Input)
SO3/P111 Pin Functions
SO3 (CMOS output)
Selects Clock of Serial Interface Channel 3
CSIM31 CSIM30
0
×
Input Clock to SCK3 pin from off-chip
1
1
Clock specified by bits 0 through 3 of timer clock select register 4 (TCL4)
Other than above
P112
(CMOS I/O)
SCK3 (Input)
1
First Bit
DIR3
FF6CH
Clear
Stops
operation
Enables
operation
Note 3 Note 3
1
After Reset
Controls Operation Controls Operation
SI3/P110
SO3/P111
SCK3/P112
of Serial Interface
of Serial Clock
Pin
Functions
Pin
Functions
Pin
Functions
Channel 3
Counter
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
×
0
Address
Setting prohibited
Notes 1. Be sure to clear bit 5 to 0.
2. These pins can be used freely as port pins.
3. This pin can be used as P110 (CMOS I/O) when only transmitting data.
Caution Port 11 has a function to detect the falling edge. To use the SI3/P110, SO3/P111, and SCK3/
P112 pins as the input/output pins of the serial interface channel 3, the falling edge detection
function must be disabled by using the key return mode register (KRM). For details, refer
to Figure 6-21 Key Return Mode Register Format.
Remark
×:
don’t care
PM××: Port mode register
P××:
Port output latch
391
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted or
received by bit in synchronization with the serial clock.
The serial I/O shift register 3 (SIO3) performs its shift operation in synchronization with the falling of the serial
clock (SCK3). The transmit data is held in the SO3 latch, and output from the SO3 pin. Also, receive data
input to the SI3 pin is latched to SIO3 at the rising edge of SCK3.
At the end of an 8-bit transfer, the operation of the SIO3 stops automatically, and the interrupt request flag
(CSIIF3) is set.
Figure 18-4. 3-Wire Serial I/O Mode Timing
SCK3
1
SI3
SO3
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Writing to SIO3
CSIIF3
End of Transfer
Transfer Start at the Falling Edge of SCK3
Caution Do not set 0 to CSIE3 during serial transfer; otherwise, an undefined value will be output.
392
CHAPTER 18
SERIAL INTERFACE CHANNEL 3
(3) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 18-5 shows the configuration of the serial I/O shift register 3 (SIO3) and internal bus. As shown in the
figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM32) of the serial operating mode register
3 (CSIM3).
Figure 18-5. Circuit of Switching in Transfer Bit Order
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO3 Latch
SI3
Serial I/O Shift Register 3 (SIO3)
D
Q
SO3
SCK3
Start bit switching is realized by switching the bit order for data write to SIO3. The SIO3 shift order remains
unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 3 (SIO3) when the following two
conditions are satisfied.
• Serial interface channel 3 operation control bit (CSIE3) = 1
• Internal serial clock is stopped or SCK3 is a high level after 8-bit serial transfer.
Caution If CSIE3 is set to "1" after data write to SIO3, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIE3)
is set.
393
[MEMO]
394
CHAPTER 19 LCD CONTROLLER/DRIVER
19.1 LCD Controller/Driver Functions
The functions of the LCD controller/driver incorporated in the µPD780308, 780308Y Subseries are shown below.
(1) Automatic output of segment signals and common signals is possible by automatic reading of the display
data memory.
(2) Any of five display modes can be selected.
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(3) Any of four frame frequencies can be selected in each display mode.
(4) Maximum of 40 segment signal outputs (S0 to S39); 4 common signal outputs (COM0 to COM3).
Sixteen of the segment signal outputs can be switched to input/output ports in units of 2 (P80/S39 to P87/
S32, P90/S31 to P97/S24).
(5) In mask ROM versions, split resistors for LCD drive voltage generation can be incorporated by mask option.
(6) Operation on the subsystem clock is also possible.
The maximum number of displayable pixels in each display mode is shown in Table 19-1.
Table 19-1. Maximum Number of Display Pixels
Bias Method
Time Division
Common Signals Used
Maximum Number of Pixels
Note
—
Static
COM0 (COM1, 2, 3)
40 (40 segments × 1 common)
1
1/2
2
COM0, COM1
80 (40 segments × 2 commons)
2
3
COM0 to COM2
120 (40 segments × 3 commons)
3
COM0 to COM3
160 (40 segments × 4 commons)
4
1/3
3
4
Notes 1. 5 digits on
type LCD panel with 8 segments/digit.
2. 10 digits on
type LCD panel with 4 segments/digit.
3. 13 digits on
type LCD panel with 3 segments/digit.
4. 20 digits on
type LCD panel with 2 segments/digit.
395
CHAPTER 19
LCD CONTROLLER/DRIVER
19.2 LCD Controller/Driver Configuration
The LCD controller/driver is composed of the following hardware.
Table 19-2. LCD Controller/Driver Configuration
Item
Configuration
Display outputs
Control registers
Segment signals
: 40
Dedicated segment signals: 24
Segment signal/input/output port dual function: 16
Common signals
:4
(COM0 to COM3)
LCD display mode register (LCDM)
LCD display control register (LCDC)
Figure 19-1. LCD Controller/Driver Block Diagram
Internal Bus
Display Data Memory
FA7FH
76543210
LCD Display Mode Register
FA68H
FA67H
76543210 76543210
FA58H
76543210
LCD Display Control Register
LDON LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0
3
LCDC7 LCDC6 LCDC5 LCDC4 LEPS LIPS
3
4
2
LCD Clock Selector
fLCD
3210
3210
... ... ...
Selector
Selector
3210
3210
... ... ...
Selector
Selector
... ... ...
Timing Controller
... ... ...
LCDM3
LCD drive
Mode Selector
Segment Selector
Note ... ... ... ... ... Note
Note ... ... ...
P97 Output
Buffer
S0 ... ... ... ... ... S23
Note
396
Segment driver
Note
Common Driver
LCD Drive Voltage Controller
P80 Output
Buffer
S24/P97 ... ... ... S39/P80
COM0 COM1 COM2 COM3
VLC2
VLC1
VLC0
BIAS
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-2. LCD Clock Select Circuit Block Diagram
8
fXX/2
Selector
fW
Prescaler
fXT
6
fW/2
Clear
Prescaler
3
fLCD/2
2
fLCD/2
fLCD/2
LCDCL
Selector
fLCD
3
TCL24
TMC21
Timer Clock
Select Register 2
LCDM6 LCDM5 LCDM4
Watch Timer Mode
Control Register
LCD Display
Mode Register
Internal Bus
Remarks 1. The watch timer includes the circuit enclosed with the dotted line.
2. LCDCL : LCD clock
3. fLDC : LCD clock frequency
4. fXX = f X/2 (MCS = 0), fXX = f X (MCS = 1)
397
CHAPTER 19
LCD CONTROLLER/DRIVER
19.3 LCD Controller/Driver Control Registers
The LCD controller/driver is controlled by the following two registers.
• LCD display mode register (LCDM)
• LCD display control register (LCDC)
(1) LCD display mode register (LCDM)
This register sets display operation enabling/ disabling, the LCD clock, frame frequency, display mode, and
operating mode.
LCDM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDM to 00H.
398
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-3. LCD Display Mode Register Format
Symbol
7
6
5
4
3
2
1
0
LCDM LDON LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0
Address
After Reset
R/W
FFB0H
00H
R/W
Enables/disables LCD Display
LDON
0
Display OFF (all segment outputs are unselect signals)
1
Display ON
Selects LCD Clock Note 1
LCDM6 LCDM5 LCDM4
fXX = 5.0 MHz
fXX = 4.19 MHz
fXT = 32.768 kHz
0
0
0
f W /29 (76 Hz)
f W /29 (64 Hz)
f W /29 (64 Hz)
0
0
1
f W /28 (153 Hz)
8
f W /2 (128 Hz)
f W /28 (128 Hz)
0
1
0
f W /27 (305 Hz)
f W /27 (256 Hz)
f W /27 (256 Hz)
0
1
1
f W /26 (610 Hz)
f W /26 (512 Hz)
f W /26 (512 Hz)
Other than above
Note 2
Setting prohibited
Operating Mode of
LCDM3
LCD Controller/driver
Supply Voltage of LCD Controller/driver
Static Display Mode
0
Normal operation
2.0 to 5.5 V
1
Low-voltage operation
2.0 to 3.4 V
1/3 Bias Mode
2.5 to 5.5 V
1/2 bias Mode
2.7 to 5.5 V
Selects Display Mode of LCD Controller/driver
LCDM2 LCDM1 LCDM0
Time Division
Bias Mode
0
0
0
4
1/3
0
0
1
3
1/3
0
1
0
2
1/2
0
1
1
3
1/2
1
0
0
Static display mode
Ohter than above
Setting prohibited
Notes 1. The LCD clock is supplied from the clock timer. When LCD display is performed, 1 should be set
in bit 1 (TMC21) of the watch timer mode control register (TMC2).
2. To reduce the power consumption, clear LCDM3 to 0 when LCD display is not performed. Before
manipulating LCDM3, be sure to turn OFF the LCD display.
If TMC21 is cleared to 0 during LCD display, the LCD clock supply will be stopped and the display
will be disrupted.
Remarks 1. fW
: Watch timer clock frequency (fXX/27 or fXT)
2. fXX
: Main system clock frequency (fX or fX/2)
3. fX
: Main system clock oscillation frequency
4. fXT
: Subsystem clock oscillation frequency
399
CHAPTER 19
LCD CONTROLLER/DRIVER
Table 19-3. Frame Frequencies (Hz)
fW/2 9
(64 Hz)
fW/2 8
(128 Hz)
fW/2 7
(256 Hz)
fW/26
(512 Hz)
Static
64
128
256
512
1/2
32
64
128
256
1/3
21
43
85
171
1/4
16
32
64
128
LCDCL
Duty
Remarks 1. Figures in parentheses apply to operation with fX = 4.19 MHz or fXT = 32.768 kHz.
2. fW : Watch timer clock frequency (fXX/27 or fXT)
3. fXX : Main system clock frequency (fX or fX/2)
4. fX : Main system clock oscillation frequency
5. fXT : Subsystem clock oscillation frequency
400
CHAPTER 19
LCD CONTROLLER/DRIVER
(2) LCD display control register (LCDC)
This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and
switchover between segment output and input/output port functions.
LCDC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDC to 00H.
Figure 19-4. LCD Display Control Register Format
Symbol
7
6
5
4
LCDC LCDC7 LCDC6 LCDC5 LCDC4
3
2
0
0
1
0
LEPS LIPS
Address
After Reset
R/W
FFB2H
00H
R/W
P80/S39 to P97/S24 Pin Functions
LCDC7 LCDC6 LCDC5 LCDC4
Port Pins
Segment Pins
0
0
0
0
P80 to P97
None
0
0
0
1
P80 to P95
S24, S25
0
0
1
0
P80 to P93
S24 to S27
0
0
1
1
P80 to P91
S24 to S29
0
1
0
0
P80 to P87
S24 to S31
0
1
0
1
P80 to P85
S24 to S33
0
1
1
0
P80 to P83
S24 to S35
0
1
1
1
P80 to P81
S24 to S37
1
0
0
0
None
S24 to S39
Other than above
Setting prohibited
LEPS LIPS
LCD Driving Power Supply Selection
0
0
Does not supply power to LCD.
0
1
Supplies power to LCD from VDD pin.
1
0
Supplies power to LCD from BIAS pin. (Shorts BIAS and VLC0 pins internally.)
1
1
Setting prohibited
Cautions 1. Pins which perform segment output cannot be used as output port pins even if 0 is set in
the port register.
2. If a pin which performs segment output is read as a port, its value will be 0.
3. Pins set as segment outputs by LCDC cannot have an internal pull-up resistor used
regardless of the value of bits 0 and 1 (PUO8 and PUO9) of pull-up resistor option register
H.
401
CHAPTER 19
LCD CONTROLLER/DRIVER
19.4 LCD Controller/Driver Settings
LCD controller/driver settings should be performed as shown below. When the LCD controller/driver is used,
the watch timer should be set to the operational state beforehand.
<1> Set “watch operation enabled” in timer clock selection register 2 (TCL2) and the watch timer mode control
register (TMC2).
<2> Set the initial value in the display data memory (FA58H to FA7FH).
<3> Set the pins to be used as segment outputs in the LCD display control register (LCDC).
<4> Set the display mode, operating mode, and the LCD clock in the LCD display mode register (LCDM).
Next, set data in the display data memory according to the display contents.
402
CHAPTER 19
LCD CONTROLLER/DRIVER
19.5 LCD Display Data Memory
The LCD display data memory is mapped onto addresses FA58H to FA7FH. The data stored in the LCD display
data memory can be displayed on an LCD panel by the LCD controller/driver.
Figure 19-5 shows the relationship between the LCD display data memory contents and the segment outputs/
common outputs.
Any area not used for display can be used as normal RAM.
Figure 19-5. Relationship between LCD Display Data Memory
Contents and Segment/Common Outputs
Address
b7
b6
b5
b4
b3
b2
b1
b0
FA7FH
S0
FA7EH
S1
FA7DH
S2
FA7CH
S3
FA5AH
S37/P82
FA59H
S38/P81
FA58H
S39/P80
COM3
COM2
COM1
COM0
Caution The higher 4 bits of the LCD display data memory do not incorporate memory. Be sure to
set them to 0.
403
CHAPTER 19
LCD CONTROLLER/DRIVER
19.6 Common Signals and Segment Signals
An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal
and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD).
As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals, it is driven
by AC voltage.
(1) Common signals
For common signals, the selection timing order is as shown in Table 19-4 according to the number of time
divisions set, and operations are repeated with these as the cycle. In the static display mode, the same
signal is output to COM0 to COM3.
With 2-time-division operation, pins COM2 and COM3 are left open, and with 3-time-division operation, the
COM3 pin is left open.
Table 19-4. COM Signals
COM signal
COM0
COM1
COM2
COM3
Open
Open
Time division
Static
2-time division
3-time division
Open
4-time division
(2) Segment signals
Segment signals correspond to a 40-byte LCD display data memory (FA58H to FA7FH). Each display data
memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the COM0, COM1, COM2 and COM3 timings
respectively, and if the value of the bit is 1, it is converted to the selection voltage. If the value of the bit
is 0, it is converted to the non-selection voltage and output to a segment pin (S0 to S39) (S24 to S39 have
a dual function as input/output port pins).
Consequently, it is necessary to check what combination of front surface electrodes (corresponding to the
segment signals) and rear surface electrodes (corresponding to the common signals) of the LCD display
to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the
pattern to be displayed.
In addition, because LCD display data memory bits 1 and 2 are not used with the static display mode, bits
2 and 3 are not used with the 2-time-division method, and bit 3 is not used with the 3-time-division method,
these can be used for other than display purposes.
Bits 4 to 7 are fixed at 0.
404
CHAPTER 19
LCD CONTROLLER/DRIVER
(3) Common signal and segment signal output waveforms
The voltages shown in Table 19-5 are output in the common signals and segment signals.
The ±VLCD ON voltage is only produced when the common signal and segment signal are both at the selection
voltage; other combinations produce the OFF voltage.
Table 19-5. LCD Drive Voltages
(a) Static display mode
Segment
Select
Non-select
Common
VSS1, VLC0
VLC0, VSS1
VLC0, VSS1
–VLCD, +V LCD
0 V, 0 V
(b) 1/2 bias method
Segment
Common
Select level
Non-select level
Select
Non-select
VSS1, VLC0
VLC0, VSS1
V LC0, VSS1
–VLCD, +V LCD
0 V, 0 V
VLC1 = VLC2
–1/2VLCD, +1/2V LCD
+1/2VLCD, –1/2VLCD
(c) 1/3 bias method
Segment
Common
Select
Non-select
VSS1, VLC0
V LC1, VLC2
Select level
VLC0, V SS1
–VLCD, +V LCD
–1/3VLCD, +1/3V LCD
Non-select level
VLC2, VLC1
–1/3VLCD, +1/3V LCD
–1/3VLCD, +1/3V LCD
405
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-6 shows the common signal waveform, and Figure 19-7 shows the common signal and segment signal
voltages and phases.
Figure 19-6. Common Signal Waveform
(a) Static display mode
VLC0
COMn
VLCD
(Static)
VSS1
TF = T
Remarks 1. T: One LCDCL cycle
2. TF: Frame frequency
(b) 1/2 bias method
VLC0
COMn
VLC2
VLCD
(Divided by 2)
VSS1
TF = 2 × T
VLC0
COMn
VLC2
VLCD
(Divided by 3)
VSS1
TF = 3 × T
Remarks 1. T: One LCDCL cycle
2. TF: Frame frequency
(c) 1/3 bias method
VLC0
COMn
VLC1
VLC2
(Divided by 3)
VLCD
VSS1
TF = 3 × T
VLC0
COMn
VLC1
(Divided by 4)
VLC2
VSS1
TF = 4 × T
Remarks 1. T: One LCDCL cycle
2. TF: Frame frequency
406
VLCD
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-7. Common Signal and Static Signal Voltages and Phases
(a) Static display mode
Selected
Not Selected
VLC0
VLCD
Common Signal
VSS1
VLC0
VLCD
Segment Signal
VSS1
T
Remark
T
T : One LCDCL cycle
(b) 1/2 bias method
Selected
Not Selected
VLC0
VLC2
Common Signal
VLCD
VSS1
VLC0
Segment Signal
VLC2
VLCD
VSS1
T
Remark
T
T : One LCDCL cycle
(c) 1/3 bias method
Selected
Not Selected
VLC0
VLC1
VLC2
Common Signal
VLCD
VSS1
VLC0
VLC1
VLC2
Segment Signal
VLCD
VSS1
T
Remark
T
T : One LCDCL cycle
407
CHAPTER 19
19.7
LCD CONTROLLER/DRIVER
Supply of LCD Drive Voltages VLC0, VLC1, VLC2
Split resistors for producing the LCD drive voltages can be incorporated in the mask ROM products (µPD780306,
780308, 780306Y, and 780308Y) by mask option (the PROM products (µPD78P0308, 78P0308Y) do not incorporate
split resistors). Incorporating the split resistors makes it possible to produce LCD drive voltages appropriate to the
various bias methods shown in Table 19-6 without using external split resistors.
Also, an LCD drive voltage can be externally supplied from the BIAS pin to produce other LCD drive voltages.
Table 19-6. LCD Drive Voltages (with On-Chip Split Resistor)
Bias Method
LCD
Drive Voltage
No Bias
1/2
1/3
(Static Mode)
Bias
Bias
VLC0
VLCD
VLCD
VLCD
VLC1
2/3 V LCD
1/2 V LCD Note
2/3 V LCD
VLC2
1/3 V LCD
Note
1/3 V LCD
With the 1/2 bias method, the VLC1 pin and VLC2 pin must be connected
externally.
Remarks 1. When the BIAS pin and VLC0 pin are open, V LCD = 3/5 VDD (with onchip split resistor).
2. When the BIAS pin and VLC0 pin are connected, VLCD = V DD1.
Examples of internal supply of the LCD drive voltage in accordance with Table 19-6 are shown in Figures 198 and 19-9. An example of supply of the LCD drive voltage from off-chip is shown in Figure 19-10. Stepless LCD
drive voltages can be supplied by means of variable resistor r.
408
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-8. LCD Drive Power Supply Connection Examples (with On-Chip Split Resistor)
(a)
1/3 bias method and static display mode
(Example with VDD1 = 5 V, VLCD = 3 V)
(b)
1/2 bias method mode
(Example with VDD1 = 5 V, VLCD = 5 V)
VDD1
LIPS
VDD1
LIPS
P-ch
P-ch
BIAS pin
LEPS
(= 0)
P-ch
BIAS pin
LEPS
(= 0)
2R
VLC0
P-ch
2R
VLC0
R
R
VLC1
VLC1
VLCD
VLCD
R
VLC2
R
VLC2
R
R
VSS1
VSS1
VSS1
VLCD = 3/5VDD1
(c)
VSS1
VLCD = VDD1
1/3 bias method and static display mode
(Example with VDD1 = 5 V, VLCD = 5 V)
VDD1
P-ch
LIPS
BIAS pin
LEPS
(= 0)
P-ch
2R
VLC0
R
VLC1
VLCD
R
VLC2
R
VSS1
VSS1
VLCD = VDD1
409
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-9. LCD Drive Power Supply Connection Examples (with External Split Resistor)
(a)
Static display mode Note
(b)
(Example with VDD1 = 5 V, VLCD = 5 V)
Static display mode
(Example with VDD1 = 5 V, VLCD = 3 V)
VDD1
VDD1
LIPS
LIPS
P-ch
P-ch
BIAS pin
BIAS pin
LEPS
(= 0)
LEPS
(= 0)
P-ch
P-ch
VLC0
VLC0
VLC1
VLC1
2R
3R
VLCD
VLCD
VLC2
VLC2
VSS1
VSS1
VSS1
VSS1
VLCD = 3/5VDD1
VLCD = VDD1
Note
(c)
LIPS should always be set to 1 (including in standby mode).
1/2 bias method
(d)
(Example with VDD1 = 5 V, VLCD = 3 V)
1/3 bias method
(Example with VDD1 = 5 V, VLCD = 3 V)
VDD1
LIPS
VDD1
LIPS
P-ch
P-ch
BIAS pin
LEPS
(= 0)
P-ch
4R
BIAS pin
LEPS
(= 0)
VLC0
P-ch
VLC0
3R
R
VLC1
VLC1
VLCD
VLCD
VLC2
R
VLC2
3R
VSS1
R
VSS1
VSS1
VLCD = 3/5VDD1
410
2R
VSS1
VLCD = 3/5VDD1
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-10. Example of LCD Drive Voltage Supply from Off-Chip
VDD1
LIPS
(= 0)
P-ch
LEPS
P-ch
VDD1
r
BIAS pin
VLC0
R
VLC1
VLCD
R
VLC2
R
VSS1
VSS1
VLCD =
3R VDD1
3R + r
411
CHAPTER 19
LCD CONTROLLER/DRIVER
19.8 Display Modes
19.8.1 Static display example
Figure 19-12 shows the connection of a static type 5-digit LCD panel with the display pattern shown in Figure
19-11 with the µPD780308, 780308Y Subseries segment (S0 to S39) and common (COM0) signals. The display
example is “123.45,” and the display data memory contents (addresses FA58H to FA7FH) correspond to this.
An explanation is given here taking the example of the third digit “3.” (
). In accordance with the display pattern
in Figure 19-11, selection and non-selection voltages must be output to pins S16 to S23 as shown in Table 19-7
at the COM0 common signal timing.
Table 19-7. Selection and Non-Selection Voltages (COM0)
Segment
S16
S17
S18
S19
S20
S21
S22
S23
S
S
S
S
NS
S
NS
S
Common
COM0
S: Selection, NS: Non-selection
From this, it can be seen that 10101111 must be prepared in the BIT0 bits of the display data memory (addresses
FA68H to FA6FH) corresponding to S16 to S23.
The LCD drive waveforms for S19, S20, and COM0 are shown in Figure 19-13. When S19 is at the selection
voltage at the timing for selection with COM0, it can be seen that the +VLCD/–VLCD AC square wave, which is the
LCD illumination (ON) level, is generated.
Shorting the COM0 to COM3 lines increases the current drive capability because the same waveform as COM0
is output to COM1 to COM3.
Figure 19-11. Static LCD Display Pattern and Electrode Connections
S8n + 3
S8n + 4
S8n + 2
S8n + 5
S8n + 6
S8n + 1
S8n
S8n + 7
n = 0 to 4
412
COM0
Data Memory Addresses
1
0
1
1
0
1
0
1
1
1
0
1
0 BIT0
× × × × × × × ×
× × × × × × × × × × × × × × × ×
× × × × × × × × BIT1
× × × × × × × ×
× × × × × × × ×
× × × × × × × × × × × × × × × ×
× × × × × × × × BIT2
× × × × × × × ×
× × × × × × × ×
× × × × × × × × × × × × × × × ×
× × × × × × × × BIT3
LCD CONTROLLER/DRIVER
COM3
COM2
COM1
COM0
S0
S1
S2
S4
S3
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S36
S35
S37
S38
S39
Can be shorted.
LCD Panel
CHAPTER 19
1
× × × × × × × ×
Figure 19-12. Static LCD Panel Connection Example
0
FA7FH
1 1 0
E
1
D
1
B
A
0
C
9
1
8
0
7
1
6
A
0
5
9
0
4
8
1
3
7
0 1
2
6
0
1
5
1
0
4
3
0 1
FA6FH
2
1
E
1
1
D
0
FA5FH
0
B
E
0
C
D
A
0
B
9
0
C
FA58H
0
Timing Strobes
413
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-13. Static LCD Drive Waveform Examples
TF
VLC0
COM0
VSS1
VLC0
S19
VSS1
VLC0
S20
VSS1
+VLCD
COM0 to S19
0
–VLCD
+VLCD
COM0 to S20
0
–VLCD
414
CHAPTER 19
LCD CONTROLLER/DRIVER
19.8.2 2-time-division display example
Figure 19-15 shows the connection of a 2-time-division type 10-digit LCD panel with the display pattern shown
in Figure 19-14 with the µPD780308, 780308Y Subseries segment signals (S0 to S39) and common signals (COM0,
COM1). The display example is “123456.7890,” and the display data memory contents (addresses FA58H to
FA7FH) correspond to this.
An explanation is given here taking the example of the eighth digit “3” ( ). In accordance with the display pattern
in Figure 19-14, selection and non-selection voltages must be output to pins S28 to S31 as shown in Table 19-8
at the COM0 and COM1 common signal timings.
Table 19-8. Selection and Non-Selection Voltages (COM0, COM1)
Segment
S28
S29
S30
S31
COM0
S
S
NS
NS
COM1
NS
S
S
S
Common
S: Selection, NS: Non-selection
From this, it can be seen that, for example, ××10 must be prepared in the display data memory (address FA60H)
corresponding to S31.
Examples of the LCD drive waveforms between S31 and the common signals are shown in Figure 19-16. When
S31 is at the selection voltage at the COM1 selection timing, it can be seen that the +VLCD/–VLCD AC square wave,
which is the LCD illumination (ON) level, is generated.
2-Time-Division LCD Display Pattern and Electrode Connections
,,,,,,,
,,,
Figure 19-14.
S4n + 2
,
,,,,,,,
S4n + 3
n = 0 to 9
S4n + 1
COM0
S4n
COM1
415
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-15. 2-Time-Division LCD Panel Connection Example
Timing Strobes
COM3
COM2
Open
COM1
1 1 0
1
1
C
1
B
1
1
1
8
0
7
1
0
0
9
1
1
5
1
0
4
3
1
1
1
0
1
0
FA5FH
1
1
D
0
1
C
1
B
1
0
9
0
0
FA58H
0
A
0
0
1
E
1
0 1
2
0 0
0 0
6
1 0
0
1
A
BIT3
× × × × × × × ×
BIT2
× × × × × × × ×
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
Remark In bits marked ×, any data can be stored because this is a 2-time-division display.
416
LCD Panel
0 1 0
D
× × × × × × × × × × × × × × × × × × × × × × × ×
1
E
× × × × × × × ×
0
1
0
FA6FH
1
0
1
1
1
2
× ×
3
× × × × × × × × × × × × × × × × × × × × × ×
4
× × × × × × × ×
BIT1
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
5
1
6
1
7
1
8
1
9
1
A
1
B
0
C
0
D
1
E
0
BIT0
COM0
FA7FH
Data Memory Addresses
Open
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-16. 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
COM0
VLC1 (VLC2)
VSS1
VLC0
COM1
VLC1 (VLC2)
VSS1
VLC0
S31
VLC1 (VLC2)
VSS1
+VLCD
+1/2VLCD
COM0 to S31
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
COM1 to S31
0
–1/2VLCD
–VLCD
417
CHAPTER 19
LCD CONTROLLER/DRIVER
19.8.3 3-time-division display example
Figure 19-18 shows the connection of a 3-time-division type 13-digit LCD panel with the display pattern shown
in Figure 19-17 with the µPD780308, 780308Y Subseries segment signals (S0 to S38) and common signals (COM0
to COM2). The display example is “123456.7890123,” and the display data memory contents (addresses FA59H
to FA7FH) correspond to this.
An explanation is given here taking the example of the eighth digit “6.” (
). In accordance with the display pattern
in Figure 19-17, selection and non-selection voltages must be output to pins S21 to S23 as shown in Table 19-9
at the COM0 to COM2 common signal timings.
Table 19-9. Selection and Non-Selection Voltages (COM0 to COM2)
Segment
S21
S22
S23
COM0
NS
S
S
COM1
S
S
S
COM2
S
S
—
Common
S: Selection, NS: Non-selection
From this, it can be seen that ×110 must be prepared in the display data memory (address FA6AH) corresponding
to S21.
Examples of the LCD drive waveforms between S21 and the common signals are shown in Figure 19-19 (1/2
bias method) and Figure 19-20 (1/3 bias method). When S21 is at the selection voltage at the COM1 selection
timing, and S21 is at the selection voltage at the COM2 selection timing, it can be seen that the +VLCD/–VLCD AC
square wave, which is the LCD illumination (ON) level, is generated.
Figure 19-17. 3-Time-Division LCD Display Pattern and Electrode Connections
,,
,
COM0
S3n + 1
S3n + 2
n = 0 to 12
418
S3n
,,,
,,,,
,,
,,
,, ,,
COM1
COM2
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-18. 3-Time-Division LCD Panel Connection Example
Timing Strobes
COM3
COM1
C
B
0
0
9
0
0
1
A
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
LCD Panel
0 BIT2
× × × × × × × × BIT3
× × × × × × × × × ×
0 ×' 1
0 ×' 1
0 ×' 0
0 ×' 1
×' 0
0 ×' 1 0
× × × × × × × × × × × × × × × × × × × × ×
0
1
1
1
0
1
0 1
1
D
1
E
0
0
FA5FH
1
1
0 1
2
1 ×' 0
1 BIT1
1
0
0 1
1
1
1
4
3
1 1
5
1
6
0 ×' 1
7
0 ×' 0 0 ×' 1
8
0 ×' 1
0
1
1
1
1
0
0
9
1
A
1
B
0
C
1
D
0 ×' 1
1
1
E
1
FA6FH
×' 0
1
1
0
0
0
0
1
0
0
0
1
0
1
1
1
0
1 1 1
1
1
2
1
3
0
4
1
5
1 1 1
6
1
7
1
8
1
9
1
A
0
B
1
C
1
D
1
E
1 BIT0
COM0
FA7FH
Data Memory Addresses
Open
COM2
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
FA58H
Remarks 1. ×’ : Irrelevant bits because they have no corresponding segment in the LCD panel
2. × : Irrelevant bits because this is a 3-time-division display
419
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-19. 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
COM0
VLC1 (VLC2)
VSS1
VLC0
COM1
VLC1 (VLC2)
VSS1
VLC0
COM2
VLC1 (VLC2)
VSS1
VLC0
S21
VLC1 (VLC2)
VSS1
+VLCD
+1/2VLCD
COM0 to S21
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
COM1 to S21
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
COM2 to S21
0
–1/2VLCD
–VLCD
420
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-20. 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
COM0
VLC1
VLC2
VSS1
VLC0
COM1
VLC1
VLC2
VSS1
VLC0
COM2
VLC1
VLC2
VSS1
VLC0
S21
VLC1
VLC2
VSS1
+VLCD
+1/3VLCD
COM0 to S21
0
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
COM1 to S21
0
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
COM2 to S21
0
–1/3VLCD
–VLCD
421
CHAPTER 19
LCD CONTROLLER/DRIVER
19.8.4 4-time-division display example
Figure 19-22 shows the connection of a 4-time-division type 20-digit LCD panel with the display pattern shown
in Figure 19-21 with the µPD780308, 780308Y Subseries segment signals (S0 to S39) and common signals (COM0
to COM3). The display example is “123456.78901234567890,” and the display data memory contents (addresses
FA58H to FA7FH) correspond to this.
An explanation is given here taking the example of the 15th digit “6.” (
). In accordance with the display pattern
in Figure 19-21, selection and non-selection voltages must be output to pins S28 and S29 as shown in Table 1910 at the COM0 to COM3 common signal timings.
Table 19-10. Selection and Non-Selection Voltages (COM0 to COM3)
Segment
S28
S29
COM0
S
S
COM1
NS
S
COM2
S
S
COM3
S
S
Common
S: Selection, NS: Non-selection
From this, it can be seen that 1101 must be prepared in the display data memory (address FA63H) corresponding
to S28.
Examples of the LCD drive waveforms between S28 and the COM0 and COM1 signals are shown in Figure 1923 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When S28 is at the selection
voltage at the COM0 selection timing, it can be seen that the +VLCD/–VLCD AC square wave, which is the LCD
illumination (ON) level, is generated.
Figure 19-21. 4-Time-Division LCD Display Pattern and Electrode Connections
,,
,,,,,,
,
S2n
S2n + 1
n = 0 to 18
422
,,
,,
COM0
COM2
COM1
COM3
CHAPTER 19
LCD CONTROLLER/DRIVER
Figure 19-22. 4-Time-Division LCD Panel Connection Example
Timing Strobes
COM3
COM2
COM1
0
0
0
1
1
0
S27
S30
S32
S33
S34
S36
0
1
S35
0
1
0
S31
0
0
0 1
1
S28
0
1 0
0
0
0
1
0
1
1
1
1
1
0 0
1
1
1
0
1
S25
S26
S29
1
1 1
1 0
1
S24
0
1 0
S21
S22
S23
1
1
0
1
1
1
S17
LCD Panel
BIT2
BIT3
0
0
0
0
0
0 1
0
0
1
0
1
0
1
BIT1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1 1
0 1
1
0
1
1
0
1
0
S16
1
1 0 1
S15
0
1 1 1
S13
S14
0
1 0 0
1
1
1
0
9
FA58H
1
1
A
S12
1
1
1
1
B
0
C
0
D
0
E
0
0
FA5FH
1
1
0 1
2
S11
1
4
3
S9
S10
S20
1
5
1
6
S8
S18
S19
0
0
0
1
7
1
8
1
9
1 1
A
1
B
1
C
1
D
1
E
1
FA6FH
0
1
0
S6
S7
1
1
1
S5
1
1
2
0 1 0
3
S3
1
1 1
4
0
5
S2
S4
1
7
0
8
0
1
9
1
1
A
1
B
1
C
1
S1
D
6
Data Memory Addresses
S0
1
E
1
FA7FH
1
BIT0
COM0
S37
S38
S39
423
CHAPTER 19
,,
LCD CONTROLLER/DRIVER
,
,
Figure 19-23. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
COM0
TF
VLC0
VLC1
VLC2
VSS1
VLC0
COM1
VLC1
VLC2
VSS1
VLC0
COM2
VLC1
VLC2
VSS1
VLC0
COM3
VLC1
VLC2
VSS1
VLC0
S28
VLC1
VLC2
VSS1
+VLCD
+1/3VLCD
COM0 to S28
0
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
COM1 to S28
0
–1/3VLCD
–VLCD
424
CHAPTER 20 INTERRUPT AND TEST FUNCTIONS
20.1 Interrupt Function Types
The following three types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally (that is, even in interrupt disabled state). It does not undergo
interrupt priority control and is given top priority over all other interrupt requests.
It generates a standby release signal.
One interrupt request from the watchdog timer is provided as a non-maskable interrupt.
(2) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, and PR1L).
Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same
priority are simultaneously generated, each interrupts has a predetermined priority (see Table 20-1).
A standby release signal is generated.
Six external interrupt requests and 13 internal interrupt requests are provided as maskable interrupts.
(3) Software interrupt
This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in
interrupt disabled state. The software interrupt does not undergo interrupt priority control.
425
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
20.2 Interrupt Sources and Configuration
Twenty-one non-maskable, maskable, and software interrupts are provided as interrupt sources (see Table 201).
Table 20-1. Interrupt Source List
Interrupt
Type
Default
Priority Note 1
Interrupt Source
Name
NonMaskable
—
INTWDT
Watchdog timer overflow (with
watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow (with
interval timer mode selected)
1
INTP0
2
Trigger
Pin input edge detection
Internal/
External
Vector
Address
Internal
0004H
Type
Note 2
(A)
(B)
External
0006H
(C)
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTCSI0
End of serial interface channel 0
transfer
8
INTSER
Serial interface channel 2 UART reception
error generation
0018H
9
INTSR
End of serial interface channel 2
UART reception
001AH
INTCSI2
End of serial interface channel 2
3-wire transfer
10
INTST
End of serial interface channel 2
UART transfer
001CH
11
INTTM3
Reference time interval signal from
001EH
Internal
0014H
(B)
watch timer
Software
12
INTTM00
Generation of 16-bit timer register,
capture/compare register (CR00)
match signal
0020H
13
INTTM01
Generation of 16-bit timer register,
capture/compare register (CR01)
match signal
0022H
14
INTTM1
Generation of 8-bit timer/event
counter 1 match signal
0024H
15
INTTM2
Generation of 8 bit timer/event
counter 2 match signal
0026H
16
INTAD
End of A/D converter conversion
0028H
17
INTCSI3
End of serial interface channel 3
transfer
002AH
—
BRK
BRK instruction execution
–
003EH
(E)
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests.
0 is the highest priority and 17 is the lowest priority.
2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 20-1.
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Figure 20-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Standby
Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
Interrupt
Request
IE
PR
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby
Release Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Interrupt
Request
Sampling Clock
Select Register
(SCS)
External Interrupt Mode
Register (INTM0)
Sampling
Clock
Edge
Detector
MK
IF
IE
PR
Priority Control
Circuit
ISP
Vector Table
Address
Generator
Standby
Release Signal
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Figure 20-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
Interrupt
Request
Edge
Detector
MK
IE
PR
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby
Release Signal
(E) Software interrupt
Internal Bus
Interrupt
Request
Priority Control
Circuit
IF
:
Interrupt request flag
IE
:
Interrupt enable flag
ISP :
428
In-service priority flag
MK :
Interrupt mask flag
PR :
Priority specify flag
Vector Table
Address
Generator
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
20.3 Interrupt Function Control Registers
The following six types of registers are used to control the interrupt functions.
• Interrupt request flag register (IF0L, IF0H, IF1L)
• Interrupt mask flag register (MK0L, MK0H, MK1L)
• Priority specify flag register (PR0L, PR0H, PR1L)
• External interrupt mode register (INTM0, INTM1)
• Sampling clock select register (SCS)
• Program status word (PSW)
Table 20-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding
to interrupt request sources.
Table 20-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source
Interrupt Request Flag
Interrupt Mask Flag
Priority Specify Flag
Register
Register
Register
INTWDT
TMIF4
IF0L
INTP0
PIF0
PMK0
PPR0
INTP1
PIF1
PMK1
PPR1
INTP2
PIF2
PMK2
PPR2
INTP3
PIF3
PMK3
PPR3
INTP4
PIF4
PMK4
PPR4
INTP5
PIF5
PMK5
PPR5
INTCSI0
CSIIF0
INTSER
SERIF
SERMK
SERPR
INTSR/INTCSI2
SRIF
SRMK
SRPR
INTST
STIF
STMK
STPR
INTTM3
TMIF3
TMMK3
TMPR3
INTTM00
TMIF00
TMMK00
TMPR00
INTTM01
TMIF01
TMMK01
TMPR01
INTTM1
TMIF1
INTTM2
TMIF2
TMMK2
TMPR2
INTAD
ADIF
ADMK
ADPR
INTCSI3
CSIIF3
CSIMK3
CSIPR3
IF0H
IF1L
TMMK4
CSIMK0
TMMK1
MK0L
MK0H
MK1L
TMPR4
CSIPR0
TMPR1
PR0L
PR0H
PR1L
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used
as a 16-bit register IF0 use a 16-bit memory manipulation instruction for the setting.
RESET input clears these registers to 00H.
Figure 20-2. Interrupt Request Flag Register Format
Symbol
7
6
5
4
3
2
IF0L
0
PIF5
PIF4
PIF3
PIF2
PIF1
7
6
5
4
3
2
IF0H TMIF01 TMIF00 TMIF3 STIF SRIF SERIF
7
IF1L WTIF
Note
6
5
4
0
0
0
3
0
PIF0 TMIF4
1
0
0
CSIIF0
1
0
CSIIF3 ADIF TMIF2 TMIF1
××IF
Note
2
1
Address
After Reset
R/W
FFE0H
00H
R/W
FFE1H
00H
R/W
FFE2H
00H
R/W
Interrupt Request Flag
0
No interrupt request signal
1
Interrupt request signal is generated; Interrupt request state
WTIF is test input flag. Vectored interrupt request is not generated.
Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If
a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0.
2. Set always 0 in IF1L bits 4 to 6, IF0L bit 7, and IF0H bit 1.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set
standby clear enable/disable.
MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H
are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 20-3. Interrupt Mask Flag Register Format
Symbol
7
MK0L
1
6
5
4
3
2
PMK5 PMK4 PMK3 PMK2 PMK
7
6
5
3
4
2
MK0H TMMK01 TMMK00 TMMK3 STMK SRMK SERMK
7
MK1L WTMK
Note
6
5
4
1
1
1
3
0
PMK TMMK4
1
0
1
CSIMK0
1
0
CSIMK3 ADMK TMMK2 TMMK1
××MK
Note
2
1
Address
After
Reset
R/W
FFE4H
FFH
R/W
FFE5H
FFH
R/W
FFE6H
FFH
R/W
Interrupt Servicing Control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
WTMK controls standby mode release enable/disable. This bit does not control the interrupt function.
Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value
becomes undefined.
2. Because port 0 has a dual function as the external interrupt request input, when the
output level is changed by specifying the output mode of the port function, an interrupt
request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the
output mode.
3. Set always 1 in MK1L bits 4 to 6, MK0L bit 7, and MK0H bit 1.
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(3) Priority specify flag registers (PR0L, PR0H, and PR1L)
The priority specify flag is used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 20-4. Priority Specify Flag Register Format
Symbol
7
PR0L
1
7
6
5
4
3
2
0
PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 TMPR4
6
5
4
3
2
PR0H TMPR01TMPR00 TMPR3 STPR SRPR SERPR
PR1L
1
7
6
5
4
1
1
1
1
××PR
3
2
1
0
1
CSIPR0
1
0
CSIPR3 ADPR TMPR2 TMPR1
Address
After
Reset
R/W
FFE8H
FFH
R/W
FFE9H
FFH
R/W
FFEAH
FFH
R/W
Priority Level Selection
0
High priority level
1
Low priority level
Cautions 1. When a watchdog timer is used in watchdog timer mode 1, set 1 in TMPR4 flag.
2. Set always 1 in PR1L bits 4 to 7, PR0L bit 7, and PR0H bit 1.
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(4) External interrupt mode register (INTM0, INTM1)
These registers set the valid edge for INTP0 to INTP5.
INTM0 and INTM1 are set with an 8-bit memory manipulation instructions.
RESET input clears these registers to 00H.
Figure 20-5. External Interrupt Mode Register 0 Format
Symbol
7
6
5
4
3
2
INTM0 ES31 ES30 ES21 ES20 ES11 ES10
1
0
Address
After
Reset
R/W
0
0
FFECH
00H
R/W
INTP2 Valid Edge Selection
ES31 ES30
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
INTP1 Valid Edge Selection
ES21 ES20
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
INTP0 Valid Edge Selection
ES11 ES10
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
Caution Set the valid edges of the INTP0/TI00 pins after setting 16-bit timer mode control register bit 1
to bit 3 (TMC01 to TMC03) to 0 and stopping the timer operation.
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Figure 20-6. External Interrupt Mode Register 1 Format
Symbol
7
6
INTM1
0
0
5
4
3
2
0
ES61 ES60 ES51 ES50 ES41 ES40
Address
After
Reset
R/W
FFEDH
00H
R/W
INTP5 Valid Edge Selection
ES61 ES60
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
INTP4 Valid Edge Selection
ES51 ES50
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
INTP3 Valid Edge Selection
ES41 ES40
434
1
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
(5) Sampling clock select register (SCS)
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled
data reception is carried out using INTP0, digital noise is removed with sampling clocks.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS to 00H.
Figure 20-7. Sampling Clock Select Register Format
Symbol
7
6
5
4
3
2
SCS
0
0
0
0
0
0
1
0
SCS1 SCS0
Address
After
Reset
R/W
FF47H
00H
R/W
INTP0 Sampling Clock Selection
SCS1 SCS0
MCS = 1
MCS = 0
N
0
0
fXX/2
0
1
fX/27 (39.1 kHz)
8
fX/2 (19.5 kHz)
1
0
5
fX/2 (156.3 kHz)
6
fX/2 (78.1 kHz)
1
1
6
fX/2 (78.1 kHz)
7
fX/2 (39.1 kHz)
Caution fXX/2N is a clock to be supplied to the CPU and fXX/25, fXX/26 and fXX/27 are clocks to be supplied
to the peripheral hardware. fXX/2N stops in the HALT mode.
Remarks 1. N
:
Value (N = 0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register
2. fXX
:
Main system clock frequency (fX or fX/2)
3. fX
:
Main system clock oscillation frequency
4. MCS :
Oscillation mode select register bit 0
5. Values in parentheses when operated with fX = 5.0 MHz.
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The noise remover sets the interrupt request flag (PIF0) to 1 if the input level of the sampled INTP0 is active
twice in succession.
Figure 20-8 shows the noise remover input/output timing.
Figure 20-8. Noise Remover Input/Output Timing (during rising edge detection)
(a) When input is less than the sampling cycle (tSMP)
tSMP
Sampling Clock
INTP0
"L"
PIF0
PIF0 output remains low because the level of INTP0 is not high when
it is sampled.
(b) When input is equal to or twice the sampling cycle (tSMP)
tSMP
Sampling Clock
INTP0
1
2
PIF0
PIF0 flag is set to 1 because the sampled INTP0 level is high twice
in succession.
(c) When input is twice or more than the cycle frequency (tSMP)
t SMP
Sampling Clock
INTP0
PIF0
PIF0 flag is set to 1 when INTP0 goes high two or more times in succession.
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(6) Program status word (PSW)
The program status word is a register to hold the instruction execution result and the current status for interrupt
request. The IE flag to set maskable interrupt request enable/disable and the ISP flag to control multiple
interrupt servicing are mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and
dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK
instruction is executed, the contents of the PSW are automatically saved into the stack, and the IE flag is reset
to 0. If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged
interrupt are transferred to the ISP flag. The contents of the PSW are also saved to the stack by the PUSH
PSW instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 20-9. Program Status Word Format
PSW
7
6
5
4
3
2
1
0
IE
Z
RBS1
AC
RBS0
0
ISP
CY
After Reset
02H
Used when normal instruction is executed
ISP
Priority of Interrupt Currently Being Received
0
High-priority interrupt servicing
(low-priority interrupt disable)
1
Interrupt request not acknowledged or low-priority
interrupt servicing
(all-maskable interrupts enable)
IE
Interrupt Request Acknowledge Enable/Disable
0
Disable
1
Enable
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20.4 Interrupt Request Servicing Operations
20.4.1 Non-maskable interrupt request acknowledge operation
A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge
disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, program
status word (PSW) and program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector table
contents are loaded into PC and branched.
A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program
is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following
RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request
is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt
request is acknowledged after termination of the non-maskable interrupt service program execution.
Figure 20-10 shows the flowchart illustrating generation and acknowledgement of the non-maskable interrupt
request. Figure 20-11 shows the timing of acknowledging the non-maskable interrupt request. Figure 20-12 illustrates
how nested non-maskable interrupt requests are acknowledged.
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CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
Figure 20-10. Non-Maskable Interrupt Request Acknowledge Flowchart
Start
WDTM4 = 1
(with watchdog timer
mode selected)?
No
Interval Timer
Yes
Overflow in WDT?
No
Yes
WDTM3 = 0
(with non-maskable
interrupt request
selected)?
No
Reset Processing
Yes
Interrupt Request Generation
WDT interrupt servicing?
No
Interrupt Request
Held Pending
Yes
Interrupt control
register unaccessed?
No
Yes
Interrupt
Service Start
WDTM: Watchdog timer mode register
WDT:
Watchdog timer
Figure 20-11. Non-Maskable Interrupt Request Acknowledge Timing
CPU Instruction
Instruction
Instruction
PSW and PC Save, Jump Interrupt Sevicing
to Interrupt Servicing
Program
TMIF4
Interrupt request generated during this interval is acknowledged at
.
TMIF4: Watchdog timer interrupt request flag
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Figure 20-12. Non-Maskable Interrupt Request Acknowledge Operation
(a)
If a new non-maskable interrupt request is generated during
non-maskable interrupt servicing program execution
Main Routine
NMI Request <1>
NMI Request <2>
Execution of NMI request <1>
NMI request <2> held pending
Execution of 1 Instruction
Servicing of NMI request <2> that was pended
(b)
If two non-maskable interrupt requests are generated during
non-maskable interrupt servicing program execution
Main Routine
NMI Request <1>
NMI Request <2>
Execution of 1 Instruction
NMI Request <3>
Execution of NMI request <1>
NMI request <2> held pending
NMI request <3> held pending
Servicing of NMI request <2> that was pended
NMI request <3> not acknowledged
(Although two or more NMI requests have been generated,
only one request is acknowledged.)
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20.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and a mask
(MK) flag of the interrupt is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state
(with IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt request
service (with ISP flag reset to 0).
Table 20-3 shows the time required until interrupt servicing is executed since a maskable interrupt request has
been generated.
For the interrupt request acknowledge timing, refer to Figures 20-14 and 20-15.
Table 20-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Note
Minimum Time
Maximum Time Note
When ××PR× = 0
7 clock cycles
32 clock cycles
When ××PR× = 1
8 clock cycles
33 clock cycles
If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock cycle = 1/CPU clock frequency (fCPU)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority
with the priority specify flag is acknowledged first. If the same priorities are specified by the priority specify flag, the
interrupt with the highest default priority is acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 20-13 shows interrupt request acknowledge algorithms.
If a maskable interrupt request is acknowledged, the contents are saved in the stacks, program status word (PSW)
and program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged interrupt priority specify flag
contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded
into PC and branched.
Return from the interrupt is possible with the RETI instruction.
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INTERRUPT AND TEST FUNCTIONS
Figure 20-13. Interrupt Request Acknowledge Processing Algorithm
Start
No
××IF = 1?
Yes (Interrupt Request
Generation)
No
××MK = 0?
Yes
Interrupt Request
Reserve
Yes (High priority)
××PR = 0?
No (Low Priority)
Yes
Interrupt Request
Reserve
Any highpriority interrupt request
among simultaneously generated
××PR = 0 interrupt
requests?
No
No
Interrupt Request
Reserve
IE = 1?
Yes
Vectored Interrupt
Servicing
Any
Simultaneously
generated ×× PR = 0
interrupt
requests?
Yes
Interrupt Request
Reserve
No
Any
Simultaneously
generated high-priority
interrupt
requests?
Yes
Interrupt Request
Reserve
No
IE = 1?
No
Interrupt Request
Reserve
Yes
ISP = 1?
No
Yes
Interrupt Request
Reserve
Vectored Interrupt
Servicing
××IF:
Interrupt request flag
××MK: Interrupt mask flag
××PR: Priority specify flag
IE:
Flag controlling acknowledgement of maskable interrupt request (1 = Enabled, 0 = Disabled)
ISP:
Flag indicating priority of interrupt currently served (0 = Interrupt with high priority is serviced,
1 = No interrupt request is acknowledged, or interrupt with low priority is serviced).
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Figure 20-14. Interrupt Request Acknowledge Timing (Minimum Time)
6 Clocks
CPU Processing
Instruction
Instruction
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
××IF
(××PR = 1)
8 Clocks
××IF
(×× PR = 0)
7 Clocks
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock)
Figure 20-15. Interrupt Request Acknowledge Timing (Maximum Time)
25 Clocks
CPU Processing
Instruction
Divide Instruction
6 Clocks
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
××IF
(×× PR = 1)
33 Clocks
××IF
(×× PR = 0)
32 Clocks
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock)
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20.4.3 Software interrupt request acknowledge operation
A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled.
If a software interrupt request is acknowledged, the contents are saved in the stacks, program status word (PSW)
and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and
003FH) are loaded into PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution Do not use the RETI instruction for returning from the software interrupt.
20.4.4 Multiple interrupt request servicing
Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except
non-maskable interrupts). Also, when an interrupt request is received, interrupt requests acknowledge becomes
disabled (IE = 0). Therefore, to enable multiple interrupts, it is necessary to set (to 1) the IE flag with the EI instruction
during interrupt servicing to enable interrupt acknowledge.
Moreover, even if interrupts are enabled, multiple interrupts may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupts.
In the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower
than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for
multiple interrupt servicing. Interrupt requests that are not enabled because of the interrupt disable state or they have
a lower priority are held pending. When servicing of the current interrupt ends, the pended interrupt request is
acknowledged following execution of one main processing instruction execution.
Multiple interrupt servicing is not possible during non-maskable interrupt servicing.
Table 20-4 shows interrupt requests enabled for multiple interrupt servicing, and Figure 20-14 shows multiple
interrupt examples.
Table 20-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Multiple Interrupt Non-maskable
Interrupt
Request
Request
Interrupt Servicing
Maskable Interrupt Request
PR = 0
PR = 1
IE = 1
IE = 0
IE = 1
IE = 0
Non-maskable interrupt
D
D
D
D
D
Maskable interrupt
ISP = 0
E
E
D
D
D
ISP = 1
E
E
D
E
D
E
E
D
E
D
Software interrupt
Remarks 1. E : Multiple interrupt enable
2. D : Multiple interrupt disable
3. ISP and IE are the flags contained in PSW
ISP = 0 : An interrupt with higher priority is being serviced
ISP = 1 : An interrupt request is not accepted or an interrupt with lower priority is being serviced
IE = 0
: Interrupt request acknowledge is disabled
IE = 1
: Interrupt request acknowledge is enabled
4. PR is a flag contained in PR0L, PR0H, PR1L
PR = 0 : Higher priority level
PR = 1 : Lower priority level
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Figure 20-16. Multiple Interrupt Example (1/2)
Example 1. Two multiple interrupts generated
INTxx
Servicing
Main Processing
IE = 0
IE = 0
EI
INTzz
Servicing
IE = 0
EI
EI
INTyy
(PR = 0)
INTxx
(PR = 1)
INTyy
Servicing
INTzz
(PR = 0)
RETI
RETI
RETI
During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a
multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledge,
and the interrupt request acknowledge enable state is set.
Example 2. Multiple interrupt is not generated by priority control
Main Processing
EI
INTxx
Servicing
INTyy
Servicing
IE = 0
EI
INTxx
(PR = 0)
1 Instruction
Execution
INTyy
(PR = 1)
RETI
IE = 0
RETI
The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because
the interrupt priority is lower than that of INTxx, and a multiple interrupt is not generated. INTyy
request is retained and acknowledged after execution of 1 instruction execution of the main
processing.
PR = 0 : Higher priority level
PR = 1 : Lower priority level
IE = 0 : Interrupt request acknowledge disable
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Figure 20-16. Multiple Interrupt Example (2/2)
Example 3. A multiple interrupt is not generated because interrupts are not enabled
Main Processing
EI
INTxx
(PR = 0)
1 Instruction
Execution
INTxx
Servicing
INTyy
Servicing
IE = 0
INTyy
(PR = 0)
RETI
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued),
interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy
request is reserved and acknowledged after 1 instruction execution of the main processing.
PR = 0 : Higher priority level
IE = 0 : Interrupt request acknowledge disable
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20.4.5 Interrupt request reserve
Some instructions keep an interrupt request, if any, pending until the completion of execution of the next instruction.
These instructions (that keep an interrupt request pending) are listed below.
• MOV
PSW, #byte
• MOV
A, PSW
• MOV
PSW, A
• MOV1
PSW.bit, CY
• MOV1
CY, PSW.bit
• AND1
CY, PSW.bit
• OR1
CY, PSW.bit
• XOR1
CY, PSW.bit
• SET1
PSW.bit
• CLR1
PSW.bit
• RETB
• RETI
• PUSH
PSW
• POP
PSW
• BT
PSW.bit, $addr16
• BF
PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
• EI
• DI
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers
Caution The BRK instruction does not belong to the above group of instructions. However, the software
interrupt that is started by execution of the BRK instruction clears the IE flag to 0. Therefore,
even if a maskable interrupt request is generated, it is not acknowledged when the BRK
instruction is executed.
The timing with which interrupt requests are held pending is shown in Figure 20-17.
Figure 20-17. Interrupt Request Hold
CPU Processing
Instruction N
Instruction M
Save PSW and PC,
Jump to interrupt service
Interrupt service
program
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instructions other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
447
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
20.5 Test Functions
The test function sets the corresponding test input flag to 1 and generates a standby release signal when the watch
timer overflows and when the falling edge of port 4 is detected.
Unlike the interrupt function, this function does not perform vector processing.
There are two test input factors as shown in Table 20-5. The basic configuration is shown in Figure 20-18.
Table 20-5. Test Input Factors
Test Input Factors
Name
Internal/
External
Trigger
INTWT
Watch timer overflow
Internal
INTPT11
Falling edge detection at port 11
External
Figure 20-18. Basic Configuration of Test Function
Internal Bus
MK
Test Input
Signal
Standby
Release Signal
IF
IF: Test input flag
MK: Test mask flag
20.5.1 Registers controlling the test function
The test function is controlled by the following three registers.
• Interrupt request flag register 1L (IF1L)
• Interrupt mask flag register 1L (MK1L)
• Key return mode register (KRM)
The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table
20-6.
Table 20-6. Flags Corresponding to Test Input Signals
Test Input Signal Name
INTWT
INTPT11
448
Test Input Flag
WTIF
KRIF
Test Mask Flag
WTMK
KRMK
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
(1) Interrupt request flag register 1L (IF1L)
It indicates whether a watch timer overflow is detected or not.
It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction.
RESET input clears IF1L to 00H.
Figure 20-19. Format of Interrupt Request Flag Register 1L
Symbol
7
IF1L WTIF
6
5
4
0
0
0
3
2
1
0
CSIIF3 ADIF TMIF2 TMIF1
WTIF
Address
After Reset
R/W
FFE2H
00H
R/W
Watch Timer Overflow Detection Flag
0
Not detected
1
Detected
Caution Be sure to set bits 4 to 6 to 0.
(2) Interrupt mask flag register 1L (MK1L)
It is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer.
It is set with a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction.
RESET input sets MK1L to FFH.
Figure 20-20. Format of Interrupt Mask Flag Register 1L
Symbol
7
MK1L WTMK
WTMK
6
5
4
1
1
1
3
2
1
0
CSIMK3 ADMK TMMK2 TMMK1
Address
After Reset
R/W
FFE6H
FFH
R/W
Standby Mode Control by Watch Timer
0
Enables releasing the standby mode.
1
Disables releasing the standby mode.
Caution Be sure to set bits 4 to 6 to 1.
449
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
(3) Key return mode register (KRM)
This register is used to set enable/disable of standby function clear by key return signal (port 11 falling edge
detection), and selects port 11 falling edge input.
KRM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM to 02H.
Figure 20-21. Key Return Mode Register Format
Symbol
7
6
5
4
KRM
0
0
0
0
3
2
1
0
KRM3 KRM2 KRMK KRIF
KRM3 KRM2
Address
After Reset
R/W
FFB8H
02H
R/W
Selection of Port 11 Falling Edge Input
0
0
P117
0
1
P114 to P117
1
0
P112 to P117
1
1
P110 to P117
KRMK
Standby Mode Control by Key Return Signal
0
Standby mode release enabled
1
Standby mode release disabled
Key Return Signal Detection Flag
KRIF
0
Not detected
1
Detected (port 11 falling edge detection)
Caution When port 11 falling edge detection is used, be sure to clear KRIF to 0 (not cleared to 0
automatically).
450
CHAPTER 20
INTERRUPT AND TEST FUNCTIONS
20.5.2 Test input signal acknowledge operation
(1) Internal test input signal (INTWT)
The internal test input signal (INTWT) is generated when the watch timer overflows. This signal sets the WTIF
flag. At this time, the standby release signal is generated if it is not masked by the interrupt mask flag (WTMK).
By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer, a watch function can
be realized.
(2) External test input signal (INTPT4)
The external test input signal (INTPT4) is generated when the falling edge is input to the pins of port 4 (P40
to P47). As the result, the KRIF flag is set. At this time, the standby release signal is generated if it is not
masked by the KRMK flag. By using port 4 to input the key return signal of a key matrix, the presence or absence
of key input can be checked according to the status of the KRIF flag.
451
[MEMO]
452
CHAPTER 21
STANDBY FUNCTION
21.1 Standby Function and Configuration
21.1.1 Standby function
The standby function is designed to decrease power consumption of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.
System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in
the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out
intermittent operations such as in watch applications.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops
and the whole system stops. CPU current consumption can be considerably decreased.
Data memory low-voltage hold (down to VDD = 1.8 V) is possible. Thus, the STOP mode is effective to hold
data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt
request, it enables intermittent operations to be carried out.
However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode
is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request.
In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The
input/output port output latch and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the system operates with the main system clock
(subsystem clock oscillation cannot be stopped). The HALT mode can be used with either
the main system clock or the subsystem clock.
2. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and
execute the STOP instruction.
3. The following sequence is recommended for power consumption reduction of the A/D
converter when the standby function is used: first clear bit 7 (CS) of A/D converter mode
register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP
instruction.
453
CHAPTER 21
STANDBY FUNCTION
21.1.2 Standby function control register
A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with
the oscillation stabilization time select register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, it takes 217/fX, not 218/fX, until the STOP mode is cleared by RESET
input.
Figure 21-1. Oscillation Stabilization Time Select Register Format
Symbol
7
6
5
4
3
OSTS
0
0
0
0
0
2
1
0
Address
After Reset
R/W
FFFAH
04H
R/W
OSTS2 OSTS1 OSTS0
Selection of Oscillation Stabilization Time when STOP Mode is Released
OSTS2 OSTS1 OSTS0
MCS = 1
MCS = 0
0
0
0
212/f x (819 µ s)
213/f x (1.64 ms)
0
0
1
214/f x (3.28 ms)
215/f x (6.55 ms)
0
1
0
15
2 /f x (6.55 ms)
16
2 /f x (13.1 ms)
0
1
1
2 /f x (13.1 ms)
1
0
0
2 /f x (26.2 ms)
16
2 /f x (26.2 ms)
17
17
2 /f x (52.4 ms)
18
Other than above Setting prohibited
Caution The wait time after STOP mode clear does not include the time (see "a" in the illustration below)
from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by
interrupt request generation.
STOP Mode Clear
X1 Pin
Voltage
Waveform
a
VSS1
Remarks 1. fX
: Main system clock oscillation frequency
2. MCS : Oscillation mode select register bit 0
3. Values in parentheses apply to operating at fX = 5.0 MHz
454
CHAPTER 21
STANDBY FUNCTION
21.2 Standby Function Operations
21.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating status in the HALT mode is described below.
Table 21-1. HALT Mode Operating Status
HALT Mode Setting
HALT Execution During Main
HALT Execution During Subsystem
System Clock Operation
Clock Operation
Item
Without Subsystem
Clock Note 1
With Subsystem
Clock Note 2
Main System
Clock Oscillates
Main System
Clock Stops
Clock Generator
Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops.
CPU
Operation stop.
Port (output latch)
Status before HALT mode setting is held.
16-bit timer/event counter
Operable.
Operable when watch timer output
with fXT selected as count clock (fXT
is selected as count clock for watch
timer).
8-bit timer/event counter 1 and 2
Operable.
Operable when TI1 or TI2 is
selected as count clock.
Operable if fXX/27
Watch timer
Operable.
Operable if fXT is selected as
count clock.
is selected as
count clock.
Watchdog timer
Operable.
Operation stops.
A/D converter
Operable.
Operation stops.
Serial Interface
Operable
Operable at external SCK.
LCD controller/driver
Operable if fXX/27
is selected as
count clock.
External
interrupt
INTP0
Operable when a clock (fXX/25, fXX/26, fXX/27) for the
peripheral hardware is selected as sampling clock.
INTP1 to INTP5
Operable.
Operable.
Operable if fXT is selected as
count clock.
Operation stops.
Notes 1. Including case when external clock is not supplied.
2. Including case when external clock is supplied.
455
CHAPTER 21
STANDBY FUNCTION
(2) HALT mode clear
The HALT mode can be cleared with the following four types of sources.
(a) Clear upon unmasked interrupt request
An unmasked interrupt request is used to clear the HALT mode. If interrupt request acknowledge is
enabled, vectored interrupt request service is carried out. If disabled, the next address instruction is
executed.
Figure 21-2. HALT Mode Clear upon Interrupt Request Generation
HALT
Instruction
Wait
Standby
Release Signal
Operating
Mode
HALT Mode
Wait
Operating Mode
Oscillation
Clock
Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby
status is acknowledged.
2. Wait time will be as follows:
• When vectored interrupt service is carried out:
8 to 9 clocks
• When vectored interrupt service is not carried out: 2 to 3 clocks
(b) Clear upon non-maskable interrupt request
The HALT mode is cleared and vectored interrupt request service is carried out whether interrupt request
acknowledge is enabled or disabled.
(c) Clear upon unmasked test input
The HALT mode is cleared by unmasked test input and the next address instruction of the HALT instruction
is executed.
456
CHAPTER 21
STANDBY FUNCTION
(d) Clear upon RESET input
As is the case with normal reset operation, a program is executed after branch to the reset vector address.
Figure 21-3. HALT Mode Release by RESET Input
Wait
17
(2 /f X : 26.2 ms)
HALT
Instruction
RESET
Signal
Operating
Mode
HALT Mode
Oscillation
Clock
Oscillation
Stabilization
Wait Status
Reset
Period
Oscillation
stop
Operating
Mode
Oscillation
Remarks 1. fX : Main system clock oscillation frequency
2. Time value in parentheses is when fX = 5.0 MHz.
Table 21-2. Operation after HALT Mode Release
Release Source
MK××
PR××
IE
ISP
Operation
Maskable interrupt
0
0
0
×
Next address instruction execution
request
0
0
1
×
Interrupt service execution
0
1
0
1
Next address instruction execution
0
1
×
0
0
1
1
1
Interrupt service execution
1
×
×
×
HALT mode hold
–
–
×
×
Interrupt service execution
0
–
×
×
Next address instruction execution
1
–
×
×
HALT mode hold
–
–
×
×
Reset processing
Non-maskable interrupt
request
Test input
RESET input
×: don't care
457
CHAPTER 21
STANDBY FUNCTION
21.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD1 via a pull-up
resistor to minimize the leakage current at the crystal oscillator. Thus, do not use
the STOP mode in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset
to the HALT mode immediately after execution of the STOP instruction. After the wait
set using the oscillation stabilization time select register (OSTS), the operating mode
is set.
The operating status in the STOP mode is described below.
Table 21-3. STOP Mode Operating Status
STOP Mode Setting
With Subsystem Clock
Without Subsystem Clock
Item
Clock Generator
Only main system clock stops oscillation.
CPU
Operation stop.
Port (output latch)
Status before STOP mode setting is held.
16-bit timer/event counter
Operable when watch timer output with fXT selected
Operation stops.
is selected as count clock (fXT is selected as count
clock for watch timer).
8-bit timer/event counter 1 and 2
Operable when TI1 and TI2 are selected for the count clock.
Watch timer
Operable when fXT is selected for the count clock.
Watchdog timer
Operation stops.
A/D converter
Operation stops.
Serial
Other than UART
Interface
UART
LCD controller/driver
Operable when externally supplied clock is specified as the serial clock.
Operation stops.
Operable when fXT is selected for the count clock.
External
INTP0
Operation is impossible.
interrupt
INTP1 to INTP5
Operable.
458
Operation stops.
Operation stops.
CHAPTER 21
STANDBY FUNCTION
(2) STOP mode release
The STOP mode can be cleared with the following three types of sources.
(a) Release by unmasked interrupt request
An unmasked interrupt request is used to release the STOP mode. If interrupt request acknowledge is
enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt
request acknowledge is disabled, the next address instruction is executed.
Figure 21-4. STOP Mode Release by Interrupt Request Generation
Wait
(Time set by OSTS)
STOP
Instruction
Standby
Release Signal
Clock
Operationg
Mode
STOP Mode
Oscillation Stabilization
Wait Status
Oscillation
Oscillation Stop
Oscillation
Operating
Mode
Remark The broken line indicates the case when the interrupt request which has cleared the standby
status is acknowledged.
(b) Release by unmasked test input
The STOP mode is cleared by unmasked test input. After the lapse of oscillation stabilization time, the
instruction at the next address of the STOP instruction is executed.
459
CHAPTER 21
STANDBY FUNCTION
(c) Release by RESET input
The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried
out.
Figure 21-5. Release by STOP Mode RESET Input
Wait
17
(2 /f X : 26.2 ms)
STOP
Instruction
RESET
Signal
Operating
Mode
STOP Mode
Oscillation
Reset
Period
Oscillation Stop
Oscillation
Stabilization
Wait Status
Operating
Mode
Oscillation
Clock
Remarks 1. fX : Main system clock oscillation frequency
2. Time value in parentheses is when fX = 5.0 MHz.
Table 21-4. Operation after STOP Mode Release
Release Source
Maskable interrupt request
Test input
RESET input
×: don't care
460
MK××
PR××
IE
ISP
Operation
0
0
0
×
Next address instruction execution
0
0
1
×
Interrupt service execution
0
1
0
1
Next address instruction execution
0
1
×
0
0
1
1
1
Interrupt service execution
1
×
×
×
STOP mode hold
0
–
×
×
Next address instruction execution
1
–
×
×
STOP mode hold
–
–
×
×
Reset processing
CHAPTER 22 RESET FUNCTION
22.1 Reset Function
The following two operations are available to generate the reset signal.
(1)
External reset input with RESET pin
(2)
Internal reset by watchdog timer overrun time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
is set to the status as shown in Table 22-1. Each pin has high impedance during reset input or during oscillation
stabilization time just after reset clear.
When a high level is input to the RESET input, the reset is cleared and program execution starts after the lapse
of oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically cleared after
a reset and program execution starts after the lapse of oscillation stabilization time (217/fX) (see Figure 22-2 to 224).
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. During reset input, main system clock oscillation remains stopped but subsystem clock
oscillation continues.
3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pin becomes high-impedance.
Figure 22-1. Block Diagram of Reset Function
RESET
Count Clock
Reset
Signal
Reset Control Circuit
Watchdog Timer
Overflow
Interrupt
Function
Stop
461
CHAPTER 22 RESET FUNCTION
Figure 22-2. Timing of Reset Input by RESET Input
X1
Oscillation
Stabilization
Time Wait
Reset Period
(Oscillation
Stop)
Normal Operation
Normal Operation
(Reset Processing)
RESET
Internal
Reset Signal
Delay
Delay
Hi-Z
Port Pin
Figure 22-3. Timing of Reset due to Watchdog Timer Overflow
X1
Reset Period
(Oscillation
Stop)
Normal Operation
Watchdog
Timer
Overflow
Normal Operation
(Reset Processing)
Oscillation
Stabilization
Time Wait
Internal
Reset Signal
Hi-Z
Port Pin
Figure 22-4. Timing of Reset Input in STOP Mode by RESET Input
X1
STOP Instruction Execution
Stop Status
(Oscillation
Stop)
Normal Operation
Reset Period
(Oscillation
Stop)
Oscillation
Stabilization
Time Wait
Normal Operation
(Reset Processing)
RESET
Internal
Reset Signal
Delay
Port Pin
462
Delay
Hi-Z
CHAPTER 22
RESET FUNCTION
Table 22-1. Hardware Status after Reset (1/2)
Hardware
Program counter (PC)
Note 1
The contents of reset vector
tables (0000H and 0001H) are
set.
Stack pointer (SP)
Undefined
Program status word (PSW)
RAM
Port (Output latch)
Status after Reset
02H
Data memory
Undefined Note 2
General register
Undefined Note 2
Ports 0 to 3, Port 7 to 11 (P0 to P3, P7 to P11)
00H
Port mode register (PM0 to PM3, PM5 to PM7, PM12, PM13)
FFH
Pull-up resistor option register (PUOH, PUOL)
00H
Processor clock control register (PCC)
04H
Oscillation mode select register (OSMS)
Internal memory size switching register (IMS)
00H
Note 3
Internal expansion RAM size switching register (IXS)
0AH
Oscillation stabilization time select register (OSTS)
04H
16-bit timer/event counter
Timer register (TM0)
Capture/compare register (CR00, CR01)
8-bit timer/event counter 1, 2
0000H
Undefined
Clock select register (TCL0)
00H
Mode control register (TMC0)
00H
Capture/compare control register 0 (CRC0)
04H
Output control register (TOC0)
00H
Timer register (TM1, TM2)
00H
Compare registers (CR10, CR20)
Undefined
Clock select register (TCL1)
00H
Mode control registers (TMC1)
00H
Output control register (TOC1)
00H
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remains unchanged after reset.
2. The post-reset status is held in the standby mode.
3. The values after reset depend on the product.
µ PD780306, 780306Y: CCH, µ PD780308, 780308Y: CFH, µ PD78P0308, 78P0308Y: CFH
463
CHAPTER 22 RESET FUNCTION
Table 22-1. Hardware Status after Reset (2/2)
Hardware
Watch timer
Watchdog timer
Serial interface
Status after Reset
Mode control register (TMC2)
00H
Clock select register (TCL2)
00H
Mode register (WDTM)
00H
Clock select register (TCL3, TCL4)
88H
Shift registers (SIO0, SIO3)
Undefined
Mode registers (CSIM0, CSIM2, CSIM3)
00H
Serial bus interface control register (SBIC)
00H
Slave address register (SVA)
Undefined
Asynchronous serial interface mode register (ASIM)
00H
Asynchronous serial interface status register (ASIS)
00H
Baud rate generator control register (BRGC)
00H
Serial interface pin select register (SIPS)
00H
Transmit shift register (TXS)
FFH
Receive buffer register (RXB)
A/D converter
Interrupt timing specify register (SINT)
00H
Mode register (ADM)
01H
Conversion result register (ADCR)
Input select register (ADIS)
LCD controller/driver
Interrupt
464
Undefined
00H
Display mode register (LCDM)
00H
Display control register (LCDC)
00H
Request flag register (IF0L, IF0H, IF1L)
00H
Mask flag register (MK0L, MK0H, MK1L)
FFH
Priority specify flag register (PR0L, PR0H, PR1L)
FFH
External interrupt mode register (INTM0, INTM1)
00H
Key return mode register (KRM)
02H
Sampling clock select register (SCS)
00H
CHAPTER 23 µPD78P0308, 78P0308Y
The µPD78P0308, 78P0308Y replace the internal mask ROM of the µPD780308, 780308Y with one-time PROM
or EPROM. Table 23-1 lists the differences among the µPD78P0308, 78P0308Y and the mask ROM versions
(µPD780306, 780306Y, 780308, 780308Y) .
Table 23-1. Differences among µPD78P0308, 78P0308Y, and Mask ROM Versions
Item
Note
µPD78P064, 78P064Y
Mask ROM versions
ROM structure
One-time PROM/EPROM
Mask ROM
ROM capacity
60 Kbytes
µPD780306, 780306Y: 48 Kbytes
µPD780308, 780308Y: 60 Kbytes
Changing internal ROM
capacity by memory size
select register
Possible Note
Impossible
IC pin
None
Available
VPP pin
Available
None
On-chip mask option
split resistors for LCD
driving power supply
None
Available
Electrical characteristics
Refer to Data Sheet of individual model.
The internal PROM capacity is set to 60 Kbytes at RESET.
Caution PROM versions and mask ROM versions differ in their noise tolerance and noise emission. If
replacing PROM versions with mask ROM versions when switching from test production to mass
production, be sure to perform sufficient evaluation with CS versions (not ES version) of mask
ROM versions.
465
CHAPTER 23
µPD78P0308, 78P0308Y
23.1 Internal Memory Size Switching Register
The µPD78P0308, 78P0308Y allows users to define its internal ROM and high-speed RAM sizes using the internal
memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a
different-size internal ROM and high-speed RAM is possible.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Figure 23-1. Internal Memory Size Switching Register Format
Symbol
7
6
5
IMS RAM2 RAM1 RAM0
4
0
3
2
1
0
Other than above
Address
After
Reset
R/W
FFF0H
CFH
R/W
Internal High-Speed RAM Capacity Selection
1024 bytes
Setting prohibited
ROM3 ROM2 ROM1 ROM0
Internal ROM Capacity Selection
1
1
0
0
48 Kbytes
1
1
1
1
60 Kbytes
Other than above
0
ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0
1
1
Setting prohibited
The IMS settings to give the same memory map as mask ROM versions are shown in Table 23-2.
Table 23-2. Examples of Internal Memory Size Switching Register Settings
Relevant Mask ROM Version
466
IMS Setting
µPD780306, 780306Y
CCH
µPD780308, 780308Y
CFH
CHAPTER 23
µPD78P0308, 78P0308Y
23.2 Internal Expansion RAM Size Switching Register
The µPD78P0308 and 78P0308Y can select the internal expansion RAM size by using the internal expansion RAM
size switching register (IXS). By setting IXS, the memory mapping of the µPD78P0308 and 78P0308Y can be made
the same as that of the mask ROM models with a different internal expansion RAM capacity.
IXS is set with an 8-bit memory manipulation instruction.
RESET input sets IXS to 0AH.
Figure 23-2. Internal Expansion RAM Size Switching Register Format
Symbol
7
6
5
4
IXS
0
0
0
0
3
2
1
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
1
0
1
0
Other than above
0
Address
After
Reset
R/W
FFF4H
0AH
W
Internal ROM Capacity Selection
1024 bytes
Setting prohibited
The IXS settings to give the same memory map as mask ROM versions are shown in Table 23-3.
Table 23-3. Examples of Internal Expansion RAM Size Switching Register
Relevant Mask ROM Version
µPD780306, 780306Y
IXS Setting
0AH
µPD780308, 780308Y
467
CHAPTER 23
µPD78P0308, 78P0308Y
23.3 PROM Programming
The µ PD78P0308 and 78P0308Y each incorporate a 60-Kbyte PROM as program memory. To write a
program into the µ PD78P0308 or 78P0308Y PROM, make the device enter the PROM programming mode by
setting the levels of the V PP and RESET pins as specified. For the connection of unused pins, see paragraph
(2) PROM programming mode in Section 1.5 or 2.5.
Caution Write the program in the range of addresses 0000H to EFFFH (specify the last address as
EFFFH.)
The program cannot be correctly written by a PROM programmer which does not have a write
address specification function.
23.3.1 Operating modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the µPD78P0308
and µPD78P0308Y are set to the PROM programming mode. This is one of the operating modes shown in Table
23-4 below according to the setting of the CE, OE, and PGM pins.
The PROM contents can be read by setting the read mode.
Table 23-4. PROM Programming Operating Modes
Pin
Operating mode
RESET
VPP
VDD
CE
OE
PGM
Page data latch
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High impedance
×
L
L
L
L
H
Data output
Output disabled
L
H
×
High impedance
Standby
H
×
×
High impedance
Read
+5 V
+5 V
D0 to D7
×: L or H
(1) Read mode
Read mode is set by setting CE to L and OE to L.
(2) Output disable mode
If OE is set to H, data output becomes high impedance and the output disable mode is set.
Therefore, if multiple µPD78P0308s or 78P0308Ys are connected to the data bus, data can be read from any
one device by controlling the OE pin.
468
CHAPTER 23
µPD78P0308, 78P0308Y
(3) Standby mode
Setting CE to H sets the standby mode.
In this mode, data output becomes high impedance irrespective of the status of OE.
(4) Page data latch mode
Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.
In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
(5) Page write mode
After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed
by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE = H and OE = H. After this, program
verification can be performed by setting CE to L and OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X ≤ 10).
(6) Byte write mode
A byte write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE = L and
OE = H. After this, program verification can be performed by setting OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X ≤ 10).
(7) Program verify mode
Setting CE to L, PGM to H, and OE to L sets the program verify mode.
After writing is performed, this mode should be used to check whether the data was written correctly.
(8) Program inhibit mode
The program inhibit mode is used when the OE pins, VPP pins and pins D0 to D7 of multiple µPD78P0308s
or 78P0308Ys are connected in parallel and any one of these devices must be written to.
The page write mode or byte write mode described above is used to perform a write. At this time, the write
is not performed on the device which has the PGM pin driven high.
469
CHAPTER 23
µPD78P0308, 78P0308Y
23.3.2 PROM write procedure
Figure 23-3. Page Program Mode Flowchart
Start
Address = G
VDD = 6.5 V, V PP = 12.5 V
G = Start address
X=0
N = Last address of program
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Address = Address + 1
Latch
X=X+1
No
X = 10?
0.1-ms Program Pulse
Yes
Fail
Verify 4 Bytes
Pass
No
Address = N?
Yes
VDD = 4.5 to 5.5 V, V PP = VDD
Pass
All bytes verified?
Fail
All Pass
End of Write
470
Defective Product
CHAPTER 23
µPD78P0308, 78P0308Y
Figure 23-4. Page Program Mode Timing
Page Data Latch
Page
Program
Program Verify
A2 to A16
A0, A1
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
471
CHAPTER 23
µPD78P0308, 78P0308Y
Figure 23-5. Byte Program Mode Flowchart
Start
Address = G
G = Start address
N = Last address of program
VDD = 6.5 V, V PP = 12.5 V
X=0
X=X+1
No
X = 10?
0.1-ms Program Pulse
Address = Address + 1
Verify
Yes
Fail
Pass
No
Address = N?
Yes
VDD = 4.5 to 5.5 V, V PP = VDD
Pass
All bytes verified?
Fail
All Pass
End of Write
472
Defective Product
CHAPTER 23
µPD78P0308, 78P0308Y
Figure 23-6. Byte Program Mode Timing
Program
Program Verify
A0 to A16
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1. Be sure to apply VDD before applying VPP, and cut it off after cutting VPP.
2. VPP must not exceed +13.5 V including overshoot voltage.
3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied
to the VPP pin may have an adverse affect on device reliability.
473
CHAPTER 23
µPD78P0308, 78P0308Y
23.3.3 PROM reading procedure
PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.
(1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in paragraph,
(2) PROM programming mode in Section 1.5 or 2.5.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of data to be read to pins A0 to A16.
(4) Read mode is entered.
(5) Data is output to pins D0 to D7.
The timing for steps (2) through (5) above is shown in Figure 23-7.
Figure 23-7. PROM Read Timing
A0 to A16
Address Input
CE (Input)
OE (Input)
Hi-Z
D0 to D7
474
Hi-Z
Data Output
CHAPTER 23
µPD78P0308, 78P0308Y
23.4 Erasure Procedure (µPD78P0308KL-T and 78P0308YKL-T Only)
With the µPD78P0308KL-T or 78P0308YKL-T, it is possible to erase ( or set all contents to FFH) the data contents
written in the program memory, and rewrite the memory.
The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter.
Typically, data is erased by 254-nm ultraviolet light rays. The minimum lighting level to completely erase the written
data is shown below.
• UV intensity × exposure time: 30 W.s/cm2 or more
• Exposure time: 40 minutes or more (using a 12 mW/cm2 ultraviolet lamp. A longer exposure time may be
required in case of deterioration of the ultraviolet lamp or dirt on the package window).
When erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube.
23.5 Opaque Film Masking the Window (µPD78P0308KL-T and 78P0308YKL-T Only)
To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from malfunction
due to light coming in through the erasure window, mask the window with opaque film after writing the EPROM.
23.6 Screening of One-Time PROM Versions
One-time PROM versions ( µ PD78P0308GC-8EU, 78P0308GF-3BA, and µ PD78P0308YGF-3BA) cannot
be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have
written data into the PROM, screening should be implemented by user: that is, store devices at high temperature
for one day as specified below, and verify their contents after the devices have returned to room temperature.
Storage Temperature
Storage Time
125°C
24 hours
For users who do not wish to implement screening by themselves, NEC provides such users with a charged
service in which NEC performs a series of processes from writing one-time PROMs and screening them to verifying
their contents for users by request. The PROM version devices which provide this service are called QTOPTM
microcontrollers. This service for the µPD78P0308 and 78P0308Y is under preparation. For details, please consult
an NEC sales representative.
475
[MEMO]
476
CHAPTER 24 INSTRUCTION SET
This chapter describes each instruction set of the µPD780308 and 780308Y Subseries as list table. For details
of its operation and operation code, refer to the 78K/0 Series User’s Manual—Instructions (U12326E).
477
CHAPTER 24
INSTRUCTION SET
24.1 Legends Used in Operation List
24.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more
description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and
must be described as they are. Each symbol has the following meaning.
• # : Immediate data specification
• !
: Absolute address specification
• $ : Relative address specification
• [ ] : Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $, and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 24-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol Note
sfrp
Special-function register symbol (16-bit manipulatable register even addresses only) Note
saddr
saddrp
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even address only)
addr16
addr11
addr5
0000H to FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H to 0FFFH Immediate data or labels
0040H to 007FH Immediate data or labels (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn
RB0 to RB3
Note
Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark
478
For special-function register symbols, refer to Table 5-3 Special-Function Register List.
CHAPTER 24
INSTRUCTION SET
24.1.2 Description of “operation” column
A
: A register; 8-bit accumulator
X
: X register
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
AX
: AX register pair; 16-bit accumulator
BC
: BC register pair
DE
: DE register pair
HL
: HL register pair
PC
: Program counter
SP
: Stack pointer
PSW
: Program status word
CY
: Carry flag
AC
: Auxiliary carry flag
Z
: Zero flag
RBS
: Register bank select flag
IE
: Interrupt request enable flag
NMIS : Non-maskable interrupt servicing flag
()
: Memory contents indicated by address or register contents in parentheses
×H, ×L : Higher 8 bits and lower 8 bits of 16-bit register
: Logical product (AND)
: Logical sum (OR)
: Exclusive logical sum (exclusive OR)
: Inverted data
addr16 : 16-bit immediate data or label
jdisp8 : Signed 8-bit data (displacement value)
24.1.3 Description of “flag operation” column
(Blank) : Not affected
0
: Cleared to 0
1
: Set to 1
×
: Set/cleared according to the result
R
: Previously saved value is restored
479
CHAPTER 24
INSTRUCTION SET
24.2 Operation List
Clock
Instruction
Mnemonic
Group
Operands
Byte
8-bit data
transfer
Flag
Operation
2
4
–
r ← byte
saddr, #byte
3
6
7
(saddr) ← byte
3
–
7
sfr ← byte
A, r
Note 3
1
2
–
A←r
r, A
Note 3
1
2
–
r←A
A, saddr
2
4
5
A ← (saddr)
saddr, A
2
4
5
(saddr) ← A
A, sfr
2
–
5
A ← sfr
sfr, A
2
–
5
sfr ← A
A, !addr16
3
8
9
A ← (addr16)
!addr16, A
3
8
9
(addr16) ← A
PSW, #byte
3
–
7
PSW ← byte
A, PSW
2
–
5
A ← PSW
PSW, A
2
–
5
PSW ← A
A, [DE]
1
4
5
A ← (DE)
[DE], A
1
4
5
(DE) ← A
A, [HL]
1
4
5
A ← (HL)
[HL], A
1
4
5
(HL) ← A
A, [HL + byte]
2
8
9
A ← (HL + byte)
[HL + byte], A
2
8
9
(HL + byte) ← A
A, [HL + B]
1
6
7
A ← (HL + B)
[HL + B], A
1
6
7
(HL + B) ← A
A, [HL + C]
1
6
7
A ← (HL + C)
[HL + C], A
1
6
7
(HL + C) ← A
1
2
–
A↔r
A, saddr
2
4
6
A ↔ (saddr)
A, sfr
2
–
6
A ↔ sfr
A, !addr16
3
8
10
A ↔ (addr16)
A, [DE]
1
4
6
A ↔ (DE)
A, [HL]
1
4
6
A ↔ (HL)
A, r
XCH
Note 2
r, #byte
sfr, #byte
MOV
Note 1
Note 3
A, [HL + byte]
2
8
10
A ↔ (HL + byte)
A, [HL + B]
2
8
10
A ↔ (HL + B)
A, [HL + C]
2
8
10
A ↔ (HL + C)
Z AC CY
×
×
×
×
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
480
CHAPTER 24
Clock
Instruction
Mnemonic
Group
16-bit
data
transfer
MOVW
Operands
Byte
Flag
Operation
Z AC CY
6
–
rp ← word
saddrp, #word
4
8
10
(saddrp) ← word
sfrp, #word
4
–
10
sfrp ← word
AX, saddrp
2
6
8
AX ← (saddrp)
saddrp, AX
2
6
8
(saddrp) ← AX
AX, sfrp
2
–
8
AX ← sfrp
2
–
8
sfrp ← AX
AX, rp
Note 3
1
4
–
AX ← rp
rp, AX
Note 3
1
4
–
rp ← AX
3
10
12
AX ← (addr16)
3
10
12
(addr16) ← AX
1
4
–
AX ↔ rp
2
4
–
A, CY ← A + byte
×
×
×
3
6
8
(saddr), CY ← (saddr) + byte
×
×
×
2
4
–
A, CY ← A + r
×
×
×
!addr16, AX
AX, rp
Note 3
A, #byte
saddr, #byte
A, r
8-bit
operation
Note 2
3
AX, !addr16
ADD
Note 1
rp, #word
sfrp, AX
XCHW
INSTRUCTION SET
Note 4
r, A
2
4
–
r, CY ← r + A
×
×
×
A, saddr
2
4
5
A, CY ← A + (saddr)
×
×
×
A, !addr16
3
8
9
A, CY ← A + (addr16)
×
×
×
A, [HL]
1
4
5
A, CY ← A + (HL)
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A + (HL + byte)
×
×
×
A, [HL + B]
2
8
9
A, CY ← A + (HL + B)
×
×
×
A, [HL + C]
2
8
9
A, CY ← A + (HL + C)
×
×
×
A, #byte
2
4
–
A, CY ← A + byte + CY
×
×
×
3
6
8
(saddr), CY ← (saddr) + byte + CY
×
×
×
2
4
–
A, CY ← A + r + CY
×
×
×
r, A
2
4
–
r, CY ← r + A + CY
×
×
×
A, saddr
2
4
5
A, CY ← A + (saddr) + CY
×
×
×
A, !addr16
3
8
9
A, CY ← A + (addr16) + CY
×
×
×
A, [HL]
1
4
5
A, CY ← A + (HL) + CY
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A + (HL + byte) + CY
×
×
×
A, [HL + B]
2
8
9
A, CY ← A + (HL + B) + CY
×
×
×
A, [HL + C]
2
8
9
A, CY ← A + (HL + C) + CY
×
×
×
saddr, #byte
A, r
Note 4
ADDC
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except "r = A"
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
481
CHAPTER 24
Clock
Instruction
Mnemonic
Group
Operands
Byte
A, #byte
saddr, #byte
A, r
SUB
Note 3
2
4
–
A, CY ← A – byte
×
×
×
3
6
8
(saddr), CY ← (saddr) – byte
×
×
×
2
4
–
A, CY ← A – r
×
×
×
Z AC CY
2
4
–
r, CY ← r – A
×
×
×
2
4
5
A, CY ← A – (saddr)
×
×
×
A, !addr16
3
8
9
A, CY ← A – (addr16)
×
×
×
A, [HL]
1
4
5
A, CY ← A – (HL)
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A – (HL + byte)
×
×
×
A, [HL + B]
2
8
9
A, CY ← A – (HL + B)
×
×
×
A, [HL + C]
2
8
9
A, CY ← A – (HL + C)
×
×
×
A, #byte
2
4
–
A, CY ← A – byte – CY
×
×
×
3
6
8
(saddr), CY ← (saddr) – byte – CY
×
×
×
2
4
–
A, CY ← A – r – CY
×
×
×
r, A
2
4
–
r, CY ← r – A – CY
×
×
×
A, saddr
2
4
5
A, CY ← A – (saddr) – CY
×
×
×
A, !addr16
3
8
9
A, CY ← A – (addr16) – CY
×
×
×
A, [HL]
1
4
5
A, CY ← A – (HL) – CY
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A – (HL + byte) – CY
×
×
×
A, [HL + B]
2
8
9
A, CY ← A – (HL + B) – CY
×
×
×
A, [HL + C]
2
8
9
A, CY ← A – (HL + C) – CY
×
×
×
A, #byte
2
4
–
A←A
×
3
6
8
(saddr) ← (saddr)
2
4
–
A←A
r, A
2
4
–
r←r
A, saddr
2
4
5
A←A
(saddr)
×
A, !addr16
3
8
9
A←A
(addr16)
×
A, [HL]
1
4
5
A←A
(HL)
×
Note 3
saddr, #byte
A, r
AND
Note 2
r, A
saddr, #byte
SUBC
Flag
Operation
Note 1
A, saddr
A, r
8-bit
operation
INSTRUCTION SET
Note 3
byte
byte
r
×
×
×
A
A, [HL + byte]
2
8
9
A←A
(HL + byte)
×
A, [HL + B]
2
8
9
A←A
(HL + B)
×
A, [HL + C]
2
8
9
A←A
(HL + C)
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
482
CHAPTER 24
Clock
Instruction
Mnemonic
Group
Operands
Byte
Note 2
2
4
–
A ← A byte
×
3
6
8
(saddr) ← (saddr) byte
×
2
4
–
A←A r
×
r, A
2
4
–
r←r A
×
A, saddr
2
4
5
A ← A (saddr)
×
A, !addr16
3
8
9
A ← A (addr16)
×
A, [HL]
1
4
5
A ← A (HL)
×
saddr, #byte
A, r
Note 3
2
8
9
A ← A (HL + byte)
×
A, [HL + B]
2
8
9
A ← A (HL + B)
×
A, [HL + C]
2
8
9
A ← A (HL + C)
×
A, #byte
2
4
–
A←A
×
3
6
8
(saddr) ← (saddr)
4
–
A←A
r, A
2
4
–
r←r
A, saddr
2
4
5
A←A
(saddr)
×
Note 3
byte
r
×
×
×
A
A, !addr16
3
8
9
A←A
(addr16)
×
A, [HL]
1
4
5
A←A
(HL)
×
A, [HL + byte]
2
8
9
A←A
(HL + byte)
×
A, [HL + B]
2
8
9
A←A
(HL + B)
×
A, [HL + C]
2
8
9
A←A
(HL + C)
×
A, #byte
2
4
–
A – byte
×
×
×
3
6
8
(saddr) – byte
×
×
×
2
4
–
A–r
×
×
×
r, A
2
4
–
r–A
×
×
×
A, saddr
2
4
5
A – (saddr)
×
×
×
A, !addr16
3
8
9
A – (addr16)
×
×
×
A, [HL]
1
4
5
A – (HL)
×
×
×
A, [HL + byte]
2
8
9
A – (HL + byte)
×
×
×
A, [HL + B]
2
8
9
A – (HL + B)
×
×
×
A, [HL + C]
2
8
9
A – (HL + C)
×
×
×
saddr, #byte
A, r
CMP
byte
2
A, r
XOR
Z AC CY
A, [HL + byte]
saddr, #byte
8-bit
operation
Flag
Operation
Note 1
A, #byte
OR
INSTRUCTION SET
Note 3
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
483
CHAPTER 24
Clock
Instruction
Mnemonic
Group
16-bit
operation
Multiply/
divide
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
AX, #word
3
6
–
AX, CY ← AX + word
×
×
×
SUBW
AX, #word
3
6
–
AX, CY ← AX – word
×
×
×
CMPW
AX, #word
3
6
–
AX – word
×
×
×
MULU
X
2
16
–
AX ← A × X
DIVUW
C
2
25
–
AX (Quotient), C (Remainder) ← AX ÷ C
r
1
2
–
r←r+1
×
×
saddr
2
4
6
(saddr) ← (saddr) + 1
×
×
r
1
2
–
r←r–1
×
×
saddr
2
4
6
(saddr) ← (saddr) – 1
×
×
INCW
rp
1
4
–
rp ← rp + 1
DECW
rp
1
4
–
rp ← rp – 1
ROR
A, 1
1
2
–
(CY, A7 ← A0, Am – 1 ← Am) × 1 time
×
ROL
A, 1
1
2
–
(CY, A0 ← A7, Am + 1 ← Am) × 1 time
×
RORC
A, 1
1
2
–
(CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time
×
ROLC
A, 1
1
2
–
(CY ← A7, A0 ← CY, A m + 1 ← Am) × 1 time
×
ROR4
[HL]
2
10
12
A3 – 0 ← (HL)3 – 0, (HL)7 – 4 ← A3 – 0,
(HL)3 – 0 ← (HL)7 – 4
ROL4
[HL]
2
10
12
A3 – 0 ← (HL)7 – 4, (HL)3 – 0 ← A3 – 0,
(HL)7 – 4 ← (HL)3 – 0
ADJBA
2
4
–
Decimal Adjust Accumulator after
Addition
×
×
×
ADJBS
2
4
–
Decimal Adjust Accumulator after
Subtract
×
×
×
CY, saddr.bit
3
6
7
CY ← (saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← sfr.bit
×
CY, A.bit
2
4
–
CY ← A.bit
×
CY, PSW.bit
3
–
7
CY ← PSW.bit
×
×
Increment/
DEC
decrement
BCD
adjust
Operands
ADDW
INC
Rotate
INSTRUCTION SET
Bit
manipulate MOV1
CY, [HL].bit
2
6
7
CY ← (HL).bit
saddr.bit, CY
3
6
8
(saddr.bit) ← CY
sfr.bit, CY
3
–
8
sfr.bit ← CY
A.bit, CY
2
4
–
A.bit ← CY
PSW.bit, CY
3
–
8
PSW.bit ← CY
[HL].bit, CY
2
6
8
(HL).bit ← CY
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
484
CHAPTER 24
Clock
Instruction
Mnemonic
Group
AND1
OR1
XOR1
Bit
manipulate
SET1
CLR1
INSTRUCTION SET
Operands
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
CY, saddr.bit
3
6
7
CY ← CY
(saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← CY
sfr.bit
×
CY, A.bit
2
4
–
CY ← CY
A.bit
×
CY, PSW.bit
3
–
7
CY ← CY
PSW.bit
×
CY, [HL].bit
2
6
7
CY ← CY
(HL).bit
×
CY, saddr.bit
3
6
7
CY ← CY (saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← CY sfr.bit
×
CY, A.bit
2
4
–
CY ← CY A.bit
×
CY, PSW.bit
3
–
7
CY ← CY PSW.bit
×
CY, [HL].bit
2
6
7
CY ← CY (HL).bit
×
CY, saddr.bit
3
6
7
CY ← CY
(saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← CY
sfr.bit
×
CY, A.bit
2
4
–
CY ← CY
A.bit
×
CY, PSW.bit
3
–
7
CY ← CY
PSW.bit
×
CY, [HL].bit
2
6
7
CY ← CY
(HL).bit
×
saddr.bit
2
4
6
(saddr.bit) ← 1
sfr.bit
3
–
8
sfr.bit ← 1
A.bit
2
4
–
A.bit ← 1
PSW.bit
2
–
6
PSW.bit ← 1
[HL].bit
2
6
8
(HL).bit ← 1
saddr.bit
2
4
6
(saddr.bit) ← 0
sfr.bit
3
–
8
sfr.bit ← 0
A.bit
2
4
–
A.bit ← 0
×
×
×
×
×
×
PSW.bit
2
–
6
PSW.bit ← 0
[HL].bit
2
6
8
(HL).bit ← 0
SET1
CY
1
2
–
CY ← 1
1
CLR1
CY
1
2
–
CY ← 0
0
NOT1
CY
1
2
–
CY ← CY
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
485
CHAPTER 24
INSTRUCTION SET
Clock
Instruction
Mnemonic
Group
Operands
Byte
Note 1
Z AC CY
CALL
!addr16
3
7
–
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLF
!addr11
2
5
–
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,
PC15 – 11 ← 00001, PC10 – 0 ← addr11,
SP ← SP – 2
1
6
–
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
BRK
1
6
–
(SP – 1) ← PSW, (SP – 2) ← (PC + 1)H,
(SP – 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP – 3, IE ← 0
RET
1
6
–
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
1
6
–
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
R
R
RETB
1
6
–
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3
R
R R
PSW
1
2
–
(SP – 1) ← PSW, SP ← SP – 1
rp
1
4
–
(SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
PSW
1
2
–
PSW ← (SP), SP ← SP + 1
R
R
rp
1
4
–
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, #word
4
–
10
SP ← word
SP, AX
2
–
8
SP ← AX
CALLT
[addr5]
Call/return
PUSH
Stack
manipulate POP
MOVW
Unconditional
branch
Flag
Operation
Note 2
BR
AX, SP
2
–
8
AX ← SP
!addr16
3
6
–
PC ← addr16
$addr16
2
6
–
PC ← PC + 2 + jdisp8
AX
2
8
–
PCH ← A, PCL ← X
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if CY = 1
Conditional BNC
branch
BZ
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if CY = 0
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if Z = 0
BC
R
R
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
486
CHAPTER 24
Clock
Instruction
Mnemonic
Group
BT
BF
Conditional
branch
BTCLR
DBNZ
Operands
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
saddr.bit, $addr16
3
8
9
PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16
4
–
11
PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
8
–
PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
3
–
9
PC ← PC + 3 + jdisp8 if PSW.bit = 1
[HL].bit, $addr16
3
10
11
PC ← PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16
4
10
11
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16
4
–
11
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
8
–
PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16
4
–
11
PC ← PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr16
3
10
11
PC ← PC + 3 + jdisp8 if (HL).bit = 0
saddr.bit, $addr16
4
10
12
PC ← PC + 4 + jdisp8
if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16
4
–
12
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16
3
8
–
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16
4
–
12
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
[HL].bit, $addr16
3
10
12
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
B, $addr16
2
6
–
B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6
–
C ← C –1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr. $addr16
3
8
10
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
2
4
–
RBS1, 0 ← n
NOP
1
2
–
No Operation
EI
2
–
6
IE ← 1 (Enable Interrupt)
DI
2
–
6
IE ← 0 (Disable Interrupt)
HALT
2
6
–
Set HALT Mode
STOP
2
6
–
Set STOP Mode
SEL
CPU
control
INSTRUCTION SET
RBn
×
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC) register.
487
CHAPTER 24
INSTRUCTION SET
24.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
488
CHAPTER 24
INSTRUCTION SET
Second Operand
#byte
A
r Note
sfr
saddr
!addr16
PSW
[HL]
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
RORC
First Operand
A
r
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
MOV
[HL + byte]
[HL + B] $addr16
[HL + C]
[DE]
SUBC
ADDC
ADDC ADDC
ADDC ADDC
AND
SUB
SUB
SUB
OR
SUBC
SUBC SUBC
SUB
None
ROLC
SUB
SUBC SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
1
MOV
INC
ADD
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
DBNZ
sfr
MOV
MOV
saddr
MOV
MOV
ADD
DBNZ
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
MOV
PSW
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note
Except r = A
489
CHAPTER 24
INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
#word
AX
rp Note
sfrp
saddrp
!addr16
SP
None
First Operand
AX
ADDW
MOVW
SUBW
XCHW
MOVW
MOVW
MOVW
MOVW
CMPW
rp
MOVW
MOVW Note
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
MOVW
SP
MOVW
Note
MOVW
Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
First Operand
A.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
sfr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
saddr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
PSW.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
[HL].bit
MOV1
BT
SET1
BF
CLR1
BTCLR
CY
490
MOV1
MOV1
MOV1
MOV1
MOV1
SET1
AND1
AND1
AND1
AND1
AND1
CLR1
OR1
OR1
OR1
OR1
OR1
NOT1
XOR1
XOR1
XOR1
XOR1
XOR1
CHAPTER 24
INSTRUCTION SET
(4) Call/instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
AX
!addr16
!addr11
[addr5]
$addr16
First Operand
Basic instruction
BR
CALL
CALLF
CALLT
BR
BR
BC
BNC
BZ
BNZ
Compound
instruction
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
491
[MEMO]
492
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems which employ the µPD780308 and
780308Y Subseries. Figure A-1 shows the configuration example of the tools.
Figure A-1. Development Tool Configuration
Enbedded Software
PROM Programmer Control Software
• Real-time OS, OS
• Fuzzy Inference Development
Support System
• PG-1500 Controller
Language Processor Software
•
•
•
•
•
Assembler Package
C Compiler Package
C Library Source File
System Simulator
Screen Debugger or
Integrated Debugger
• Device File
Host Machine
(PC or EWS)
Interface Adapter
(Only When Integrated
Debugger is Used)
PROM Writing
Environment
In-Circuit Emulator
Interface Adapter
(Only When Integrated
Debugger is Used)
PROM
Progammer
Progammer
Adapter
Emulation Board
PROM-Contained
Model
Emulation Probe
Conversion Socket or
Conversion Adapter
Target System
493
APPENDIX A
A.1
DEVELOPMENT TOOLS
Language Processing Software
RA78K/0 (Assembler Package)
This assembler converts a program written in mnemonics into an object code
executable with a microcontroller.
Further, this assembler is provided with functions capable of automatically
creating symbol tables and branch instruction optimization. This data file is
used together with DF780308 device file (option).
Part Number: µS××××RA78K0
CC78K/0 (C Compiler Package)
This compiler converts a program written in C language into an object code
executable with a microcontroller. This data file is used together with RA78K/
0 assembler package and DF780308 device file (option).
Part Number: µS××××CC78K0
DF780308 (Device File)
Note 1
File storing information peculiar to a device. This data file is used together
with RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0.
Part Number: µS××××DF78064 Note 2
CC78K/0-L (C Compiler Library Source File)
Source program of a function configuring object library included in CC78K/
0 C compiler. This file is necessary when customers change the object library
in CC78K/0 following their specifications.
Part Number: µS××××CC78K0-L
Notes 1. This device file can be used for any of RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0.
2. DF78064 is the package name of device file DF780308.
Remark
×××× of the part number differs depending on the host machine and OS used. Refer to the table below.
µS×××× RA78K0
µS×××× CC78K0
µS×××× DF780308
µS×××× CC78K0-L
××××
5A13
Host Machine
PC-9800 Series
OS
Medium
MS-DOS
5A10
3.5-inch 2HD
(ver. 3.30 to 6.2)
7B13
IBM PC/AT or
7B10
compatible machine
Note
Refer to Section A.4.
3.5-inch 2HC
5-inch 2HC
HP9000 Series
300TM
HP-UXTM
3P16
HP9000 Series
700TM
HP-UX (rel.9.01)
Digital audio tape (DAT)
3K15
SPARCstationTM
SunOSTM
Cartidge tape (QIC-24)
3M15
EWS4800 Series (RISC)
EWS-UX/V (rel.4.0)
3H15
Note
(rel.7.05B)
(rel.4.1.1)
Cartidge tape (QIC-24)
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
494
5-inch 2HD
APPENDIX A
DEVELOPMENT TOOLS
A.2 PROM Writing Tools
A.2.1 Hardware
PG-1500 PROM programmer
This PROM programmer can program PROM-contained single-chip microcontrollers in stand alone mode or under control of a host machine when an
accessory board and optional PROM programmer adapter are connected.
It can also program representative PROMs from 256K-bit to 4M-bit models.
PA-78P0308GC
PA-78P0308GF
PA-78P0308KL-T
PROM programmer adapter
This is a PROM programmer adapter for the µPD78P0308 and 78P0308Y and
is connected to the PG-1500.
PA-78P0308GC: For 100-pin plastic QFP (GC-SEU type)
PA-78P0308GF: For 100-pin plastic QFP (GF-3BA type)
PA-78P0308KL-T: For 100-pin ceramic WQFN (KL-T type)
A.2.2 Software
PG-1500 controller
This controller connects the PG-1500 and a host machine with a serial and
parallel interface, to control the PG-1500 on the host machine.
Part Number: µS××××PG1500
Remark
×××× of the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××PG1500
××××
5A13
Host Machine
PC-9800 Series
5A10
7B13
7B10
Note
OS
MS-DOS
(ver. 3.30 to 6.2)
IBM PC/AT or
compatible machine
Medium
3.5-inch 2HD
Note
Refer to Section A.4.
5-inch 2HD
3.5-inch 2HD
5-inch 2HC
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
495
APPENDIX A
A.3
DEVELOPMENT TOOLS
Debugging Tools
A.3.1
Hardware
IE-78000-R-A (in-circuit emulator)
This is an in-circuit emulator for debugging the hardware and software of an
(supporting integrated debugger)
application system using the 78K/0 Series. It supports the integrated debugger
(ID78K0). This emulator is used in combination with an interface adapter to
connect the emulation probe and host machine.
IE-70000-98-IF-B
(interface adapter)
This is an adapter necessary for using the PC-9800 Series (except the notebook
type) as the host machine of the IE-78000-R-A.
IE-70000-98N-IF
(interface adapter)
This is an adapter and a cable necessary for using the notebook type PC-9800
Series as the host machine of the IE-78000-R-A.
IE-70000-PC-IF-B
(interface adapter)
This is an adapter necessary for using the IBM PC/AT as the host machine of the
IE-78000-R-A.
IE-78000-R-SV3
(interface adapter)
This is an adapter and a cable necessary for using an EWS as the host machine
of the IE-78000-R-A and is connected to the board of the IE-78000-R-A.
It supports 10Base-5 as EthernetTM. To use the other modes, a commercially
available conversion adapter is necessary.
IE-78000-R (in-circuit emulator)
(supporting screen debugger)
This is an in-circuit emulator used to debug the hardware and software when
developing an application system using the 78K/0 Series. It supports the screen
debugger (SD78K/0), and is used in combination with an emulation probe.
This emulator is connected to a host machine and a PROM programmer for efficient
debugging.
IE-780308-R-EM
(emulation board)
This is a board to emulate the peripheral hardware peculiar to a device (2.0 to 5.5
V), and is used in combination with an in-circuit emulator.
EP-78064GC-R (emulation probe)
This is a probe to connect an in-circuit emulator and the target system. This probe
is for 100-pin plastic QFP (GC-8EU type).
One 100-pin conversion adapter, TGC-100SDW, which facilitates connection to
the target system, is supplied.
TGC-100SDW
(conversion adapter)
EP-78064GF-R (emulation probe)
EV-9200GF-100
(conversion socket)
EV-9900
Remark
This is a conversion adapter that connects a target system designed to mount 100pin plastic QFP (GC-8EU type) and the EP-78064GC-R. This conversion adapter
is a product of TOKYO ELETECH CORPORATION (Tokyo: (03) 5295-1661).
To purchase this product, contact an NEC dealer.
This is a probe that connects an in-circuit emulator and the target system. It is for
100-pin plastic QFP (GF-3BA type).
One 100-pin conversion socket, EV-9200GF-100, which facilitates connection to
the target system, is supplied.
This is a conversion socket that connects a target system designed to mount 100pin plastic QFP (GF-3BA type) and the EP-78064GF-R.
Instead of connecting the EP-78064GF-R, the µPD78P0308KL-T or 78P0308YKLT (ceramic WQFN) can be mounted.
This is a jig used to remove the µPD78P0308KL-T or 78P0308YKL-T from the EV9200GF-100.
The TGC-100SDW is available in one unit.
The EV-9200GF-100 is available in a set with one set consisting of five EV-9200GF-100s.
496
APPENDIX A
A.3.2
DEVELOPMENT TOOLS
Software (1/3)
SM78K0 (system simulator)
This simulator can debug the target system at the C source level or assembler
level while simulating the operation of the target system on the host machine.
The SM78K0 runs on Windows.
By using the SM78K0, the logic and performances of the application system
can be verified independently of hardware development even if an in-circuit
emulator is not used, so that the development efficiency can be enhanced and
the software quality can be improved.
This simulator is used in combination with an optional device file (DF780308).
Part Number: µS××××SM78K0
Remark
×××× of the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××SM78K0
××××
Host Machine
OS
Medium
Note
AA13
PC-9800 Series
MS-DOS (ver. 3.30 to 6.2)
+ Windows (ver. 3.0 and 3.1)
3.5-inch 2HD
AB13
IBM PC/AT or
compatible machine
(on Japanese Windows)
Refer to Section A.4.
3.5-inch 2HC
BB13
IBM PC/AT or
compatible machine
(on English Windows)
Note
3.5-inch 2HC
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
497
APPENDIX A
DEVELOPMENT TOOLS
A.3.2 Software (2/3)
ID78K0 (integrated debugger)
This is a control program to debug the 78K/0 Series.
It employs Windows on a personal computer and OSF/MotifTM as a graphical
user interface, and supplies appearance and operability conforming to them.
It also has reinforced debugging functions supporting C language, and the
trace result can be displayed at C language level by using the window
integrated function that associates the source program, disassemble display,
and memory display with trace result. In addition, by using function expansion
modules such as a task debugger and system performance analyzer, the
debugging efficiency of the program using real-time OS can be enhanced.
This debugger is used in combination with an optional device file (DF780308).
Part Number: µS××××ID78K0
Remark
×××× of the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××ID78K0
××××
Host Machine
OS
Medium
Note
AA13
PC-9800 Series
MS-DOS (ver. 3.30 to 6.2)
+ Windows (ver. 3.0 and 3.1)
3.5-inch 2HD
AB13
IBM PC/AT or
compatible machine
(on Japanese Windows)
Refer to Section A.4.
3.5-inch 2HC
BB13
IBM PC/AT or
compatible machine
(on English Windows)
3P16
HP9000 Series 700
3.5-inch 2HC
HP-UX (rel.9.01)
Digital audio
tape (DAT)
3K15
SPARCstation
SunOS (rel.4.1.1)
NEWSTM
NEWS-OSTM
3K13
3R16
3.5-inch 2HC
(RISC)
(6.1x)
3R13
3M15
Note
1/4-inch CGMT
3.5-inch 2HC
EWS4800 Series (RISC)
EWS-UX/V (rel.4.0)
Cartridge
tape (QIC-24)
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
498
Cartridge
tape (QIC-24)
APPENDIX A
DEVELOPMENT TOOLS
A.3.2 Software (3/3)
SD78K/0 (screen debugger)
This is a program to connect the IE-78000-R and the host machine with a
serial interface (RS-232-C) to control the IE-78000-R on the host machine.
It is used in combination with an optional device file (DF780308).
Part Number: µS××××SD78K0
DF780308
Note 1
(device file)
This file stores information peculiar to a device.
It is used in combination with optional RA78K/0, CC78K/0, SM78K0, ID78K0,
or SD78 K/0.
Part Number: µS××××DF78064 Note 2
Notes 1. The DF780308 can be used commonly with all the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/
0.
2. DF78064 is the package name of device file DF780308.
Remark
×××× of the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××SD78K0
µS××××DF780308
××××
5A13
Host Machine
PC-9800 Series
OS
MS-DOS (ver. 3.30 to 6.2)
5A10
7B13
7B10
Note
Medium
Note
3.5-inch 2HD
5-inch 2HD
IBM PC/AT or
compatible machine
Refer to Section A.4.
3.5-inch 2HC
5-inch 2HC
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
499
APPENDIX A
A.4
DEVELOPMENT TOOLS
Operating Systems for IBM PC
The following operating systems are available for IBM PC.
If SM78K0, ID78K0, and FE9200 (see Section B.2 Fuzzy Inference Development Support System) are to be
operated, Windows version 3.0 or 3.1 is also required.
OS
PC DOS
Version
Version 5.02 to 5.02
J6.1/V to J6.3/V Note
IBM DOSTM
J5.02/V Note
MS-DOS
Version 5.0 to 6.22
5.0/V to 6.2V Note
Note
Supports English versions only.
Caution The task swap function is not available with this software though the function is provided in MSDOS version 5.0 or later.
500
APPENDIX A
DEVELOPMENT TOOLS
A.5 Upgrading Other In-Circuit Emulators to In-Circuit Emulator for 78K/0 Series
If you already have an in-circuit emulator of the 78K Series or 75X/XL Series, you can upgrade the function of your
in-circuit emulator to that of the IE-78000-R or IE-78000-R-A for the 78K/0 Series by exchanging the break board
of your in-circuit emulator with the IE-78000-R-BK.
Table A-1. Upgrading Other In-Circuit Emulators to IE-78000-R
Series Name
In-circuit Emulator Owned
75X/XL Series
IE-75000-R Note, IE-75001-R
78K/I Series
IE-78130-R, IE-78140-R
78K/II Series
IE-78230-R Note, IE-78230-R-A,
Board to be Purchased
IE-78000-R-BK
IE-78240-R Note, IE-78240-R-A
78K/III Series
IE-78320-R Note, IE-78327-R,
IE-78330-R, IE-78350-R
Note
Maintenance parts
Table A-2. Upgrading Other In-Circuit Emulators to IE-78000-R-A
Series Name
In-circuit Emulator Owned
75X/XL Series
IE-75000-R Note 1, IE-75001-R
78K/I Series
IE-78130-R, IE-78140-R
78K/II Series
IE-78230-R Note 1, IE-78230-R-A,
Board to be Purchased
IE-78000-R-BK Note 2
IE-78240-R Note 1, IE-78240-R-A
78K/III Series
IE-78320-R Note 1, IE-78327-R,
IE-78330-R, IE-78350-R
78K/0 Series
IE-78000-R
— Note 2
Notes 1. Maintenance parts
2. Bring your in-circuit emulator to NEC to modify part of the housing and replacing the control trace board
with a supervisor board.
501
APPENDIX A
DEVELOPMENT TOOLS
Drawing for Conversion Adapter (TGC-100SDW)
Figure A-2. TGC-100SDW Drawing (For Reference Only) (Unit: mm)
A
B
X
N
L
M
V
F E D
H I J K
X
T
Protrusion height
W
C
O
PQR S
U
G
Y
Z
e
a
n
m
k
g
d
c
I
b
j
i
f
h
ITEM
A
note: Product of TOKYO ELETECH CORPORATION.
502
MILLIMETERS
INCHES
ITEM
21.55
0.848
a
MILLIMETERS
14.45
INCHES
0.569
B
0.5x24=12
0.020x0.945=0.472
b
1.85±0.25
0.073±0.010
C
D
0.5
0.5x24=12
0.020
0.020x0.945=0.472
c
d
3.5
2.0
0.138
0.079
E
F
15.0
21.55
0.591
0.848
e
f
3.9
0.25
0.154
0.010
G
φ 3.55
φ 0.140
g
φ 4.5
φ 0.177
H
I
10.9
13.3
0.429
0.524
h
i
16.0
1.125±0.3
0.630
0.044±0.012
J
K
15.7
18.1
0.618
0.713
j
k
0~5°
5.9
0.000~0.197°
0.232
0.031
L
13.75
0.541
l
0.8
M
0.5x24=12.0
0.020x0.945=0.472
m
2.4
0.094
N
O
1.125±0.3
1.125±0.2
0.044±0.012
0.044±0.008
n
2.7
0.106
P
7.5
0.295
Q
R
10.0
11.3
0.394
0.445
S
18.1
0.713
T
φ 5.0
φ 0.197
U
5.0
0.197
V
4- φ 1.3
4-φ 0.051
W
1.8
0.071
X
C 2.0
C 0.079
Y
Z
φ 0.9
φ 0.3
φ 0.035
φ 0.012
TGC-100SDW-G1E
APPENDIX A
DEVELOPMENT TOOLS
Drawing and Footprint for Conversion Socket (EV-9200GF-100)
Figure A-3. EV-9200GF-100 Drawing (For Reference Only) (Unit: mm)
A
B
E
M
N
O
L
K
S
J
D
C
R
F
EV-9200GF-100
Q
1
No.1 pin index
P
G
H
I
EV-9200GF-100-G0
ITEM
MILLIMETERS
INCHES
A
24.6
0.969
B
21
0.827
C
15
0.591
D
18.6
0.732
E
4-C 2
4-C 0.079
F
0.8
0.031
G
12.0
0.472
H
22.6
0.89
I
25.3
0.996
J
6.0
0.236
K
16.6
0.654
L
19.3
0.76
M
8.2
0.323
N
8.0
0.315
O
2.5
0.098
P
2.0
0.079
Q
0.35
0.014
R
φ 2.3
φ 0.091
S
φ 1.5
φ 0.059
503
APPENDIX A
DEVELOPMENT TOOLS
Figure A-4. EV-9200GF-100 Footprint (For Reference Only) (Unit: mm)
G
J
H
D
F
E
K
I
L
C
B
A
EV-9200GF-100-P1
ITEM
MILLIMETERS
A
26.3
B
21.6
1.035
0.85
C
0.65±0.02 × 29=18.85±0.05
D
+0.003
0.65±0.02 × 19=12.35±0.05 0.026+0.001
–0.002 × 0.748=0.486 –0.002
0.026+0.001
–0.002
× 1.142=0.742+0.002
–0.002
E
15.6
0.614
F
20.3
0.799
G
12 ± 0.05
0.472+0.003
–0.002
H
6 ± 0.05
0.236+0.003
–0.002
I
0.35 ± 0.02
0.014+0.001
–0.001
J
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
K
φ 2.3
φ 0.091
L
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
504
INCHES
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).
APPENDIX B
EMBEDDED SOFTWARE
This section describes the embedded software which are provided for the µPD780308 and 780308Y Subseries
to allow users to develop and maintain the application program for these subseries.
B.1
Real-time OS (1/2)
RX78K/0 is a real-time OS which is based on the µITRON specification.
RX78K/0
Real-Time OS
Supplied with the RX78K/0 nucleus and a tool to prepare multiple information tables (configurator). When
using the RX78K/0, the RA78K/0 assembler package and the DF780308 device file (options) are necessary.
Part Number: µS××××RX78013-∆∆∆∆
Caution When purchasing the RX78K/0, fill in the purchase application form in advance, and sign the Use
Approval Contract.
Remark
×××× and ∆∆∆∆ of the part number differs depending on the host machine and OS used. Refer to the
table below.
µS××××RX78013-∆∆∆∆
∆∆∆∆
Product outline
Max. No. for use in mass production
001
Evaluation object
Do not use for mass production
100K
Mass-production object
100,000
001M
1,000,000
010M
10,000,000
S01
××××
5A13
Source program
Source program for mass-production object
Host Machine
PC-9800 Series
5A10
OS
Medium
MS-DOS
3.5-inch 2HD
(ver. 3.30 to 6.2) Note
5-inch 2HD
Refer to Section A.4.
3.5-inch 2HC
7B13
IBM PC/AT or
7B10
compatible machine
3H15
HP9000 Series 300
HP-UX (rel.7.05B)
Cartridge tape (QIC-24)
3P16
HP9000 Series 700
HP-UX (rel.9.01)
Digital tape (DAT)
3K15
SPARCstation
SunOS (rel.4.1.1)
Cartridge tape (QIC-24)
3M15
EWS4800 Series (RISC)
EWS-UX/V (rel.4.0)
Note
5-inch 2HC
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
505
APPENDIX B
EMBEDDED SOFTWARE
B.1 Real-time OS (2/2)
MX78K0 OS
MX78K/0 is an OS for subsets based on the µITRON specification.
Supplied with the MX78K0 nucleus. This OS manages tasks, events, and time. In task management
operation, it controls the execution orders of tasks, and switches processing to the task to be executed next.
Part Number: µS××××MX78K0-∆∆∆
Remark
×××× and ∆∆∆ of the part number differs depending on the host machine and OS used. Refer to the
table below.
µS××××MX78K0-∆∆∆
∆∆∆
Product outline
Remark
001
Evaluation object
Use for preproduction.
xx
Mass-production object
Use for mass-production.
S01
Source program
Available only when purchasing mass-production
object
××××
5A13
Host Machine
PC-9800 Series
5A10
7B13
IBM PC/AT or
compatible machine
OS
MS-DOS
3.5-inch 2HD
(ver. 3.30 to 6.2) Note
5-inch 2HD
Refer to Section A.4.
3.5-inch 2HC
7B10
5-inch 2HC
3H15
HP9000 Series 300
HP-UX (rel.7.05B)
Cartridge tape (QIC-24)
3P16
HP9000 Series 700
HP-UX (rel.9.01)
Digital tape (DAT)
3K15
SPARCstation
SunOS (rel.4.1.1)
Cartridge tape (QIC-24)
3M15
EWS4800 Series (RISC)
EWS-UX/V (rel.4.0)
Note
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
506
Medium
APPENDIX B
B.2
EMBEDDED SOFTWARE
Fuzzy Inference Development Support System
FE9000/FE9200 (Fuzzy Knowledge Data Creation tool)
Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing
(edit), and evaluation (simulation). FE9200 operates on Windows.
µS××××FE9000 (PC-9800 Series)
Part number:
µS××××FE9200 (IBM PC/AT or compatible machine)
FT9080/FT9085 (Translator)
Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to
RA78K/0 assembler source program.
µS××××FT9080 (PC-9800 Series)
Part number:
µS××××FT9085 (IBM PC/AT or compatible machine)
FI78K0 (Fuzzy Inference Module)
Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge data
converted by translator.
µS××××FI78K0 (PC-9800 Series, IBM PC/AT or compatible machine)
Part number:
FD78K0 (Fuzzy Inference Debugger)
Support software evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit
emulator.
Part number:
Remark
µS××××FD78K0 (PC-9800 Series, IBM PC/AT or compatible machine)
×××× of the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××FE9000
µS××××FT9080
µS××××FI78K0
µS××××FD78K0
××××
5A13
Host Machine
PC-9800 Series
OS
MS-DOS
Medium
3.5-inch 2HD
(ver. 3.30 to 6.2) Note
5A10
5-inch 2HD
µS××××FE9200
µS××××FT9085
µS××××FI78K0
µS××××FD78K0
××××
7B13
Host Machine
IBM PC/AT
OS
Refer to Section A.4.
Medium
3.5-inch 2HC
or compatible machine
7B10
Note
5-inch 2HC
The task swap function is not available with this software though the
function is provided in MS-DOS version 5.0 or later.
507
[MEMO]
508
APPENDIX C REGISTER INDEX
C.1
Register Name Index
[A]
A/D converter input select register (ADIS) ... 230
A/D converter mode register (ADM) ... 228
A/D conversion result register (ADCR) ... 227
Asynchronous serial interface status register (ASIS) ... 352, 362
Asynchronous serial interface mode register (ASIM) ... 349, 359, 361, 375
[B]
Baud rate generator control register (BRGC) ... 353, 363, 376
[C]
Capture/compare control register 0 (CRC0) ... 144
Capture/compare register 00 (CR00) ... 138
Capture/compare register 01 (CR01) ... 138
Compare register 10 (CR10) ... 181
Compare register 20 (CR20) ... 181
[E]
8-bit timer mode control register (TMC1) ... 184
8-bit timer output control register (TOC1) ... 185
8-bit timer register 1 (TM1) ...
181
8-bit timer register 2 (TM2) ...
181
External interrupt mode register 0 (INTM0) ... 147, 433
External interrupt mode register 1 (INTM1) ... 231, 433
[I]
Internal expansion RAM size switching register (IXS) ... 467
Interrupt mask flag register 0H (MK0H) ... 431
Interrupt mask flag register 0L (MK0L) ... 431
Interrupt mask flag register 1L (MK1L) ... 431, 449
Interrupt request flag register 0H (IF0H) ... 430
Interrupt request flag register 0L (IF0L) ... 430
Interrupt request flag register 1L (IF1L) ... 430, 449
Interrupt timing specify register (SINT) ... 253, 270, 303, 313, 324
[K]
Key return mode register (KRM) ... 112, 450
509
APPENDIX C
REGISTER INDEX
[L]
LCD display control register (LCDC) ... 401
LCD display mode register (LCDM) ... 398
[M]
Memory size switching register (IMS) ... 466
[O]
Oscillation mode select register (OSMS) ... 120
Oscillation stabilization time select register (OSTS) ... 454
[P]
Port 0 (P0) ...
Port 1 (P1) ...
92
94
Port 2 (P2) ... 95, 97
Port 3 (P3) ... 99
Port 7 (P7) ... 100
Port 8 (P8) ... 102
Port 9 (P9) ... 103
Port 10 (P10) ... 104
Port 11 (P11) ... 105
Port mode register 0 (PM0) ... 108
Port mode register 1 (PM1) ... 108
Port mode register 2 (PM2) ... 108
Port mode register 3 (PM3) ... 108, 146, 186, 219, 224
Port mode register 7 (PM7) ... 108
Port mode register 8 (PM8) ... 108
Port mode register 9 (PM9) ... 108
Port mode register 10 (PM10) ... 108
Port mode register 11 (PM11) ... 108
Priority specify flag register 0H (PR0H) ... 432
Priority specify flag register 0L (PR0L) ... 432
Priority specify flag register 1L (PR1L) ... 432
Processor clock control register (PCC) ... 117
Pull-up resistor option register H (PUOH) ... 111
Pull-up resistor option register L (PUOL) ... 111
[R]
Receive buffer register (RXB) ... 347
510
APPENDIX C
REGISTER INDEX
[S]
Sampling clock select register (SCS) ... 148, 435
Serial bus interface control register (SBIC) ... 251, 256, 268, 287, 301, 307, 312, 322
Serial I/O shift register 0 (SIO0) ... 246, 296
Serial I/O shift register 3 (SIO3) ... 387
Serial interface pin select register (SIPS) ... 357, 367
Serial operating mode register 0 (CSIM0) ... 249, 255, 267, 286, 299, 306, 311, 321
Serial operating mode register 2 (CSIM2) ... 348, 358, 360, 374
Serial operating mode register 3 (CSIM3) ... 389
16-bit timer mode control register (TMC0) ... 142
16-bit timer output control register (TOC0) ... 145
16-bit timer register (TM0) ... 139
Slave address register (SVA) ... 246, 296
[T]
Timer clock select register 0 (TCL0) ... 140, 217
Timer clock select register 1 (TCL1) ... 182
Timer clock select register 2 (TCL2) ... 202, 210, 222
Timer clock select register 3 (TCL3) ... 248, 298
Timer clock select register 4 (TCL4) ... 387
Transmit shift register (TXS) ... 347
[W]
Watch timer mode control register (TMC2) ... 205
Watchdog timer mode register (WDTM) ... 212
511
APPENDIX C
C.2
REGISTER INDEX
Register Symbol Index
[A]
ADCR: A/D conversion result register
... 227
ADIS: A/D converter input select register
ADM: A/D converter mode register
... 230
... 228
ASIM: Asynchronous serial interface mode register
... 349, 359, 361, 375
ASIS: Asynchronous serial interface status register ... 352, 362
[B]
BRGC: Baud rate generator control register
... 353, 363, 376
[C]
CR00: Capture/compare register 00
... 138
CR01: Capture/compare register 01
... 138
CR10: Compare register 10
... 181
CR20: Compare register 20
... 181
CRC0: Capture/compare control register 0
... 144
CSIM0: Serial operating mode register 0
... 249, 255, 267, 286, 299, 306, 311, 321
CSIM2: Serial operating mode register 2
... 348, 358, 360, 374
CSIM3: Serial operating mode register 3
... 389
[I]
IF0H: Interrupt request flag register 0H
... 430
IF0L: Interrupt request flag register 0L
... 430
IF1L: Interrupt request flag register 1L
... 430, 449
IMS: Memory size switching register
... 466
INTM0: External interrupt mode register 0
... 147, 433
INTM1: External interrupt mode register 1
... 231, 433
IXS: Internal expansion RAM size switching register
[K]
KRM: Key return mode register
... 112, 450
[L]
LCDC: LCD display control register
LCDM: LCD display mode register
... 401
... 398
[M]
MK0H: Interrupt mask flag register 0H
... 431
MK0L: Interrupt mask flag register 0L ... 431
MK1L: Interrupt mask flag register 1L
512
... 431, 449
... 467
APPENDIX C
REGISTER INDEX
[O]
OSMS: Oscillation mode select register
... 120
OSTS: Oscillation stabilization time select register
...
454
[P]
P0: Port 0
... 92
P1: Port 1
... 94
P2: Port 2
... 95, 97
P3: Port 3
... 99
P7: Port 7
... 100
P8: Port 8
... 102
P9: Port 9
... 103
P10: Port 10
... 104
P11: Port 11
... 105
PCC: Processor clock control register
... 117
PM0: Port mode register 0
... 108
PM1: Port mode register 1
... 108
PM2: Port mode register 2
... 108
PM3: Port mode register 3
... 108, 146, 186, 219, 224
PM7: Port mode register 7
... 108
PM8: Port mode register 8
... 108
PM9: Port mode register 9
... 108
PM10: Port mode register 10
... 108
PM11: Port mode register 11
... 108
PR0H: Priority specification flag register 0H
... 432
PR0L: Priority specification flag register 0L
... 432
PR1L: Priority specification flag register 1L
... 432
PUOH: Pull-up resistor option register H
... 111
PUOL: Pull-up resistor option register L
... 111
[R]
RXB: Receive buffer register
... 347
[S]
SBIC: Serial bus interface control register
SCS: Sampling clock select register
SINT: Interrupt timing specify register
... 251, 256, 268, 287, 301, 307, 312, 322
... 148, 435
... 253, 270, 303, 313, 324
SIO0: Serial I/O shift register 0
... 246, 296
SIO3: Serial I/O shift register 3
... 387
SIPS: Serial interface pin select register
SVA: Slave address register
... 357, 367
... 246, 296
513
APPENDIX C
REGISTER INDEX
[T]
TCL0: Timer clock select register 0
... 140, 217
TCL1: Timer clock select register 1
... 182
TCL2: Timer clock select register 2
... 202, 210, 222
TCL3: Timer clock select register 3
... 248, 298
TCL4: Timer clock select register 4
... 387
TM0: 16-bit timer register
...
139
TM1: 8-bit timer register 1
... 181
TM2: 8-bit timer register 2
... 181
TMC0: 16-bit timer mode control register
TMC1: 8-bit timer mode control register
... 142
... 184
TMC2: Watch timer mode control register
... 205
TOC0: 16-bit timer output control register
... 145
TOC1: 8-bit timer output control register
TXS: Transmit shift register
... 185
... 347
[W]
WDTM: Watchdog timer mode register ... 212
514
APPENDIX D REVISION HISTORY
The revision history of this document is shown below. “Chapter” indicates the chapter of the previous edition where
revision was made.
(1/2)
Edition
2nd editon
Major Revision from Previous Edition
Chapter
Addition of “ µ PD780306(A), 780308(A) ... under planning”
Change of package as follows:
• Deletion of 100-pin plastic QFP (GC-7EA type)
• Addition of 100-pin plastic QFP (GC-8EU type)
Change of minimum supply voltage from 1.8 to 2.0 V
Throughout
• Addition of description on following subseries to 1.6 78K/0 Series
Line-up
µ PD78075B, 78075BY, 780018, 780018Y, 780058, 780058Y,
780034, 780034Y, 780024, 780024Y, 78014H, 780964, 780924,
780228, 78044H, 78044F, 78098B, 780973, 78P0914
CHAPTER 1 OUTLINE
(µ PD780308 Subseries)
• 2.5 Pin Configuration
Addition of connection diagram of 100-pin plastic LQFP
(GC-8EU type)
CHAPTER 2 OUTLINE
(µ PD780308Y Subseries)
Correction of following text in
• 5.1.4 Data memory addressing
• 5.2.1 Control registers (a) Interrupt enable flag (IE),
(e) In-service priority flag (ISP)
• 5.3.1 Relative addressing
• 5.3.2 Immediate addressing
• 5.3.3 Table indirect addressing
• 5.4.2 Register addressing
• 5.4.6 Register indirect addressing
• 5.4.7 Based addressing
• 5.4.8 Based indexed addressing
CHAPTER 5 CPU
ARCHITECTURE
• 7.3 Clock Generator
Change of Figure 7-3
Addition of Table 7-2
Minimum Instruction
Control Register
CHAPTER 7 CLOCK
Processor Clock Control Register Format GENERATOR
Relation between CPU Clock and
Execution Time
• 9.4.1 8-bit timer/event counter mode
Addition of Figure 9-10 Square Wave Output Operation Timing
• Correction of text in 9.4.2 16-bit timer/event counter mode
Addition of Figure 9-13 Square Wave Output Operation Timing
CHAPTER 9 8-BIT TIMER/
EVENT COUNTERS 1 AND 2
• 11.2 Watchdog Timer Configuration
Change of Figure 11-1 Watchdog Timer Configuration
CHAPTER 11 WATCHDOG
TIMER
• 14.2 A/D Converter Configuration
Correction of Figure 14-1 A/D Converter Block Diagram
Addition of caution on voltage
CHAPTER 14 A/D
CONVERTER
• 15.1 Serial Interface Channel 0 Functions
Addition of caution on operation mode
CHAPTER 15 SERIAL
INTERFACE CHANNEL 0
• 15.3 Serial Interface Channel 0 Control Registers
Addition of caution on operation mode
(µ PD780308 Subseries)
515
APPENDIX D
REVISION HISTORY
(2/2)
Edition
2nd editon
Major Revision from Previous Edition
Chapter
• 16.1 Serial Interface Channel 0 Functions
Addition of caution on operation mode
CHAPTER 16 SERIAL
INTERFACE CHANNEL 0
• 16.3 Serial Interface Channel 0 Control Registers
(µ PD780308Y Subseries)
Addition of caution on operation mode
• 17.4.2 Asynchronous serial interface (UART) mode
Change of Figure 17-11 Receive Error Timing
Correction of note on (3) UART mode
CHAPTER 17 SERIAL INTER
FACE CHANNEL 2
• 17.4.3 3-wire serial I/O mode
Addition of Figure 17-14 Circuit of Switching in Transfer Bit
Order
• Addition of 17.4.4 Limitations of UART mode
• 18.4.2 3-wire serial I/O mode
Addition of description on selecting MSB/LSB first
Addition of Figure 18-5 Circuit of Switching in Transfer Bit
Order
CHAPTER 18 SERIAL INTER
FACE CHANNEL 3
• 20.3 Interrupt Function Control Registers
Change of Table 20-2 Various Flags Corresponding to
Interrupt Request Sources
CHAPTER 20 INTERRUPT
AND TEST FUNCTIONS
• 20.4 Interrupt Request Servicing Operations
Correction of Figure 20-11 Non-Maskable Interrupt
Acknowledge Timing
Correction of Figure 20-12 Non-Maskable Interrupt Request
Acknowledge Operation
Addition of description on flags to Figure 20-13 Interrupt
Request Acknowledge Processing Algorithm
• Correction of text in 20.4.4 Multiple interrupt servicing
Correction of Figure 20-16 Multiple Interrupt Example
• Correction of text in 20.4.5 Interrupt reserve
• 20.5 Test Functions
Correction of text in 20.5.2 Test input signal acknowledge
operation
• A.1 Language Processing Software
Change of part number of device file from “DF780308” to
“DF78064”
• A.3 Debugging Tools
A.3.1 Hardware
Change of conversion adapter name from “EV-9500GC-100” to
“TGC-100SDW”
Deletion of 5-inch supply media supporting Windows
516
APPENDIX A DEVELOPMENT
TOOLS
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