VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Features • Redundant High Speed I/O • Serializes 16 Inputs at 155.52Mb/s onto a 2.488Gb/s Serial Output • Suitable for Both Coaxial and Optical Link Applications • Deserializes a 2.488Gb/s Serial Input to 16 155.52Mb/s Outputs • Low Power Operation - 2.5 W Max • Clock Multiplier generates 2.488 GHz clock from 77.76 or 155.52 MHz Reference Clock • Single +3.3V Supply • 100 Pin, 14 mm Thermally Enhanced PQFP • Digital Clock Recovery Unit has Automatic Lock-to-Reference Function General Description The VSC7164 is a 2.488Gb/s transceiver optimized for non-SONET Telecom applications. It accepts 16 155.52Mb/s serial inputs streams, latches them on the rising edge of BCLK, which runs at 155.52 MHz, and serializes the data onto the high speed differential outputs at a 2.488Gb/s. The VSC7164 also samples serial receive data on the high speed differential inputs, recovers the clock and data, deserializes it onto 16 serial outputs at 155.52Mb/s and outputs a recovered clocks at 155.52 MHz. The VSC7164 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock and extraction of the clock from the received serial stream. Redundant high speed I/O are controlled by separate enables for the dual transmitters and a single select line for the dual receivers. A loopback mode is provided for on-board self-test functionality. A mode control input configures the reference clock speed to 77.76 or 155.52 MHz. VSC7164 Block Diagram LPBK Serial Data (2.488Gb/s) 16 R0:15 QD 155.52Mb/s Serial to Parallel Retimed Data QD Clock Recovery 4:1 Recovered Clock RBC+ RBC- ÷ 16 RXA+ RXARXB+ RXBSELB 155.52 MHz 16 T0:15 155.52Mb/s SYNC BCLK+ BCLK- In Reg. Parallel to Serial Serial Data (2.488Gb/s) DQ Synthesized Clock (2.488GHz) 155.52 MHz ENTXB Divider 155.52 MHz REFCLK+ REFCLKREFMODE G52244-0, Rev. 1.5 02/18/99 ENTXA TXA+ TXATXB+ TXB- 155.52 or 77.76 MHz TCLKO+ TCLKO- CMU x16/x32 1 = 155.52 MHz 0 = 77.76 MHz VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s 16:1 / 1:16 Transceiver Target Specification VSC7164 Functional Description Clock Multiplier Unit (CMU): The VSC7164 clock synthesizer multiplies the differential LVPECL reference clock on REFCLK+/REFCLK- (aka REFCLK) by either 16 or 32 (as selected by the REFMODE input) to generate the 2.488 GHz baud rate clock. For proper operation, REFCLK should be either 155.52 MHz (selected when REFMODE=HIGH) or 77.76 MHz (selected when REFMODE=LOW). The VSC7164 will not operate properly if the correct configuration is not used. The CMU multiplies REFCLK then divides it by 16 or 32 (REFMODE = 1 or 0 respectively) to produce TCLKO at 155.52 MHz, which is then sent through an output LVPECL driver. This CMU contains a fully monolithic PLL which does not require any external components. Because REFCLK is used for generating the timing to the entire communications channel, a stable, low-jitter REFCLK should be provided to minimize output jitter and maximize jitter tolerance. Serializer: The VSC7164 accepts sixteen 155.52Mb/s single-ended, LVPECL input data (T0:15) on the rising edge of the differential LVPECL input clock, BCLK+/BCLK-. The frequency of BCLK has to match the T0:15 data bus frequency, that is at 155.52 MHz. This data is then serialized in a 16:1 multiplexer for transmission as a serial output at 2.488Gb/s. T0 is transmitted first. The Clock Multiplier unit aligns a internally generated 155.52 MHz clock with the rising edges of BCLK in order to latch T0:15 into the input register. The serializer accepts a SYNC input signal that, when active, will cause the T0:15 bus to be bypassed and have an internally-generated alternating 0101... bit pattern serialized instead (hex character $5555). The synch pattern will continuously be serialized until SYNC is disabled. Two high-speed transmit outputs are provided, TXA which is selctable by ENTXA and TXB which is selectable by ENTXB. Both outputs function identically and are redundant channels. On-chip termination resistors are provided at the high-speed transmit outputs TXA and TXB at nominally 50 ohms so that no additional components are required externally. Clock Recovery Unit (CRU): The VSC7164 accepts differential high speed serial inputs from three potential sources: RXA, RXB and the internal transmitter. If LPBK is HIGH, the CRU input comes from the internal transmitter. If LPBK is LOW, the CRU input comes from RXA or RXB, depending on SELB. If SELB is HIGH then RXB is chosen as the input. If SELB is LOW then RXA is the chosen input. The digital CRU recovers the clock from the data source and then extracts the data. Recovered serial data is then passed onto the deserializer. The recovered clock is used to time the deserializer and a divided-by-16 version of the recovered clock is output on RBC in order to synchronize the deserialized recovered data. Deserializer: The retimed serial bit stream is deserialized into 16 LVPECL outputs which are aligned with the rising edge of RBC. No framing of the data occurs so data on R0:15 will not appear in the same bit location as it was sent on T0:15. If serial input data is not present the VSC7164 will continue to produce a recovered clock and RBC will automatically lock to the REFCLK. This eliminates the need for a Lock-to-Reference input pin and simplifies the support software for that function. Page 2 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 AC Characteristics Figure 1: Transmit Timing Waveforms BCLK+ BCLKT2 T1 T0:15 16 Bit Data Data Valid Data Valid Data Valid Table 1: Transmit AC Characteristics Parameters Description Min Max Units T1 T0:15 Setup time to the rising edge of BCLK 1.5 — ns. T2 T0:15 hold time after the rising edge of BCLK 1.0 — ns. TSDR,TSDF TX+/TX- rise and fall time 75 160 ps. TLAT Latency from rising edge of BCLK to T0 appearing on TX+/TX- - 20bc + 1ns — 8 Conditions Measured between the valid data level of T0:15 to the midpoint of BCLK Between VOH(min) and VOL(max) Bit Clock Periods (PLL locked.) bc = bit clocks (This is an estimate) Transmitter Output Jitter Allocation TRJ TDJ G52244-0, Rev. 1.5 02/18/99 Serial data output random jitter (RMS) Serial data output deterministic jitter (p-p) — 60 ps. RMS, tested on a 11110000 repeating pattern. ps. Peak to peak, tested with a PRBS 231-1 pattern. (NOTE: This is estimated from measured performance of the VSC7146) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 3 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Figure 2: Receive Timing Waveforms RBC+ RBCT1 R0:15 Data Valid Data Valid Data Valid Table 2: Receive AC Characteristics Parameters Min. Max. Units Conditions T1 Delay from rising edge of RBC to R[0:15] -0.3 1.2 ns. Measured between the midpoint of RBC’s rising edge and a valid level of R0:15. All outputs driving 50Ω load. TRR, TFR R[0:15] rise and fall time - 0.30 ns. 20% to 80% into a 50Ω load. RBC rise and fall time - 0.25 ns. 20% to 80% into a 50Ω load. Rlat Latency from RX to R0:15 - 32 Bit Clocks DC RBC Duty Cycle 40% 60% period TRRBC, TFRBC When locked to valid data. (This is an estimate) Tested on a sample basis. This reflects a 99.9% probability of recovery for data aquisition with a 101010... pattern as input to the receiver. Data acquisition lock time @ 2.488Gb/s — 1250 Bit Clocks TJTD Total receive jitter tolerance (p-p) — 0.74 UI IEEE 802.3Z Clause 38.68, tested on a sampled basis DJTD Total deterministic jitter tolerance (p-p) — 0.46 UI IEEE 802.3Z Clause 38.69, tested on a sampled basis TLOCK Page 4 Description VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Figure 3: BCLK, REFCLK and TCLKO Timing Waveforms TH Vih(min) REFCLK BCLK Vil(max) TL T2 REFCLK T1 BCLK Table 3: BCLK, REFCLK and TCLKO AC Characteristics Parameters Description Min Max Units Conditions T1 Lag time between BCLK and REFCLK - 5.2 ns Measured from rising edge of REFCLK to rising edge of BCLK. T2 Lead time between BCLK and REFCLK - 1.2 ns Measured from rising edge of REFCLK to rising edge of BCLK FR Frequency Range for REFMODE=1 (top number) REFMODE=0 (bottom number) 155 77.5 156 78 MHz Range over which both transmit and receive reference clocks on any link may be centered. TL,TH Pulse Width, Low / High for REFMODE=1 (min) REFMODE=0 (max) 2.5 7.7 ns Low is measured from VIL(max) to VIL(max), High is measured from VIH(min) to VIH(min). DCI BCLK+/- & REFCLK+/duty cycle 40 60 % Measured at 50% TIR,TIF BCLK+/- & REFCLK+/rise and fall time 0.6 ns. Measured between 20% and 80% levels G52244-0, Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 5 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 DC Characteristics (Over recommended operating conditions). Parameters Description Min Typ Max Unit s Conditions TTL INPUTS VIH Input HIGH voltage 2.0 — 5.5 V VIL Input LOW voltage 0 — 0.8 V — IIH Input HIGH current — 500 µA VIN = 2.4 V IIL Input LOW current — — -500 µA VIN = 0.5 V LVPECL INPUTS VIH Input HIGH voltage (LVPECL) VDD1.1 — VDD0.7 V 50 Ohm Termination to VDD-2.0V VIL Input LOW voltage (LVPECL) VDD2.0 — VDD1.54 V — IIH Input HIGH current (LVPECL) — — 200 µA VIN = VIH(max) IIL Input LOW current (LVPECL) -50 — — µA VIN = VIL(min) ∆VI Input Voltage Swing 440 — 1300 mV Calculated from VIH & VIL LVPECL OUTPUTS VOH Output HIGH voltage (LVPECL) VDD1.02 — VDD0.70 V 50 Ohm Termination to VDD-2.0V VOL Output LOW voltage (LVPECL) VDD2.0 — VDD1.62 V — 600 — 1300 mV ∆VOLVPECL Low speed output voltage single-ended, peak-to-peak swing Calculated from VOH & VOL HIGH SPEED DIFFERENTIAL INPUTS IIH Input HIGH current — — 200 µA VIN = VIH(max) IIL Input LOW current -50 — — µA VIN = VIL(min) Input Differential Voltage 200 VIH Input HIGH voltage 1.30 VIL Input LOW voltage 0 ∆VIDF mV 2.50 V V HIGH SPEED DIFFERENTIAL OUTPUTS Page 6 ∆VODF Output Differential Voltage 350 ∆VOCM Output Common Mode Voltage 2.10 550 800 mV 100 Ohm Termination between TX+ and TX- 3.00 V 100 Ohm Termination between TX+ and TX- VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Parameters Description Min Typ Max Unit s Conditions MISCELLANEOUS VDD Supply voltage 3.14 — 3.47 V 3.3V +/- 5% PD Power dissipation — 1.8 2.5 W Outputs open, VDD = VDD max IDD Supply Current — 550 720 mA Outputs open, VDD = VDD max Zo Back Termination Impedance 40 50 60 ohms Guaranteed, not tested Absolute Maximum Ratings (1) Power Supply Voltage, (VDD) ......................................................................................................... -0.5V to +4V DC Input Voltage (LVPECL Inputs).....................................................................................-0.5V to VDD +0.5V DC Input Voltage (TTL Inputs) .............................................................................................-0.5V to VDD+0.5V DC Output Voltage (LVPECL Outputs) ..............................................................................-0.5V to VDD + 0.5V Output Current (TTL Outputs) .............................................................................................................. +/-50mA Output Current (LVPECL Outputs)........................................................................................................+/-50mA Case Temperature Under Bias ...................................................................................................... -55o to +125oC Storage Temperature.................................................................................................................. -65oC to +150oC Relative Humidity (Storage)........................................................................................ 0-95% (Non Condensing) Relative Humidity (Operating) ...................................................................................................................8-80% Maximum Input ESD (Human Body Model).............................................................................................1500V Recommended Operating Conditions Power Supply Voltage, (VDD) .............................................................................................................+3.3V+5% Operating Temperature Range ...........................................................0oC Ambient to +90oC Case Temperature Notes: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. G52244-0, Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 7 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Input Structures Figure 4: Input Structures VDD +3.3 V Current Limit INPUT R R GND TTL Inputs Figure 5: High Speed I/O Biasing Resistors Transmitter Output Receiver Input 3.3K 50 50 50 ohm Transmission Line 50 3.3K 50 3.3K VSC7164 Page 8 Off Chip 3.3K VSC7164 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Figure 6: PECL Inputs and Outputs Single-Ended PECL Input Internally Generated VBIAS (2.0 V) 155Mbps Data Input VBIAS C 0.1uF R1 0V R2 R1 || R2 = 700 Ω When not in use, tie VBIAS (pin #37) to ground through a capacitor. All internal VBIAS nodes are electrically connected. Single-Ended PECL Output OUTPUT G52244-0, Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 9 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Package Pin Descriptions VSS R15 R14 VSS VSS 77 79 LPBK TEST1 TEST2 TEST3 81 VDDP VDDP VSS 83 RBC- VSS VSS 87 RBC+ R7 89 85 R5 VDDP R6 91 93 95 97 99 VSS R0 R1 (Top View) VSS R2 R3 VDDP R4 Figure 7: Package Pin Diagram VDD VDD RXB+ RXBVDD RXA+ 1 75 3 73 5 71 7 69 9 67 11 65 13 63 15 61 17 59 VDD T4 19 57 VDD_TX TXA+ T5 VDD T6 T7 VSS 21 55 TXA- 23 53 25 51 VSS R13 R12 RXAVSS VDD_ANA VSS_ANA SYNC VDD_TX TXB+ TXBVDD_TX VSS_TX VSS_TX 49 VDD_TX VDD ENTXB VDD ENTXA VDD 47 SELB 45 43 41 TCLKOTCLKO+ VDDP REFCLKREFCLK+ VSS REFMODE 39 37 35 T14 T15 VBIAS BCLKBCLK+ VSS 33 31 29 T10 T11 VDD T12 T13 VDD 27 T9 VSS VSS T8 VDDP R11 R10 VDDP R9 R8 VSS T0 T1 VSS T2 T3 NOTE: Heat Sink is not connected electrically. It should not be connected electrically by the user. Page 10 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Table 4: Pin Identification Pin # Name Description [53 Signal Pins] 14, 15, 17,18, 20, 21, 23, 24, 26,27, 29, 30, 32, 33, 35, 36 T0:15 Transmit Data Bus, Bits 0 thru 15. INPUTS - Single Ended LVPECL 16-bit transmit bus at 155.52Mb/s synchronous to BCLK. T0 is transmitted first. 45, 44 REFCLK+ REFCLK- Reference Clock INPUT - Differential LVPECL REFCLK is the input to the CMU which is multiplied by 16 (REFMODE is HIGH) or 32 (REFMODE is LOW). 39, 38 BCLK+, BCLK- Byte Clock. INPUT - Differential LVPECL This rising edge of this clock latches T0:15 into the input register. 42, 41 TCLKO+, TCLKO- 56, 55 TXA+, TXA- Transmitter Serial Outputs. Channel A High speed serial data at 2.488Gb/s. OUTPUTS - Differential 62, 61 TXB+, TXB- Transmitter Serial Outputs. Channel B High speed serial data at 2.488Gb/s. OUTPUTS - Differential 49 ENTXA Enable Transmitter Serial Outputs. Channel A INPUT - TTL Enables TXA+/- when HIGH. When LOW, TXA+=HIGH, TXA-=LOW 52 ENTXB Enable Transmitter Serial Outputs. Channel B INPUT - TTL Enables TXB+/- when HIGH. When LOW, TSB+=HIGH, TXB-=LOW Transmit Byte Clock Out. OUPUTS - Differential LVPECL Divide by 16 version of a multiplied REFCLK from the CMU. Receive Data Bus, Bits 0 thru 15 OUTPUTS - Single Ended LVPECL 16-bit received bus at 155.52Mb/s. R0 is the first bit received on RX+/RX-. Synchronous to RBC. 99, 98, 96, 95, 93, 92, 90, 89,12, 11, 9, 8, 6, 5, 3, 2 R0:15 47 REFMODE REFCLK Rate Selector (155/77 MHz) INPUT - TTL LOW for 77.76 MHz REFCLK. HIGH for 155.52 MHz REFCLK. 81 LPBK LooPBacK Mode. INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled. 70, 69 RXA+, RXA- Receive Serial Inputs. Channel A INPUTS Differential The receiver inputs when EWRAP is LOW and SELB is LOW. 73, 72 RXB+, RXB- Receive Serial Inputs. Channel B INPUTS - Differential The receiver inputs when EWRAP is LOW and SELB is HIGH. 48 SELB Select RXB+/- or RXA+/INPUT - TTL Selects RXB+/- when HIGH and RXA+/- when LOW. This assumes EWRAP is LOW. G52244-0, Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 11 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Table 4: Pin Identification Pin # Name Description 85, 86 RBC+, RBC- Recovered Byte Clock OUTPUT - Differential LVPECL Recovered clock at 155.52 MHz synchronous to R0:15. SYNC Synchronize Word Generate INPUT - TTL Active HIGH. Interrupts T[15:0] input bus on the next rising edge of BCLK+ and generates a sync word in serializer. Synch word is sixteen bit alternating 01 (HEX 5555). When LOW allows T[15:0] bus to get serialized (normal operation). 37 VBIAS PECL Input Buffer Bias Voltage Over-ride INPUT - Analog Can be used to over-ride internally generated bias voltage on the single-ended PECL inputs (see fig.5 on page 11). When not in use, tie to ground through a capacitor. 80, 79, 78 TEST1, TEST2, TEST3, TEST Pins - TTL For internal test use only. Tie these inputs HIGH. 19, 22, 31, 34, 50, 51, 53, 71, 74, 75 VDD Digital Power Supply at 3.3V 7, 10, 43, 83, 84, 91, 94 VDDP PECL Power Supply at 3.3V 66 VDDA 54, 57, 60, 63 VDD_TX Analog Power Supply at 3.3V High Speed Transmit Output Power Supply at 3.3V 1, 4, 13, 16, 25, 28, 40, 46, 67, 68, 76, 77, 82, 87, 88, 97, 100 VSS 65 VSSA 58, 59 VSS_TX 64 Page 12 [53 Signal Pins] INPUT Digital and PECL Ground Analog Ground High Speed Transmit Output Ground VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Package Thermal Considerations The VSC7164 is packaged in an 100 pin, 14 mm Thermally Enhanced PQFP with an externally exposed heat spreader. This package uses industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the package is as shown in Figure 6. The VSC7164 is designed to operate with a case temperature up to 90oC. The user must guarantee that the temperature specification is not violated. In still air this results in an ambient temperature of: 90oC - (2.5W x 35oC/W) = 2.5oC. If this temperature cannot be provided, the user must supply a heat sink or sufficient air flow to ensure compliance with the maximum case temperature specification. Figure 8: Package Cross Section Plastic Molding Compound Exposed Heat Slug Insulator Lead Wire Bond Thermal Epoxy Die Table 5: 100-Pin PQFP Thermal Resistance Symbol Value Units Thermal resistance from junction to case 2.5 oC/W Thermal resistance from case to ambient, still air 35 oC/W θca-100 Thermal resistance from case to ambient, 100 LFPM air 29 oC/W θca-200 Thermal resistance from case to ambient, 200 LFPM air 26 oC/W θca-400 Thermal resistance from case to ambient, 400 LFPM air 22 oC/W θca-600 Thermal resistance from case to ambient, 600 LFPM air 19 oC/W θjc θca-0 G52244-0, Rev. 1.5 02/18/99 Description VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 13 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Package Information 100 PQFP: (14 x 14 x 2.0 mm) Package Drawing (Top View) Body +3.2mm Footprint EXPOSED HEATSINK 6.86 ±.50 DIA. D D1 E1 E Key mm Tolerance A 2.35 MAX A1 0.25 MAX A2 2.00 +.10/-.05 D 17.20 ±.25 D1 14.00 ±.10 E 17.20 ±.25 E1 14.00 ±.10 L .88 +.15/-.10 e .50 BASIC ±.05 b .22 θ 0°-7° R .30 TYP R1 .20 TYP HEATSINK INTRUSION .0127 MAX 10 o TYP A2 A e 10 o TYP R R1 6° ± 4° A A1 0.25 θ NOTES: (1) Drawings not to scale. (2) All units in millimeters unless otherwise noted 0.17 MAX L b Page 14 Package #: 101-318-3 Issue #: 2 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION Target Specification 2.488Gb/s 16:1 / 1:16 Transceiver VSC7164 Ordering Information The order number for this product is formed by a combination of the device number and package type. VSC7164 QQ Device Type VSC7164 - 2.488Gb/s Transceiver Package Type QQ: 100 Pin Thermally Enhanced PQFP, 14mmx14mm Body Notice This document contains information about a proposed product during its design phase of development and is subject to change without notice at any time. All features and specifications are design goals only. Please contact Vitesse Semiconductor to obtain the latest product status and most recent versions of this specification. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52244-0, Rev. 1.5 02/18/99 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.488Gb/s 16:1 / 1:16 Transceiver Target Specification VSC7164 Revision History 1.0 Target Spec written. 1.1 Added wording to packaging and corrected typos from 1.0 1.2 Added SYNC and VBIAS pins. 1.3 Modified block diagram, fig. 5 and package thermal characteristics. 1.4 Modified jitter test on p4, Modified jitter tolerance on p5 Modified Fig 2 for consistancy with spec, Modified BCLK/REFCLK phase relationship restrictions, p6 Modified spec methodology for LVPECL and Hi Speed I/Os, p7/p8 1.5 Replaced pins R15-R8 with R7-R0 and vice-versea, p12/13. Page 16 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G52244-0 Rev. 1.5 02/18/99