Intelligent Panel Controller Pro for Standard Frame System CXD4732R 1. Description The CXD4732R performs picture quality enhancement signal processing for post-scaling full-HD and WXGA progressive scan signals. This IC can achieve high-end picture quality easily, and provides even further added value in end products. The CXD4732R has high-performance MC-3DNR functions, Super resolution functions, dynamic contrast functions, and color representation improvement functions. The device is provided a 128-pin LQFP package. Neither external DRAM nor any special firmware is required. (Applications: LCD TV, Panel Module) 2. Features ◆ High performance video processing ◆ 3D noise reduction combined with motion compensation(MC-3DNR) ◆ MPEG-NR, ◆ Gradation ◆ Super especially effective for mosquito noise, block noise creation Resolution ◆ Screen division contrast enhancement ◆ Chromaticity ◆ 2D diagram based color conversion Sharpness ◆ Basic user controls : static contrast, color saturation, brightness ◆ Digital Gamma Function with two selectable 12bit GBR independent LUT ◆ Dither Function for 8bit panel system ◆ IC Interface ◆ LVDS receiver and transmitter which support single/dual links 8bit GBR or 10bit GBR ◆ Tolerates ◆ SSCG Spread Spectrum clock at the LVDS input (Spread Spectrum Clock Generator) for LVDS Tx clock ◆ Support display resolutions WXGA(1366x768p) or Full-HD(1920x1080p) ◆ Support I2C Slave Interface for external host CPU (100kHz~400kHz) ◆ Support I2C Master Interface for stand-alone startup with 64kbit or 128kbit external EEPROM (optional) 1 E12108 CXD4732R Contents 1. Description --------------------------------------------------------------------------------------------------------------------------------------- 1 2. Features ------------------------------------------------------------------------------------------------------------------------------------------ 1 Contents----------------------------------------------------------------------------------------------------------------------------------------------------- 2 3. Package ------------------------------------------------------------------------------------------------------------------------------------------ 5 4. Structure ------------------------------------------------------------------------------------------------------------------------------------------ 5 5. Block Diagram----------------------------------------------------------------------------------------------------------------------------------- 5 6. Pin Configuration ------------------------------------------------------------------------------------------------------------------------------- 6 7. Pin Description ---------------------------------------------------------------------------------------------------------------------------------- 7 8. Electrical Characteristics ------------------------------------------------------------------------------------------------------------------- 12 8.1. Absolute Maximum Ratings ------------------------------------------------------------------------------------------------------------ 12 8.2. Recommended Operating Conditions ----------------------------------------------------------------------------------------------- 12 8.3. DC characteristics ------------------------------------------------------------------------------------------------------------------------ 13 8.3.1. Digital In/Out Terminal---------------------------------------------------------------------------------------------------------------- 13 8.3.2. LVDS Receiver ------------------------------------------------------------------------------------------------------------------------- 13 8.3.3. LVDS Transmitter---------------------------------------------------------------------------------------------------------------------- 14 8.4. AC characteristics ------------------------------------------------------------------------------------------------------------------------ 15 8.4.1. System Clock and Reset Input ----------------------------------------------------------------------------------------------------- 15 8.4.2 I C Slave Interface -------------------------------------------------------------------------------------------------------------------- 16 8.4.3. I C Master Interface ------------------------------------------------------------------------------------------------------------------ 17 8.4.4. LVDS Receiver ------------------------------------------------------------------------------------------------------------------------- 18 8.4.5. LVDS Transmitter---------------------------------------------------------------------------------------------------------------------- 19 9. 2 2 Description of Functions -------------------------------------------------------------------------------------------------------------------- 20 9.1. LVDS Receiver ---------------------------------------------------------------------------------------------------------------------------- 20 9.1.1. Picture Size ----------------------------------------------------------------------------------------------------------------------------- 21 9.1.2. Link Swap Function, 9.1.3. Video Clock Selector ----------------------------------------------------------------------------------------------------------------- 21 9.1.4. 8-bit /10-bit Input Mode Selector -------------------------------------------------------------------------------------------------- 21 9.1.5. Support Frequency Range ---------------------------------------------------------------------------------------------------------- 22 9.1.6. Video Sync Mode---------------------------------------------------------------------------------------------------------------------- 22 Master/Slave Link --------------------------------------------------------------------------------------- 21 9.1.6.1. Sync through Mode---------------------------------------------------------------------------------------------------------------- 22 9.1.6.2. Sync through Mode---------------------------------------------------------------------------------------------------------------- 22 9.1.7. LVDS Data Format -------------------------------------------------------------------------------------------------------------------- 23 9.1.8. [Important] Restrictions for VS,HS,DE ------------------------------------------------------------------------------------------- 24 9.2. LVDS Transmitter ------------------------------------------------------------------------------------------------------------------------- 26 9.2.1. Link Swap Function ------------------------------------------------------------------------------------------------------------------- 26 9.2.2. 8-bit / 10-bit Output Mode Selector ----------------------------------------------------------------------------------------------- 27 9.2.3. LVDS Tx Output Differential Voltage Adjusting -------------------------------------------------------------------------------- 27 9.2.4. LVDS Tx Output Disable ------------------------------------------------------------------------------------------------------------- 27 2 CXD4732R 9.2.5. Spread-spectrum Clock Generator (SSCG) for LVDS Tx ------------------------------------------------------------------- 27 9.2.6. Spread-spectrum Clock Tracking Capability of LVDS Rx ------------------------------------------------------------------- 28 9.3. Color Management ----------------------------------------------------------------------------------------------------------------------- 29 9.3.1. Color Control Algorithm -------------------------------------------------------------------------------------------------------------- 29 9.3.2. Gray Out Function--------------------------------------------------------------------------------------------------------------------- 30 9.4. Intelligent Contrast Enhancer(iCE) ----------------------------------------------------------------------------------------------- 31 9.4.1 Brightness Contrast Gain Control ------------------------------------------------------------------------------------------------- 31 9.4.2 Color Contrast Gain Control -------------------------------------------------------------------------------------------------------- 32 9.4.3. Black level Control -------------------------------------------------------------------------------------------------------------------- 33 9.5. 2D-Sharpness ----------------------------------------------------------------------------------------------------------------------------- 35 9.6. Basic user Controls----------------------------------------------------------------------------------------------------------------------- 37 9.7. MC-3DNR ----------------------------------------------------------------------------------------------------------------------------------- 37 9.8. Basic user Controls----------------------------------------------------------------------------------------------------------------------- 37 9.9. SUPER RESOLUTON ------------------------------------------------------------------------------------------------------------------- 38 9.10. Digital Gamma Function ---------------------------------------------------------------------------------------------------------------- 39 9.11. Dither----------------------------------------------------------------------------------------------------------------------------------------- 40 9.11.1. FRC (Frame rate conversion)--------------------------------------------------------------------------------------------------- 40 9.11.2. Pattern Dither ----------------------------------------------------------------------------------------------------------------------- 40 10. Description of Operation -------------------------------------------------------------------------------------------------------------------- 41 10.1. Power and Reset Sequence ----------------------------------------------------------------------------------------------------------- 41 10.1.1. Turn on Sequence without External EEPROM ----------------------------------------------------------------------------- 41 10.1.2. Turn on Sequence with External EEPROM --------------------------------------------------------------------------------- 42 10.2. Gamma Correction Look-up Table Setup ------------------------------------------------------------------------------------------- 43 10.2.1. Initializing Gamma LUT Group-A ---------------------------------------------------------------------------------------------- 43 10.2.2. Initializing Gamma LUT Group-B ---------------------------------------------------------------------------------------------- 44 10.3. Host I/F -------------------------------------------------------------------------------------------------------------------------------------- 45 2 10.3.1. I C Slave Interface----------------------------------------------------------------------------------------------------------------- 45 10.3.2. I C Slave Write Cycle ------------------------------------------------------------------------------------------------------------- 45 10.3.3. I C Slave Read Cycle ------------------------------------------------------------------------------------------------------------- 45 10.3.4. I C Slave Page Address---------------------------------------------------------------------------------------------------------- 46 10.3.5. I C Master Interface --------------------------------------------------------------------------------------------------------------- 47 10.3.6. I C Bus through mode ------------------------------------------------------------------------------------------------------------ 48 11. 2 2 2 2 2 Control Register Map ------------------------------------------------------------------------------------------------------------------------ 49 2 11.1. I C Slave Address ------------------------------------------------------------------------------------------------------------------------ 49 11.2. I C Page Address Map ------------------------------------------------------------------------------------------------------------------ 49 11.3. I C Sub Address Map -------------------------------------------------------------------------------------------------------------------- 51 2 2 11.3.1. Common Registers (No Page Address, Sub Address = E0h~FFh) --------------------------------------------------- 51 11.3.2. EXPRESSION Control Registers (Page Address = 00h, Sub Address = 00h~DFh) ------------------------------ 51 11.3.3. Digital Gamma Function Look-up Table Registers (Page Address = 01h~18h, Sub Address = 00h~BFh) - 53 3 CXD4732R 11.3.4. Video Input Control Registers (Page Address = 1Ah, Sub Address = 00h~7Fh) ---------------------------------- 56 11.3.5. Video Output Control Registers (Page Address = 1Ah, Sub Address = 80h~DFh) ------------------------------- 56 11.3.6. MC-3DNR Control Registers (Page Address = 1Bh, Sub Address = 00h~DFh) ----------------------------------- 57 11.3.7. Super Resolution Control Registers (Page Address = 1Ch, Sub Address = 00h~DFh) -------------------------- 58 11.3.8. GRC Control Registers (Page Address = 1Dh, Sub Address = 00h~DFh) ------------------------------------------ 59 11.3.9. Gamma and Dither Control Registers (Page Address = 1Fh, Sub Address = 00h~3Fh) ------------------------ 59 11.3.10. Other System Control Registers-1 (Page Address = 1Dh, Sub Address = 40h~DFh) ---------------------------- 60 11.3.11. Other System Control Registers-2 (Page Address = 1Eh, Sub Address = 00h~DFh) ---------------------------- 60 11.3.12. Other System Control Registers-3 (Page Address = 1Fh, Sub Address = 40h~DFh) ---------------------------- 60 11.4. 2 I C Register Description----------------------------------------------------------------------------------------------------------------- 61 11.4.1. Common Registers (No Page Address) -------------------------------------------------------------------------------------- 61 11.4.2. EXPRESSION Registers--------------------------------------------------------------------------------------------------------- 61 11.4.3. Video Input Control Registers (Page Address = 1Ah) -------------------------------------------------------------------- 64 11.4.4. Video Output Control Registers (Page Address = 1Ah) ------------------------------------------------------------------ 65 11.4.5. Gamma and Dither Control Registers (Page Address = 1Fh) ---------------------------------------------------------- 66 11.4.6. MC-3DNR Control Registers (Page Address = 1Bh) --------------------------------------------------------------------- 66 12. Example of Application Circuit ------------------------------------------------------------------------------------------------------------ 69 13. Package Outline ------------------------------------------------------------------------------------------------------------------------------ 70 14. Marking ----------------------------------------------------------------------------------------------------------------------------------------- 71 Note -------------------------------------------------------------------------------------------------------------------------------------------------------- 72 4 CXD4732R 3. Package QFP 128pin (0.5mm pin pitch, body size 20mm×14mm) 4. Structure Silicon gate CMOS IC 5. Block Diagram RXBCK (clock) clock 5ch LVDS-Tx sync SSCG PLL clock Dither R G B sync 5ch LVDS-Tx RGB Double Gamma Correction 2D-Sharpness B Basic User Controls (Static Contrast, Color Saturation, Brightness) sync Screen Division Contrast Enhancement (iCE) B Chrominance Diagram based Color Conversion (Color Management) G Super Resolution R Gradation Creation PLL MPEG Noise Reduction sync 3-D Noise Reduction w/MC 5ch LVDS-Tx R G B clock 5ch LVDS-Tx Expression Clear R G PLL Register Interface Block I2C Slave Interface I2C Master Interface Clock Circuits I2C Bus Through Path SCL/SDA 2bits SCL/SDA Slave Address Selector Host I/F Master Address Selector Master Busy Signal Clock Input 20MHz to 30MHz (25MHz for I2C Master I/F use) EEPROM for self start-up (Optional) Figure 5.1 CXD4732R Block Diagram 5 Reset Input TXACK (clock) TXBCK (clock) TXB0~TXB4(8bit/10bit) RXB0~RXB4(8bit/10bit) RXACK (clock) LVDS Transmitter CXD4732R TXA0~TXA4(8bit/10bit) RXA0~RXA4(8bit/10bit) LVDS Receiver CXD4732R 128 VSS 125 120 115 110 105 TXAVDD33 TXDVDD VDDIO VSSIO IIC_MST_EN VDDIO VSSIO VDD VSS TESTMODE IIC_SLV_SADSEL1 N.C VSSIO VDDIO N.C N.C N.C N.C N.C VSSIO VDDIO VDD VSS N.C N.C VDD 6. Pin Configuration 103 TXA0N 1 RXDVDD TXA0P Pin1 index RXDVSS 100 RXA0N RXA0P TXA1P TXA2N 5 RXA1N TXA2P RXA1P TXACKN RXA2N 95 RXA2P RXACKN TXDVSS TXDVDD RXA3N TXDVDD33 RXA3P 90 RXA4N TXA4N TXA4P CXD4732R RXAVDD VDD VSS TXAVDD33 85 TXPLLAVDD TXPLLAVSS RXB0N TXAVDD33 RXB0P 80 RXB1N TXB1N TXB1P RXB2P TXB2N RXBCKN 75 RXBCKP TXBCKP TXAVDD33 RXB4N TXDVSS RXB4P 70 RXAVSS TXDVDD TXDVDD33 TXB3N 35 VSS TXB3P VSSIO TXB4N 38 65 Note) Exposed Pad must be connected to GND and soldered to PCB. Figure 6.1 CXD4732R Pin Configuration 6 TXDVDD VSSIO VDDIO 64 VSS VDD VSSIO IIC_SLV_BUSY VDDIO IIC_MST_SCL 60 IIC_MST_SDA RST_X IIC_MST_SADSEL N.C. SCLKI PLLVSSA 55 PLLVDDA VSS VDD 50 VSSIO VDDIO IIC_SLV_SCL VSSIO IIC_SLV_SDA 45 VDDIO VDD 40 VDDIO IIC_SLV_SADSEL0 TXB2P TXBCKN 30 RXB3P RXAVDD TXB0N TXB0P 25 RXB2N RXB3N CMCT TXPLLDVDD (Package Top View) 20 RXDVSS RXB1P TXA3N TXA3P 15 RXAVSS RXDVDD TXACKP TXAVDD33 10 RXACKP RXA4P TXA1N TXB4P CXD4732R 7. Pin Description Pin # Pin Name Type Pin Descriptions Condition at Hard Reset Note 4 RXA0N LVDS IN LVDS receiver data input, Link A, Channel 0 (-) (1) 5 RXA0P LVDS IN LVDS receiver data input, Link A, Channel 0 (+) (1) 6 RXA1N LVDS IN LVDS receiver data input, Link A, Channel 1 (-) (1) 7 RXA1P LVDS IN LVDS receiver data input, Link A, Channel 1 (+) (1) 8 RXA2N LVDS IN LVDS receiver data input, Link A, Channel 2 (-) (1) 9 RXA2P LVDS IN LVDS receiver data input, Link A, Channel 2 (+) (1) 10 RXACKN LVDS IN LVDS receiver clock input for Link A (-) (1) 11 RXACKP LVDS IN LVDS receiver clock input for Link A (+) (1) 12 RXA3N LVDS IN LVDS receiver data input, Link A, Channel 3 (-) (1) 13 RXA3P LVDS IN LVDS receiver data input, Link A, Channel 3 (+) (1) 14 RXA4N LVDS IN LVDS receiver data input, Link A, Channel 4 (-) (1) In 8bit input mode, this pin is disabled. LVDS receiver data input, Link A, Channel 4 (+) 15 RXA4P LVDS IN (1) In 8bit input mode, this pin is disabled. 22 RXB0N LVDS IN LVDS receiver data input, Link B, Channel 0 (-) (1) 23 RXB0P LVDS IN LVDS receiver data input, Link B, Channel 0 (+) (1) 24 RXB1N LVDS IN LVDS receiver data input, Link B, Channel 1 (-) (1) 25 RXB1P LVDS IN LVDS receiver data input, Link B, Channel 1 (+) (1) 26 RXB2N LVDS IN LVDS receiver data input, Link B, Channel 2 (-) (1) 27 RXB2P LVDS IN LVDS receiver data input, Link B, Channel 2 (+) (1) 28 RXBCKN LVDS IN LVDS receiver clock input for Link B (-) (1) 29 RXBCKP LVDS IN LVDS receiver clock input for Link B (+) (1) 30 RXB3N LVDS IN LVDS receiver data input, Link B, Channel 3 (-) (1) 31 RXB3P LVDS IN LVDS receiver data input, Link B, Channel 3 (+) (1) 32 RXB4N LVDS IN LVDS receiver data input, Link B, Channel 4 (-) (1) In 8bit input mode, this pin is disabled. LVDS receiver data input, Link B, Channel 4 (+) 33 RXB4P LVDS IN (1) In 8bit input mode, this pin is disabled. 102 TXA0N LVDS OUT LVDS transmitter data output, Link A, Channel 0 (-) Uncertain value (high or low) (2) 101 TXA0P LVDS OUT LVDS transmitter data output, Link A, Channel 0 (+) Uncertain value (high or low) (2) 100 TXA1N LVDS OUT LVDS transmitter data output, Link A, Channel 1 (-) Uncertain value (high or low) (2) 99 TXA1P LVDS OUT LVDS transmitter data output, Link A, Channel 1 (+) Uncertain value (high or low) (2) 98 TXA2N LVDS OUT LVDS transmitter data output, Link A, Channel 2 (-) Uncertain value (high or low) (2) 97 TXA2P LVDS OUT LVDS transmitter data output, Link A, Channel 2 (+) Uncertain value (high or low) (2) 7 CXD4732R Pin # Pin Name Type Pin Descriptions Condition at Hard Reset Note 96 TXACKN LVDS OUT LVDS transmitter clock output for Link A (-) Uncertain value (high or low) (2) 95 TXACKP LVDS OUT LVDS transmitter clock output for Link A (+) Uncertain value (high or low) (2) 90 TXA3N LVDS OUT LVDS transmitter data output, Link A, Channel 3 (-) Uncertain value (high or low) (2) 89 TXA3P LVDS OUT LVDS transmitter data output, Link A, Channel 3 (+) Uncertain value (high or low) (2) 88 TXA4N LVDS OUT Uncertain value (high or low) (2) Uncertain value (high or low) (2) LVDS transmitter data output, Link A, Channel 4 (-) In 8bit output mode, this pin is disabled. LVDS transmitter data output, Link A, Channel 4 (+) 87 TXA4P LVDS OUT In 8bit output mode, this pin is disabled. 80 TXB0N LVDS OUT LVDS transmitter data output, Link B, Channel 0 (-) Uncertain value (high or low) (2) 79 TXB0P LVDS OUT LVDS transmitter data output, Link B, Channel 0 (+) Uncertain value (high or low) (2) 78 TXB1N LVDS OUT LVDS transmitter data output, Link B, Channel 1 (-) Uncertain value (high or low) (2) 77 TXB1P LVDS OUT LVDS transmitter data output, Link B, Channel 1 (+) Uncertain value (high or low) (2) 76 TXB2N LVDS OUT LVDS transmitter data output, Link B, Channel 2 (-) Uncertain value (high or low) (2) 75 TXB2P LVDS OUT LVDS transmitter data output, Link B, Channel 2 (+) Uncertain value (high or low) (2) 74 TXBCKN LVDS OUT LVDS transmitter clock output for Link B (-) Uncertain value (high or low) (2) 73 TXBCKP LVDS OUT LVDS transmitter clock output for Link B (+) Uncertain value (high or low) (2) 68 TXB3N LVDS OUT LVDS transmitter data output, Link B, Channel 3 (-) Uncertain value (high or low) (2) 67 TXB3P LVDS OUT LVDS transmitter data output, Link B, Channel 3 (+) Uncertain value (high or low) (2) 66 TXB4N LVDS OUT Uncertain value (high or low) (2) Uncertain value (high or low) (2) LVDS transmitter data output, Link B, Channel 4 (-) In 8bit output mode, this pin is disabled. LVDS transmitter data output, Link B, Channel 4 (+) 65 TXB4P LVDS OUT In 8bit output mode, this pin is disabled. 51 SCLKI 52 N.C. 53 RST_X 3.3V IN System Reset input. This signal is active low. 38 IIC_SLV_SADSEL0 3.3V IN I2C address selector bit 0 for I2C slave interface 113 IIC_SLV_SADSEL1 3.3V IN I2C address selector bit 1 for I2C slave interface 3.3V IN 3.3V OUT System clock input. Do not Connect this terminal. (3) 43 IIC_SLV_SDA Open Drain I2C data signal for I2C slave interface (4) 44 IIC_SLV_SCL Open Drain I2C clock signal for I2C slave interface (4) 54 IIC_MST_SADSEL 3.3V IN 2 2 I C address selector for I C master interface I2C data signal for I2C master interface. If external EEPROM 55 IIC_MST_SCL Open Drain is not used (IIC_MST_EN = Low), connect this pin to the (4) GND. I2C clock signal for I2C master interface. If external EEPROM 56 IIC_MST_SDA Open Drain is not used (IIC_MST_EN = Low), connect this pin to the GND. 8 (4) CXD4732R Pin # 59 Pin Name IIC_SLV_BUSY Type 3.3V OUT Pin Descriptions Condition at Hard Reset 2 I C slave interface busy signal output. High: busy 2 107 IIC_MST_EN 3.3V IN I C master interface enable, High: enable, Low: disable 112 TESTMODE 3.3V IN Always Connect this terminal to digital ground (VSSIO). 114 117 118 119 N.C Do not Connect this terminal. 120 121 126 127 17 RXAVDD 3.3V POWER RXAVSS GND RXDVDD 1.2V POWER RXDVSS GND Analog power (3.3V) for LVDS receiver 35 16 Ground for LVDS receiver 34 2 Digital power (1.2V) for LVDS receiver 20 3 Ground for LVDS receiver 21 72 TXAVDD33 3.3V POWER Analog power (3.3V) for LVDS transmitter 83 TXPLLAVDD 1.2V POWER PLL analog power (1.2V) for LVDS transmitter 82 TXPLLAVSS GND 84 TXPLLDVDD 1.2V POWER 85 CMCT 81 86 94 103 PLL ground for LVDS transmitter PLL digital power (1.2V) for LVDS transmitter Connect external Capacitance (>0.1uF) to this terminal and Analog IN GND 64 TXDVDD 1.2V POWER Digital power (1.2V) for LVDS transmitter TXDVDD33 3.3V POWER Digital power (3.3V) for LVDS transmitter 70 92 104 69 91 9 Low Note (5) CXD4732R Pin # Pin Name Type Pin Descriptions TXDVSS GND Ground for LVDS transmitter 50 PLLVDDA 1.2V POWER 49 PLLVSSA Analog IN 71 Condition at Hard Reset 93 PLL analog power (1.2V) for core circuits See the 12. Example Application Circuit. Do not connect this terminal to PCB GND. 18 VDD 1.2V POWER VSS GND Digital power (1.2V) for core circuit 40 47 60 110 124 128 1 Ground for core circuit 19 36 48 61 111 125 39 VDDIO 3.3V POWER VSSIO GND Digital power (3.3V) for I/O 41 45 57 62 105 108 116 123 37 Ground for I/O 42 46 58 63 106 109 115 122 10 Note CXD4732R Pin # - Pin Name Type Pin Descriptions Condition at Hard Reset Exposed Pad GND Ground for LVDS transmitter Note) (1) Unused pins must be fixed to high (3.3V) or OPEN for LVDS Rx. (2) Unused pins must be OPEN for LVDS Tx. (3) Active low reset is required after turn on. (4) External pull-up registers are required. (5) At the releasing RST_X, if the terminal “IIC_MST_EN” is high, this terminal “IIC_SLV_BUSY” becomes high till an I2C Master Reading Operation is completed. (6) Exposed Pad must be connected to GND and soldered to PCB. 11 Note (6) CXD4732R 8. Electrical Characteristics 8.1. Absolute Maximum Ratings Item Symbol Min. Max. Unit Power Supply Digital I/O VDDIO -0.5 +4.6 V Voltage LVDS Rx, Tx I/O RXAVDD, TXAVDD33, -0.5 +4.6 V TXDVDD33 Core Logic VDD -0.5 +1.6 V LVDS Rx, Tx Logic RXDVDD, TXDVDD -0.5 +1.6 V PLL PLLVDDA, TXPLLAVDD, -0.5 +1.6 V -10 +115 ℃ TXPLLDVDD Operating Junction Temperature Tj 8.2. Recommended Operating Conditions Item Symbol Min. Typ. Max. Unit Power Supply 3.3V Digital I/O VDDIO 3.0 3.3 3.6 V Voltage I2C Bus DC supply voltage for VI2C-BUS 3.0 3.3 5.0 V RXAVDD, TXAVDD33, 3.0 3.3 3.6 V output pull-up termination LVDS Rx, Tx I/O TXDVDD33 Core Logic VDD 1.1 1.2 1.3 V LVDS Rx Logic RXDVDD 1.1 1.2 1.3 V LVDS Tx Logic TXDVDD *1)1.1 1.2 1.3 V PLL PLLVDDA, TXPLLAVDD, 1.1 1.2 1.3 V 75 ℃ TXPLLDVDD Operating Ambient Temperature Ta 0 *1) If you use SSCG (LVTX_SSEN =1 ), this value is 1.15V. 12 CXD4732R 8.3. DC characteristics 8.3.1. Digital In/Out Terminal (VDDIO = 3.3V+/-0.3V) Item Symbol Digital Input High Voltage Applicable pins / Condition VIH *1), 2) Digital Input High Voltage(I C pin) VIH-I2C *3) Digital Input Low Voltage VIL *1), 2) Digital Input Low Voltage(I2C pin) VIL-I2C Digital Output High Voltage Min. Typ. Unit 3.6 V VI2C-BUS V -0.3 0.8 V *3) -0.3 0.3*VI2C-BUS VOH *4) 2.4 Digital Output High Voltage(I2C pin) VOH-I2C *3) Digital Output Low Voltage VOL *4) 0.4 V Digital Output Low Voltage(I2C pin) VOL-I2C *3) 0.4 V Operating current for 1.2V VDD IOP_1.2 *5),LVDS Clock = 74.25MHz, 700 800 mA 200 220 mA 2 2 Max. 0.7*VI2C-BUS VI2C-BUS V Output is not driven high by CXD4732R Full-HD Operating current for 3.3V VDD IOP_3.3 *6),LVDS Clock = 74.25MHz, Full-HD *1) SCLKI *2) IIC_MST_EN, IIC_MST_SADSEL, IIC_SLV_SADSEL0, IIC_SLV_SADSEL1, RST_X *3) IIC_MST_SDA, IIC_MST_SCL, IIC_SLV_SDA, IIC_SLV_SCL *4) IIC_MST_SCL, IIC_SLV_BUSY *5) 1.2V VDD includes RXDVDD, TXPLLAVDD, TXPLLDVDD, TXDVDD, PLLVDDA, VDD *6) 3.3V VDD includes RXAVDD, TXAVDD33, TXDVDD33, VDDIO 8.3.2. LVDS Receiver (RXAVDD = 3.3V+/-0.3V, RXDVDD = 1.2V+/-0.1V) Item Symbol Applicable pins / Condition Differential Input High Threshold VRXTH *1), *2) VCM = 1.2V Differential Input Low Threshold VRXTL *1), *2) VCM = 1.2V Input Voltage Range VRXIN *1) Min. Typ. Max. Unit 100 mV -100 0 mV 2.4 V *1) RXB0N, RXB0P, RXB1N, RXB1P, RXB2N, RXB2P, RXBCKN, RXBCKP, RXB3N, RXB3P, RXB4N, RXB4P, RXA0N, RXA0P, RXA1N, RXA1P, RXA2N, RXA2P, RXACKN, RXACKP, RXA3N, RXA3P, RXA4N, RXA4P *2) VCM : LVDS Common Voltage 13 CXD4732R 8.3.3. LVDS Transmitter (TXAVDD33 = TXDVDD33 = 3.3V+/-0.3V, TXDVDD = 1.2V+/-0.1V) Item Differential Output Voltage Offset Voltage Symbol VTXOD VTXOS Applicable pins / Condition Min. Typ. Max. *1), *2) RL = 100Ω, ILVDS = 3.5mA, 280 350 420 mV *1), *2) RL = 100Ω, ILVDS = 2.5mA, 200 250 300 mV 1.125 1.25 1.375 *1), *2) RL = 100Ω Unit V *1) TXA4P, TXA4N, TXA3P, TXA3N, TXACKP, TXACKN, TXA2P, TXA2N, TXA1P, TXA1N, TXA0P, TXA0N, TXB4P, TXB4N, TXB3P, TXB3N, TXBCKP, TXBCKN, TXB2P, TXB2N, TXB1P, TXB1N, TXB0P, TXB0N *2) RL: Load Condition, ILVDS: LVDS Driver Current on LVDS Tx Bus 14 CXD4732R 8.4. AC characteristics 8.4.1. System Clock and Reset Input (VDDIO = 3.3V+/-0.3V) Item Symbol System Clock Frequency 1/TSYSCLK Duty Cycle Reset Low Period TRST Applicable pins / Condition Min. Typ. Max. Unit SCLKI *1) 20 25 30 MHz SCLKI 40 50 60 % RST_X 250 2 *1) It is desirable to set frequency to 25MHz if the I C master interface is enabled. TSYSCLK SCLKI 50% Figure 8.4.1.1 System Clock SCLKI Timing Definition TRST RST_X 50% Figure 8.4.1.2 System Reset Input Waveform 15 ns CXD4732R 8.4.2 I2C Slave Interface (VDDIO = 3.3V+/-0.3V) Item Symbol Applicable pins / Condition Min. Typ. Max. Unit 400 kHz Input Clock Frequency 1/TSLC IIC_SLV_SCL Clock Pulse Width High TSLCHL IIC_SLV_SCL 600 ns Clock Pulse Width Low TSLCLL IIC_SLV_SCL 1300 ns Data In Set Up Time TSLDIS IIC_SLV_SDA 100 ns Slave Data In Hold Time TSLDIH IIC_SLV_SDA 0 ns Start Condition Hold Time TSLSTH IIC_SLV_SDA 600 ns Stop Condition Set Up Time TSLSPS IIC_SLV_SDA 600 ns Time between Stop and Next Start TSLSSH IIC_SLV_SDA 1300 ns Data Out Hold Time TSLDOH IIC_SLV_SDA 0 900 ns TSLC IIC_SLV_SCL (Input) 70% 70% 30% IIC_SLV_SDA (Input) 70% 30% 70% 70% 30% 70% 30% 30% TSLDIS IIC_SLV_SCL (Input) TSLSPS TSLCLL TSLCHL TSLSTH TSLDIH 30% 70% IIC_SLV_SDA (Output) 30% TSLDOH Figure 8.4.2 I2C Slave Interface Timing Definition 16 TSLSSH CXD4732R 8.4.3. I2C Master Interface (VDDIO = 3.3V+/-0.3V) Item Symbol Applicable pins / Min. Typ. Max. Unit Condition Output Clock Frequency 1/TMAC IIC_MST_SCL, *1) 391 kHz Clock Pulse Width High TMACHL IIC_MST_SCL 600 ns Clock Pulse Width Low TMACLL IIC_MST_SCL 1300 ns Data Out Set Up Time TMADOS IIC_MST_SDA 100 ns Data Out Hold Time TMADOH IIC_MST_SDA 0 Start Condition Hold Time TMASTH IIC_MST_SDA 600 ns Stop Condition Set Up Time TMASPS IIC_MST_SDA 600 ns Time between Stop and Next Start TMASSH IIC_MST_SDA 1300 ns Data In Set Up Time TMADIS IIC_MST_SDA 100 ns 900 ns *1) System Clock Frequency (SCLKI) = 25MHz. TMAC IIC_MST_SCL 70% 70% (Output) 30% IIC_MST_SDA 70% 70% 30% TMADOS IIC_MST_SCL (Output) TMADOH 70% 70% 30% TMADIS Figure 8.4.3 70% 30% 30% (Output) IIC_MST_SDA (Input) TMASPS TMACLL TMACHL TMASTH I2C Master Interface Timing Definition 17 70% 30% TMASSH CXD4732R 8.4.4. LVDS Receiver (RXAVDD = 3.3V+/-0.3V, RXDVDD = 1.2V+/-0.1V) Item Symbol Condition Min. Receiver Clock Period TRCP *1) 14.70 Input Data Position for Bit 1 TRIP1 *2) - TRSKM Input Data Position for Bit 0 TRIP0 *2) Input Data Position for Bit 6 TRIP6 Input Data Position for Bit 5 Typ. Max. Unit 11.77 ns 0 + TRSKM ns (1/7) TRCP - TRSKM (1/7) TRCP (1/7) TRCP + TRSKM ns *2) (2/7) TRCP - TRSKM (2/7) TRCP (2/7) TRCP + TRSKM ns TRIP5 *2) (3/7) TRCP - TRSKM (3/7) TRCP (3/7) TRCP + TRSKM ns Input Data Position for Bit 4 TRIP4 *2) (4/7) TRCP - TRSKM (4/7) TRCP (4/7) TRCP + TRSKM ns Input Data Position for Bit 3 TRIP3 *2) (5/7) TRCP - TRSKM (5/7) TRCP (5/7) TRCP + TRSKM ns Input Data Position for Bit 2 TRIP2 *2) (6/7) TRCP - TRSKM (6/7) TRCP (6/7) TRCP + TRSKM ns Receiver Skew Margin TRSKM *2) -0.35 0.35 ns *1) RXBCKN, RXBCKP, RXACKN, RXACKP *2) RXB0N, RXB0P, RXB1N, RXB1P, RXB2N, RXB2P, RXB3N, RXB3P, RXB4N, RXB4P, RXA0N, RXA0P, RXA1N, RXA1P, RXA2N, RXA2P, RXA3N, RXA3P, RXA4N, RXA4P TRCP RXACKN / RXBCKN 50% RXACKP / RXBCKP Next Cycle Previous Cycle RXA0N / RXB0N RXA0P / RXB0P RXA1N / RXB1N RXA1P / RXB1P RXA2N / RXB2N RXA2P / RXB2P RXA3N / RXB3N RXA3P / RXB3P RXA4N / RXB4N RXA4P / RXB4P TRIP1 TRIP0 TRIP6 TRIP5 TRIP4 TRIP3 TRIP2 TRCP RXACKN / RXBCKN RXACKP / RXBCKP TRCP/7 TRCP/7 TRCP/7 TRCP/7 TRCP/7 TRCP/7 TRCP/7 RXAxN, RXBxN, RXAxP, RXBxP (x=0, 1, 2, 3, 4) +/-TRSKM +/-TRSKM +/-TRSKM +/-TRSKM +/-TRSKM Figure 8.4.4 LVDS Receiver Timing Definition 18 +/-TRSKM +/-TRSKM CXD4732R 8.4.5. LVDS Transmitter (TXAVDD33 = TXDVDD33 = 3.3V+/-0.3V, TXDVDD = 1.2V+/-0.1V) Item Symbol Condition Min. Transmitter Clock Period TTCP *1) 14.70 Input Data Position for Bit 1 TTOP1 *2) - TRSK Input Data Position for Bit 0 TTOP0 *2) Input Data Position for Bit 6 TTOP6 Input Data Position for Bit 5 Typ. Max. Unit 11.77 ns 0 + TRSK ns (1/7) TRCP - TRSK (1/7) TRCP (1/7) TRCP + TRSK ns *2) (2/7) TRCP - TRSK (2/7) TRCP (2/7) TRCP + TRSK ns TTOP5 *2) (3/7) TRCP - TRSK (3/7) TRCP (3/7) TRCP + TRSK ns Input Data Position for Bit 4 TTOP4 *2) (4/7) TRCP - TRSK (4/7) TRCP (4/7) TRCP + TRSK ns Input Data Position for Bit 3 TTOP3 *2) (5/7) TRCP - TRSK (5/7) TRCP (5/7) TRCP + TRSK ns Input Data Position for Bit 2 TTOP2 *2) (6/7) TRCP - TRSK (6/7) TRCP (6/7) TRCP + TRSK ns Transmitter Skew TTSK *2) -0.35 0.35 ns *1) TXACKP, TXACKN, TXBCKP, TXBCKN *2) TXA4P, TXA4N, TXA3P, TXA3N, TXA2P, TXA2N, TXA1P, TXA1N, TXA0P, TXA0N, TXB4P, TXB4N, TXB3P, TXB3N, TXB2P, TXB2N, TXB1P, TXB1N, TXB0P, TXB0N TTCP TXACKN / TXBCKN 50% TXACKP / TXBCKP Next Cycle Previous Cycle TXA0N / TXB0N, TXA0P / TXB0P TXA1N / TXB1N, TXA1P / TXB1P TXA2N / TXB2N, TXA2P / TXB2P TXA3N / TXB3N, TXA3P / TXB3P TXA4N / TXB4N, TXA4P / TXB4P TTOP1 TTOP0 TTOP6 TTOP5 TTOP4 TTOP3 TTOP2 TTCP TXACKN / TXBCKN TXACKP / TXBCKP TTCP/7 TTCP/7 TTCP/7 TTCP/7 TTCP/7 TTCP/7 TTCP/7 TXAxN / TXBxN, TXAxP / TXBxP (x=0, 1, 2, 3, 4) +/-TTSK +/-TTSK Figure 8.4.5 +/-TTSK +/-TTSK +/-TTSK LVDS Transmitter Timing Definition 19 +/-TTSK +/-TTSK CXD4732R 9. Description of Functions 9.1. LVDS Receiver The CXD4732R has two links of LVDS Receiver for 8bit/10bit video input. The external termination registers (100 Ω) are needed for each differential pair. Place them near each pin. RXA0P RXA0N 100 Green_A RXA1P RXA1N Blue_A 100 100 Red_A LVDS Rx Link-A RXA2P RXA2N Hsync_A Vsync_A RXA3P RXA3N DE_A 100 100 RXACKP RXACKN CLK_A PLL 100 Link Swap Function RXB0P RXB0N Core Circuits RXA4P RXA4N 100 RXB2P RXB2N Green_B Blue_B 100 100 Red_B LVDS Rx Link-B RXB1P RXB1N Hsync_B Vsync_B RXB3P RXB3N DE_B 100 RXB4P RXB4N 100 RXBXKP RXBXKN CLK_B PLL 100 Clock Selector Register CLK_RXCLK_SEL Figure 9.1 Input Link Swap Function Register VIN_LNKMS_SEL LVDS Receiver Block Diagram 20 CXD4732R 9.1.1. Picture Size This LSI supports two video formats as follows. That mode is applied to both LVDS Rx and Tx. To change the mode, refer to Application note. Mode Active Video Size Number of Link WXGA 1366×768 Single Link (default link is Link-A) FHD 1920×1080 Dual Link (default master link is Link-A, slave link is Link-B) Master Link: pixel 1, 3, 5, 7, …, 1919 Slave Link: pixel 2, 4, 6, 8, …, 1920 9.1.2. Link Swap Function, Master/Slave Link LVDS Rx link swap function can replace Link-B with Link-A. For single link (WXGA), choose Link-A or B by this function. If st Link-B is used, change the link by the VIN_LNKMS_SEL. For dual link (FHD), 1 link (1, 3, 5, …, 1919) is Master link, and 2 nd link (2, 4, 6, …, 1920) is Slave link. 9.1.3. Master/Slave link can be swapped by this function. Video Clock Selector One of LVDS Rx links is selected for the internal video clock as shown in Figure 9.1. For single link, select to active link. For dual link, choose from the Link A or B. To select the clock, use the CLK_RXCLK_SEL. 9.1.4. 8-bit /10-bit Input Mode Selector This LSI supports both 8-bit and 10-bit inputs. In 8-bit mode, Channel 4 of each link is disabled. The LVDS bit assignment is shown in chapter “9.1.7 LVDS Data Format”. This setting is applied to both Link A and B. To change this mode, see application note. 21 CXD4732R 9.1.5. Support Frequency Range WXGA / Single Link Input Mode Item Symbol Min. LVDS Rx Clock Frequency 1/Tc_wxga Frame Rate Fv_wxga - Vertical Total Tv_wxga 785 Vertical Active Tvact_wxga Blanking Total Tvblank_wxga Horizontal Total Th_wxga Horizontal Active Thact_wxga Blanking Total Thblank_wxga 84 LVDS Rx Clock Frequency 1/Tc_fhd 68 Frame Rate Fv_fhd - Vertical Total Tv_fhd 1100 Vertical Active Tvact_fhd Blanking Total Tvblank_fhd Horizontal Total Th_fhd Horizontal Active Thact_fhd Blanking Total Thblank_fhd Vertical Section Typ. Typ. 50Hz 60Hz System System 68 82.86 Max. 85 50 60 838 950 768 20 1450 Unit MHz Hz Th_wxga Th_wxga 70 1978 1648 182 Th_wxga 2050 Tc_wxga Horizontal 1366 Tc_wxga FHD / Dual Link Input Section Vertical Section 612 282 74.25 50 60 1125 684 Tc_wxga 80 MHz 1200 1080 20 2150 / 2 Th_fhd Th_fhd 45 2640 / 2 Hz 2200 / 2 120 Th_fhd 2690 / 2 Tc_fhd Horizontal 1920 / 2 Tc_fhd Section 9.1.6. 230 / 2 720 / 2 280 / 2 770 / 2 Tc_fhd Video Sync Mode This LSI supports the following two video sync modes. 9.1.6.1. Sync through Mode If input video signal is associated with V-Sync, H-Sync and DataEnable, this LSI works on the Sync through mode. In this mode, this LSI operates with V-Sync, H-Sync and DataEnable and outputs them with processed video signals. This mode is set by SYNC_MODE =1h, VIN_SYNC1 =13h, VIN_SYNC2 =13h, VIN_SYNC3 =13h and VOT_SYNC1 =1h. 9.1.6.2. Sync through Mode If there is neither V-Sync nor H-Sync in input video signal, but the input signal is associated with DataEnable (DE), this LSI operates on the DE-only mode. In this mode, only DE is used for video sync. V-Sync and H-Sync are disregarded and there is neither V-Sync output nor H-Sync output from this LSI. This mode is set by SYNC_MODE =0h, VIN_SYNC1 =14h, VIN_SYNC2 =14h, VIN_SYNC3 =14h and VOT_SYNC1 =0h. 22 CXD4732R 9.1.7. LVDS Data Format This LSI supports two modes, VESA and JEIDA. Bit assignment is shown in the Figure 9.1.7. To change this format, see Application note. Selected format is applied to both Link A and B, and LVDS Rx and Tx. Format: VESA, 8bit Current Cycle RXACK RXA0 G0 R5 R4 R3 R2 R1 R0 RXA1 B1 B0 G5 G4 G3 G2 G1 RXA2 DE VS(*) HS(*) B5 B4 B3 B2 B7 B6 G7 G6 R7 R6 0 0 0 0 0 0 RXA3 reserved 0 RXA4 (Not used) Format: VESA, 10bit Current Cycle RXACK RXA0 G0 R5 R4 R3 R2 R1 R0 RXA1 B1 B0 G5 G4 G3 G2 G1 RXA2 DE VS(*) HS(*) B5 B4 B3 B2 RXA3 reserved B7 B6 G7 G6 R7 R6 RXA4 reserve B9 B8 G9 G8 R9 R8 d Format: JEIDA, 8bit Current Cycle RXACK RXA0 G2 R7 R6 R5 R4 R3 R2 RXA1 B3 B2 G7 G6 G5 G4 G3 RXA2 DE VS(*) HS(*) B7 B6 B5 B4 B1 B0 G1 G0 R1 R0 0 0 0 0 0 0 RXA3 RXA4 reserved 0 (Not used) 23 CXD4732R Format: JEIDA, 10bit Current Cycle RXACK RXA0 G4 R9 R8 R7 R6 R5 R4 RXA1 B5 B4 G9 G8 G7 G6 G5 RXA2 DE VS(*) HS(*) B9 B8 B7 B6 RXA3 reserved B3 B2 G3 G2 R3 R2 RXA4 reserve B1 B0 G1 G0 R1 R0 Figure 9.1.7 9.1.8. d LVDS Formats (reserved bit is not used, VS(*) and HS(*) are don’t care in DE-only mode) [Important] Restrictions for VS,HS,DE Input signal VS,HS,DE must be satisfied following three restrictions. ① Logical cycles of VS,HS,DE both Link-A and Link-B must be synchronized. (see Figure 9.1.8) Link-A HS Link-A HS Link-A VS Link-A VS Link-A DE Link-A DE Link-B HS Link-B HS -2≦n≦2 RX(A/B)CK n Link-B VS Link-B VS Link-B DE Link-B DE n OK OK Link-A HS Link-A HS Link-A VS Link-A VS Link-A DE Link-A DE n≠m n n≠m Link-B HS Link-B HS m n Link-B VS Link-B VS m n Link-B DE Link-B DE NG NG Figure 9.1.8 24 LVDS input Restriction 1 CXD4732R ②First data must be started from Master link. (see Figure 9.1.9) Master link : Link-A DE DE Link-A D1 D3 D5 Link-A D2 D4 D6 Link-B D2 D4 D6 Link-B D1 D3 D5 OK NG Master link : Link-B DE DE Link-A D1 D3 D5 Link-A D2 D4 D6 Link-B D2 D4 D6 Link-B D1 D3 D5 OK NG Figure 9.1.9 LVDS input Restriction 2 ③DE must be 0 when VS and HS are rising. (see Figure 9.1.10) HS (Except DE-only Mode) HS VS VS DE DE OK NG Figure 9.1.10 LVDS input Restriction 3 25 CXD4732R 9.2. LVDS Transmitter This LSI has also two links of LVDS Transmitter for 8bit/10bit video output. TXA0P TXA0N Green_A Red_A TXA1P TXA1N LVDS Tx Link-A Blue_A TXA2P TXA2N Hsync_A TXA3P TXA3N Vsync_A DE_A TXA4P TXA4N iPC Core Circuits PLL SSCG TXACKP TXACKN Link Swap Function TXB0P TXB0N Green_B TXB1P TXB1N Blue_B Hsync_B LVDS Tx Link-B Red_B Vsync_B DE_B TXB2P TXB2N TXB3P TXB3N TXB4P TXB4N TXBCKP TXBCKN Output Link Swap Function Register VOT_LNKSWP Figure 9.2 9.2.1. LVDS Transmitter Block Diagram Link Swap Function As shown Figure 9.2, LVDS Tx link swap function can replace Link-B with Link-A. For single link (WXGA), choose Link-A st or B by this function. For dual link (FHD), 1 link (1, 3, 5… 1919) and 2 nd link (2, 4, 6… 1920) can be swapped by this function. The VOT_LNKSWP is used to control this function. The LVDS Tx link swap function operates independently from the LVDS Rx link swap function. 26 CXD4732R 9.2.2. 8-bit / 10-bit Output Mode Selector This LSI supports both 8-bit and 10-bit outputs. In 8-bit mode, Channel 4 of each link is disabled. The LVDS bit assignment is shown in chapter “9.1.7 LVDS Data Format”. This setting is applied to both Link-A and B. To change this mode, see application note. This function works independently from LVDS Rx. 9.2.3. LVDS Tx Output Differential Voltage Adjusting LVDS Tx differential voltage is selectable from 250mV or 350mV. This is selected by register LVTX_SWING. 9.2.4. LVDS Tx Output Disable The registers LVTX_ENA for LVDS Tx Link-A, LVTX_ENB for LVDS Tx Link-B are used to disable the LVDS Tx all signals which include both clock and data. If those signals are disabled, the differential voltages of each pair for all clock and data are set at common voltage. The initial value of this registers are “0” (it is disabled at reset). 9.2.5. Spread-spectrum Clock Generator (SSCG) for LVDS Tx This LSI includes the SSCG to reduce EMI. It supports Center Spreading as shown in Figure 9.2.5.1. To enable this SSCG function, set to LVTX_SSEN. Output Clock Frequency F0 : Reference frequency ( if SS = OFF, output frequency = F0. ) F0 Modulation Depth time Modulation Frequency Center Spreading Figure 9.2.5.1 SSCG Modulation Frequency and Depth The modulation frequency is calculated by the expression of reference frequency / N. N is selected from 4 conditions by setting LVTX_FRSEL. For example, at the Reference frequency = 74.25MHz and N = 512, then Modulation Frequency = 145 kHz. LVTX_FRSEL N 00h N/A 01h 512 02h 640 03h 1024 Modulation depth is selected from 8 conditions by setting LVTX_SSEL and LVTX_SRSEL. 27 CXD4732R LVTX_SSEL LVTX_SRSEL Modulation Depth (Center Spreading) 00h 00h ±0.625 % 00h 01h ±1.25 % 00h 02h N/A 00h 03h N/A 01h 00h N/A 01h 01h N/A 01h 02h N/A 01h 03h N/A Note) This SSCG uses the LVDS Rx clock for source clock. In case of the internal SSCG is enabled, non-SS clock is required for the LVDS Rx clock. If the LVDS Rx clock is SSC (Spread-spectrum Clock), internal SSCG must be disabled. 9.2.6. Spread-spectrum Clock Tracking Capability of LVDS Rx Internal SSCG is OFF and the LVDS Rx clock is SSC, the tracking range of that SSC is shown the following table (Note: these values are only for reference). Tracking Frequency Range Tracking Depth Range 70~150kHz (Tracking Frequency Range * Tracking Depth Range(%)) ≦±150kHz ・% 28 CXD4732R 9.3. Color Management The Color Management function can tune the color reproduction for user's liking. 9.3.1. Color Control Algorithm The color area which a user wants to adjust is selectable from nine color area independently. The colors are Green, Pale Orange1, Red, Blue, Yellow, Magenta, Cyan, Pink, and White when COM_MODE =0h. When COM_MODE =1h, the colors are Green, Pale Orange1, Pale Orange2 (fix area), Red, Blue, Yellow, Magenta, Cyan and White. The Figure 9.3.1.1 shows the concept of the Color Management. This function changes a normalized chromaticity (x, y) only in that color area to an arbitrary chromaticity by setting the direction (dx, dy) and quantity of movement (gain). Maximum chromaticity ranges of each nine color area are fixed and those color area are not overlapped each other. This is to keep color consecutiveness between different color areas after a color changes. Color Change Gain y COM_(color)_GAIN dy k COM_(color)_DY Fixed size Color Change Direction(y) (x, y) dx Target Color Center Location (COM_(color)_SX, COM_(color)_SY) Color Change Direction(x) COM_(color)_DX Fixed size Fixed size Fixed size sy sx Example White is adjustable Figure 9.3.1.1 Color Management 29 x CXD4732R The Table 9.3.1 shows the Registers to control colors in this function, there is only 45 parameters. Color Target Color Coordinates(-8~+7) Color Change Direction (-8~+7) and Gain (0~31) sx sy dx dy gain (x & y) White COM_W_SX COM_W_SY COM_W_DX COM_W_DY COM_W_GAIN Green COM_G_SX COM_G_SY COM_G_DX COM_G_DY COM_G_GAIN Pale Orange1 COM_PO_SX COM_PO_SY COM_PO_DX COM_PO_DY COM_PO_GAIN Red COM_R_SX COM_R_SY COM_R_DX COM_R_DY COM_R_GAIN Blue COM_B_SX COM_B_SY COM_B_DX COM_B_DY COM_B_GAIN Yellow COM_Y_SX COM_Y_SY COM_Y_DX COM_Y_DY COM_Y_GAIN Magenta COM_M_SX COM_M_SY COM_M_DX COM_M_DY COM_M_GAIN Cyan COM_C_SX COM_C_SY COM_C_DX COM_C_DY COM_C_GAIN COM_P_SX COM_P_SY COM_P_DX COM_P_DY COM_P_GAIN - - COM_P_DX COM_P_DY COM_P_GAIN Pink (COM_MODE=0) Pale Orange2 (COM_MODE=1) Table 9.3.1 9.3.2. Color Management registers (Page 00h for all registers. See the register map for details) Gray Out Function The Gray Out function can drop a color ingredient except a selected color to confirm a chosen color area. The COM_GO_EN is used to enable/disable this function. A color is selected by the COM_GON_COL. Gray Out Enable (example: red is selected) Normal Mode Figure 9.3.2 Gray Out Function 30 CXD4732R 9.4. Intelligent Contrast Enhancer(iCE) The iCE function improves contrast feeling depending on picture content adaptively. The iCE function measures histogram of brightness signals for every frame, and a characteristic of a picture is extracted. The contrast gain result is calculated for every frame. The contrast gain level can be adjusted by the ICE_A, ICE_B, and ICE_C. ICE_A and ICE_B decide compensation quantity of gain compensation characteristic A, B determined by histogram of a brightness signal for the whole picture. ICE_C decides quantity of gain compensation determined by calculating histogram of a partial brightness signal for a picture 9.4.1 Brightness Contrast Gain Control ICE_A :iCE A function gain When the brightness histogram of all the pictures concentrates on a center or sides as shown in Figure 9.4.1.1 (a) and (b), iCE adjusts contrast with gain compensation curve where compensation quantity turns over with the center gray level. The ICE_A adjusts quantity of gain compensation for the histogram. If the ICE_A value is high, the quantity of gain compensation increases. For example, when brightness of all the pictures concentrates on a center level and contrast lacks generally as shown in Figure 9.4.1.1 (a), iCE expands brightness distribution to the level shown in the dashed line. When brightness of all the pictures concentrates to the sides (black and white) as shown in Figure 9.4.1.1 (b),iCE also expands brightness distribution to the level shown in dashed line. Output Gray Code Gain compensation curve Output Gray Code Histogram Histogram Input Gray Code Input Gray Code (a) Figure 9.4.1.1 (b) iCE example histogram, case A ICE_B:iCE B function gain When the brightness histogram of all the pictures concentrates on a black or white such as Figure 9.4.1.2 (a) and (b), iCE adjusts contrast with gain compensation curve which connects a white level from a black level smoothly. The ICE_B adjusts quantity of gain compensation for such histogram. If the ICE_B value is high, the quantity of gain compensation increases. For example, when brightness of all the pictures concentrates to high level and contrast lacks on white as shown in Figure 9.4.1.2 (a), iCE expands brightness distribution to low gray level shown in the dashed line. When brightness of all the pictures concentrates to low level and contrast lacks on black as shown in Figure 9.4.1.2 (b), iCE expands brightness distribution to high gray level shown in the dashed line. Therefore, average brightness level (APL or 31 CXD4732R DC level) of a picture is adjusted by this function automatically. Output Gray Code Gain compensation curve Output Gray Code Histogram Histogram Input Gray Code Input Gray Code (a) (b) Figure 9.4.1.2 iCE example histogram, case B ICE_C:iCE C function gain ICE_C controls the signal gain to improve the contrast to react accordingly to the histogram condition of a brightness signal on the each part of the picture. The characteristics of the ICE_C gain compensation is faithful to the histogram of a brightness signal which is shown in Figure 9.4.1.3. Same as ICE_A/ICE_B, the user can adjust how much compensate when checking the result of this control on the real picture to set the register setting. Output Gray Code Gain compensation curve Histogram Input Gray Code Figure 9.4.1.3 9.4.2 iCE example histogram for type C Color Contrast Gain Control ICE_COLOR_GAIN_A:iCE Color gain compensation(DC gain) This register sets the levels of chroma signal values to match the brightness signal values. When brightness signal contrast is enhanced, the balance between brightness signal and chroma signal may be unbalanced. Especially, when the brightness signal distribution after enhancing the contrast by ICE_B setting would be closer to the black level, the average level of luminance (APL) is increased. It makes the picture to be whiter as close as being lacking of chroma signal value. 32 CXD4732R The setting of the ICE_COLOR_GAIN_A is made as shown in Figure 9.4.1.2 (b). The better setting would be available only by user's eyes checking at the effects after changing the value ICE_B. When setting “0” to this register, the function can be set to “Off”. ICE_COLOR_GAIN_B iCE Color gain compensation(Differential gain) Same as ICE_COLOR_GAIN_A, the ICE_COLOR_GAIN_B can adjust the signal balance between brightness and chroma. Especially this register is effective to improve balance in case of histogram which is shown for Figure 9.4.1.1 (a). In other words this register is effective in a case without much change in average level of brightness (APL).The setting of the ICE_COLOR_GAIN_B would be made as shown in Figure 9.4.1.1 (a). Same as ICE_COLOR_GAIN_A, the better setting would be available only by user's eyes checking at the effects after changing the value ICE_A. When setting “0” to this register, the function can be set to “Off”. ICE_SCENE_CHDET iCE Scene change detect sense The iCE function measures histogram of a brightness signal for every frame, and contrast gain is calculated by using this result for every frame. When the gain control speed is fast, brightness level change of a picture can be seen, and the picture seems unnatural. Therefore a gain control circuit has a time constant so that gain change speed becomes slow. In case of “scene change”, brightness histogram of a picture changes greatly and quantity of gain compensation changes greatly. Then, an image just after scene change becomes unnatural by the influence of time constant. The iCE can detect “scene change” by calculating quantity of change in the histogram, iCE makes time constant fast. The ICE_SCENE_CHDET controls threshold of brightness histogram change quantity to detect scene change. When this register is set to low, scene change detection sensitivity is high. ICE_COLOR_GAIN_LMT iCE Color Gain Compensation Limiter The ICE_COLOR_GAIN_LMT limits quantity of color gain compensation set with the ICE_COLOR_GAIN_A, ICE_COLOR_GAIN_B. A color gain does not become too large with this register because it is difficult to decide quantity of color gain compensation corresponding to quantity of brightness gain compensation theoretically. The limiter value is shown in the Table 9.4.1. Table 9.4.1 9.4.3. ICE_COLOR_GAIN_LMT register definition ICE_COLOR_GAIN_LMT Limiter Level (dB) ICE_COLOR_GAIN_LMT Limiter Level (dB) 0 0.0 4 3.5 1 0.5 5 6.0 2 1.0 6 8.0 3 2.0 7 9.0 Black level Control ICE_A_BLACKLEV1 iCE_A Black level compensation knee down point 33 CXD4732R knee down point ICE_A_BLAC KLEV1=0 ICE_A_BLA CKLEV1=3 Figure 9.4.3.1 When ICE_A works, if the value of ICE_A_BLACKLEV1 is increased, minus gain versus linear go up. ICE_A_BLACKLEV1 controls knee down point as shown Figure 9.4.3.1. ICE_A_BLACKLEV2 iCE_A Black level compensation level ICE_A_BLAC KLEV2=0 ICE_A_BLA CKLEV2=7 compensation level Figure 9.4.3.2 When ICE_A works, if the value of ICE_A_BLACKLEV2 is increased, minus gain versus linear go up. ICE_A_BLACKLEV2 controls minus gain level as shown Figure 9.4.3.2. 34 CXD4732R 9.5. 2D-Sharpness This LSI includes two sharpness functions; Y sharpness (Frequency ingredient emphasis of a brightness signal) and CTI (Chrominance Transient Improvement). The Y sharpness function can improve sharpness independently (show Figure 9.5.1) by using a filter of the optimum band-pass, high-pass type for a vertical, horizontal and diagonal of Y signal. Horizontal is 11-tap filter and it has 5 kinds of coefficient. Vertical is 5-tap filter with 4-line memory and it has 2 kinds of coefficient. Those characteristics are changed by the registers of YHSHP_HBAND, YHSHP_VBAND, YVSHP_HBAND and YVSHP_VBAND. The emphasis level can adjust it to ±2 times by using each register YHSHP for horizontal, YVSHP for vertical, and YTSHP for diagonal. The emphasis waveform can be adjusted as shown in Figure. 9.5.2. The YSHP_WB is used for it. Vertical Diagonal Horizontal Figure 9.5.1 Y sharpness control area This function has coring; it can control noise increase more than it for a picture with many noises. Coring level is changed to four phases with register YSHP_CORE. 15: black side/min, white side max Original Y Signal + Emphasis ingredient 8: top and bottom is symmetric Selectable Output Y Signal YSHP_WB = 0: black side/max, white side min Figure 9.5.2 Y sharpness over, under balance 35 CXD4732R For color-difference signal (Cb/Cr), CTI function can improve a through rate of a color edge part of a picture. Edge detection has horizontal filter only. Center frequency can be changed by CTI_F0 and level can be changed by CTI_LEV. Input color-difference signal After improvement Figure 9.5.3 Color transient improvement 36 CXD4732R 9.6. Basic user Controls As other video signal processing, there are Brightness for GBR signals, Color saturation for Cb/Cr signals, and Static contrast for GBR signals. G out B out R out G in B in R in + Limiter Register BRIGHT -128 ~ +127, step 1 @8bit -512 ~ +508, step 4 @10bit (a) Brightness control Cb in Cr in Cb out Cr out × Limiter Register COLOR 0 ~ 255/128 (b) Color saturation control G in B in R in × G out B out R out Limiter Register CONTRAST 0 ~ 255/128 (c)Static Contrast control Figure 9.6 9.7. MC-3DNR This is MC-3DNR function for luminance signal. This function has following features, then reduces random noise in luminance signal. MC-3DNR uses compensation picture optimally according to reliability of motion estimation. MC-3DNR is basically controlled by 3 registers. YNR controls MC-3DNR ON/OFF. FBHISTTH and NLFB control time constant of MC-3DNR filter. And the effort of MC-3DNR is controlled by registers combination. Now 5 levels setting from weakest to strongest are available. For more information, see application note. 9.8. Basic user Controls GRC(GRadation Creation) includes following two functions. ・Adaptive horizontal smoothing ・Adaptive horizontal and vertical coring ・Mosquito noise reduction (MNR) When GRC_EN is enabled, adaptive horizontal smoothing function works for only low frequency component in input signal. For only high frequency component in input signal, adaptive horizontal and vertical coring is prepared. GRC_HCORE and GRC_VCORE are controlling registers. These three functions work to reduce pseudo outline. MNR is mosquito noise reduction. For mosquito noise around edge signals, MNR_FLAT_LEV is used. If mosquito noise also exists in flat area, MNR_FLAT_LEV is more used. 37 CXD4732R 9.9. SUPER RESOLUTON This function achieves super resolution with noise inhibiting. It adjusts the most appropriate effect automatically by analyzing input picture pixel by pixel. You can also adjust the effect of super resolution with the following items. If you want to control everything, there is manual control mode, too. [Whole gain adjustment] Relative I2C register: VOLE_BVD, NSHIFT Increasing this gain, the effect of super resolution and noise reducing is up. [Adjustment around TEXT] Relative I2C register: VOLERATIOMAX, VOLERATIOMIN This is used to control effect around text. If you don’t like shoots around text or line, turn down this value. [Control in pale orange area] Relative I2C register: HADAON, HADA_EFFECT, NLIMIT When you use this function, the effect of Super Resolution in pale orange area is reduced. And its degree is controllable. [Manual control] Relative I2C register: ICONTON, VOLN, VOLR, VOLE You can stop Super Resolution automatic adjustment, and you can control the effect of super resolution and noise reducing according to your preference. Whole gain is able to be controlled. Even if you select manual control mode, “Adjustment around TEXT” and “Control in pale orange area” are available. About register’s relation see Figure 9.9.1. VOLE_BVD NSHIFT VOLE VOLN VOLR Automatic Control ICONTON Select control type Manual Control Video Signal in Super Resolution Core SPCOFF HADAON HADA_EFFECT NLIMIT VOLERATIOMIN VOLERATIOMAX Figure 9.9.1 Super Resolution Block 38 Video Signal out CXD4732R 9.10. Digital Gamma Function This LSI includes digital gamma function with two look-up tables (Group A and B). Each group has GBR independent 12bit 2 Full-Size LUT. While one group works, another group can be updated to arbitrary 12 bits curve by I C interface. Active group and inactive/updating group are changed by GMTBL_SEL. All digital gamma function can be disabled by GMTBL_EN. At the power-on reset, GMTBL_EN is 0 (default is disabled). Change to enable this register after setup was completed. Refer to the register map about details of LUT data transfer format (Chapter 11.3.3 Table Registers) and setup sequence (Chapter 10.2 Digital Gamma Function Look-up Digital Gamma Function Look-up Table Setup). GBR Data In G (10bit) B (10bit) R (10bit) GBR independent gamma LUT Group A 12bit × 1024word 12bit × 1024word 10 x 3 A 12bit × 1024word LUT GBR independent gamma LUT ON Group B 12bit × 1024word 12bit × 1024word Dither Block B 12bit × 1024word LUT 12 x 3 OFF (Through) Delay Vsync Latch Group ON/OFF(through) Selection Register GMTBL_EN Group A/B Selection Register GMTBL_SEL Figure 9.10 GBR Data Out G (12bit) B (12bit) R (12bit) Digital Gamma Function and Dither Block Diagram 39 G B R 8bit x 3 or 10bit x 3 CXD4732R 9.11. Dither This function includes four methods to reduce the video data width from 12bit to 8 (or 10) bit. Those methods are Rounding, FRC (Frame rate conversion), 2 x 2 matrix pattern dithers, and 4 x 4 matrix pattern dithers. FRC and dither methods provide good gradation performance for 8bit/10bit panel. See the register map for details to control this function. 9.11.1. FRC (Frame rate conversion) FRC is a time sharing process for lower 2bit of 12bit. As shown in Figure 9.11.1, the yellow frame means round-up and gray frame mean round-down. Time (Frame) error = 0 error = 1 error = 2 Figure 9.11.1 9.11.2. error = 3 FRC Bit Processing Pattern Dither Pattern dither is a space error spreading process for lower 2bit/4bit of 12bit. As shown in Figure 9.11.2, the number in the box is threshold value for error. For example, in 2 x 2 pattern dither, if error = 2 then “0” and “1” pixels are round-up, “2” and “3” pixels are round-down. In 4 x 4 pattern dither, same procedure is used. Here the yellow box means round-up and gray box means round-down. Horizontal 0 0 3 2 Horizontal 1 Vertical 8 2 10 12 4 14 6 3 11 1 9 15 7 13 5 Vertical (a) 2 x 2 pattern (b) 4 x 4 pattern Figure 9.11.2 40 Pattern Dither CXD4732R 10. Description of Operation 10.1. Power and Reset Sequence There is no constraint about the turn-on/off order of two power supply voltages (1.2V and 3.3V). But it is preferable to apply both voltages at the same time. 10.1.1. Turn on Sequence without External EEPROM 3.3V Power Supply 3.0V 1.2V Power Supply 1.1V 0V SCLKI Unstable External clock is stable External System Clock Release reset RST_X Hard Reset >250ns IIC_MST_EN Fixed Low (Master I/F is disabled) I2C Master Enable IIC_SCL IIC_SDA I 2C Bus Disable I2C Slave I/F bus enable Slave I/F External I2C Host can access to CXD4732 registers (~350m sec for minimum setup) Registers for clock system are written. LVDS Rx Unstable/Unknown Video Clock In Data In LVDS Tx Frame n Unstable n+2 Circuites are starting LVDS Tx clock is stable Video Clock Out LVDS Tx Frame n+1 ~6ms (PLL and LVDS-Tx lock time after setting registers) Unknown Frame n+1 Video Data Out Figure 10.1.1 Power On and Reset Sequence (I2C Slave I/F Only) 41 n+2 CXD4732R 10.1.2. Turn on Sequence with External EEPROM If the terminal IIC_MST_EN is high when the reset RST_X is released, the registers are initialized automatically by reading 2 an initial value from an external EEPROM. (See the Chapter 10.3.5 I C Master Interface for details) 3.3V Power Supply 3.0V 1.2V Power Supply 1.1V 0V SCLKI Unstable External clock is stable External System Clock Release reset RST_X Hard Reset >250ns Fixed High (Master I/F is enabled) IIC_MST_EN I2C Master Enable Internal I2C Master I/F access to External EEPROM ~400ms for maximum setup (SCLKI=25MHz) IIC_SCL IIC_SDA I2C Master I/F enable I2C Master I/F I2C system Slave I/Fare buswritten. enable Registers for clock IIC_SLV_BUSY Output signal IIC_SCL IIC_SDA Bus Disable I2C Slave I/F bus enable I2C Slave I/F LVDS Rx External I2C Host can access to CXD4732 registers Unstable/Unknown Video Clock In Data In LVDS Tx Frame n n+2 ~6ms (PLL and LVDS-Tx lock time after setting registers) Circuites are starting Unstable LVDS Tx clock is stable Video Clock Out LVDS Tx Frame n+1 Unknown Frame n+1 Video Data Out Figure 10.1.1 Power On and Reset Sequence (I2C Slave I/F Only) 42 n+2 CXD4732R 10.2. Gamma Correction Look-up Table Setup The following sequence is required when writing/updating the gamma correction look-up table (LUT). 10.2.1. Initializing Gamma LUT Group-A (1) Gamma correction function control registers setup: write registers as below, Sub address FFh, data 1Fh // page change to 1Fh. Sub address 03h, data 00h // gamma function disable Sub address 00h, data 00h // Group-A I2C write enable Sub address 01h, data 00h // Group-A I2C write enable Sub address 02h, data 00h // Group-A I2C write enable Sub address 04h, data 01h // Group-B Normal mode Sub address 05h, data 01h // Group-B Normal mode Sub address 06h, data 01h // Group-B Normal mode Sub address 07h, data 00h // Group-A/B select If the table for Group-B is already initialized, it is possible to use the Gamma LUT Group-B while writing Group-A. In this case, Sub address 03h > data 01h, Sub address 07h > data 01h. (2) Look-up table for Group A (3) Exit LUT setup mode and go to Normal mode. Sub address FFh, data 1Fh // page change to 1Fh. Sub address 00h, data 01h // Group-A Normal mode Sub address 01h, data 01h // Group-A Normal mode Sub address 02h, data 01h // Group-A Normal mode Sub address 04h, data 01h // Group-B Normal mode Sub address 05h, data 01h // Group-B Normal mode Sub address 06h, data 01h // Group-B Normal mode Sub address 07h, data 00h // Group-A is selected Sub address 03h, data 01h // gamma function enable 43 CXD4732R 10.2.2. Initializing Gamma LUT Group-B (1) Gamma correction function control registers setup: write registers as below, Sub address FFh, data 1Fh // page change to 1Fh. Sub address 03h, data 00h // gamma function disable Sub address 00h, data 01h // Group-A Normal mode Sub address 01h, data 01h // Group-A Normal mode Sub address 02h, data 01h // Group-A Normal mode Sub address 04h, data 00h // Group-B I2C write enable Sub address 05h, data 00h // Group-B I2C write enable Sub address 06h, data 00h // Group-B I2C write enable Sub address 07h, data 01h // Group-A/B select If the table for Group-A is already initialized, it is possible to use the Gamma LUT Group-A while writing Group-B. In this case, Sub address 03h > data 01h, Sub address 07h > data 00h. (2) Look-up table for Group B (3) Exit LUT setup mode and go to Normal mode. Sub address FFh, data 1Fh // page change to 1Fh. Sub address 00h, data 01h // Group-A Normal mode Sub address 01h, data 01h // Group-A Normal mode Sub address 02h, data 01h // Group-A Normal mode Sub address 04h, data 01h // Group-B Normal mode Sub address 05h, data 01h // Group-B Normal mode Sub address 06h, data 01h // Group-B Normal mode Sub address 07h, data 01h // Group-B is selected Sub address 03h, data 01h // gamma function enable 44 CXD4732R 10.3. Host I/F 10.3.1. I2C Slave Interface 2 This LSI has an I C bus slave transceiver. This supports 7 bits slave address and fast transfer mode (400kbit / sec). Slave address can be selectable from four addresses by setting external pin. 10.3.2. I2C Slave Write Cycle After sending slave address from the external master interface to this slave interface, the write start sub- address is set by the master. The next cycle is 1st data to write control register and the write cycle is repeated by host I/F. When data is written in continually, the internal sub-address is automatically incremented. S Slave Address W [7:1] (7bit) “0” A Start Sub Address A Write Data (8bit) A Last Write Data (8bit) A P (8bit) Note) Gray: From Master (External Host) to Slave (CXD4732R). White: From Slave to Master S: Start Bit P: Stop Bit A: Acknowledge 10.3.3. I2C Slave Read Cycle Before reading control registers, set the read start sub-address by the same method as write cycle. After then, the external master interface sends the slave address with read command and the internal slave interface returns the read data after next cycle. When data is read in continually, internal sub-address is automatically incremented. S S Slave Address W [7:1] (7bit) “0” Slave Address R [7:1] (7bit) “1” A Start Sub Address A P (8bit) A Read Data A Last Read Data (8bit) (8bit) Note) Gray: From Master (External Host) to Slave (CXD4732R). White: From Slave to Master S: Start Bit P: Stop Bit A: Acknowledge N: No Acknowledge 45 N P CXD4732R 10.3.4. I2C Slave Page Address This LSI can transfer more than 256 bytes of register by using the Page Addressing method. The last 32bytes (E0h~FFh) of sub-address are used for common registers that include page address. Sub-address 00h~DFh are used for function registers. It have some pages (00h~1Fh pages) and the page is changed by common register PAGE (sub address: FFh, bit [4:0]). Total function registers are 224 address x 32 pages. 2 Refer to Chapter 11.2 I C Page Address Map. To change the page address, the following sequence is required. New page writing: (1) Set/Change page S Slave Address W [7:1] (7bit) “0” A Page Sub Address A Write Page FFh A P (new page) (2) Write register S Slave Address W [7:1] (7bit) “0” A Start Sub Address A Write Data (8bit) A Last Write Data (8bit) (8bit) New page reading: (1) Set/Change page S Slave Address W [7:1] (7bit) “0” A Page Sub Address A Write Page FFh A P N P (new page) (2) Set start address for reading S Slave Address W [7:1] (7bit) “0” A Start Sub Address A P (8bit) (3) Read register S Slave Address R [7:1] (7bit) “1” A Read Data A Last Read Data (8bit) (8bit) Note) Gray: From Master (External Host) to Slave (CXD4732R). White: From Slave to Master S: Start Bit P: Stop Bit A: Acknowledge 46 A P CXD4732R 10.3.5. I2C Master Interface 2 This LSI includes I C master interface. It operates once automatically after releasing hard reset to initialize the internal registers. 2 When the IIC_MST_EN pin is held High, I C master I/F is enabled. After the hard reset pin RST_X becomes High from 2 Low, I C master interface automatically reads the initial register settings from external serial EEPROM which is connected to 2 2 the I C master interface, and write it to the internal registers. If it cannot read data correctly, the I C master interface is 2 stopped and the I C slave interface is enabled. CXD4732R Internal Registers CXD4732R Internal Registers Once after releasing reset. IIC_MST_SCL IIC_MST_SDA IIC_MST_EN IIC_SLV_SDA IIC_MST_SDA IIC_MST_EN IIC_MST_SCL External Host CPU, etc. Serial EEPROM I2C Master I/F IIC_SLV_BUSY (Open) External Host CPU, etc. VDDIO IIC_SLV_SCL I2C Slave I/F I2C Master I/F IIC_SLV_BUSY IIC_SLV_SCL IIC_SLV_SDA I2C Slave I/F VSSIO Recommended EEPROM: M24128 or Equivalent 2 (b) I C Slave interface only (a) Using Serial EEPROM Figure 10.3.5.1 I2C Interface 2 2 This LSI supports 128 Kbit I C serial EEPROM. As shown in Figure 10.3.5.1(a), the I C master interface operates 2 2 2 independently of I C slave interface. While the I C master interface operates, the I C slave interface can only read. 2 Therefore, before writing registers from external master device such as Host CPU through the I C slave interface of this LSI, 2 2 check the status by status register or the IIC_SLV_BUSY pin. (While the I C master interface is operating, the I C slave interface accepts write command and returns Acknowledge. Note that the internal data path is disconnected.) In case of no external EEPROM as shown in Figure 10.3.5.1(b), all registers must be written by external host device to initialize this LSI. RST_X IIC_SLV_BUSY I2C Master I/F I2C Slave I/F IDLE Read EEPROM data IDLE Normal Operation Read only Normal operation Figure 10.3.5.2 47 Startup sequence CXD4732R 10.3.6. I2C Bus through mode 2 2 2 This LSI connects I C master interface and I C slave interface in I C Bus through mode, as shown in Figure 10.3.6.1. 2 Host CPU can access EEPROM in this mode. When the IIC_MUST_BTHR = 1, it becomes I C Bus through mode. 2 Note) Please check the status of I C master interface by the status register IIC_MST_BUSY or the IIC_SLV_BUSY pin 2 before switching into the I C Bus through mode. CXD4732R Internal Registers External Host CPU, etc. IIC_MST_SCL IIC_MST_SDA IIC_MST_EN I2C Master I/F IIC_SLV_BUSY IIC_SLV_SCL Status Register Read Only IIC_SLV_SDA I2C Slave I/F Serial EEPROM M24128 or Equivalent Figure 10.3.6.1 48 I2C Bus through mode VDDIO ~ 7Fh 80h ~ BFh FFh 49 Lower 8bit LUT 080h~0FFh Lower 8bit LUT 100h~17Fh Lower 8bit LUT 180h~1FFh Lower 8bit LUT 200h~27Fh Lower 8bit LUT 280h~2FFh Lower 8bit LUT 300h~37Fh Upper 4bit Upper 4bit Upper 4bit Upper 4bit Upper 4bit Upper 4bit (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) 06h Lower 8bit LUT 000h~07Fh 05h Upper 4bit 04h (reserved) 03h Lower 8bit LUT 380h~3FFh 02h Upper 4bit Lower 8bit LUT 280h~2FFh Upper 4bit (reserved) 01h (reserved) Lower 8bit LUT 200h~27Fh Upper 4bit (reserved) Sub Lower 8bit LUT 300h~37Fh Lower 8bit LUT 180h~1FFh Upper 4bit (reserved) IIC_MST_SADSEL Upper 4bit Lower 8bit LUT 100h~17Fh Upper 4bit (reserved) IIC_SLV_SADSEL1 (reserved) Lower 8bit LUT 080h~0FFh DFh Upper 4bit ~ (reserved) 00h Lower 8bit LUT 000h~07Fh C0h 00h Upper 4bit Address (reserved) 11. EXPRESSION Control Registers CXD4732R Control Register Map 11.1. I C Slave Address 2 Slave address in CXD4732R can be selected from four (for slave interface), two (for Master interface) in the list below by the combination of the IIC_SLV_SADSEL0, IIC_SLV_SADSEL1, and IIC_MST_SADSEL pins. IIC_SLV_SADSEL0 07h I2C Slave Address I2C Slave Address (write) (read) 0 0 90h 91h 0 1 92h 93h 1 0 94h 95h 1 1 96h 97h EEPROM Slave Address EEPROM Slave Address (write) (read) 0 ACh ADh 1 AEh AFh 11.2. I C Page Address Map 2 Page Address 08h 09h E0h ~ Common Registers (FFh: Page Address Setting) 0Ah Digital Gamma Table (Green) 0Bh 0Ch Digital Gamma 0Dh 0Eh 0Fh Table (Blue) Lower 8bit LUT 200h~27Fh Lower 8bit LUT 280h~2FFh Upper 4bit Upper 4bit (reserved) (reserved) FFh 50 E0h ~ Common Registers (FFh: Page Address Setting) (reserved) 1Fh Gamma/Dither Control Registers 00h System Control Registers ) 1Eh System Control Registers Digital Gamma Table (Red) 1Dh GRC Control Registers 1Ch (reserved) 1Bh System Control Registers 1Ah (reserved) 19h Super Resolution Control Registers 18h Control Registers 17h MC-3DNR 16h Video Input Control Registers 15h Video Output Control Registers 14h Lower 8bit LUT 380h~3FFh (Blue 13h Upper 4bit 12h (reserved) 11h Lower 8bit LUT 300h~37Fh 10h Upper 4bit Sub (reserved) (reserved) Lower 8bit LUT 180h~1FFh Upper 4bit (reserved) DFh Lower 8bit LUT 100h~17Fh ~ Upper 4bit C0h (reserved) BFh Lower 8bit LUT 080h~0FFh ~ Upper 4bit 80h (reserved) 7Fh Lower 8bit LUT 000h~07Fh ~ Upper 4bit 40h (reserved) 3Fh Lower 8bit LUT 380h~3FFh ~ Upper 4bit Address (reserved) CXD4732R Page Address (Continued) CXD4732R 2 11.3. I C Sub Address Map Explanatory note: when the fixed value is written in the list, the value with "h" indicates hexadecimal number and the other value of "0" or "1" indicates the binary number. The “-“means “don’t care”. The register with “*” requires to write the default settings values in accordance with a system. 11.3.1. Common Registers (No Page Address, Sub Address = E0h~FFh) Page Addr. - E0h - E1h Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] **** Bit [ 2 ] Bit [ 1 ] *** CLK_RXCLK_SEL ~ Bit [ 0 ] ******** E5h - E6h - E7h - E8h *** LVTX_SWING ** LVTX_SRSEL ~ 1 LVTX_ENB LVTX_ENA 0 LVTX_SSEL LVTX_SSEN 0 0 0 IIC_MST_BTHR LVTX_FRSEL ******** E9h - EAh - EBh 0 0 0 0 ~ ******** F1h - F2h - - - - - - - VREG_VLTEN F3h - - - - - - -- 0 - IIC_MST_NVM_ERR F4h~ F6h - F7h - F8 ~ - - - - IIC_MST_BUSY FEh - FFh 0 0 PAGE 0 11.3.2. EXPRESSION Control Registers (Page Address = 00h, Sub Address = 00h~DFh) Page Addr. Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] Bit [ 0 ] 00h 00h - * 00h 01h ******* I_GBR_RANGE 00h 02h~ ******** 13h 00h 14h ******* 51 O_GBR_RANGE CXD4732R 00h 15h CONTRAST 00h 16h BRIGHT 00h 17h COLOR 00h 18h~ 19h 00h 1Ah - * 00h 1Bh - * 00h 1Ch COM_GON_COL 00h 1Dh COM_W_SX COM_W_SY 00h 1Eh COM_G_SX COM_G_SY 00h 1Fh COM_PO_SX COM_PO_SY 00h 20h COM_R_SX COM_R_SY 00h 21h COM_B_SX COM_B_SY 00h 22h COM_Y_SX COM_Y_SY 00h 23h COM_M_SX COM_M_SY 00h 24h COM_C_SX COM_C_SY 00h 25h COM_P_SX COM_P_SY 00h 26h COM_W_DX COM_W_DY 00h 27h COM_G_DX COM_G_DY 00h 28h COM_PO_DX COM_PO_DY 00h 29h COM_R_DX COM_R_DY 00h 2Ah COM_B_DX COM_B_DY 00h 2Bh COM_Y_DX COM_Y_DY 00h 2Ch COM_M_DX COM_M_DY 00h 2Dh COM_C_DX COM_C_DY 00h 2Eh COM_P_DX COM_P_DY 00h 2Fh *** COM_W_GAIN 00h 30h *** COM_G_GAIN 00h 31h *** COM_PO_GAIN 00h 32h *** COM_R_GAIN 00h 33h *** COM_B_GAIN 00h 34h *** COM_Y_GAIN 00h 35h *** COM_M_GAIN 00h 36h *** COM_C_GAIN 00h 37h *** COM_P_GAIN 00h 38h - COM_MODE 00h 39h - * 00h 3Ah - ICE__A COMACT_SEL ICE_B 52 COM_GO_EN COM_EN CXD4732R 00h 3Bh - ICE_C 00h 3Ch - 00h 3Dh - ICE_COLOR_GAIN_A 00h 3Eh *** ICE_COLOR_GAIN_B 00h 3Fh 00h 40h 00h 41h 00h 42h 00h 43h YHSHP 00h 44h YVSHP 00h 45h YTSHP 00h 46h 00h 47h 00h 48h 00h 49h 00h 4A ~ ***** ICE_SCENE_CHDET ICE_A_BLACKLEV1 ICE_FILT_TC - ICE_COLOR_GAIN_LMT - ICE_BGFACT ICE_A_BLACKLEV2 ICE_B_BALANCE - YHSHP_HBAND ** YHSHP_VBAND YVSHP_HBAND YSHP_WB YVSHP_VBAND - YSHP_CORE - CTI_LEV ******** - CTI_F0 DFh 11.3.3. Digital Gamma Function Look-up Table Registers (Page Address = 01h~18h, Sub Address = 00h~BFh) Page Addr. 01h 00 ~ Bit [ 7 ] BFh 02h Digital Gamma 03h 04h Digital Gamma Bit [ 1 ] Bit [ 0 ] LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 000h) * 2 + 0) LUT Lower 8bit [7:0] for Green LUT Upper 4bit [11:8] for Green <Odd Code> Digital Gamma LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 080h) * 2 + 0) Digital Gamma LUT Lower 8bit [7:0] for Green Gamma table address = (Sub Address + 100h) Digital Gamma LUT Upper 4bit [11:8] for Green <Odd Code> Digital Gamma Gamma table address = ((Sub Address - 80h + 100h) * 2 + 1) LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 100h) * 2 + 0) Digital Gamma 7Fh BFh Digital Gamma Gamma table address = ((Sub Address - 80h + 080h) * 2 + 1) 00 ~ 80 ~ Bit [ 2 ] Gamma table address = (Sub Address + 080h) 7Fh BFh LUT Upper 4bit [11:8] for Green <Odd Code> Digital Gamma 00 ~ 80 ~ Bit [ 3 ] LUT Lower 8bit [7:0] for Green Gamma table address = ((Sub Address - 80h + 000h) * 2 + 1) 7Fh BFh Bit [ 4 ] Gamma table address = (Sub Address +000h) 00 ~ 80 ~ Bit [ 5 ] Digital Gamma 7Fh 80 ~ Bit [ 6 ] LUT Lower 8bit [7:0] for Green Gamma table address = (Sub Address + 180h) Digital Gamma LUT Upper 4bit [11:8] for Green <Odd Code> Gamma table address = ((Sub Address - 80h + 180h) * 2 + 1) Digital Gamma LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 180h) * 2 + 0) 53 CXD4732R 05h 00 ~ Digital Gamma 7Fh 80 ~ BFh 06h Gamma table address = (Sub Address + 200h) Digital Gamma 07h Digital Gamma 08h 09h Digital Gamma Gamma table address = ((Sub Address - 80h + 300h) * 2 + 1) Digital Gamma Gamma table address = (Sub Address + 380h) Digital Gamma LUT Upper 4bit [11:8] for Green <Odd Code> Gamma table address = ((Sub Address - 80h + 380h) * 2 + 1) Digital Gamma Digital Gamma LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 000h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 080h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 100h) LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 100h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 180h) BFh LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 180h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 200h) BFh Digital Gamma LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 180h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 100h) * 2 + 0) 00 ~ Digital Gamma LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 080h) * 2 + 0) 00 ~ Digital Gamma LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 000h) * 2 + 0) Gamma table address = (Sub Address + 080h) Digital Gamma LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 380h) * 2 + 0) 7Fh 80 ~ 0Eh LUT Lower 8bit [7:0] for Green Digital Gamma BFh LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 300h) * 2 + 0) 00 ~ 80 ~ 0Dh Digital Gamma Gamma table address = (Sub Address + 000h) BFh 0Ch LUT Upper 4bit [11:8] for Green <Odd Code> 7Fh 80 ~ 0Bh LUT Lower 8bit [7:0] for Green Digital Gamma BFh LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = ((Sub Address - 80h + 280h) * 2 + 0) 00 ~ 80 ~ 0Ah Digital Gamma Gamma table address = (Sub Address + 300h) 7Fh BFh LUT Upper 4bit [11:8] for Green <Odd Code> Digital Gamma 00 ~ 80 ~ LUT Lower 8bit [7:0] for Green Gamma table address = ((Sub Address - 80h + 280h) * 2 + 1) 7Fh BFh LUT Upper 4bit [11:8] for Green <Even Code> Gamma table address = (Sub Address + 280h) 00 ~ 80 ~ Digital Gamma Gamma table address = ((Sub Address - 80h + 200h) * 2 + 0) Digital Gamma 7Fh BFh LUT Upper 4bit [11:8] for Green <Odd Code> Gamma table address = ((Sub Address - 80h + 200h) * 2 + 1) 00 ~ 80 ~ LUT Lower 8bit [7:0] for Green LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 200h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 200h) * 2 + 0) 00 ~ Digital Gamma 7Fh Gamma table address = (Sub Address + 280h) 54 LUT Lower 8bit [7:0] for Blue CXD4732R 80 ~ BFh 0Fh Gamma table address = (Sub Address + 300h) 14h 15h 16h 17h LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 300h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 380h) Digital Gamma LUT Upper 4bit [11:8] for Blue <Odd Code> Gamma table address = ((Sub Address - 80h + 380h) * 2 + 1) LUT Lower 8bit [7:0] for Blue Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 000h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 000h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 080h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 080h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 100h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 100h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 180h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 180h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 200h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 200h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 280h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 280h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma Digital Gamma 7Fh Gamma table address = (Sub Address + 300h) Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 300h) * 2 + 1) LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 280h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 200h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 180h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 100h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 080h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 000h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 380h) * 2 + 0) 00 ~ 80 ~ LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 300h) * 2 + 0) 00 ~ BFh 13h Digital Gamma LUT Upper 4bit [11:8] for Blue <Even Code> Gamma table address = ((Sub Address - 80h + 280h) * 2 + 0) 7Fh 80 ~ 12h Gamma table address = ((Sub Address - 80h + 280h) * 2 + 1) Digital Gamma Digital Gamma BFh 11h LUT Upper 4bit [11:8] for Blue <Odd Code> 00 ~ 80 ~ 10h Digital Gamma LUT Upper 4bit [11:8] for Red <Odd Code> LUT Lower 8bit [7:0] for Red Digital Gamma LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 300h) * 2 + 0) 55 CXD4732R 18h 00 ~ Digital Gamma 7Fh Gamma table address = (Sub Address + 380h) 80 ~ Digital Gamma BFh Gamma table address = ((Sub Address - 80h + 380h) * 2 + 1) LUT Lower 8bit [7:0] for Red LUT Upper 4bit [11:8] for Red <Odd Code> Digital Gamma LUT Upper 4bit [11:8] for Red <Even Code> Gamma table address = ((Sub Address - 80h + 380h) * 2 + 0) 11.3.4. Video Input Control Registers (Page Address = 1Ah, Sub Address = 00h~7Fh) Page Addr. Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] Bit [ 0 ] 1Ah 00h 0 0 0 0 0 0 VIN_LNKMS_SEL * VIN_LINK_MD * 1Ah 01h * * * * * * * * 1Ah 02h * * VIN_SYNC1 1Ah 03h * * VIN_SYNC2 1Ah 04h * * VIN_SYNC3 1Ah 05h * * * * * * DEVALID * 1Ah 06~ * * * * * * * * VIN_LVRMP_8BSFT * * * * * * * 0Fh 1Ah 10h 1Ah 11h 1Ah 12h 1Ah 13 ~ 00h - VIN_LVRM_LVFMTSEL* * 00h 48h 1Ah 49 ~ 7Fh 11.3.5. Video Output Control Registers (Page Address = 1Ah, Sub Address = 80h~DFh) Page Addr. Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] 1Ah 80h 1Ah 81h * * * * * * * * 1Ah 82h * * * * * * * * 1Ah 83h * * * * * 1Ah 84 ~ * * * * * * * 00h * VOT_SYNC1 * * * Bit [ 0 ] VOT_LINK_MD 86h 1Ah 87h VOT_LVTMP_8BSFT * 00h 1Ah 88h * * * * * * * * 1Ah 89h * * * * * * * * 1Ah 8Ah VOT_LNKSWP * * * 1Ah 8Bh * * * * 00h * * * * 56 CXD4732R 1Ah 8Ch 1Ah 8Dh 1Ah 8E ~ * * * 00h * * * VOT_LVTMP_LVFMTSEL * * * * SYNC_MODE Bit [ 1 ] Bit [ 0 ] 00h 00h AFh 1Ah B0 ~ ******** B3h 1Ah B4h * 1Ah B5h * 1Ah B6h * 1Ah B7 ~ * * * VWIDTH HWIDTH * * * * * ******* DFh 11.3.6. MC-3DNR Control Registers (Page Address = 1Bh, Sub Address = 00h~DFh) Page Addr. 1Bh 00h~ Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] Bit [ 2 ] ******* 0Bh 1Bh 0Ch 1Bh 0Dh ******* YNR ******* ~ 21h 1Bh 22h ******* MINALFA 1Bh 23h ******* MAXALFA 1Bh 24h~ ******* 2Ch 1Bh 2Dh 1Bh 2Eh 1Bh 2Fh~ ******* PNR_PK CLIPKMAX ******* ******* 32h 1Bh 33h ******* FBHISTTH 1Bh 34h ******* NLFB 1Bh 35h~ ******* 57h 1Bh 58h 1Bh 59h~ ******* BKYCTRL_DEFVOL ******* 5Ah 1Bh 5Bh 1Bh 5Ch ******* BKYCTRL_VP BKYCTRL_GRDV_H 57 CXD4732R 1Bh 5Dh 1Bh 5Eh BKYCTRL_GRDV_L ~ ******* B9h 1Bh BAh ~ - DFh Sony provides the register setting sets corresponding to the intensity of noise reduction. 11.3.7. Super Resolution Control Registers (Page Address = 1Ch, Sub Address = 00h~DFh) Page Addr. 1Ch 00h~ Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] ******* 0Fh 1Ch 10h VOLN 1Ch 11h VOLR 1Ch 12h VOLE 1Ch 13h~ ******* 1Ah 1Ch 1Bh VOLERATIOMIN 1Ch 1Ch VOLERATIOMAX 1Ch 1Dh ******* ~ 23h 1Ch 24h 1Ch 25h~ ******* NSHIFT ******* 3Dh 1Ch 3Eh VOLE_BVD 1Ch 3Fh~ ******** 6Ch 1Ch 6Dh 1Ch 6Eh NLIMIT **** ******* ~ 7Fh 1Ch 80h 1Ch 81h~ HADAON ******* ******* 85h 1Ch 86h SPCOFF ******* 58 Bit [ 0 ] CXD4732R 1Ch 87h 1Ch 88h 1Ch 89h~ ******* ICONTON ******* ******* 8Ah 1Ch 8Bh 1Ch 8Ch ******* HADA_EFFECT ******* ~ DFh 11.3.8. GRC Control Registers (Page Address = 1Dh, Sub Address = 00h~DFh) Page Addr. 1Dh 00h~ Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] Bit [ 0 ] ******* 2Dh 1Dh 2Eh 1Dh 2Fh 1Dh 30h 1Dh 31h 1Dh 32h~ ******* ******* GRC_EN GRC_VCORE ******* GRC_HCORE ******* MNR_FLAT_LEV ******* MNR_EDGE_LEV ******* DFh 11.3.9. Gamma and Dither Control Registers (Page Address = 1Fh, Sub Address = 00h~3Fh) Page Addr. Bit [ 7 ] 1Bh 00h 00h TBLA_SCLK_MSK 1Bh 01h 00h TBLA_RDEN 1Bh 02h 00h TBLA_VCLK_EN 1Bh 03h 00h GMTBL_EN 1Bh 04h 00h TBLB_SCLK_MSK 1Bh 05h 00h TBLB_RDEN 1Bh 06h 00h TBLB_VCLK_EN 1Bh 07h 00h GMTBL_SEL 1Bh 08h 1Bh 09h 1Bh 0Ah 1Bh 0B ~ 0 Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] DITH_BIT Bit [ 2 ] Bit [ 1 ] DITH_MODE 00h DITH_EN DITH_INC ******** 3Fh 59 Bit [ 0 ] CXD4732R 11.3.10. Other System Control Registers-1 (Page Address = 1Dh, Sub Address = 40h~DFh) Page Addr. 1Dh 40h Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] ~ Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] Bit [ 0 ] ******* BFh 1Dh C0h ~ - DFh 11.3.11. Other System Control Registers-2 (Page Address = 1Eh, Sub Address = 00h~DFh) Page Addr. 1Eh 00h Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] ~ Bit [ 3 ] Bit [ 2 ] Bit [ 1 ] Bit [ 0 ] ******* 3Fh 1Eh 40h ~ - DFh 11.3.12. Other System Control Registers-3 (Page Address = 1Fh, Sub Address = 40h~DFh) Page Addr. 1Fh 40 ~ Bit [ 7 ] Bit [ 6 ] Bit [ 5 ] Bit [ 4 ] Bit [ 3 ] ******* 6Fh 1Fh 70h ~ - DFh 60 Bit [ 2 ] Bit [ 1 ] Bit [ 0 ] CXD4732R 2 11.4. I C Register Description Explanatory note: The value with "h" indicates hexadecimal number, the value of "0" or "1" indicates the binary number, and other value indicates decimal number. In a row of Direction, “R” means Read Only Register, “W” means Write Only register, and “W/R” means both Write and Read Register. The registers with “*” are V-latched registers. Those register values are reflected by every V-sync. 11.4.1. Common Registers (No Page Address) Function Page Addr. bit Direction Register Name Description - FFh [4:0] W/R PAGE Page select from 00h~1Bh - EAh [0] W/R IIC_BTHR I2C slave port to master port through operation Category I2C Function 0:disable - F7h [0] R 1:through operation enable I2C master busy flag. 0: master is not busy, so accessing to I2C slave is not IIC_MST_BUSY inhibited 1: master is busy, so accessing to I2C slave port is inhibited. - F7h [2:1] R IIC_MST_NVM_ERR NVM access error status Clock Path - E0h [3] LVDS Tx and - E6h SSCG control - 0: no error other: error W/R CLK_RXCLK_SEL Video clock source select [4] W/R LVTX_SWING LVDS Tx all clocks and all data swing voltage select E6h [1] W/R LVTX_ENA LVDS Tx Link-A output enable 0: disable 1: enable - E6h [2] W/R LVTX_ENB LVDS Tx Link-B output enable 0: disable 1: enable - E7h [2] W/R LVTX_SSEN LVDS Tx spread spectrum clock (SSCG) enable - E7h [1:0] W/R LVTX_FRSEL LVDS Tx SSCG modulation frequency select - E7h [3] W/R LVTX_SSEL LVDS Tx SSCG - E7h [5:4] W/R LVTX_SRSEL LVDS Tx SSCG spread ratio select F2h [0] W/R VREG_VLTEN 0: LVDS Rx Link-A spread spectrum select 1: LVDS Rx Link-B 0: 250mV 1: 350mV 0: disable 0: center 1: enable 1: N/A Image control register’s sync latch enable The registers that control video processing parameters are reflect every V-sync at only VREG_VLTEN=1. If VREG_VLTEN=0, the video processing registers are not reflect but written values are kept. If you change the video processing registers, set VREG_VLTEN=0 first, next update the video processing registers, and finally set VREG_VLTEN=1. 0:V-sync latch disable(default) 1:V-sync latch enable 11.4.2. EXPRESSION Registers Function Page Addr. bit Direction Register Name Description 00h 1Ch [0] W*/R COM_EN Color Management Function Enable 0: disable, 1: enable 00h 1Dh [7:4] W*/R COM_W_SX White area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 1Dh [3:0] W*/R COM_W_SY White area location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 1Eh [7:4] W*/R COM_G_SX Green area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 1Eh [3:0] W*/R COM_G_SY Green area location y 0:-max ~ 8:+/-0 ~ 15:+max Category Color Management 61 CXD4732R 00h 1Fh [7:4] W*/R COM_PO_SX Pale orange area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 1Fh [3:0] W*/R COM_PO_SY Pale orange area location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 20h [7:4] W*/R COM_R_SX Red area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 20h [3:0] W*/R COM_R_SY Red are location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 21h [7:4] W*/R COM_B_SX Blue area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 21h [3:0] W*/R COM_B_SY Blue area location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 22h [7:4] W*/R COM_Y_SX Yellow area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 22h [3:0] W*/R COM_Y_SY Yellow area location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 23h [7:4] W*/R COM_M_SX Magenta area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 23h [3:0] W*/R COM_M_SY Magenta area location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 24h [7:4] W*/R COM_C_SX Cyan area location x 0:-max ~ 8:+/-0 ~ 15:+max 00h 24h [3:0] W*/R COM_C_SY Cyan area location y 0:-max ~ 8:+/-0 ~ 15:+max 00h 25h [7:4] W*/R COM_P_SX Pink area location x (COM_MODE=0 only) 0:-max ~ 8:+/-0 ~ 15:+max 00h 25h [3:0] W*/R COM_P_SY Pink area location y(COM_MODE=0 only) 0:-max ~ 8:+/-0 ~ 15:+max 00h 26h [7:4] W*/R COM_W_DX Vector for White of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 26h [3:0] W*/R COM_W_DY Vector for White of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 27h [7:4] W*/R COM_G_DX Vector for Green of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 27h [3:0] W*/R COM_G_DY Vector for Green of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 28h [7:4] W*/R COM_PO_DX Vector for Pale orange of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 28h [3:0] W*/R COM_PO_DY Vector for Pale orange of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 29h [7:4] W*/R COM_R_DX Vector for Red of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 29h [3:0] W*/R COM_R_DY Vector for Red of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Ah [7:4] W*/R COM_B_DX Vector for Blue of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Ah [3:0] W*/R COM_B_DY Vector for Blue of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Bh [7:4] W*/R COM_Y_DX Vector for Yellow of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Bh [3:0] W*/R COM_Y_DY Vector for Yellow of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Ch [7:4] W*/R COM_M_DX Vector for Magenta of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Ch [3:0] W*/R COM_M_DY Vector for Magenta of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Dh [7:4] W*/R COM_C_DX Vector for Cyan of x direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Dh [3:0] W*/R COM_C_DY Vector for Cyan of y direction 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Eh [7:4] W*/R COM_P_DX Vector for Pink(COM_MODE=0) or Pale orange2 (COM_MODE=1) direction 00h 2Eh [3:0] W*/R COM_P_DY 0:-max ~ 8:+/-0 ~ 15:+max Vector for Pink(COM_MODE=0) or Pale orange2 (COM_MODE=1) direction of y 0:-max ~ 8:+/-0 ~ 15:+max 00h 2Fh [4:0] W*/R COM_W_GAIN Vector gain for White 0:0 ~ 63:max 00h 30h [4:0] W*/R COM_G_GAIN Vector gain for Green 0:0 ~ 63:max 00h 31h [4:0] W*/R COM_PO_GAIN Vector gain for Pale orange 0:0 ~ 63:max 00h 32h [4:0] W*/R COM_R_GAIN Vector gain for Red 0:0 ~ 63:max 62 of x CXD4732R 00h 33h [4:0] W*/R COM_B_GAIN Vector gain for Blue 0:0 ~ 63:max 00h 34h [4:0] W*/R COM_Y_GAIN Vector gain for Yellow 0:0 ~ 63:max 00h 35h [4:0] W*/R COM_M_GAIN Vector gain for Magenta 0:0 ~ 63:max 00h 36h [4:0] W*/R COM_C_GAIN Vector gain for Cyan 0:0 ~ 63:max 00h 37h [4:0] W*/R COM_P_GAIN Vector gain for Pink 0:0 ~ 63:max 00h 1Ch [1] W*/R COM_GO_EN Evaluation purpose only. Highlight display selected color area by COM_GON_COL 0: disable, 00h 1Ch [7:4] W*/R COM_GON_COL 1: enable Evaluation purpose only, valid only when COM_GO_EN=1. Select a color 0:White, 1:Green, 2:Pale orange, 3:Red, 4:Blue, 5:Yellow, 6:Magenta, 7:Cyan, 8:Pink 00h 38h [0] W*/R COM_MODE Set color area select mode 0: Select from 9-color area 1: Select from 8-color area and 1 fixed area iCE 00h 3Ah [7:4] W*/R ICE_A iCE A function gain. 0: Off ~ 15: Max. 00h 3Ah [3:0] W*/R ICE_B iCE B function gain. 0: Off ~ 15: Max. 00h 3Bh [3:0] W*/R ICE_C iCE C function gain 0: Off ~ 15: Max. 00h 3Ch [0] W*/R ICE_FILT_TC iCE filter time constant 0: Slow 1:Fast 00h 3Dh [5:0] W*/R ICE_COLOR_GAIN_A iCE color gain compensation (DC) 00h 3Eh [5:0] W*/R ICE_COLOR_GAIN_B iCE color gain compensation (differential gain) 0: Off ~ 63: Max. 00h 3Fh [7:4] W*/R ICE_SCENE_CHDET iCE scene change detection sensitivity 00h 3Fh [2:0] W*/R ICE_COLOR_GAIN_LMT iCE color gain compensation (Limiter) 0: Off ~ 63: Max. 0: High ~ 15: Low 0: 0dB, 1: 0.5dB, 2: 1.0dB, 3: 2.0dB, 4: 3.5dB, 5: 6.0dB, 6: 8.0dB, 7: 9.ddB 00h 40h [7:6] W*/R ICE_A_BLACKLEV1 Set black level correction curve fold point. 0: 30IRE 1: 30IRE 2: 50IRE 3: 60IRE 2-D Sharpness 00h 40h [4:0] W*/R ICE_BGFACT Background processing 0: Off ~ 31Max 00h 41h [7:4] W*/R ICE_A_BLACKLEV2 iCE A black level correction 0: Off ~ 7 Max. (8 ~15: N/A) 00h 41h [3:0] W*/R ICE_B_BALANCE iCE B negative gain reduction 0: Off ~ 7 Max. (8 ~15: N/A) 00h 43h [7:0] W*/R YHSHP Y horizontal sharpness level 0: -max ~ 128: OFF(0dB) ~ 255: +max(about +10dB) 00h 44h [7:0] W*/R YVSHP Y vertical sharpness level 0: -max ~ 128: OFF(0dB) ~ 255: +max(about +10dB) 00h 45h [7:0] W*/R YTSHP Y diagonal sharpness level 0: -max ~ 128: OFF(0dB) ~ 255: +max(about +10dB) 00h 46h [7:5] W*/R YHSHP_HBAND Horizontal frequency band to apply Y horizontal sharpness 0: min. ~ 4: max 00h 46h [4] W*/R YHSHP_VBAND (5~7: N/A) Vertical frequency band to apply Y horizontal sharpness. 63 0: low ~ 1: high CXD4732R 00h 46h [3:1] W*/R YVSHP_HBAND Horizontal frequency band to apply Y vertical sharpness 0: min. ~ 4: max (5~7: N/A) 00h 46h [0] W*/R YVSHP_VBAND Vertical frequency band to apply Y vertical sharpness 00h 47h [7:4] W*/R YSHP_WB Top and bottom characteristic of Y sharpness 0: low ~ 1: high 0: black side/max, white side min ~ 8: top and bottom is symmetric ~ 15: black side/min, white side max 00h 47h [1:0] W*/R YSHP_CORE Quantity of coring of Y sharpness 0: OFF ~ 3: max 00h 49h [6:4] W*/R CTI_F0 CTI F0 0: f0=min. ~ 7: f0=max. 00h 49h [1:0] W*/R CTI_LEV CTI level 0: OFF ~ 3: max. Other Image 00h 15h [7:0] W*/R CONTRAST Output Contrast Control 0: x0 ~ 128: x1 ~ 255: x255/128 Control Registers 00h 16h [7:0] W*/R BRIGHT Output Brightness Control 0: -128 ~ 128: +/-0 ~ 255: +127 (8bit) At 10bit, this value becomes quadruple. 00h 17h [7:0] W*/R COLOR Output Color Saturation Control 00h 01h [0] W/R I_GBR_RANGE GBR Video Input Dynamic Range 0: 0~1023 (10bit), 0~255 (8bit) 00h 14h [0] W/R O_GBR_RANGE 0: x0 ~ 128: x1 ~ 255: x255/128 1: 64-940 (10bit), 16~235 (8bit) GBR Video Output Dynamic Range 0: 0~1023 (10bit) 0~255 (8bit) 1: 64-940 (10bit) 16~235 (8bit) 11.4.3. Video Input Control Registers (Page Address = 1Ah) Function Page Addr. bit Direction Register Name Description Video Input 1Ah 00h [0] W/R VIN_LINK_MD LVDS Rx Dual/Single Link Select Control 1Ah 00h [1] W/R VIN_LNKMS_SEL LVDS Rx master link select (Link swap function) Category 0:FHD (dual link) 1:WXGA (single link) Note) this function selects only data and data enable. Clock is selected by other register. 0: 1st pixel input to link-A, 2nd pixel input to link-B 1: 2nd pixel input to link-A, 1st pixel input to link-B 1Ah 02h [5:0] W/R VIN_SYNC1 Trigger signal Select from of LVDS Rx master link select { lvrx_ch0[6:0], lvrx_ch1[6:0], lvrx_ch2[6:0], lvrx_ch3[6:0], lvrx_ch4[6:0] } Ex. for JEIDA,VASA 19: VS-rise 20 : DE-rise When you select 20 , DEVALID ( page 1Ah sub address=05h, data[1] ) must be set to 1 . 1Ah 03h [5:0] W/R VIN_SYNC2 Trigger signal Select from of { LVDS Rx slave link select lvrx_ch0[6:0], lvrx_ch1[6:0], lvrx_ch2[6:0], lvrx_ch4[6:0] } Ex. 64 for JEIDA,VASA 19: VS-rise 20 : DE-rise lvrx_ch3[6:0], CXD4732R When you select 20 , DEVALID ( page 1Ah sub address=05h, data[1] ) must be set to 1 . 1Ah 04h [5:0] W/R VIN_SYNC3 Trigger signal of VIN fifo read start select Select from lvrx_ch0[6:0], { lvrx_ch1[6:0], lvrx_ch2[6:0], lvrx_ch3[6:0], lvrx_ch4[6:0] } Ex. for JEIDA,VASA 19: VS-rise 20 : DE-rise When you select 20 , DEVALID ( page 1Ah sub address=05h, data[1] ) must be set to 1 . 1Ah 05h [1] W/R DEVALID DE valid signal enable 0: disenable (for Sync through mode) 1: enable (for DE-only mode) 1Ah 10h [7:6] W/R VIN_LVRMP_8BSFT LVDS Rx format and bit width 0: VESA 10bit, JEIDA 10 and 8bit 3: VESA 8bit 1Ah 12h [2:1] W/R VIN_LVRM_LVFMTSEL Other value is N/A. LVDS Rx format Select 0: VESA 1: JEIDA Other value is N/A. 11.4.4. Video Output Control Registers (Page Address = 1Ah) Function Page Addr. bit Direction 1Ah 80h [0] W/R Register Name Description Category Video Output VOT_LINK_MD LVDS Tx Dual/Single Link Select. Control 1Ah 83h [6:4] W/R VOT_SYNC1 Note) set the same value as VIN_LINK_MD. 0:FHD (dual link) 1:WXGA (single link) Trigger VOT fifo read start select signal of 000:DE-rise 001:VS-rise 010:HS-rise 011:ExternalTrigger-rise 100:sreset-fall 1Ah 87h [7:6] W/R VOT_LVTMP_8BSFT LVDS Tx format and bit width 0: VESA 10bit, JEIDA 10 and 8bit 2: VESA 8bit 1Ah 8Ah [3] W/R VOT_LNKSWP Other value is N/A. LVDS Tx link swap 0: swap disable (input A->output A, input B -> output B) 1: swap enable (input A->output B, input B -> output A) 1Ah 8Dh [5:4] W/R VOT_LVTMP_LVFMTSEL LVDS Tx format 0: VESA 1Ah B4h [3:0] W/R VWIDTH 1: JEIDA Other value is N/A. Output VSYNC width select (For only Sync through mode) Unit:Line 0-: prohibited 15: 15Line 1Ah B5h [6:0] W/R HWIDTH Output VSYNC width select (For only Sync through mode) 0,1 : prohibited 65 Unit:VCLK CXD4732R 127: 127VCLK If you use SSCG (LVTX_SSEN=1), 1Ah B6h [0] W/R SYNC_MODE HWIDTH must be set over 44. Output synchronous signal select 0: For DE only mode、 1: For Sync through mode 11.4.5. Gamma and Dither Control Registers (Page Address = 1Fh) Function Page Addr. bit Direction Register Name Description 1Fh 03h [0] W*/R GMTBL_EN Gamma block output select 1Fh 07h [0] W*/R GMTBL_SEL Gamma look up table A or B select 1Fh 00h [0] W/R TBLA_SCLK_MSK Gamma Table-A I2C clock mask enable (*1) 0:clock run 1:clock stop 1Fh 04h [0] W/R TBLB_SCLK_MSK Gamma Table-B I2C clock mask enable (*1) 0:clock run 1:clock stop 1Fh 01h [0] W/R TBLA_RDEN Gamma Table-A mode switch (*1) 0: I2C write mode 1:Normal mode 1Fh 05h [0] W/R TBLB_RDEN Gamma Table-B mode switch (*1) 0: I2C write mode 1:Normal mode 1Fh 02h [0] W/R TBLA_VCLK_EN Gamma Table-A video clock run enable (*1) 0:clock stop 1:clock run 1Fh 06h [0] W/R TBLB_VCLK_EN Gamma Table-B video clock run enable (*1) 0:clock stop 1:clock run 1Fh 08h [0] W/R DITH_EN Dither enable 0:diable 1Fh 08h [3:1] W/R DITH_MODE Dither mode select 0:Reserved Category Gamma Function Dither Function 3:Reserved 0:input through 0:select table A 1:select table B 4:2x2 matrix pattern 1 6:4x4 matrix pattern 1 1Fh 08h [5:4] W/R DITH_BIT Operation bits 0: 10bit 1Fh 09h [2:0] W/R DITH_INC Pattern Increment mode 1:look up table read output 1:enable 1:round 2:Framerate conversion 5:2x2 matrix pattern 2 7:4x4 matrix pattern 2 2: 8bit Other value is N/A. 0: increment by pixel 1: increment by line 2: increment by frame 3: Reserved 11.4.6. MC-3DNR Control Registers (Page Address = 1Bh) Function Page Addr. bit Direction Register Name Description 1Bh 0Ch [0] W/R YNR NR function enable 0: disable 1Bh 33h [5:0] W/R FBHISTTH Time constant of noise detector 0: fast 63: slow 1Bh 34h [5:0] W/R NLFB Time constant of noise filter 0: fast 63: slow 1Bh 22h [5:0] W/R MINALFA NR level control registers see application note 1Bh 23h [5:0] W/R MAXALFA 1Bh 2Dh [4:0] W/R PNR_PK 1Bh 2Eh [7:4] W/R CLIPKMAX 1Bh 58h [5:0] W/R BKYCTRL_DEFVOL Category MC-3DNR 1: enable Function 66 CXD4732R 1Bh 5Bh [5:0] W/R BKYCTRL_VP 1Bh 5Ch [7:0] W/R BKYCTRL_GRDV_H 1Bh 5Dh [7:0] W/R BKYCTRL_GRDV_L 11.4.7. GRC Control Registers (Page Address = 1Fh) Function Page Addr. bit Direction Register Name Description 1Dh 2Eh [0:0] W/R GRC_EN Adaptive horizontal smoothing 1Dh 2Fh [2:0] W/R GRC_HCORE Adaptive coring for horizontal high frequency component Category GRC Function 0: off 1Dh 2Fh [6:4] W/R GRC_VCORE 0: disable 1: enable 7: max Adaptive coring for vertical high frequency component 0: off 7: max 1Dh 31h [1:0] W/R MNR_EDGE_LEV Mosquito NR for signal edge 1Dh 31h [7:4] W/R MNR_FLAT_LEV Mosquito NR for all area 0: off 3: max 0: off 15: max 11.4.8. Super Resolution Control Registers (Page Address = 1Fh) Function Page Addr. bit Direction Register Name Description 1Ch 10h [7:0] W/R VOLN 2DNR(ICONTON=0 only) 0 : min 255: max 1Ch 11h [7:0] W/R VOLR Super Resolution (ICONTON=0 only) 0: min 255 : max 1Ch 12h [7:0] W/R VOLE 2DNR+ Super Resolution gain (ICONTON=0 only) 1Ch 1Bh [7:0] W/R VOLERATIOMIN Effect around text data Category Super Resolution Function 32: min 255: max Base data is changed by value of VOLE_BVD or VOLE. Recommended value = 128*32 / VOLE_BVD (ICONTON=0 : 128*32/ VOLE ) Must be set more than recommended value 255: 1Ch 1Ch [7:0] W/R max Effect control around text data VOLERATIOMAX Sony recommends 96d~128d 1Ch 24h [3:0] W/R Control active noise range (ICONTON=1 only) 3: for net images , 4: for other NSHIFT images 1Ch 3Eh [7:0] W/R VOLE_BVD 2DNR+ Super Resolution gain(ICONTON=1 only) 32 : min 1Ch 6Dh [7:4] W/R NLIMIT limit block noise level. (HADAON-=1 only) F: max 1Ch 80h [7:7] W/R HADAON Reduce Super Resolution 0: OFF 1Ch 86h [7:7] W/R 1: ON Super Resolution enable SPCOFF 0: enable 67 1: disable 0: min effect in pale orange area 255 : max CXD4732R 1Ch 88h [7:7] W/R SUPER RESOLUTION automatic control ICONTON 0: OFF 1Ch 8Bh [1:0] W/R 1: ON Reduce level for SUPER RESOLUTION effect in pale orange area HADA_EFFECT 0 : max Note *1) refer to Chapter 10.2 “Gamma Look-up Table Setup” for details. 68 3: min CXD4732R 12. Example of Application Circuit Capacitance is placed near each terminal every one or two power supply terminals Capacitance is placed near each terminal every one or two power supply terminals DVDD1.2V 100nF 100ohm 6 100ohm 100ohm 9 10 100ohm 11 12 100ohm 13 14 100ohm 15 TXA1N TXA1P RXA2N RXA2P 22 100ohm 24 100ohm 25 26 LVDS Rx Link-B Inputs 100ohm 27 28 29 30 100ohm 32 100ohm 33 0.01uF 100 99 98 97 TXACKN TXACKP 95 RXA3N RXA3P TXA3N TXA3P 89 RXA4N RXA4P TXA4N TXA4P RXACKN RXACKP CMCT 90 88 87 85 79 RXB1N RXB1P TXB1N TXB1P 77 RXB2N RXB2P TXB2N TXB2P 75 RXB3N RXB3P RXB4N RXB4P 0.1uF 80 TXB0N TXB0P RXBCKN RXBCKP LVDS Tx Link-A Outputs 96 RXB0N RXB0P 100ohm 31 102 101 TXA2N TXA2P CXD4732R 23 TXA0N TXA0P 49pin PLLVSSA Do not connect this terminal to PCB GND RXA1N RXA1P (3.3V for Digital) VDDIO TXDVDD33 TXPLLAVDD VDD 83 TXPLLDVDD 50 TXDVDD 49 PLLVDDA 0.1uF DVDD3.3V 7 8 LVDS Rx Link-A Inputs + PLLVSSA RXA0N RXA0P TXAVDD33 4 5 RXAVDD 0.1uF (3.3V for Analog) RXDVDD 22uF AVDD3.3V (1.2V for Digiral) 0.01uF 100ohm 0.1uF 0.01uF 0.1uF (1.2V for Analog) 0.01uF AVDD1.2V 78 76 LVDS Tx Link-B Outputs 74 TXBCKN TXBCKP 73 TXB3N TXB3P 67 TXB4N TXB4P 65 68 66 DVDD3.3V 1Kohm 1Kohm 51 53 112 TXPLLAVSS 59 RXAVSS IIC_SLV_SCL TXDVSS 44 VSSIO IIC_SLV_SDA RXDVSS 43 VSS External Host I/F 1Kohm TESTMODE 1Kohm RST_X 1Kohm DVDD3.3V IIC_MST_EN N.C. IIC_SLV_SADSEL0 SCLKI IIC_SLV_SADSEL1 113 IIC_SLV_BUSY 128 107 IIC_MST_SADSEL 54 IIC_MST_SDA 56 IIC_MST_SCL 55 1Kohm DVDD3.3V 1Kohm Exposed Pad 1Kohm External EEPROM (128kbit) External Active Low Oscillator Reset (24~25MHz) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 69 CXD4732R 13. Package Outline (Unit: mm) 70 CXD4732R 14. Marking 71 CXD4732R Note Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 72