W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET W83194BR-323 Data Sheet Revision History Pages Dates Version Version Main Contents On Web 1 n.a. 2 n.a. 13/May 3 13 02/August n.a. All of the versions before 0.50 are for internal use. 1.0 n.a Change version and version on web site to 1.0 1.1 1.1 Delete Test mode register. 4 5 6 7 8 9 10 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 1 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET GENERAL DESCRIPTION The W83194BR-323 is a Clock Synthesizer for Intel Brookdale 845 chipset. W83194BR-323 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and 3V66 clocks setting. All clocks are externally selectable with smooth transitions. The W83194BR-323 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-323 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-323 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. The fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate. 1. PRODUCT FEATURES • 3 Differential pairs of CPU clock outputs • • 4 3V66 clock outputs 10 PCI synchronous clocks • • 24_48Mhz clock output for super I/O. 48 MHz clock output for USB. • • • Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz Step-less frequency programming • • I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% and +/- 0.25% center type spread spectrum • • • Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Watch Dog Timer and RESET# output pins • 48-pin SSOP package - 2 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET BLOCK DIAGRAM Driver 48MHz PLL2 24_48MHz Mux 1/2 XIN XTAL OSC XOUT 2 REF0:1 VCOCLK PLL1 Spread Spectrum 3 Divider Stop CPUCLK_T 0:2 CPUCLK_C 0:2 3 /2,/4,/8,/16 M/N/Ratio S.S.P ROM Latch & POR VTTPWRGD# FS<4:0> PD# PCI_STOP# CPU_STOP# MULTISEL 0:1 /3,/6,/12 2 4 3V66_0:3 /5,/10,/20 /7,/14 /9,/18 1 0 Stop Control Logic & Config Register PCICLK_F0:2 PCICLK_0:6 RESET# Rref *SDATA *SDCLK I2C interface 4. PIN CONFIGURATION *MULTSEL1/REF1 VDDREF Xin Xout GND PCICLK_F0/*FS2 PCICLK_F1/*FS3 PCICLK_F2/&SEL24_4 8 VDDPCI PCICLK0/*FS4 PCICLK1 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDPCI VTTPWRGD# RESET# GND 48MHz/*FS0 24_48MHz/*FS1 VDD48 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 *MULTSEL0/REF0 GND VDDCPU CPUCLK_T2 CPUCLK_C2 GND *PD# CPUCLK_T0 CPUCLK_C0 VDDCPU CPUCLK_T1 CPUCLK_C1 GND IREF VDDCORE GND VDD3V66 3V66_0 3V66_1 GND 3V66_2 3V66_3 / 48MHz /*SEL48_66 *SDCLK *SDATA * :internal 120K pull-up &:internal 120K pull-down #: active low - 3 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 5. PIN DESCRIPTION IN – Input INtp120k – Latched input at power up, internal 120kO pull up. INtd120k – Latched input at power up, internal 120kO pull down. OUT – Output OD – Open Drain I/O - Bi-directional Pin I/OD – Bi-directional Pin, Open Drain. # - Active Low * - Internal 120kΩ pull-up &- Internal 120 kΩ pull-down 5.1. Crystal I/O PIN SYMBOL 3 XIN 4 XOUT I/O IN OUT FUNCTION Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). 5.2. CPU, 3V66, and PCI Clock Outputs PIN SYMBOL 41,38, 40,37 CPUCLK_T [0:2] 45,44 CPUCLK_C [0:2] 31,30,28 27 I/O FUNCTION OUT Low skew (< 250ps) differential clock outputs for host frequencies of CPU and chipset. 3V66_0:2 OUT 3.3V 66MHz clock outputs. 3V66_3 / 48MHz OUT 3V66_3 or 48MHz clock output. *SEL48_66 INtp120k Latched input for 48MHz or 66MHz select pin. This is internal 120K pull up default 66MHz. In power on reset period, it is a hardwarelatched pin, and it can be R/W by I2C control after power on reset period. Select by register 16 bit 6. IN Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are several modes to select different current via power on trapping the Pin 1 & 48 (MULTISEL0, 1). The table is show as follows. 35 IREF 20 RESET# OD System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout. 19 VTTPWRGD# IN 42 PD# IN Power good input signal comes from ACPI with low active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL0, MULTISEL1, input are valid and is ready to sampled. This pin is low active. Power Down Function. This is power down pin, low active (PD#). Internal 120K pull up 3.3V free running PCI clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. 3.3V free running PCI clock output. 6 PCICLK_F0 *FS2 OUT INtp120k 7 PCICLK_F1 OUT - 4 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 8 10 11, 12, 14, 15, 16, 17 *FS3 INtp120k Latched input for FS3 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. PCICLK_F2 &SEL24_48 OUT 3.3V free running PCI clock outputs. INtd120k Latched input for 24MHz or 48MHz select pin. This is internal 120K pull down default 24MHz. OUT Low skew (< 250ps) PCI clock outputs. PCICLK0 *FS4 INtP120k Latched input for FS4 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. PCICLK [1:6] OUT Low skew (< 250ps) PCI clock outputs. 5.3. I2 C Control Interface Pin Number Pin Name 25 SDATA* 26 SCLK* Type I/OD IN Description Serial data of I2C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor. SYMBOL REF0 MULTSEL0* I/O OUT INtp120k REF1 MULTSEL1* OUT INtp120k 22 48MHz *FS0 OUT INtp120k 23 24_48MHz OUT *FS1 INtp120k FUNCTION 14.318NHz output. Latched input for MULTSEL0 at initial power up, internal 120K pull up 14.318NHz output. Latched input for MULTSEL1 at initial power up, internal 120K pull up 48MHz clock output for USB. Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. 24(default) or 48MHz clock output, In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 16 bit 7. Latched input for FS1 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. 5.4. Fixed Frequency Outputs PIN 48 1 5.5. Power Pins Pin Number 2 9,18 32 39,46 34 24 5, 13, 21, 29, 33, 36, 43, 47 Pin Name VDDREF VDDPCI VDD3V66 VDDCPU VDDCORE VDD48 GND Type PWR PWR PWR PWR PWR PWR PWR Description 3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for 3V66. 3.3V power supply for CPU. 3.3V power supply for analog core. Analog power 3.3V for 48MHz. Ground pin for 3.3 V - 5 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET Hardware MULTSEL [1:0] selects Function Multsel1 Multsel0 0 0 Board Target trace/Term Z 50 ? 0 0 60 ? 0 1 50 ? 0 1 60 ? 1 0 50 ? 1 0 60 ? 1 1 50 ? 1 1 60 ? 0 0 50 ? 0 0 60 ? 0 1 50 ? 0 1 60 ? 1 0 50 ? 1 0 60 ? 1 1 50 ? 1 0 60 ? Reference R,IREF = Vdd/(3*Rr) Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA - 6 - Output Current Ioh=4*IREF Voh @ Z 1.0V @ 50 Ioh=4*IREF 1.2V @ 60 Ioh=5*IREF 1.25V @ 50 Ioh=5*IREF 1.5V @ 60 Ioh=6*IREF 1.5V @ 50 Ioh=6*IREF 1.8V @ 60 Ioh=7*IREF 1.75V @ 50 Ioh=7*IREF 2.1V @ 50 Ioh=4*IREF 0.47V @ 50 Ioh=4*IREF 0.56V @ 50 Ioh=5*IREF 0.58V @ 50 Ioh=5*IREF 0.7V @ 60 Ioh=6*IREF 0.7V @ 50 Ioh=6*IREF 0.84V @ 60 Ioh=7*IREF 0.81V @ 50 Ioh=6*IREF 0.97V @ 60 Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 1 bit 6 ~ 2). FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHZ) 102.0 105.0 108.0 111.0 114.0 117.0 120.0 123.0 126.0 130.0 136.0 140.0 144.0 148.0 152.0 156.0 160.0 164.0 166.6 170.0 175.0 180.0 185.0 190.0 66.8 100.2 133.6 200.4 66.6 100.0 200.0 133.3 - 7 - 3V66(MHZ) 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 63.0 65.0 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 66.6 68.0 70.0 72.0 74.0 76.0 66.8 66.8 66.8 66.8 66.6 66.6 66.6 66.6 PCI (MHz) 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 31.5 32.5 34 35.0 36.0 37.0 38.0 39.0 40.0 41.0 33.3 34.0 35.0 36.0 37.0 38.0 33.4 33.4 33.4 33.4 33.3 33.3 33.3 33.3 Spread % +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% -0.5% -0.5% -0.5% -0.5% Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 6. I2 C CONTROL AND STATUS REGISTERS 6.1. Register 0: Frequency Select Register (default = 0) Bit 7 Name PWD Description EN_SPSP 0 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled 6 SSEL [4] 0 5 SSEL [3] 0 4 SSEL [2] 0 3 SSEL [1] 0 2 SSEL [0] 0 1 EN_SSEL 0 Frequency selection by software via I2C. Enable software program FS [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 6 ~ 2. 0 EN_SAFE_FREQ 0 Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0. 6.2. Register 1: CPU Clock Register (1 = enable, 0 = Stopped) Bit Pin # PWD Description 7 44,45 1 CPUCLK_T2 / C2 6 37,38 1 CPUCLK_T1 / C1 5 40,41 1 CPUCLK_T0 / C0 4 - X FS [4] Read back. 3 - X FS [3] Read back 2 - X FS [2] Read back 1 - X FS [1] Read back 0 - X FS [0] Read back 6.3. Register 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit Pin # PWD Description 7 48- X MULTISEL0 trapping pin data read back 6 17 1 PCICLK6 5 16 1 PCICLK5 4 15 1 PCICLK4 3 14 1 PCICLK3 2 12 1 PCICLK2 - 8 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 1 11 1 PCICLK1 0 10 1 PCICLK0 6.4. Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped) Bit Pin # PWD Description 7 22 1 48MHZ 6 23 1 24_48MHz 5 48 1 REF0 4 1 1 REF1 3 Reserved 1 Reserved 2 8 1 PCICLK_F2 1 7 1 PCICLK_F1 0 6 1 PCICLK_F0 6.5. Register 4: 3V66 Control Register (1 = enable, 0 = Stopped) Bit Pin # PWD Description 7 - 1 Reserved 6 - 1 Reserved 5 - 1 Reserved 4 - 1 Reserved 3 27 1 3V66_3 / 48MHz 2 28 1 3V66_2 1 30 1 3V66_1 0 31 1 3V66_0 6.6. Register 5: Watchdog Control Register Bit Name PWD Description 7 MULTISEL1 X MULTISEL1 trapping pin data read back 6 EN_WD 0 Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. 5 WD_TIMEOUT 0 Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only. 4 SAF_FREQ [4] 0 3 SAF_FREQ [3] 0 Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits. 2 SAF_FREQ [2] 0 1 SAF_FREQ [1] 0 - 9 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 0 SAF_FREQ [0] 0 6.7. Register 6: Watchdog Timer Register Bit Name PWD Description 7 WD_TIME [7] 0 6 WD_TIME [6] 0 5 WD_TIME [5] 0 4 WD_TIME [4] 0 3 WD_TIME [3] 1 2 WD_TIME [2] 0 1 WD_TIME [1] 0 0 WD_TIME [0] 0 Watchdog timeout time. The bit resolution is 250mS. The default time is 8*250mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value. 6.8. Register 7: M/N Program Register Bit Name PWD Description 7 N_DIV [8] 1 Programmable N divisor value. Bit 7 ~0 are defined in the Register 8. 6 TEST1 1 Test bit 1. Winbond test bit, do not change them. 5 TEST0 0 Test bit 0. Winbond test bit, do not change them . 4 M_DIV [4] 0 3 M_DIV [3] 1 2 M_DIV [2] 1 1 M_DIV [1] 0 0 M_DIV [0] 1 Programmable M divisor value. 6.9. Register 8: M/N Program Register Bit Name PWD 7 N_DIV [7] 0 6 N_DIV [6] 1 5 N_DIV [5] 1 4 N_DIV [4] 0 3 N_DIV [3] 0 2 N_DIV [2] 1 1 N_DIV [1] 1 0 N_DIV [0] 1 Description Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 7. 6.10. Register 9: Spread Spectrum Programming Register Bit Name PWD Description - 10 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7 SP_UP [3] 0 Spread Spectrum Up Counter bit 3. 6 SP_UP [2] 0 Spread Spectrum Up Counter bit 2. 5 SP_UP [1] 0 Spread Spectrum Up Counter bit 1. 4 SP_UP [0] 1 Spread Spectrum Up Counter bit 0 3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 2 SP_DOWN [2] 1 Spread Spectrum Down Counter bit 2 1 SP_DOWN [1] 1 Spread Spectrum Down Counter bit 1 0 SP_DOWN [0] 1 Spread Spectrum Down Counter bit 0 6.11. Register 10: Divisor and Step-less Enable and Skew Control Register Bit Name PWD Description 7 0 EN_MN_PROG 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 0 bit 0). 6 RATIO_SEL [3] 0 5 RATIO_SEL [2] 0 4 RATIO_SEL [1] 1 3 RATIO_SEL [0] 0 2 CPU_3V66_SKEW [2] 1 1 CPU_3V66_SKEW [1] 0 0 CPU_3V66_SKEW [0] 0 CPU, 3V66, and PCI ratio selection. The ratio is shown as following table. CPU to 3V66 skew. Table of CPU, 3V66, and PCI clock selection. I2C Reg10 Definition Reg10 Reg10 Reg10 Reg10 Bit6 Bit5 Bit4 Bit3 CPU 3V66 PCI SSEL3 SSEL2 SSEL1 SSEL0 Ratio Ratio Ratio 0 0 0 0 2 5 10 0 0 0 1 2 6 12 0 0 1 0 3 6 12 0 0 1 1 4 6 12 0 1 0 0 4 8 16 0 1 0 1 6 6 12 - 11 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET Register 11: Winbond Chip ID Register (Read Only) Bit Name PWD Description 7 CHPI_ID [7] 0 Winbond Chip ID. W83194BR-323 is 0x57. 6 CHPI_ID [6] 1 Winbond Chip ID. 5 CHPI_ID [5] 0 Winbond Chip ID. 4 CHPI_ID [4] 1 Winbond Chip ID. 3 CHPI_ID [3] 0 Winbond Chip ID. 2 CHPI_ID [2] 1 Winbond Chip ID. 1 CHPI_ID [1] 1 Winbond Chip ID. 0 CHPI_ID [0] 1 Winbond Chip ID. 6.12. Register 12: Winbond Chip ID Register (Read Only) Bit Name PWD Description 7 SUB_ID [3] 0 Winbond Sub-Chip ID. The sub-chip ID of W83194BR-323 is defined as 0010b. 6 SUB_ID [2] 0 Winbond Sub-Chip ID. 5 SUB_ID [1] 1 Winbond Sub-Chip ID. 4 SUB_ID [0] 0 Winbond Sub-Chip ID. 3 VER_ID [3] 0 Winbond Version ID. The Version ID of W83194BR-323 is 0010b. 2 VER_ID [2] 0 Winbond Version ID. 1 VER_ID [1] 1 Winbond Version ID. 0 VER_ID [0] 0 Winbond Version ID. 6.13. Register 13: Reserved Bit Name PWD Description 7 Reserved 0 Reserved 6 Reserved 0 Reserved 5 Reserved 1 Reserved 4 Reserved 0 Reserved 3 Reserved 0 Reserved 2 Reserved 1 Reserved 1 Reserved 1 Reserved 0 Reserved 1 Reserved 6.14. Register 14: CPU to PCI Skew Control Bit Name PWD 7 Reserved 1 6 Reserved 0 5 Reserved 0 Description - 12 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 4 CPU_PCI_SKEW [2] 1 3 CPU_PCI_SKEW [1] 0 2 CPU_PCI_SKEW [0] 0 1 Reserved 0 0 Reserved 0 CPU to PCI Skew 6.15. Register 15: SEL24_48 and SEL48_66 Control Bit Name 7 SEL24_48 PWD Description X In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. 0-> 24 MHz, 1->48MHz. 6 SEL_48_66 X In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. 0-> 48 MHz, 1->66MHz. 5 Reserved 0 Reserved for winbond internal use, do not change them 4 Reserved 0 Reserved for winbond internal use, do not change them 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 1 7. ACCESS INTERFACE The W83194BR-323 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-323 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. 7.1. Block Read and Block Write Protocol 7.1 Block Write protocol 7.2 Block Read protocol ## In block mode, the command code must filled 8’h00 - 13 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.3 Byte Write protocol 7.4 Byte Read protocol 7.2. The serial bus access timing (a) Serial bus writes to internal address register followed by the data byte 0 7 8 0 0 D7 7 8 SCL SDA 1 0 Start By Master 1 1 0 0 1 R/W D6 Ack by Slave Frame 1 Serial Bus Address Byte D5 D4 D3 D2 D1 D0 Ack by Slave Frame 2 Internal Index Register Byte 7 8 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by 784R Stop by Master Frame 3 Data Byte Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus writes to internal address register only 0 7 8 0 7 8 SCL SDA 1 0 Start By Master 1 1 0 0 1 R/W D7 D6 Ack by Slave Frame 1 Serial Bus Address Byte D5 D4 D3 D2 D1 D0 Ack by Slave Frame 2 Internal Index Register Byte Stop by Master 0 Figure 2. Serial Bus Write to Internal Address Register Only (c) Serial bus read from a register with the internal address register prefer to desired location 0 7 8 0 7 8 SCL SDA 1 Start By Master 0 1 1 0 0 1 R/W D7 D6 Ack by Slave Frame 1 Serial Bus Address Byte D5 D4 D3 D2 Frame 2 Internal Index Register Byte D1 D0 Ack by Master Stop by Master 0 Figure 3. Serial Bus Read from Internal Address Register - 14 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET (d) Serial bus read from a register with writing to internal address register 0 7 8 0 7 8 ... SCL SDA 1 0 Start By Master 1 1 0 0 1 R/W D7 D6 Ack by Slave Frame 1 Serial Bus Address Byte D5 D4 D3 D2 D1 ... D0 Ack by Slave Frame 2 Internal Index Register Byte 0 SCL SDA 0 ... ... 1 Repeat Start By Master 7 0 1 1 0 0 1 8 0 R/W D7 Ack by Slave Frame 1 Serial Bus Address Byte 7 D6 D5 D4 D3 D2 Frame 2 Internal Index Register Byte D1 8 D0 Ack by Master Stop by Master 0 Figure 4. Serial Bus Read from Writing Internal Address Register - 15 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7. ORDERING INFORMATION Part Number Package Type Production Flow W83194BR-323 48 PIN SSOP Commercial, 0°C to +70°C 8. HOW TO READ THE TOP MARKING W83194BR323 28051234 1st line: Winbond logo and the type number: W83194BR-323 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 214 G B B 214: packages made in '2002, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 16 - Publication Release Date: August 2002 Revision 1.1 W83194BR-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 9. PACKAGE DRAWING AND DIMENSIONS Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics No. 4, Creation Rd. III Rm. 803, World Trade Square, Tower II (North America) Corp. Science-Based Industrial Park Hsinchu, Taiwan 123 Hoi Bun Rd., Kwun Tong 2727 North First Street Kowloon, Hong Kong San Jose, California 95134 TEL: 852-27516023-7 TEL: 1-408-9436666 FAX: 852-27552064 FAX: 1-408-9436668 TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 17 - Publication Release Date: August 2002 Revision 1.1