WFP6131AGSR Advanced Product Information Features 9/11-Channel Buffer • • • • • • 11 High Drive Buffers on a Chip Full Spec. Operation from 3.3v to 5.5v High Output Drive Current: 350mA Low Supply Current: 3mA (Typ) A/B Channel Input per Buffer Each Buffer stable with output load of up to 240nF • 9 Ouput Power Save Mode Product Description The WFP6131AGSR is an 11-channel buffer amplifier that provides a single-chip solution to the reference voltage requirements of TFT-LCD drivers. It can also be used in any cost sensitive application that requires large number (11 maximum) of high drive buffers in a space saving TSSOP package. The WFP6131AGSR has two selectable inputs per buffer allowing the selection of two reference voltages via one on-chip multiplexer for all 11 buffers. The WFP6131AGSR supports 9 or 11 reference voltage systems. For 9 reference applications, the 2 unused amplifiers may be disabled to reduce power dissipation. Applications • Reference Buffer for SVGA/XGA TFTLCD drive circuit. • Electronic Notebooks • Electronic Games • Personal Communication Devices • Personal Digital Assistants (PDA) • Active Filter • Multi-Voltage Buffering Voltage References WFP6840 Signal Driver 309 Data Graphics Controller Control Control Control WFP6840 Signal Driver 309 ... WFP6840 Signal Driver 309 Gate Driver HSYNC VSYNC PCLK Data Enable January 5, 2000 Rev. 0.02 LCD Control ASIC WFP6131A GSR Buffer ....... 9 or 11 P17-P 0 1024 x 768 262,144-Color LCD Gate Driver Control 1 WFP6131AGSR 11-Channel Buffer Features & Benefits Features • High Integration • Low Power Operation Benefits • 11 high drive reference voltage outputs • Internal multiplexors allow polarity-dependent reference values to be selected via A/B_SEL input. • Analog supply voltage: 3.3 V ± 0.3 V to 5.0 V ± 0.5 V • Low supply headroom allows wide output dynamic range and minimizes power dissipation. • Low quiescent current of less than 0.5 mA per reference output (typical). • EN_11 pin (internally pulled-down) disables OUT_1 & OUT_11 amplifiers to reduce power dissipation in 9 reference amplifier applications. May be set to logic high to enable OUT_1 & OUT_11. • High Performance Amplifiers • Typical slew rate of 2V/µs with 0.24 µF load • Typically settles to within 50 mV of final value in 6µs with 0.24 µF load. • Drives Large Load Capacitance • Maintains stable operation with load capacitance of 100 pF to 0.24 µF. • Die SIze: 2.25 x 4.5 mm • Small die size for chip-on-board applications. • 48-pin TSSOP Package • TSSOP package reduces cost and board space. 2 January 5, 2000 Rev. 0.02 WFP6131AGSR 11-Channel Buffer 48 Pin TSSOP Package Dimensions (millimeters) 12.5 +/- 0.1 -A48 25 8.1 6.1 +/- 0.1 -B- 4.05 1 0.2 C 24 B A ALL LEAD TIPS 0.1 C (0.90) ALL LEAD TIPS 1.1 MAX -C- 0.5 TYP 0.10 ± 0.05 TYP 0.17 - 0.27 TYP SEE DETAIL A 0.09 - 0.20 TYP DETAIL A GAGE PLANE 0.25 +0.15 0°-8° 0.60 SEATING PLANE -0.10 FIGURE 2-1 January 5, 2000 Rev. 0.02 3 WFP6131AGSR 11-Channel Buffer Die Size and Pad Coordinates 4.5 mm 45 42 39 36 29 32 38 37 26 47 Y (0,0) X 2.25 mm 2 23 5 20 Figure 2-2: WFP6131AGSR Die Pad Signal X Y Pad Signal X Y 31 GND 1736.0 926.5 2 I1_A -2072.7 -365.9 32.1 OUT10 1323.9 562.8 3 I1_B -2072.7 -563.7 32.2 OUT10 1196.9 562.8 4 I2_A -2072.7 -763.7 33.1 OUT9 1046.3 562.8 5 I2_B -1764.9 -904.2 33.2 OUT9 919.3 562.8 6 I3_A -1513.1 -904.2 34.1 OUT8 768.7 562.8 7 I3_B -1269.8 -904.2 34.2 OUT8 641.7 562.8 8 I4_A -1062.8 -904.2 35.1 OUT7 491.1 562.8 9 I4_B -846.2 -904.2 35.2 OUT7 364.1 562.8 213.5 562.8 10 I5_A -631.1 -904.2 36.1 OUT6 11 I5_B -372.6 -904.2 36.2 OUT6 86.5 562.8 12 I6_A -122.8 -904.2 37 GND -70.3 562.8 13 I6_B 127.2 -904.2 38 VDDA -207.3 562.8 14 I7_A 377.0 -904.2 39.1 OUT5 -364.1 562.8 15 I7_B 635.5 -904.2 39.2 OUT5 -491.1 562.8 16 I8_A 850.6 -904.2 40.1 OUT4 -641.7 562.8 17 I8_B 1067.2 -904.2 40.2 OUT4 -768.7 562.8 18 I9_A 1274.2 -904.2 41.1 OUT3 -919.3 562.8 19 I9_B 1517.5 -904.2 41.2 OUT3 -1046.3 562.8 20 I10_A 1769.3 -904.2 42.1 OUT2 -1196.9 562.8 21 I10_B 2072.7 -763.7 42.2 OUT2 -1323.9 562.8 22 I11_A 2072.7 -563.7 43 GND -1736.0 926.5 23 I11_B 2072.7 -365.9 44 VDDA -1873.0 926.5 26.1 OUT11 2069.0 250.8 45 EN_11 -2069.0 647.5 26.2 OUT11 2069.0 377.8 47.1 OUT1 -2069.0 377.8 29 A/B_SEL 2069.0 647.5 47.2 OUT1 -2069.0 250.8 30 VDDA 1873.0 926.5 Table 2-1: Die Pad Coordinates Table 2-1: Die Pad Coordinates January 5, 2000 Rev. 0.02 4 WFP6131AGSR 11-Channel Buffer Function & Pin Information Table 3–1 Mux Function A/B_SEL OUT_x logic low Ix_B logic high Ix_A Table 3–2 EN_11 Function EN_11 Outputs Enabled logic low or n.c. OUT_2..OUT_10 logic high OUT_1..OUT_11 VDDA EN_11 45 A/B_SEL 44,38,30 29 I1_A I1_B 2 3 MUX + - . 47 OUT_1 I2_A I2_B 4 5 MUX + - . 42 OUT_2 I3_A I3_B 6 7 MUX + - . 41 OUT_3 I4_A I4_B 8 9 MUX + - . 40 OUT_4 I5_A I5_B 10 11 MUX + - . 39 OUT_5 I6_A I6_B 12 13 MUX + - . 36 OUT_6 I7_A I7_B 14 15 MUX + - . 35 OUT_7 I8_A I8_B 16 17 MUX + - . 34 I9_A I9_B 18 19 MUX + - . 33 OUT_9 I10_A I10_B 20 21 MUX + - . 32 OUT_10 I11_A I11_B 23 24 MUX + - . 26 OUT_11 OUT_8 43,37,31 GND FIGURE 3-1 January 5, 2000 Rev. 0.02 5 WFP6131AGSR 11-Channel Buffer Application Information VDDA VDDA + A/B_SEL no connect 45 + 3.3 uf A/B_SEL 0.1 uf 44,38,30 29 45 EN_11 0.1 uf 44,38,30 29 EN_11 I1_A I1_B 2 3 MUX + - . 47 no connect I1_A I1_B 2 3 MUX + - . 47 OUT_1 I2_A I2_B 4 5 MUX + - . 42 OUT_2 I2_A I2_B 4 5 MUX + - . 42 OUT_2 I3_A I3_B 6 7 MUX + - . 41 OUT_3 I3_A I3_B 6 7 MUX + - . 41 OUT_3 I4_A I4_B 8 9 MUX + - . 40 OUT_4 I4_A I4_B 8 9 MUX + - . 40 OUT_4 I5_A I5_B 10 11 MUX + - . 39 OUT_5 I5_A I5_B 10 11 MUX + - . 39 OUT_5 I6_A I6_B 12 13 MUX + - . 36 OUT_6 I6_A I6_B 12 13 MUX + - . 36 OUT_6 I7_A I7_B 14 15 MUX + - . 35 OUT_7 I7_A I7_B 14 15 MUX + - . 35 OUT_7 I8_A I8_B 16 17 MUX 16 17 MUX + - . 34 OUT_8 I9_A I9_B 18 19 MUX I10_A I10_B 20 21 MUX + - . I11_A I11_B 23 24 MUX + - . + - . 34 OUT_8 I8_A I8_B + - . 33 OUT_9 I9_A I9_B 18 19 MUX + - . 33 OUT_9 32 OUT_10 I10_A I10_B 20 21 MUX + - . 32 OUT_10 26 no connect I11_A I11_B 23 24 MUX + - . 26 OUT_11 43,37,31 GND FIGURE 3-2: 9 References (OUT_1 & OUT_11 disabled) 6 3.3 uf 43,37,31 GND FIGURE 3-3: 11 References January 5, 2000 Rev. 0.02 WFP6131AGSR 11-Channel Buffer Specifications 0.1 Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VIN Input Voltage -0.3 VDDA + 0.3 Volts 1 VDDA Supply Voltage -0.3 6.0 Volts 1 IL Injection Current -100 100 mA TJ Junction Temperature 150 °C TA Operating temperature -20 85 °C TSTG Storage temperature -30 85 °C 2 Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. NOTES: 0.2 1) Voltages are with respect to ground (GND). 2) Ambient temperature under bias. Recommended Operating Conditions (Preliminary data – subject to change) Symbol Parameter Min VDDA Analog supply voltage 3.0 TA Ambient air temperature CL Output load capacitance 0 Typical 25 Max Units Notes 5.5 Volts 1 70 °C 0.3 µF NOTES: 1) Voltages are with respect to GND. January 5, 2000 Rev. 0.02 7 WFP6131AGSR 11-Channel Buffer 0.3. DC Characteristics (Preliminary data – subject to change) VDDA = 5.0 V, TA = 25° C. All voltages are with respect to GND. Symbol Parameter Min Typ Max 0.985 1.0 1.015 V/V Fig. 4-1 1 20 mV Fig. 4-1 1 4.8 V Fig. 4-1 2 A Fig. 4-3 3 mA EN_11 high AV Large Signal Gain VIO Input Offset Voltage V01 Output Voltage Range 0.2 ISC Output Short Circuit Current 0.5 IVDDA Analog Power Supply Current VIH Input Logic High VIL Input logic low IIN Input Leakage Current IEN_11 Input Current on EN_11 (high) NOTES: 1) 3 6 3.6 -5.0 Units Test Conditions Note V 4,5 0.8 V 4 5.0 µA 0 < VIN < VDDA 6 50 µA VIN = VDDA 7 RL = open and Vx = 0.0 V; RS = 2 Ω; C L = 0.24 uf, OUT_n = 2.5V 2) -75 mA < IOUTDC < 75 mA. Applies to OUT_1 .. OUT_11 3) 4) 5) OUT_n = 2.5V. Applies to A/B_SEL and EN_11 input pins. For VDDA = 4.5V, VIH min = 2.8V. 6) 7) Applies to all input pins except EN_11 in high state. Applies to EN_11 pin when VIN on EN_11 pin = VDDA 0.4. AC Characteristics (Preliminary data – subject to change) VDDA = 5.0 V, TA = 25° C. All voltages are with respect to GND. Symbol Parameter TSET Settling Time SR+,SR- Pos. & Neg. Slew Rate NOTES: 1) 2) 8 Min 0.8 Typ Max Units Test Conditions Note 8.0 µsec Fig. 4-2 1 V/µsec Fig. 4-2 1,2 RL/RS< 5, -75 mA < IOUTDC < 75 mA. CL = 0.24 µF. Measured for a 4.4V step settling to within 50 mV of final value. Applies to OUT_1 .. OUT_11 Slew rate measured between 20% and 80% points of step. January 5, 2000 Rev. 0.02 WFP6131AGSR 11-Channel Buffer 0.5. DC Characteristics (Preliminary data – subject to change) VDDA = 3.3 V, TA = 25° C. All voltages are with respect to GND. Symbol Parameter Min Typ Max 0.975 1.0 1.025 V/V Fig. 4-1 1 30 mV Fig. 4-1 1 3.1 V Fig. 4-1 2 A Fig. 4-3 3 mA EN_11 high AV Large Signal Gain VIO Input Offset Voltage V01 Output Voltage 0.2 ISC Output Short Circuit Current 0.33 IVDDA Analog Power Supply Current VIH Input Logic High VIL Input logic low IIN Input Leakage Current IEN_11 Input Current on EN_11 (high) NOTES: 1) 2) 3) 4) 5) 6) 3 5 2.0 -5.0 Units Test Conditions Note V 4 0.8 V 4 5.0 µA 0 < VIN < VDDA 5 33 µA VIN = VDDA 6 RL = open and Vx = 0.0 V; R S = 2 Ω; CL = 0.24 uf, OUT_n = 1.65 V -50 mA < IOUTDC < 50 mA. Applies to OUT_1...OUT_11 OUT_n = 1.65 V Applies to A/B_SEL and EN_11 input pins Applies to all input pins except EN_11 in high state Applies to EN_11 pin when VIN on EN_11 pin = VDDA 0.6. AC Characteristics (Preliminary data – subject to change) VDDA = 3.3 V, TA = 25° C. All voltages are with respect to GND. Symbol Parameter TSET Settling Time SR+, SR- Pos. & Neg. Slew Rate NOTES: 1) 2) Min Typ Max Units Test Conditions Note 8.0 µsec Fig. 4-2 1 V/µsec Fig. 4-2 1 0.6 RL/RS< 5, -50 mA < IOUTDC < 50 mA. CL = 0.24 µF. Measured for a 2.6V step settling to within 30 mV of final value. Applies to OUT_1 .. OUT_11 Slew rate measured between 20% and 80% points of step. January 5, 2000 Rev. 0.02 9 WFP6131AGSR 11-Channel Buffer . OUT_n DUT IOUTDC RL + V X Adjust Vx to achieve desired IOUTDC where Vx = OUT_n - IOUTDC*RL Figure 4-1 RS OUT_n DUT I OUTDC CL RL + V X Adjust Vx to achieve desired IOUTDC where Vx = OUT_n - IOUTDC*R L Figure 4-2 OUT_n ISC DUT Set VX = 2.5 V +- Vary VREF full scale (rail-to-rail). VX measure ISC Figure 4-3 10 January 5, 2000 Rev. 0.02 WFP6131AGSR 11-Channel Buffer Package Top Marking Guide For product assembled after 12/31/99 WFP6131AGSR Line 1 Winbond Flat Panel Part Number Package Type R : TSSOP XXXXXXXXXXXI Lot Number Line 2 ID Line 3 YWWKPLL Assembly Year Assembly Work Week Product Number Code Product Revision Number Subcontractor Code For product assembled before 12/31/99 CL-FP6131AGS Cirrus Logic Flat Panel Part Number Package Type GS : 48 TSSOP January 5, 2000 Rev. 0.02 11