PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µ PD160970 8-ch level shift driver IC DESCRIPTION The µ PD160970 is a level shift driver IC for LTPS (low-temperature polysilicon) TFT-LCDs featuring a 2-level output function and incorporates eight on-chip level shifters. This IC realizes a 20 V MAX. withstanding voltage due to a high-withstanding-voltage CMOS process and has an output ON-resistance and switching characteristics ideal for TFT driving in LCD panels. FEATURES • High withstanding voltage : 20 V (MAX.) • Supports low-voltage input (logic power supply voltage : 3.0 to 3.6 V) • Includes 8 level shifters (among which 2 circuits can switch between normal and inverted output) • Small thin package : 24-pin plastic TSSOP (5.72 mm (225) ) ORDERING INFORMATION Part Number Package µ PD160970MA-6A5 24-pin plastic TSSOP (5.72 mm (225) ) . The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. Not all products and/or types are availabe in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S15857EJ4V0PM00 (4th edition) Date Published January 2003 NS CP (K) Printed in Japan The mark ★ shows major revised points. 2003 µ PD160970 1. BLOCK DIAGRAM / PIN CONFIGURATION • 24-pin plastic TSSOP (5.72 mm (225) ) µ PD160970MA-6A5 2 values VI1 1 L/S 24 VO1 23 VO2 2 values VI2 2 VI3 3 22 VEE VI4A 4 21 VCC 20 VO3 19 VO4 18 VO5 17 VO6 L/S 2 values VI4B 5 L/S 2 values VDD 6 L/S 2 values VSS 7 L/S 2 values VI5B 8 VI5A 9 16 VCC VI6 10 15 VEE 14 VO7 13 VO8 L/S 2 values VI7 11 L/S 2 values VI8 12 L/S L/S : Level shifter (VDD→VCC, VSS→VEE) 2 Preliminary Product Information S15857EJ4V0PM µ PD160970 2. PIN FUNCTIONS Pin Name I/O Pin Function Pin Name Symbol VI1 1 VI2 Pin I/O Function Symbol Output High-withstanding-voltage output VO8 13 2 VO7 14 VI3 3 VEE 15 − Negative power supply for high -withstanding-voltage block VI4A 4 VCC 16 − Positive power supply for high -withstanding voltage block VI4BNote 5 Output VDD 6 Input − Logic input VO6 17 Power supply for logic block VO5 18 Logic ground VO4 19 Logic input VO3 20 High-withstanding-voltage output VSS 7 − VI5BNote 8 Input VI5A 9 VCC 21 − Negative power supply for high -withstanding-voltage block VI6 10 VEE 22 − Positive power supply for high -withstand-voltage block VI7 11 VO2 23 Output VI8 12 VO1 24 High-withstanding-voltage output Note Use the VI4B and VI5B pins at the DC level. 3. Relation of logic input and High-withstanding-voltage output 3.1 VI1 to VI3, VI6 to VI8 VIn VOn L VCC H VEE High-withstanding-voltage output VCC Logic input VDD VSS VEE 3.2 VI4A/VI4B, VI5A/VI5B VInA L H L H VInB L (DC) H (DC) VOn VCC VEE VEE VCC Preliminary Product Information S15857EJ4V0PM 3 µ PD160970 4. Usage Cautions (1) The power-on sequence is VSS → VDD → logic signal → VEE → VCC, and the power-off sequence is the reverse sequence. • VSS and VDD, and VEE and VCC can be powered on simultaneously. • To prevent an abnormal output operation, it is recommended to fix the logic input during the transition phase of VEE and VCC to either ”H” or ”L”. VCC VDD VSS VEE Logic signal Remark The term “logic signal” as used above includes not only the rising edge/falling edge of the signal, but also “H” or “L” level input. (2) To ensure the switching characteristics of the VI4A/VI4B and VI5A/VI5B signal input, be sure to make the VI4B and VI5B pins DC input. Also, be sure to fix unused input pins to “H” or “L”. (3) Perform thorough evaluation with the actual device for simultaneous switching of multiple output circuits, bearing in mind the allowable output current during switching. (4) The output transistors in this device are designed for an impedance of several tens of ohms. Therefore, if driving a large load, IC malfunction and IC destruction or degradation may result owing to the influence of an output current of several hundred mAp-p per output. To prevent such malfunction from occurring, a number of countermeasures can be implemented, including the following. <1> Use a large-capacitance decoupling capacitor with superior high-frequency characteristics. <2> Insert in series a damping resistor for limiting the output current between the output pin and the load. Since the optimum values of constants differ depending on the equipment, determine the correct constants based on careful evaluation. (5) (6) Be sure to externally short power-supply pins for which several exist (VCC and VEE). Do not use the device with multiple output pons shorted. This may cause IC malfunction, destruction, or degradation. 4 Preliminary Product Information S15857EJ4V0PM µ PD160970 5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD −0.5 to +4.5 V Positive power supply for high -withstanding-voltage block VCC −0.5 to +17.0 V Negative power supply for high -withstanding-voltage block VEE −8.0 to +0.5 V Bias power supply for high -withstanding-voltage block VCC -VEE −0.5 to +25.0 V Input Voltage VI −0.5 to VDD + 0.5 V Output Voltage VO VEE − 0.5 to VCC + 0.5 V Operating Ambient Temperature TA −10 to +60 °C Storage Temperature Tstg −40 to +125 °C Power Dissipation Note Pd 500 mW Note When a glass epoxy board (100 mm x 100 mm x 1.0 mm, copper-plated area of 15%) is mounted. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −10 to +60°C, VSS = 0 V) Parameter Supply Voltage Clock Frequency Symbol Conditions MIN. TYP. MAX. Unit VDD 3.0 3.3 3.6 V VCC 9.5 11.5 13.5 V VEE −6.5 −5.5 −4.5 V VCC -VEE 14.0 17.0 20.0 V 200 kHz fCLK Electrical Characteristics (TA = −10 to +60°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V, VCC = 11.5 V ± 1.0 V, VEE = −5.5 V ± 0.5 V, tr = tf ≤ 5.0 ns) Parameter ★ Symbol Conditions MIN. TYP. Note MAX. Unit 0.2 VDD V Low-Level Input Voltage VIL All input pins VSS High-Level Input Voltage VIH All input pins 0.7 VDD Low-Level Output Voltage VOL IOL = +1.0 mA, All output pins High-Level Output Voltage VOH IOH = −1.0 mA, All output pins Output ON Resistance RON IO = ±1.0 mA, All output pins 80 130 Ω Static Current IDD VI = VSS VDD 0.1 10 µA ICC no load VCC 0.1 10 µA Input Leak Current IIL VI = VDD or VSS, All input pins 1.0 µA Input Capacitance CI −5.42 10.37 VDD V −4.87 V 11.42 −1.0 V 7 pF Note The TYP. value is a reference value when TA = 25°C, VDD = 3.3 V, VCC = 11.5 V, VEE = −5.5 V. Preliminary Product Information S15857EJ4V0PM 5 µ PD160970 Switching Characteristics (TA = −10 to +60°°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V, VCC = 11.5 V ± 1.0 V, VEE = −5.5 V ± 0.5 V, tr = tf ≤ 5.0 ns) Parameter Output delay time1 Output delay time2 Symbol Condition MIN. TYP. Note Unit tPHL1 All output pins, no load, 35 140 ns tPLH1 VO1-VO3, VO6-VO8 45 140 ns tPHL2 All output pins, no load, 40 140 ns tPLH2 VO4, VO5 50 140 ns Note The TYP. value is a reference value when TA = 25°C, VDD = 3.3 V, VCC = 11.5 V, VEE = −5.5 V. 6 MAX. Preliminary Product Information S15857EJ4V0PM µ PD160970 Switching Characteristics Waveform tf Logic input 90% 50% tr 10% 10% tPLH1, tPLH2 VDD 90% 50% VSS tPHL1, tPHL2 VCC 50% 50% High-withstanding-voltage output VEE tPHL2 tPLH2 VCC 50% 50% High-withstanding-voltage output VEE Preliminary Product Information S15857EJ4V0PM 7 µ PD160970 6. PACKAGE DRAWING 24-PIN PLASTIC TSSOP (5.72 mm (225)) 13 24 detail of lead end F G R P L S 12 1 E A H A' I J S D M N K C M S B NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 6.65±0.10 A' 6.5±0.1 B 0.575 C 0.5 (T.P.) D E 0.22±0.05 0.1±0.05 F 1.2 MAX. G 1.0±0.05 H I J K L M 6.4±0.1 4.4±0.1 1.0±0.1 0.17±0.025 0.5 0.10 N 0.08 P 3°+5° −3° R 0.25 S 0.6±0.15 P24MA-50-6A5 8 Preliminary Product Information S15857EJ4V0PM µ PD160970 7. RECOMMENDED MOUNTING CONDITIONS The µ PD160970 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Recommended Soldering Conditions for Surface Mounting Type µ PD160970MA-6A5 : 24-pin plastic TSSOP (5.72 mm (225) ) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature : 235°C, Time : 30 seconds max. (at 210°C or higher), IR35-00-3 Count : Three times or less, Exposure, limit : None, Flux : Rosin flux with low chlorine (0.2 Wt% or below) recommended VPS Package peak temperature : 215°C, Time : 40 seconds max. (at 200°C or higher), VP15-00-3 Count : Three times or less, Exposure, limit : None, Flux : Rosin flux with low chlorine (0.2 Wt% or below) recommended Wave Soldering Package peak temperature : 260°C, Time : 10 seconds max., WS60-00-1 Preheating temperature : 120°C max., Exposure, limit : Once, Flux : Rosin flux with low chlorine (0.2 Wt% or below) recommended Caution Do not use different soldering methods together. Preliminary Product Information S15857EJ4V0PM 9 µ PD160970 [MEMO] 10 Preliminary Product Information S15857EJ4V0PM µ PD160970 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Product Information S15857EJ4V0PM 11