ETC 74ALVCH16245/D

74ALVCH16245
Low-Voltage 16-Bit
Transceiver with Bus Hold
1.8/2.5/3.3 V
(3–State, Non–Inverting)
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The 74ALVCH16245 is an advanced performance, non–inverting
16–bit transceiver. It is designed for very high–speed, very low–power
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16245 is designed with byte control. It can be
operated as two separate octals, or with the controls tied together, as a
16–bit wide function. The Transmit/Receive (T/Rn) inputs determine
the direction of data flow through the bi–directional transceiver.
Transmit (active–HIGH) enables data from A ports to B ports; Receive
(active–LOW) enables data from B to A ports. The Output Enable
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition. The data inputs include active bushold
circuitry, eliminating the need for external pull–up resistors to hold
unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: VCC = 1.65 – 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
•
•
•
•
•
•
•
•
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
IOFF Specification Guarantees High Impedance When VCC = 0 V†
Near Zero Static Supply Current in All Three Logic States (40 A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16245
MARKING DIAGRAM
48
48
74ALVCH16245DT
1
AWLYYWW
TSSOP–48
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
74ALVCH16245DTR
Package
Shipping
TSSOP
2500/Tape & Reel
†To ensure the outputs activate in the 3–state condition, the output enable pins
should be connected to VCC through a pull–up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
 Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 1
1
Publication Order Number:
74ALVCH16245/D
74ALVCH16245
48 OE1
T/R1 1
B0 2
47 A0
B1 3
46 A1
GND 4
T/R1
1
OE1
T/R2
48
24
OE2
25
45 GND
B2 5
44 A2
B3 6
43 A3
VCC 7
42 VCC
B4 8
41 A4
B5 9
40 A5
GND 10
A0:7
B0:7
A8:15
B8:15
One of Eight
39 GND
B6 11
38 A6
B7 12
37 A7
B8 13
36 A8
B9 14
35 A9
GND 15
34 GND
B10 16
33 A10
B11 17
32 A11
VCC 18
31 VCC
B12 19
30 A12
B13 20
29 A13
GND 21
28 GND
B14 22
27 A14
B15 23
26 A15
T/R2 24
25 OE2
Figure 2. Logic Diagram
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
Figure 1. 48–Lead Pinout
(Top View)
PIN NAMES
Pins
Function
OEn
T/Rn
A0–A15
B0–B15
Output Enable Inputs
Transmit/Receive Inputs
Side A Inputs or 3–State Outputs
Side B Inputs or 3–State Outputs
EN1
EN2
EN3
EN4
T/R1
48
OE1
25
OE2
24
T/R2
47
1
46
1∇
2
3
5
44
43
41
1
2∇
6
8
40
9
38
11
37
36
1
3∇
12
13
35
14
33
16
32
30
1
4∇
17
19
29
20
27
22
26
23
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
Figure 3. IEC Logic Diagram
Inputs
Inputs
O tp ts
Outputs
OE1
T/R1
L
L
Bus B0:7 Data to Bus A0:7
L
H
H
X
O tp ts
Outputs
OE2
T/R2
L
L
Bus B8:15 Data to Bus A8:15
Bus A0:7 Data to Bus B0:7
L
H
Bus A8:15 Data to Bus B8:15
High Z State on A0:7, B0:7
H
X
High Z State on A8:15, B8:15
H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable
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74ALVCH16245
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
0.5 to 4.6
V
VI
DC Input Voltage
0.5 to 4.6
V
VO
DC Output Voltage
0.5 to 4.6
V
IIK
DC Input Diode Current
VI < GND
50
mA
IOK
DC Output Diode Current
VO < GND
50
mA
IO
DC Output Sink Current
50
mA
ICC
DC Supply Current per Supply Pin
100
mA
IGND
DC Ground Current per Ground Pin
100
mA
TSTG
Storage Temperature Range
65 to 150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
JA
Thermal Resistance (Note 2)
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
2000
200
N/A
V
ILATCH–UP
Latch–Up Performance
Above VCC and Below GND at 125°C (Note 6)
250
mA
260
°C
150
°C
90
°C/W
Level 1
Oxygen Index: 30 to 35
UL 94 V–O @ 0.125 in
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
TA
Operating Free–Air Temperature
t/V
Input Transition Rise or Fall Rate
Min
Max
Unit
Operating
Data Retention Only
2.3
1.5
3.6
3.6
V
(Note 7)
–0.5
3.6
V
0
0
VCC
3.6
V
40
85
°C
0
0
20
10
ns/V
(Active State)
(3–State)
VCC = 2.5 V 0.2 V
VCC = 3.0 V 0.3 V
7. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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74ALVCH16245
DC ELECTRICAL CHARACTERISTICS
TA = 40C to 85C
Symbol
VIH
VIL
VOH
VOL
Parameter
HIGH Level Input Voltage
(Note 8)
LOW Level Input Voltage
(Note 8)
HIGH Level Output Voltage
LOW Level Output Voltage
Condition
Min
1.65 V VCC 2.3 V
0.65 VCC
2.3 V VCC 2.7 V
1.7
2.7 V VCC 3.6 V
2.0
Max
V
1.65 V VCC 2.3 V
0.35 VCC
2.3 V VCC 2.7 V
0.7
2.7 V VCC 3.6 V
0.8
1.65 V VCC 3.6 V; IOH = 100 A
VCC 0.2
VCC = 1.65 V; IOH = 4 mA
1.2
VCC = 2.3 V; IOH = 6 mA
2.0
VCC = 2.3 V; IOH = 12 mA
1.7
VCC = 2.7 V; IOH = 12 mA
2.2
VCC = 3.0 V; IOH = 12 mA
2.4
VCC = 3.0 V; IOH = 24 mA
2.0
Unit
V
V
1.65 V VCC 3.6 V; IOL = 100 A
0.2
VCC = 1.65 V; IOL = 4 mA
0.45
VCC = 2.3 V; IOL = 6 mA
0.4
VCC = 2.3 V; IOL = 12 mA
0.7
VCC = 2.7 V; IOL = 12 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
V
II
Input Leakage Current
1.65 V VCC 3.6 V; 0 V VI 3.6 V
5.0
A
II(HOLD)
(
)
Minimum Bus–hold Input
Current
VCC = 3.6 V; VIN = 0 to 3.6 V
500
A
10
A
10
A
40
A
VCC = 3.0 V, VIN = 0.8 V
75
VCC = 3.0 V, VIN = 2.0 V
75
VCC = 2.3 V, VIN = 0.7 V
45
VCC = 2.3 V, VIN = 1.7 V
45
VCC = 1.65 V, VIN = 0.58 V
25
VCC = 1.65 V, VIN = 1.07 V
25
IOZ
3–State Output Current
1.65 V VCC 3.6 V; 0 V VO 3.6 V; VI = VIH or VIL
IOFF
Power–Off Leakage Current
VCC = 0 V; VI or VO = 3.6 V
ICC
Quiescent Supply Current
(Note 9)
1.65 V VCC 3.6 V; VI = GND or VCC
1.65 V VCC 3.6 V; 3.6 V VI, VO 3.6 V
40
Increase in ICC per Input
2.7 V VCC ≤ 3.6 V; VIH = VCC 0.6 V
750
ICC
8. These values of VI are used to test DC electrical characteristics only.
9. Outputs disabled or 3–state only.
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4
A
74ALVCH16245
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 )
Limits
TA = –40°C to +85°C
VCC = 3.0 V to 3.6 V
Symbol
Parameter
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to1.95 V
Waveform
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
Input to Output
1
1.0
1.0
3.0
3.0
1.0
1.0
3.7
3.7
1.0
1.0
6.0
6.0
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.0
1.0
4.4
4.4
1.0
1.0
5.7
5.7
1.0
1.0
9.3
9.3
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.0
1.0
4.1
4.1
1.0
1.0
5.2
5.2
1.0
1.0
7.6
7.6
ns
tOSHL
tOSLH
Output–to–Output Skew
(Note 11)
0.75
0.75
ns
0.5
0.5
0.5
0.5
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Condition
Typical
Unit
CIN
Symbol
Input Capacitance
Parameter
Note 12
6
pF
COUT
Output Capacitance
Note 12
7
pF
CPD
Power Dissipation Capacitance
Note 12, 10MHz
20
pF
12. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC.
VIH
Vm
An, Bn
Vm
tPLH
0V
tPHL
Vm
Bn, An
VOH
Vm
VOL
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VIH
Vm
OEn, T/Rn
Vm
0V
tPZH
tPHZ
Vm
An, Bn
VOH
Vy
≈0V
tPZL
An, Bn
tPLZ
Vm
≈ VCC
Vx
VOL
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
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74ALVCH16245
VCC
Symbol
3.3 V ±0.3 V
2.5 V ±0.2 V
1.8 V ±0.15 V
VIH
2.7 V
VCC
VCC
Vm
1.5 V
VCC/2
VCC/2
Vx
VOL + 0.3 V
VOL + 0.15 V
VOL + 0.15 V
Vy
VOH – 0.3 V
VOH – 0.15 V
VOH – 0.15 V
VCC
PULSE
GENERATOR
RL
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 ±0.3 V;
VCC× 2 at VCC = 2.5 ±0.2 V; 1.8 V ±0.15 V
tPZH, tPHZ
GND
CL = 50 pF for VCC = 3.0 ± 0.3 V
RL = 500 or equivalent
RT = ZOUT of pulse generator (typically 50 )
Figure 5. Test Circuit
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6 V or VCC × 2
OPEN
GND
74ALVCH16245
P0
K
t
P2
D
TOP
COVER
TAPE
E
A0
+
K0
SEE
NOTE 2
B1
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008")
SEE NOTE 2
F
+
B0
W
+
P
EMBOSSMENT
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
USER DIRECTION OF FEED
CENTER LINES
OF CAVITY
D1
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004") MAX
R MIN
BENDING RADIUS
10°
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
100 mm
(3.937")
MAXIMUM COMPONENT ROTATION
EMBOSSMENT
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039") MAX
TYPICAL
COMPONENT
CENTER LINE
250 mm
(9.843")
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 6. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 13 and 14)
Tape
Size
B1
Max
24mm
20.1mm
(0.791")
D
D1
E
F
K
P
P0
P2
R
T
W
1.5 + 0.1mm
1.5mm
1.75
11.5
11.9 mm
16.0
4.0
2.0
30 mm
0.6 mm
24.3 mm
-0.0
Min
±0.1 mm ±0.10 mm
Max
±0.1 mm
±0.1 mm
±0.1 mm
(1.18")
(0.024")
(0.957")
(0.059
(0.060")
(0.069
(0.453
(0.468")
(0.63
(0.157
(0.079
+0.004" -0.0)
±0.004")
±0.004")
±0.004")
±0.004")
±0.004")
13. Metric Dimensions Govern–English are in parentheses for reference only.
14. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity.
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74ALVCH16245
t MAX
13.0 mm ±0.2 mm
(0.512" ±0.008")
1.5 mm MIN
(0.06")
A
20.2 mm MIN
(0.795")
50 mm MIN
(1.969")
FULL RADIUS
G
Figure 7. Reel Dimensions
REEL DIMENSIONS
Tape Size
A Max
G
t Max
24 mm
360 mm
(14.173")
24.4 mm + 2.0 mm, -0.0
(0.961" + 0.078", -0.00)
30.4 mm
(1.197")
DIRECTION OF FEED
BARCODE LABEL
POCKET
Figure 8. Reel Winding Direction
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8
HOLE
74ALVCH16245
CAVITY
TAPE
TOP TAPE
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
User Direction of Feed
Figure 10. Reel Configuration
ÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
É
ÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
K
L
G
48 Leads
Figure 11. Package Footprint
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9
F
74ALVCH16245
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201–01
ISSUE A
48X
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K
K1
K REF
0.12 (0.005)
M
T U
S
V
S
T U
S
J J1
48
25
0.254 (0.010)
M
SECTION N–N
B
–U–
L
N
1
24
A
–V–
PIN 1
IDENT.
N
F
DETAIL E
D
0.076 (0.003)
–T– SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
C
M
0.25 (0.010)
–W–
DETAIL E
G
H
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10
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
12.40
12.60
6.00
6.20
--1.10
0.05
0.15
0.50
0.75
0.50 BSC
0.37
--0.09
0.20
0.09
0.16
0.17
0.27
0.17
0.23
7.95
8.25
0
8
INCHES
MIN
MAX
0.488
0.496
0.236
0.244
--0.043
0.002
0.006
0.020
0.030
0.0197 BSC
0.015
--0.004
0.008
0.004
0.006
0.007
0.011
0.007
0.009
0.313
0.325
0
8
74ALVCH16245
Notes
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74ALVCH16245
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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74ALVCH16245/D