National Semiconductor Application Note 2060 Daniel Tennant June 10, 2010 Introduction The derivation for matching time constants is as follows: Sensing the inductor DCR voltage can be an accurate and lossless technique of obtaining current information in DC/DC regulators. The absence of a series current sense resistor permits high current and high efficiency designs at a lower cost and higher density. Inductor DCR sensing also allows continuous monitoring of the inductor current as opposed to MOSFET RDS(ON) sensing which usually samples the voltage information across a FET during a small interval of time. Unlike MOSFETs, inductors can be purchased with low tolerance DCR specifications thus increasing the overall current sense accuracy. The LM27402 is equipped with a low offset current sense comparator to handle inductor DCR current sense applications. A +10 µA current in series with a resistor provides a voltage offset compared to the DCR voltage to set the current limit level. This application note will walk through the process of choosing the DCR current sense circuit components to optimize the current limit performance of the LM27402 DC/DC buck regulator controller. DCR Current Sense Topology Figure 1 shows a typical topology for sensing the DCR voltage in a buck regulator. 30124301 FIGURE 1. DCR Current Sense Topology Components RS and CS create an RC filter. The time constant of the RC filter should match the time constant related to the inductor and its DCR to accurately reproduce the DCR voltage across CS. Given the following circuit: LM27402 Current Limit Circuits LM27402 Current Limit Application Circuits If the time constants do not match, the voltage VS will either lead or lag VDCR. Particularly: If τRC > τL, VS will lag VDCR by a factor of τRC/τL at any point in time << τRC. If τRC < τL, VS will lead VDCR by factor of τRC/τL at any point in time << τRC. Time constant mismatching can be useful in some situations where tight or loose limiting of current limit must be applied. For example, if a buck regulator responds readily to fast dI/dt load transients, the inductor current must supply the output current in addition to the output capacitor current. This can cause the inductor current to temporarily overshoot thereby exceeding the current limit setpoint. The VS signal can filter this event if τRC is designed moderately larger than τL in anticipation of inductor overshoot. However, time constant mismatching must be used carefully. If τRC is much greater than τL , the inductor current may reach dangerous levels before the current limit condition is detected. LM27402 DCR Current Sense Design The LM27402 is designed to detect the voltage across the DCR of an inductor through the use of a sensitive current limit comparator. Five current limit events within 32 switching cycles must occur to mitigate the effects of noise and transitory over current events before hiccup mode activates. This allows the current limit level to be set close to the peak inductor ripple current during maximum output current where the voltage across the comparator may only be several milivolts. Figure 3 shows the typical circuit used to set the current limit level: 30124302 AN-2060 FIGURE 2. DCR Sense Equivalent Circuit © 2010 National Semiconductor Corporation 301243 www.national.com AN-2060 CS- Current Source Compliance Voltage The CS- current source requires at least 1.0V of headroom to guarantee a current of +10 µA. If the voltage across the current source (VIN - VCS-) decreases below 1.0V, the current will decrease as with the voltage across RSET effectively lowering the current limit setpoint. If VIN - VOUT is less than 1.0V, the current source will lose compliance because VCS- closely follows VOUT. This can be avoided by enabling the LM27402 at an input voltage 1V higher than VOUT or by lowering the common mode voltage of the current limit comparator with a resistor divider network shown in Figure 5. 30124304 FIGURE 3. LM27402 Typical Current Limit Circuit A +10 µA current source, ICS-, is internally connected from the VIN pin to the CS- pin to set the comparator offset voltage, VSET, across RSET. During operation, VSET is compared to the voltage VS, across CS. The equation for RSET to set the current limit set point is: ILIMIT (A) is the desired current limit level, RDCR (Ω) is the rated DC resistance of the inductor (DCR), and ICS- (A) is the +10 µA current source flowing out of the CS- pin. ILIMIT should be set sufficiently higher than the peak inductor current at maximum output current to minimize false current limit signals. Components RS and CS should be chosen to match the inductor L/RDCR time constant. A typical range of capacitance used in the RSCS network is 100 nF to 1 µF. After choosing a CS capacitor, RS can be calculated by: 30124308 FIGURE 5. Resistor Divider Network The voltage divider network in Figure 5 reduces the common mode voltage of the comparator and will effectively sense the inductor current. RSET is calculated in the same way as discussed previously. RS3 should be sized to avoid a condition where VIN – VCS- is less than 1.0V. RS, RS1 and RS2 should be sized to match the ratio set by RSET and RS3. Example Application Capacitor CSBY is used to filter any noise that may exist across the CS+ and CS- pins. A working range for the CSBY capacitance is 47 pF to 100 pF. A second resistor can be placed between CS+ and the RSCS network to match the impedance into the inputs of the current sense comparator for extra noise rejection shown here as RCS+ : In this example, the application is as follows: VIN = 3.3V, VOUT = 2.5V, IOUT = 20A, ILIMIT = 25.7A, L = 0.6 µH, RDCR = 1.89 mΩ, fSW = 300 kHz. An ILIMIT of 25.7A will produce a maximum DC output current of 24.5A at 25°C. The value of RSET should be: The lowest input voltage for this application (VINMIN) is 2.7V. RS3 should be sized to force VCS- to be less than 1.7V when VIN = 2.7V to maintain at least 1V of headroom . The equation solving for RS3 is: 30124307 Substituting VINMIN - VCS- = 1V and VCS- = VINMIN – 1V results in: FIGURE 4. Added Resistor for Noise Rejection RS3 = RSET(VINMIN - 1) = 4.87 kΩ(2.7 - 1) ≈ 8.25 kΩ The value of RCS+ should be equal to RSET. www.national.com 2 Layout The circuitry to sense the DCR voltage is sensitive to noise and demands careful layout practices. Following these general guide lines will help ensure a robust design. CSBY Placement It is recommended to design the CS+ branch of resistors to be higher impedance than the CS- branch of resistors to yield a CS value in the nanofarad range. In this example, the CS+ branch impedance will be set eight times larger than the CSimpedance. RS2 is calculated as follows: The CSBY capacitor should be placed as close to the CS+ and CS- pins as possible. CSBY serves as the last line of defense between board noise and the current limit comparator. CSBY should be a small 0603 or 0402 surface mount capacitor to facilitate close placement to the LM27402. RS2 = 8RS3 ≈ 66.5 kΩ CS+ and CS- Traces Unfortunately, the ratio of RS1/RS2 is not equal to RSET/RS3 thus allowing transient differential signals to feed through the CS capacitor causing an error voltage between the CS+ and CS- pins. RS and RS1 should be sized appropriately to minimize this error. Specifically, RS should be sized 5% of 8RSET and RS1 should be sized 95% of 8RSET as shown here: Certain applications will call for long CS+ and CS- traces. For example: The LM27402 evaluation board incorporates a temperature compensated current limit circuit with a PTC resistor in series with CS-. This requires the CS- trace to be routed from the LM27402 to the inductor. It is essential to route the CS+ and CS- traces away from noise emitting nodes, particularly the switch-node and gate drives nodes on the PCB. Routing the CS+ and CS- traces side by side for close coupling and in between ground planes is a sufficient way to mitigate differential noise. RS = (.05)(8)RSET ≈ 1.96 kΩ RS1 = (.95)(8)RSET ≈ 37.4 kΩ CS is calculated using the parallel combination of RS||(RS1 +RS2) to match the inductor time constant shown here: 3 www.national.com AN-2060 Resistors RS, RS1, and RS2 must be designed to maintain the following ratio: LM27402 Current Limit Circuits Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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