Features • • • • • • Full Compliance with USB Spec Rev 1.1 Four Downstream Ports Full-speed and Low-speed Data Transfers Per Port Overcurrent Monitoring Individual Port Power Control USB Connection Status Indicators Overview Introduction The AT43312A is a 5-port USB hub chip supporting one upstream and four downstream ports. The AT43312A connects to an upstream hub or Host/Root Hub via Port0 and the other ports connect to external downstream USB devices. The hub re-transmits the USB differential signal between Port0 and Ports[1:4] in both directions. A USB hub with the AT43312A can operate as a bus-powered or self-powered through chip’s power mode configuration pin. In the self-powered mode, port power can be switched or unswitched. Overcurrent reporting and port power control can be individual or global. An on-chip power supply eliminates the need for an external 3.3V supply. Self- and Buspowered USB Hub Controller AT43312A The AT43312A supports the 12 Mb/s full speed as well as 1.5 Mb/s slow speed USB transactions. To reduce EMI, the AT43312A’s oscillator frequency is 6 MHz even though some internal circuitry operates at 48 MHz. The AT43312A consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller. PWR1 DP4 DM4 DP3 DM3 VSS DP2 DM2 CEXT DP1 DM1 DP0 DM0 STAT1 STAT2 STAT3 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DP3 DM4 DP4 PWR1 PWR2 PWR3 PWR4 VCC5 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 DMO STAT1 STAT2 STAT3 STAT4 SELF/BUS LPSTAT OVC1 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 PWR2 PWR3 PWR4 VCC5 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 OVC1 LPSTAT SELF/BUS STAT4 LQFP Top View DM3 VSS DP2 DM2 CEXT DP1 DM1 DP0 PDIP/SOIC Rev. 1255C–12/01 1 The Serial Interface Engine’s tasks are: • Manage the USB communication protocol • USB signaling detection/generation • Clock/Data separation, data encoding/decoding, CRC generation/checking • Data serialization/de-serialization The Hub Repeater is responsible for: • Providing upstream connectivity between the selected device and the Host • Managing connectivity setup and tear-down • Handling bus fault detection and recovery • Detecting connect/disconnect on each port The Hub Controller is responsible for: • Hub enumeration • Providing configuration information to the Host • Providing status of each port to the Host • Controlling each port per Host command Figure 1. Block Diagram UPSTREAM PORT PORT 0 HUB CONTROLLER ENDPOINT 0 ENDPOINT 1 SERIAL INTERFACE ENGINE PORT 1 HUB REPEATER PORT 2 PORT 3 PORT 4 TO DOWNSTREAM DEVICES Note: 2 This document assumes that the reader is familiar with the Universal Serial Bus and therefore only describes the unique features of the AT43312A chip. For detailed information about the USB and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.1, September 23, 1998. AT43312A 1255C–12/01 AT43312A PDIP/SOIC Pin Assignment Type: I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground Table 1. 32-pin PDIP/SOIC Assignment Pin Signal Type 1 PWR2 O 2 PWR3 O 3 PWR4 O 4 VCC5 V 5 VSS V 6 OSC1 I 7 OSC2 O 8 LFT I 9 TEST I 10 OVC4 I 11 OVC3 I 12 OVC2 I 13 OVC1 I 14 LPSTAT I 15 SELF/BUS I 16 STAT4 O 17 STAT3 O 18 STAT2 O 19 STAT1 O 20 DM0 B 21 DP0 B 22 DM1 B 23 DP1 B 24 CEXT O 25 DM2 B 26 DP2 B 27 VSS V 28 DM3 B 29 DP3 B 30 DM4 B 31 DP4 B 32 PWR1 O 3 1255C–12/01 LQFP Pin Assignment Type: I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground Table 2. 32-pin LQFP Assignment 4 Pin Signal Type 1 DP3 B 2 DM4 B 3 DP4 B 4 PWR1 O 5 PWR2 O 6 PWR3 O 7 PWR4 O 8 VCC5 V 9 VSS V 10 OSC1 I 11 OSC2 O 12 LFT I 13 TEST I 14 OVC4 I 15 OVC3 I 16 OVC2 I 17 OVC1 I 18 LPSTAT I 19 SELF/BUS I 20 STAT4 O 21 STAT3 O 22 STAT2 O 23 STAT1 O 24 DMO B 25 DP0 B 26 DM1 B 27 DP1 B 28 CEXT O 29 DM2 B 30 DP2 B 31 VSS V 32 DM3 B AT43312A 1255C–12/01 AT43312A Signal Description OSC1 Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. OSC2 Oscillator Output. Output of the inverting oscillator amplifier. LFT PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel with a 100Ω resistor in series with a 10 nF capacitor to ground (VSS). SELF/BUS Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high on this pin enables the self-powered mode, a low enables the bus-powered mode. LPSTAT Local Power Status. In the self-powered mode, this is an input pin that should be connected to the local power supply through a 47 kΩ resistor. The voltage on this pin is used by the chip for reporting the condition of the local power supply. In the bus-powered mode, this pin is not used. DP0 Upstream Plus USB I/O. This pin should be connected to CEXT through an external 1.5 kΩ pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to the Host Controller or an upstream Hub. DM0 Upstream Minus USB I/O. DP[1:4] Port Plus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. DM[1:4] Port Minus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor OVC[1:4] Overcurrent. This is the input signal used to indicate to the AT43312A that an overcurrent is detected at the port. If OVCx is asserted, AT43312A will assert the PWRx pin and report the status to the USB Host. PWR[1:4] Power Switch. This is an output signal used to enable or disable the external voltage regulator supplying power to a port. PWRx is de-asserted when a power supply problem is detected at OVCx. STAT[1:4] Connect Status. This is an output pin indicating that a port is properly connected. STATx is asserted when the port is enabled. 5 1255C–12/01 CEXT External Capacitor. For proper operation of the on chip regulator, a 0.27 µF capacitor must be connected to this pin. TEST Test. This pin should be connected to a logic high for normal operation. VCC 5V Power Supply. VSS Ground. Functional Description Summary The Atmel AT43312A is a USB hub controller for use in a standalone hub as well as an add-on hub for an existing non-USB peripheral such a PC display monitor or keyboard. In addition to supporting the standard USB hub functionality, the AT43312A has additional features to enhance the user friendliness of the hub. USB Ports The AT43312A’s upstream port, Port0, is a full-speed port. A 1.5 kΩ pull-up resistor to the 3.3V regulator output, CEXT, is required for proper operation. The downstream ports support both full-speed as well as low-speed devices. 15 kΩ pull-down resistors are required at their inputs. Full-speed signal requirements demand controlled rise/fall times and impedance matching of the USB ports. To meet these requirements, 22Ω resistors must be inserted in series between the USB data pins and the USB connectors. Hub Repeater The Hub Repeater is responsible for port connectivity setup and tear-down. It also supports exception handling such as bus fault detection and recovery, and connect/disconnect detection. Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is received at Port0, the AT43312A propagates it to all the enabled downstream ports. Conversely, a packet from a downstream port is transmitted from Port0. The AT43312A supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices attached to the downstream ports are determined to be either full-speed or lowspeed depending which data line (DP or DM) is pulled high. If a port is enumerated as low-speed, its output buffers operate at a slew rate of 75 - 300 ns, and the AT43312A will not propagate any traffic to that port unless it is prefaced with a preamble PID. Lowspeed data following the preamble PID is propagated to both low- and full-speed devices. The AT43312A will enable low-speed drivers within four full-speed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP. Packets out of Port0 are always transmitted using the full-speed drivers. All the AT43312A ports independently drive and monitor their DP and DM pins so that they are able to detect and generate the “J”, “K”, and SE0 bus signaling states. Each hub port has single-ended and differential receivers on its DP and DM lines. The port I/O buffers comply with the voltage levels and drive requirements as specified in the USB Specifications Rev 1.0. 6 AT43312A 1255C–12/01 AT43312A The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets reset every time an SOF token is received from the Host. Serial Interface Engine The Serial Interface Engine handles the USB communication protocol. It performs the USB clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC generation and checking, USB packet ID decoding and generation, and data serialization and de-serialization. The on-chip phase locked loop generates the high frequency clock for the clock/data separation circuit. Power Management A hub is a high-powered device and is allowed to draw up to 500 mA of current from the host or upstream hub. The AT43312A chip itself and its external hub circuitry consume much less than 100 mA. The AT43312A’s power management logic works with external devices to detect overcurrent and control power to the ports. Overcurrent sensing is on a per port basis and is achieved through the OVCx pins. Whenever the voltage at OVCx is asserted, the AT43312A treats it as an overcurrent condition. This could be caused by an overload, or even a short circuit, and causes the AT43312A to set the port’s PORT_OVER_CURRENT status bit and its C_PORT_OVER_CURRENT status change bit. At the same time, power to the offending port is shut off and its STATx generates a square wave with a frequency of about 1 second. An external device is needed to monitor the overcurrent condition and perform the actual switching of the ports’ power under control of the AT43312A. The signals to control the external switches are the PWRx pins. Any type of suitable switch or device is acceptable. However, it should have a low-voltage drop across it even when the port absorbs full-power. In its simplest form this switch can be a P-channel MOSFET. One advantage of using a MOSFET switch is its very low-voltage drop and low-cost. Each one of the AT43312A’s port has its own power control pin which is asserted only when a SetPortFeature[PORT-POWER] request is received from the host. PWRx is deasserted under the following conditions: 1. Power-up 2. Reset and initialization 3. Overcurrent condition 4. Requested by the host through a ClearPortFeature [PORT_POWER] for ALL the ports Self-powered Mode In the self-powered mode, power to the downstream ports must be supplied by an external power supply. This power supply must be capable of supplying 500 mA per port for a total of 2A. The USB specifications require that the voltage drop at the power switch and board traces be no more than 100 mV. A good conservative maximum drop at the power switch itself should be no more than 75 mV. Careful design and selection of the power switch and PC board layout is required to meet the specifications. When using a MOSFET switch, its resistance must be 140 m Ω or less under worst case conditions. A suitable MOSFET switch for an AT43312A based hub is an integrated high side dual MOSFET switch such as the Micrel MIC2526. 7 1255C–12/01 Bus Powered Mode In the bus powered mode, all the power for the hub itself as well as the downstream ports is supplied by the root hub or upstream hub through the USB. Only 100 mA is available for each of the hub’s downstream devices and therefore only low power devices are supported. The power switch and overcurrent protection works exactly like the self-powered mode, except that the allowable switch resistance is higher: 700 mΩ or less under the worst case condition. The diagrams of Figure 2 and Figure 3 show examples of the power supply and management connections for a typical AT43312A port in the self-powered mode and bus powered mode. Figure 2. Self-powered Hub Power Supply BUS_POWER GND U1 VCC GND LPSTAT OVC CTL FLG U2 PS5 POWER SUPPLY PWR R1 47K AT43312A IN 5V OUTPUT OUT SWITCH GND PORT_POWER GND To Downstream Device Figure 3. Bus Powered Hub Power Supply BUS_POWER GND U1 VCC GND AT43312A LPSTAT PWR OVC CTL FLG U2 IN OUT PORT POWER SWITCH To Downstream Device GND 8 AT43312A 1255C–12/01 AT43312A Port Status Pin The STATx pins are signals that are not required by the USB specification. Their function is to allow the hub to provide feedback to the user whenever a device is properly connected to the port. An LED and series resistor connected to STATx can be used to provide a visual feedback. If an overcurrent condition is detected at a port, the STATx of the offending port will alternately turn on and off causing an LED to blink. The LED will continue to blink until power to the offending port is turned off by the host or until the hub is re-enumerated. The default state of STATx is inactive. After a port is enabled AT43312A will assert the port’s STATx. Any condition that causes the port to be disabled inactivates STATx. Hub Controller The Hub Controller of the AT43312A provides the mechanism for the Host to enumerate the Hub and the AT43312A to provide the Host with its configuration information. It also provides a mechanism for the Host to monitor and control the downstream ports. Power is applied, on a per port basis, by the Hub Controller upon receiving a command, SetPortFeature[PORT_POWER], from the Host. The AT43312A must be configured first by the Host before the Hub Controller can apply power to external devices. The Hub Controller contains two endpoints, Endpoint0 and Endpoint1 and maintains a status register, Controller Status Register, which reflects the AT43312A’s current settings. At power up, all bits in this register will be set to 0’s. Table 3. Control Status Register Bit 0 1 Endpoint 0 Function Hub configuration status Value Description 0 1 Set to 0 or 1 by a Set_Configuration Request Hub is not currently configured Hub is currently configured 0 1 Set to 0 or 1 by ClearFeature or SetFeature request Default value is 0 Hub is currently not enabled to request remote wakeup Hub is currently enabled to request remote wakeup Hub remote wakeup status 2 Endpoint0 STALL status 0 1 Endpoint0 is not stalled Endpoint0 is stalled 3 Endpoint1 STALL status 0 1 Endpoint1 is not stalled Endpoint1 is stalled Endpoint 0 is the AT43312A’s default endpoint used for enumeration of the Hub and exchange of configuration information and requests between the Host and the AT43312A. Endpoint 0 supports control transfers. The Hub Controller supports the following descriptors: Device Descriptor, Configuration Descriptor, Interface Descriptor, Endpoint Descriptor, and Hub Descriptor. These Descriptors are described in detail elsewhere in this document. Standard USB Device Requests and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint descriptor for Endpoint0. Endpoint 1 Endpoint1, an interrupt endpoint, is used by the Hub Controller to send status change information to the Host. The Hub Controller samples the changes at the end of every frame at time marker EOF2 in preparation for a potential data transfer in the subsequent frame. The sampled information is stored in a byte wide register, the Status Change Register, using a bitmap scheme. Each bit in the Status Change Register corresponds to one port as shown on the following page. 9 1255C–12/01 Table 4. Status Change Register Bit Function Value Meaning 0 Hub status change 0 1 No change in status Change in status detected 1 Port1 status change 0 1 No change in status Change in status detected 2 Port2 status change 0 1 No change in status Change in status detected 3 Port3 status change 0 1 No change in status Change in status detected 4 Port4 status change 0 1 No change in status Change in status detected 5-7 Reserved 000 Default values An IN Token packet from the Host to Endpoint 1 indicates a request for port change status. If the Hub has not detected any change on its ports, or any changes in itself, then all bits in this register will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0 - 4 is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a status change when polled until that particular change has been removed by a ClearPortFeature request from the Host. No status change will be reported by Endpoint 1 until the AT43312A has been enumerated and configured by the Host via Endpoint 0. Oscillator and Phase-LockedLoop All clock signals required to run the AT43312A are derived from an on-chip oscillator. To reduce EMI and power dissipation in the system, the oscillator is designed to operate with a 6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 PPM. Even though the oscillator circuit would work with a ceramic resonator, its use is not recommended because a resonator would not have the frequency accuracy and stability. A 6 MHz series resonance quartz crystal with a load capacitance of approximately 10 pF is recommended. The oscillator is a special low-power design and in most cases no external capacitors and resistors are necessary. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor between OSC2 and the crystal pin is recommended. The clock can also be externally sourced. In this case, connect the clock source to the OSC1 pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V (see Table 8) and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. 10 AT43312A 1255C–12/01 AT43312A Figure 4. Oscillator and PLL Connections U1 OSC1 Y1 6.000 MHz OSC2 R1 100 C1 10nF AT43312A LFT C2 2nF For proper operation of the PLL, an external RC filter consisting of a series RC network of 100Ω and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin to VSS. To provide the best operating condition for the AT43312A, careful consideration of the power supply connections are recommended. Use short, low-impedance connections to all power supply lines: VCC5, and VSS. Use sufficient decoupling capacitors to reduce noise: 0.1 µF decoupling capacitors of high quality, soldered as close as possible to the package pins are recommended. 11 1255C–12/01 Electrical Specification Absolute Maximum Ratings* Operating Temperature (TO) .......................-40°C to +125°C *NOTICE: Storage Temperature (TS)...........................-65°C to +150°C Maximum 5V Power Supply (VCC5) ................................5.5V DC Input Voltage (VI) ...............-0.3V – VCEXT + 0.3, 4.6 max Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Voltage (VO) ...........-0.3V – VCEXT + 0.3, 4.6 max DC Characteristics The values shown in this table are valid for TA = 0°C to 85°C, VCC = 4.4V to 5.25V, unless otherwise noted. Table 5. Power Supply Symbol Parameter VCC 5V Power Supply ICC ICCS Condition Min Max Unit 4.4 5.25 V 5V Supply Current 24 mA Suspended Device Current 150 µA Max Unit Table 6. USB Signals: DPx, DMx Symbol Parameter VIH Input Level High (driven) 2.0 V VIHZ Input Level High (floating) 2.7 V VIL Input Level Low VDI Differential Input Sensitivity VCM Differential Command Mode Range VOL1 Static Output Low RL of 1.5 kΩ to 3.6V VOH1 Static Output High RL of 1.5 kΩ to GND VCRS Output Signal Crossover CIN Input Capacitance 12 Condition Min 0.8 DPx and DMx 0.2 0.8 V V 2.5 V 0.3 V 2.8 3.6 V 1.3 2.0 V 20 pF AT43312A 1255C–12/01 AT43312A Table 7. PWR, STAT, OVC Symbol Parameter Condition VOL2 Output Low Level, PWR, STAT, OVC IOL = 4 mA VOH2 Output High Level, PWR IOH = 4 mA Cout Output Capacitance 1 MHz VIL3 Input Low Level VIH3 Input High Level Cout Output Capacitance Min Max Unit 0.5 V 0.5 VCEXT V 10 pF 0.3 VCEXT V 0.7 VCEXT 1 MHz V 10 pF Min Max Unit Table 8. Oscillator Signals: OSC1, OSC2 Symbol Parameter VLH OSC1 Switching Level 0.47 1.20 V VHL OSC1 Switching Level 0.67 1.44 V CX1 Input Capacitance, OSC1 17 pF CX2 Output Capacitance, OSC2 17 pF C12 OSC1/2 Capacitance 1 pF tsu Start-up Time 6 MHz, fundamental 2 ms DL Drive Level VCC = 3.3V, 6 MHz crystal, 100Ω equiv. series resistor 150 µW Note: Condition OSC2 must not be used to drive other circuitry. Table 9. DPx, DMx Driver Characteristics, Full-speed Operation Symbol Parameter Condition Min Max Unit tR Rise Time CL = 50 pF 4 20 ns tF Fall Time CL = 50 pF 4 20 ns tRFM TR/TF Matching 90 110 % zDRV Driver Output Resistance(1) 28 44 Ω Note: Steady state drive 1. With external 22Ω series resistor. Figure 5. Data Signal Rise and Fall Time RISE TIME VCRS 10% 90% FALL TIME 90% 10% DIFFERENTIAL DATA LINES tR tF 13 1255C–12/01 Table 10. DPx, DMx Source Timings, Full-speed Operation Symbol Parameter tDRATEq Full Speed Data Rate(1) tFRAME Frame Interval Condition Average Bit Rate (1) Min Max Unit 11.97 12.03 Mb/s 0.9995 1.0005 ms tRFI Consecutive Frame Interval Jitter (1) No clock adjustment 42 ns tRFIADJ Consecutive Frame Interval Jitter(1) No clock adjustment 126 ns Source Diff Driver Jitter tDJ1 To Next Transition -2 2 ns tDJ2 For Paired Transitions -1 1 ns tFDEOP Source Jitter for Differential Transition to SEO Transitions -2 5 ns tDEOP Differential to EOP Transition Skew -2 5 ns -18.5 18.5 ns -9 9 ns 175 ns Recvr Data Jitter Tolerance tJR1 To Next Transition tJR2 To Paired Transitions tFEOPT Source SEO Interval of EOP 160 tFEOPR Receiver SEO Interval of EOP 82 tFST Width of SEO Interval During Differential Transition Note: ns 14 ns 1. With 6.000 MHz, 100 ppm crystal. Figure 6. Full-speed Load TxD+ RS CL TxD- RS CL CL = 50 pF Table 11. DPx, DMx Driver Characteristics, Low-speed Operation Symbol Parameter Condition Min Max Unit tR Rise Time CL = 200 - 600 pF 75 300 ns tF Fall Time CL = 200 - 600 pF 75 300 ns tRFM TR/TF Matching 80 125 % 14 AT43312A 1255C–12/01 AT43312A Figure 7. Low-speed Downstream Port Load TxD+ RS CL TxD- 3.6V 1.5 kΩ RS CL CL = 200 pF to 600 pF Table 12. DPx, DMx Hub Timings, Full-speed Operation Symbol Parameter tHDD2 Hub Differential Data Delay without Cable Condition Min Max Unit 44 ns Hub Diff Driver Jitter tHDJ1 To Next Transition -3 3 ns tHDJ2 To Paired Transition -1 1 ns tFSOP Data Bit Width Distortion after SOP -5 5 ns tFEOPD Hub EOP Delay Relative to THDD 0 15 ns tFHESK Hub EOP Output Width Skew -15 15 ns Min Max Unit 300 ns Table 13. DPx, DMx Hub Timings, Low-speed Operation Symbol Parameter tLHDD Hub Differential Data Delay Condition Downstr Hub Diff Driver Jitter tLHDJ1 To Next Transition, downst -45 45 ns tLHDJ2 For Paired Transition, downst -15 15 ns tLUKJ1 To Next Transition, upstr -45 45 ns tLUKJ2 For Paired Transition, upstr -45 45 ns tSOP Data Bit Width Distortion after SOP -60 60 ns tLEOPD Hub EOP Delay Relative to THDD 0 200 ns tLHESK Hub EOP Output Width Skew -300 300 ns 15 1255C–12/01 Figure 8. Differential Data Jitter TPERIOD DIFFERENTIAL DATA LINES CROSSOVER POINTS CONSECUTIVE TRANSITIONS N*TPERIOD+TXJR1 PAIRED TRANSITIONS N*TPERIOD+TXJR2 Figure 9. Differential-to-EOP Transition Skew and EOP Width CROSSOVER POINT EXTENDED TPERIOD DIFFERENTIAL DATA LINES DIFF. DATA-toSE0 SKEW N*TPERIOD+TDEOP SOURCE EOP WIDTH: TFEOPT TLEOPT RECEIVER EOP WIDTH: TFEOPR, TLEOPR Figure 10. Receiver Jitter Tolerance TPERIOD DIFFERENTIAL DATA LINES TJR TJR1 TJR2 CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 16 AT43312A 1255C–12/01 AT43312A Figure 11. Hub Differential Delay, Differential Jitter, and SOP Distortion UPSTREAM END OF CABLE 50% POINT OF INITIAL SWING VSS DIFFERENTIAL DATA LINES VSS CROSSOVER POINT DOWNSTREAM PORT VSS HUB DELAY DOWNSTREAM THDD1 CROSSOVER POINT HUB DELAY UPSTREAM THDD2 UPSTREAM PORT VSS A. DOWNSTREAM HUB DELAY WITH CABLE DOWNSTREAM PORT CROSSOVER POINT B. UPSTREAM HUB DELAY WITHOUT CABLE CROSSOVER POINT VSS UPSTREAM PORT OR END OF CABLE VSS HUB DELAY UPSTREAM THDD1, THDD2 CROSSOVER POINT C. UPSTREAM HUB DELAY WITH OR WITHOUT CABLE Figure 12. Hub EOP Delay and EOP Skew 50% POINT OF INITIAL SWING UPSTREAM END OF CABLE VSS DOWNSTREAM PORT CROSSOVER POINT EXTENDED UPSTREAM PORT VSS TEOP- TEOP+ CROSSOVER POINT EXTENDED DOWNSTREAM PORT VSS TEOP- TEOP+ CROSSOVER POINT EXTENDED VSS A. DOWNSTREAM EOP DELAY WITH CABLE B. DOWNSTREAM EOP DELAY WITHOUT CABLE CROSSOVER POINT EXTENDED DOWNSTREAM PORT VSS UPSTREAM PORT OR END OF CABLE VSS TEOP- TEOP+ CROSSOVER POINT EXTENDED C. UPSTREAM EOP DELAY WITH OR WITHOUT CABLE 17 1255C–12/01 Table 14. Hub Event Timings Symbol Parameter tDCNN tDDIS Condition Min Max Unit Time to Detect a Downstream Port Connect Event Awake Hub Suspended Hub 2.5 2.5 2000 12000 µs µs Time to Detect a Disconnect Event and Downstream Port Awake Hub Suspended Hub 2.5 2.5 2.5 10000 µs µs 100 µs 10 20 ms tURSM Time from Detecting Downstream Resume to Rebroadcast tDRST Duration of Driving Reset to a Downstream Device tURLK Time to Detect a Long K From Upstream 2.5 100 µs tURLSEO Time to Detect a Long SEO From Upstream 2.5 10,000 µs tURPSEO Time of repeating SEO Upstream 23 FS bit time 18 Only for a SetPortFeature (PORT_RESET) request AT43312A 1255C–12/01 AT43312A 0 Ordering Information Ordering Code Package AT43312A-6AC AT43312A-6PC AT43312A-6SC 32A 32P6 32R Operating Range Commercial (0°C to 70°C) Package Type 32A 32-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP) 32R 32-lead, 0.440" Wide, Plastic Gull Wing Small Outline (SOIC) 32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 19 1255C–12/01 Packaging Information 32A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 32A B AT43312A 1255C–12/01 AT43312A 32R Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 0.508(0.020) 0.356(0.014) 11.30(0.445) 14.40(0.567) 11.05(0.435) 14.05(0.553) PIN 1 1.27(0.050) BSC 21.08(0.830) 20.83(0.820) 2.54(0.100) 2.29(0.090) 0.254(0.010) 0.102(0.004) 0.22(0.0085) 0.10(0.0040) 0º ~ 8º 1.04(0.041) 0.53(0.021) 04/11/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32R, 32-lead, 0.440" Body, Plastic Gull Wing Small Outline (SOIC) DRAWING NO. REV. 32R A 21 1255C–12/01 32P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 41.783 – 42.291 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). e NOTE Note 1 Note 1 2.540 TYP 09/28/01 R 22 2325 Orchard Parkway San Jose, CA 95131 TITLE 32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 32P6 REV. B AT43312A 1255C–12/01 Atmel Headquarters Atmel Product Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 1150 E. Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1255C–12/01/0M