ETC C3ENPA1-DS

Freescale Semiconductor, Inc.
Data Sheet
C-3e NETWORK PROCESSOR
Freescale Semiconductor, Inc...
SILICON REVISION A1
C3ENPA1-DS/D
Rev 03 PRELIMINARY
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C-3e Network Processor
Silicon Revision A1
Pr
Freescale Semiconductor, Inc...
Data Sheet
C3ENPA1-DS/D
Rev 03
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Copyright © 2002 Motorola, Inc. All rights reserved. No part of this documentation may
be reproduced in any form or by any means or used to make any derivative work (such as
translation, transformation, or adaptation) without written permission from Motorola.
Freescale Semiconductor, Inc...
Motorola reserves the right to revise this documentation and to make changes in content
from time to time without obligation on the part of Motorola to provide notification of
such revision or change.
Motorola provides this documentation without warranty, term, or condition of any kind,
either implied or expressed, including, but not limited to, the implied warranties, terms or
conditions of merchantability, satisfactory quality, and fitness for a particular purpose.
Motorola may make improvements or changes in the product(s) and/or the program(s)
described in this documentation at any time.
C-5e, C-3e, C-5, Q-5, Q-3, C-Port, and C-Ware are all trademarks of C-Port, a Motorola
Company. Motorola and the stylized Motorola logo are registered in the US Patent &
Trademark Office. All other product or service names are the property of their respective
owners.
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C3ENPA1-DS/D
Rev 03
Freescale Semiconductor, Inc...
CONTENTS
About This Guide
Guide Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using PDF Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 1
Functional Description
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Massive Processing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Functional Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 2
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Signal Descriptions
Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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C3ENPA1-DS/D REV 03
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
6
CONTENTS
Gigabit Ethernet and Fibre Channel TBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SONET OC-3 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SONET OC-12 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Executive Processor System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fabric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QMU SRAM (Internal Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QMU to Q-5/Q-3 (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDcode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 3
Electrical Specifications
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Package Conduction Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heat Sink Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CP Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C3ENPA1-DS/D REV 03
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MOTOROLA GENERAL BUSINESS INFORMATION
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CONTENTS
7
DS1/DS3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10/100 Ethernet Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications . . . . . . . . . . . . . . . . . . 83
OC-3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
OC-12 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Executive Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MDIO Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Low Speed Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PROM Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fabric Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
TLU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
QMU SRAM (Internal Mode) Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
QMU to Q-5/Q-3 (External Mode) Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
CHAPTER 4
Mechanical Specifications
Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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C3ENPA1-DS/D REV 03
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CONTENTS
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8
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
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C3ENPA1-DS/D
Rev 03
Freescale Semiconductor, Inc...
LIST OF FIGURES
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C-3e Network Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Locations (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Cell Design That Can Be Used for Both Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . 68
Bringup Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package Cross Section View with Serveral Heat Sink Options . . . . . . . . . . . . . . . . . . . . . . . 76
Package with Heat Sink Mounted to the Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . 77
Test Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
QMU SRAM (Internal Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
QMU to Q-5/Q-3 (External Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
C-3e Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
C-3e Network Processor BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
C-3e Network Processor BGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
MOTOROLA GENERAL BUSINESS INFORMATION
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C3ENPA1-DS/D REV 03
Freescale Semiconductor, Inc.
LIST OF FIGURES
Freescale Semiconductor, Inc...
10
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
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Freescale Semiconductor, Inc.
C3ENPA1-DS/D
Rev 03
Freescale Semiconductor, Inc...
LIST OF TABLES
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30
Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Navigating Within a PDF Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
C-3e Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
C-Port Silicon Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TLU SRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . . . . . . 36
Gigabit Ethernet (GMII/MII) Signals One Cluster Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PROM Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fabric Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Utopia1*, 2, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping . . . . . . 50
Utopia1*, 2, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping . . . . . . . 50
BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
QMU SRAM (Internal Mode) Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
QMU to Q-5/Q-3 (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Power Supply Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . . . . 57
Signals Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
JTAG Internal Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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LIST OF TABLES
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31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
C3ENPA1-DS/D REV 03
Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
C-3e Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
C-3e Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .72
C-3e Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
C-3e Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
C-3e Network Processor Power and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
QMU SRAM (Internal Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .99
QMU to Q-5/Q-3 (External Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Signal Groups in QMU to Q-5/Q-3 (External Mode) Timimg Diagrams . . . . . . . . . . . . . . . . . . . 101
Package Measurements (Reference Figure 28, Figure 29 and Figure 30 for Symbols). . . . 106
C-3e Network Processor Marking Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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ABOUT THIS GUIDE
Guide Overview
The C-3e Network Processor Data Sheet describes the hardware layout specifications
including pinouts, memory configuration guidelines, timing diagrams, power and power
sequencing guidelines, thermal design guidelines, and mechanical specifications. This
document contains information on a pre-production product. Specifications and
information herein are subject to change without notice.
This guide assumes a good understanding of the C-3eTM Network Processor (NP)
architecture. See the C-5e/C3e Network Processor Architecture GuidE (part number
C5EC3EARCH-RM/D) for more detail about how the hardware works.
This guide also assumes good working knowledge of the C-Ware Software Toolset.
This guide covers the following topics:
•
•
•
•
Functional Description
Signal Descriptions
Electrical Specifications
Mechanical Specifications
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ABOUT THIS GUIDE
Data Sheet Classifications
Table 1 describes the Data Sheet classifications of Advance, Preliminary, and Production.
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Table 1 Data Sheet Classifications
Using PDF Documents
CLASSIFICATION
DESCRIPTION
Advance
Information
Used to advise customers of the proposed addition to the product line. This
document will typically contain some useful information including
interfacing with the user’s system and some specifications. The goal of this
document is to allow customers to begin designs but with expectation of
changes. Specification details may be changed later without notice.
Preliminary
Information
Describes pre-production or first production devices and is usually indicative
of production stage performance. Minor changes should be expected as
characteristic spreads become better controlled. Specification details may be
changed slightly without notice, but the customer can design their product
based on this data sheet.
Production Data
Defines the long-term specified production limits based on fully
characterized data. It includes a disclaimer to allow improvements in
specifications and modifications that do not affect form, fit or function in
original applications; if absolute maximum ratings are changed, they should
improve rather than downgrade.
Electronic documents are provided as PDF files. Open and view them using the Adobe®
Acrobat® Reader application, version 3.0 or later. If necessary, download the Acrobat
Reader from the Adobe Systems, Inc. web site:
http://www.adobe.com/prodindex/acrobat/readstep.html
PDF files offer several ways for moving among the document’s pages, as follows:
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•
To move quickly from section to section within the document, use the Acrobat
bookmarks that appear on the left side of the Acrobat Reader window. The bookmarks
provide an expandable outline view of the document’s contents. To display the
document’s Acrobat bookmarks, press the “Display both bookmarks and page” button
on the Acrobat Reader tool bar.
•
To move to the referenced page of an entry in the document’s Contents or Index, click
on the entry itself, each of which is hyperlinked.
•
To follow a cross-reference to a heading, figure, or table, click the blue text.
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•
To move to the beginning or end of the document, to move page by page within the
document, or to navigate among the pages you displayed by clicking on hyperlinks,
use the Acrobat Reader navigation buttons shown in this figure:
Beginning
of document
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15
End of
Previous or next hyperlink
Previous
Next page
Table 2 summarizes how to navigate within an electronic document.
Table 2 Navigating Within a PDF Document
TO NAVIGATE THIS WAY
CLICK THIS
Move from section to section within the
document.
A bookmark on the left side of the Acrobat Reader
window
Move to an entry in the Table of Contents.
The entry itself
Move to an entry in the Index.
The page number
Move to an entry in the List of Figures or List
of Tables.
The Figure or Table number
Follow a cross-reference (highlighted in blue The cross-reference text
text).
Move page by page.
The appropriate Acrobat Reader navigation
buttons
Move to the beginning or end of the
document.
The appropriate Acrobat Reader navigation
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Move backward or forward among a series of The appropriate Acrobat Reader navigation
hyperlinks you have selected.
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ABOUT THIS GUIDE
Guide Conventions
The following visual elements are used throughout this guide, where applicable:
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This icon and text designates information of special note.
Warning: This icon and text indicate a potentially dangerous procedure. Instructions
contained in the warnings must be followed.
Warning: This icon and text indicate a procedure where the reader must take
precautions regarding laser light.
This icon and text indicate the possibility of electrostatic discharge (ESD) in a procedure
that requires the reader to take the proper ESD precautions.
Revision History
Table 3 provides details about changes made for each revision of this guide.
Table 3 C-3e Network Processor Data Sheet Revision History
REVISION DATE
CST REVISION
CDS REVISION
CHANGES
November 8, 2002
2.2
2.0
• Added information about optional
capacitors, nominal values for
recommended operating
conditions, and updated package
measurement values.
• Pin number typographical
correction in Table 28, pin AF12
corrected to FIN4 (instead of
FIN14), and pin AE5 corrected to
PAD23 (instead of PAD27).
• Typographic corrections
throughout.
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Related Product Documentation
Related Product
Documentation
17
Table 4 lists the user and reference documentation for Motorola ‘s C-Port silicon
documentation set.
Table 4 C-Port Silicon Documentation Set
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DOCUMENT
SUBJECT
DOCUMENT NAME
PURPOSE
DOCUMENT ID
Describes the full architecture of the C-5 network
processor.
C5NPARCH-RM/D
C-5 Network Processor Data Sheet
Describes hardware design specifications for the
C-5 network processor.
C5NPDATA-DS/D
C-5e/C-3e Network Processor Architecture
Guide
Describes the full architecture of the C-5e and C-3e C5EC3EARCH-RM/D
network processors.
C-5e Network Processor Data Sheet
Describes hardware design specifications for the
C-5e network processor.
C5ENPA1-DS/D
C-3e Network Processor Data Sheet
Describes hardware design specifications for the
C-3e network processor.
C3ENPA1-DS/D
C-5 Network Processor to C-5e Network
Processor Comparison Delta Document
Describes key architectural features of the C-5e,
and highlights main differences between C-5 and
C-5e.
C5C5EDELTA-RM/D
M-5 Channel Adapter Architecture Guide
Describes the full architecture of the M-5 channel
adapter.
M5CAARCH-RM/D
M-5 Channel Adapter Data Sheet
Describes hardware design specifications for the
M-5 channel adapter.
M5CA0-DS/D
Q-5/Q-3 Traffic Management Coprocessor
Architecture Guide
Describes the full architecture of the Q-5 and Q-3
traffic management coprocessor.
Q5Q3ARCH-RM/D
Q-5 Traffic Management Coprocessor Data
Sheet
Describes hardware design specifications for the
Q-5 traffic management coprocessor.
Q5TMCA0-DS/D
Processor
C-5 Network Processor Architecture Guide
Information
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C3ENPA1-DS/D REV 03
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Rev 03
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FUNCTIONAL DESCRIPTION
Features
Key features of the C-3eTM Network Processor (NP) are its massive processing capabilities
and its high level of functional integration on one chip.
Massive Processing
Power
High Functional
Integration
•
•
•
Operating frequencies: up to 180MHz
•
•
•
•
•
Up to 9 million packets per second transmitted at wire speed
•
•
728 pin Ball Grid Array (BGA) package
3Gbps of bandwidth (for non-blocking throughput)
More than 3,000MIPS of computing power (for adding services throughout the
protocol stack)
17 programmable RISC Cores (for cell/packet forwarding)
32 programmable Serial Data Processors (for processing bit streams)
Up to 133 million table lookups per second
Three internal buses for 46Gbs of aggregate bandwidth
16 Channel Processors (8 CP’s with full functionality configurable for full I/O or
recirculation, and 8 CP’s with limited functionality configurable only for bit and byte
level recirculation) including:
– Embedded OC-3c, OC-12, OC-12c SONET framers
– Programmable MAC interface
– RISC Cores
– Programmable pin PHY interfaces
•
Embedded coprocessors for table lookup (classification), buffer management (payload
control), and queue management (QoS implementation)
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CHAPTER 1: FUNCTIONAL DESCRIPTION
•
•
•
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Block Diagram
Dedicated Fabric Processor and port
Embedded RISC Executive Processor
Integrated 32bit 33/66MHz PCI bus interface
The C-3eTM NP, has an architecture specifically designed for networking applications. The
following sections describe each component of the C-3e NP.
The main components of the C-3e NP are:
•
•
•
•
•
•
Channel Processors
Executive Processor
Fabric Processor
Buffer Management Unit
Table Lookup Unit
Queue Management Unit
The C-3e NP conforms with both SONET and SDH. Therefore, OC-3(STS-3/STM-1), and
OC-12 (STS-12/STM-4).
Figure 1 shows a block diagram of the C-3e NP, including its potential external interfaces.
For more information about the architecture of the C-3e NP, see the C-5e/C-3e Network
Processor Architecture Guide (part number C5EC3EARCH-RM/D).
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Block Diagram
21
Figure 1 C-3e Network Processor Block Diagram
Q-5 or Q-3
(optional)
SRAM
External
Host CPU
(optional)
SRAM
Fabric
External
PROM
(optional)
SDRAM
Control
Logic
(optional)
Table
Lookup
Unit
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Fabric
Processor
Queue
Mgmt
Unit
C-3e
NP
PCI
Serial
PROM
Executive Processor
Buffer
Mgmt
Unit
Buses (64Gbps Bandwidth)
CP-0 CP-1 CP-2 CP-3
Channel
Processors
CP-12 CP-13 CP-14 CP-15
Cluster
Cluster
Processor Boundary
PHY
16 Channel Processors:
8 (CP0 to CP7) full functionality
8 (CP8 to CP15) Internal-only
PHY
PHY
PHY
PHY Interface Examples:
10/100 Ethernet
Gigabit Ethernet - Aggregated
OC-3
OC-12
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CHAPTER 1: FUNCTIONAL DESCRIPTION
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Channel Processors
The C-3e NP contains eight programmable external Channel Processors (CPs) that receive,
process, and transmit network data, plus an additional eight internal CPs that process
data. Typically one CP is assigned to each port for medium bandwidth applications (Fast
Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel
aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports
can be assigned to a single CP, with the addition of an external multiplexor, for low
bandwidth applications, such as DS1 to DS3.
The C-3e NP’s architecture supports a variety of industry-standard serial and parallel
protocols and individual port data rates including:
•
•
•
•
•
•
10/100Mb Ethernet (RMII)
1Gb Ethernet (GMII and TBI)
OC-3c
OC-12
100Mbit FibreChannel
DS1/DS3, supported through the use of external framers/multiplexors
The C-3e NP’s programmability can also support a variety of special interfaces, such as
various xDSL encapsulations and proprietary protocols.
Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet
processing and a set of microprogrammable, special-purpose processors, called Serial
Data Processors (SDPs), that provide features such as Ethernet MAC and SONET/SDH
framing, multichannel HDLC, and ATM cell delineation. This means you usually only need
to include PHYs to complete the system.
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Executive Processor
Executive Processor
23
The Executive Processor (XP) serves as a centralized computing resource for the C-3e NP
and manages the system interfaces.
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The XP performs conventional supervisory tasks in the C-3e NP, including:
•
•
•
•
•
System Interfaces
Reset and initialization of the C-3e NP
Program loading and control of CPs
Centralized exception handling
Management of a host interface through the PCI
Management of system interfaces (PCI, Serial Bus, PROM)
The system interfaces to the XP are:
•
PCI — Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level
shared resources. The PCI has both initiator and target capabilities. The PCI interface is
typically connected to a host processor.
•
Serial Bus Interface — Provides a general purpose bi-directional, two-wire serial bus
and I/O port that allows the C-3e NP to control external logic with either of two
standard protocols:
– The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of
addressing and supports transfers up to 25MHz.
– The low-speed protocol: uses an 8bit data format followed by an acknowledge bit
and supports transfers up to 400kbps.
Software is used to select which protocol to use, by setting the appropriate bits in the
Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is
driven by the C-3e NP to indicate which protocol is being used (SPLD=0 indicates
MDIO protocol; SPLD=1 indicates low-speed protocol).
Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up
resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because
of the pull-up resistor. The output stages of the devices connected to the bus must
have either an open-drain or open-collector in order to perform the wired-AND
function required for its arbitration mechanism.
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CHAPTER 1: FUNCTIONAL DESCRIPTION
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•
Fabric Processor
PROM Interface — Allows the XP to boot from nonvolatile, flash memory. The PROM
interface is a low-speed, serial I/O port that runs at 1/2 to 1/16 the core clock rate. The
maximum PROM size addressable is 4MBytes, and must use a “by 16” part. External
board logic is required to perform serial-to-parallel conversion for PROM address
outputs and parallel-to-serial conversion for PROM data inputs.
The Fabric Processor (FP) acts as a high-speed network interface port with advanced
functionality. It allows the C-3e NP to interface to an application-specific switching
solution internal to your design. The FP port supports the bidirectional transfer of
segments from the C-3e NP to a hardware interface that provides connectivity to other
network processors or other similar line processing hardware. There are numerous
parameters that can be configured within the FP to allow the interface to be adapted to
different fabric protocols. The FP can be configured to conform to three (3) different fabric
interfaces that include: UTOPIA-1, -2, -3.
The FP can be configured to run at any frequency up to 125MHz, with the receive and
transmit data buses up to 16 bits wide. This allows a wide range of supported bandwidths
to and from the switching fabric, all the way up to 2000 Mbps full duplex bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-3e NP to external pipeline
architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned
and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It
is also used as second level storage in the XP memory hierarchy.
The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two
internal control bits, and nine SECDED (single error correction-double error detection) ECC
(error correction code) bits. The interface is compliant with the PC100 standard and
operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh
period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the
C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D) for more
details).
The C-3e NP non-configurable interface transfers four beats of data for each read and
write using a sequential burst type. In addition, the C-3e NP uses an auto-refresh mode for
the RAM’s.
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Table Lookup Unit
25
Freescale Semiconductor, Inc...
Some of these parameters are programmed into the SDRAMs’ mode register and can be
applied only once per power cycle. The ECC functionality can be enabled or disabled via
configuration register writes.
If needed, the interface can narrowed to 128bits by disabling ECC and providing board
pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the
board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU
supports SDRAM devices that use 12 address lines. Internal address calculation paths limit
the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
Table Lookup Unit
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used
for statistics accumulation and retrieval and as general data storage. The TLU
simultaneously supports multiple application-defined tables and multiple search
strategies, such as those needed for routing, circuit switching, and QoS lookup tasks.
The C-3e NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules
(at frequencies up to 125MHz) for storage of its tables. These modules allow
implementation of tables with 225 x 64bit entries using 8Mbit SRAM technology. The
maximum amount of memory supported by the TLU is 128MBytes in four banks, when
SRAM technology supports 4M x 18pins parts.
Table 5 TLU SRAM Configurations
SRAM TECHNOLOGY
MIN TABLE SIZE
(ONE BANK)
MAXIMUM TABLE SIZE
(FOUR BANKS)
1Mbit (32k x 32pins)
256kBytes
1MBytes
2Mbit (64k x 32pins)
512kBytes
2MBytes
4Mbit (256k x 18pins)
2MBytes
8MBytes
8Mbit (512k x 18pins)
4MBytes
16MBytes
16Mbit (1M x 18pins)
8MBytes
32MBytes
32Mbit (2M x 18pins)
16MBytes
64MBytes
64Mbit (4M x 18pins)
32MBytes
128MBytes
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CHAPTER 1: FUNCTIONAL DESCRIPTION
Queue Management Unit
The Queue Management Unit (QMU) autonomously manages a number of
application-defined descriptor queues. It handles inter-CP and inter-C-3e NP descriptor
flows by providing switching and buffering. It also performs descriptor replication for
multicast applications. A number of up to 128 queues can be assigned to each CPRC for
QoS-based services.
Freescale Semiconductor, Inc...
The QMU provides a queuing engine internal to the chip and uses external SRAM to store
the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and
16, 384 descriptor buffers. A descriptor buffer holds an application-defined “descriptor”,
which is a structure that defines the payload buffer handle and other attributes of the
forwarded cell or packet.
The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single
bank of up to 128k, 32bit words. This interface runs at up to 150MHz frequency.
The C-3e provides two modes for managing queues. They consist of:
•
•
Internal Mode (using the internal QMU only)
External Mode (using the internal QMU and the external Q-5 Traffic Management
Coprocessor, or using the internal QMU and the external Q-3 Traffic Management
Coprocessor).
See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D),
as well as, the Q-5/Q-3 Traffic Management Coprocessor Architecture Guide (part number
Q5Q3ARCH-RM/D) for more details.
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Chapter 2
Rev 03
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SIGNAL DESCRIPTIONS
Signal Summary
There are nine (9) functional groupings of signals in the C-3e Network Processor:
•
•
•
Clock — 7 pins
Channel Processors (CP0 - CP7) — 8x7 = 56 pins
Executive Processor (XP) — 57 pins
– PCI Interface — 50 pins
– PROM Interface — 4 pins
– Serial Bus Interface — 2 pins
– General System Interface — 1 pin
•
•
•
•
•
•
Fabric Processor (FP) — 42 pins
Buffer Management Unit (BMU) — 160 pins
Table Lookup Unit (TLU) — 99 pins
Queue Management Unit (QMU) — 59 pins
Power — 234 pins
Test — 14 pins
Two (2) of the sections (CPs and FP) are configurable, depending on the type of device
being implemented.
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28
CHAPTER 2: SIGNAL DESCRIPTIONS
Pinout Diagram
The C-3e NP contains 728 pins. These pin numbers are referenced throughout the
remaining chapter. Figure 2 shows the pin locations from the top view. In contrast,
Figure 3 shows the pin locations from the bottom view.
Freescale Semiconductor, Inc...
Figure 2 Pin Locations (Top View)
27
26
25
24
23
22
21
20
19
16
15
AG
CP0_0
CP0_6
CP1_3
CP2_2
CP2_6
CP3_5
CP4_2
CP5_1
CP6_0
CP6_5 FOUT0
FOUT2
FOUT8
11
10
9
8
7
6
FIN9
FIN15
FRXCLK
PAD9
PAD15
PAD19
AF
CP0_1
VDD33
CP1_4
CP2_3
CP3_0
GND
CP4_3
CP5_2
CP6_1 VDD33 FOUT1
FOUT3
FOUT9
FTXCTL6 FIN4 FIN10
VDD33
PAD3
PAD8
PAD14
AE
CP0_2
CP1_0
CP1_5
VDD33
CP3_1
CP3_6
CP4_4
CP5_3
CP6_2
CP6_6 CP7_3
FOUT4 FOUT10 FOUT15 FTXCLK FIN5 FIN11 FRXCTL0
PAD2
PAD7
AD
CP0_3
GND
CP1_6
CP2_4
CP3_2
VDD33
CP4_5
CP5_4
GND
CP7_0 CP7_4
FOUT5 FOUT11
AC
CP0_4
CP1_1
CP2_0
GND
CP3_3
CP4_0
CP4_6
CP5_5
CP6_3
CP7_1 CP7_5
AB
CP0_5
CP1_2
CP2_1
CP2_5
CP3_4
CP4_1
CP5_0
CP5_6
CP6_4
CP7_2 CP7_6
AA
MD0
VDD33
MD1
MD2
MD3
GND
MD4
MD5
VDD33
GND
VDD33
GND
VDD33
GND
VDD33
17
Y
MD6
MD7
MD8
GND
MD9
W
MD13
MD14
MD15
VDD33
V
MD20
GND
MD21
U
MD26
MD27
T
MD34
R
14
13
12
MD10
MD11
MD12
GND
VDD
GND
VDD
GND
VDD
MD16
MD17
MD18
MD19
VDD33
GND
VDD
GND
VDD
MD22
MD23
VDD33
MD24
MD25
GND
VDD
GND
VDD
MD28
MD29
MD30
MD31
MD32
MD33
VDD33
GND
VDD
MD35
MD36
GND
MD37
MD38
MD39
MD40
GND
VDD
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
VDD33
P
MD49
VDD33
MD50
MD51
MD52
GND
MD53
MD54
N
MD55
MD56
MD57
MD58
MD59
MD60
MD61
M
MD63
MD64
MD65
VDD33
MD66
MD67
L
MD70
MD71
MD72
MD73
MD74
K
MD78
GND
MD79
MD80
J
MD84
MD85
MD86
H
MD91
MD92
G
MD98
F
FOUT14 FTXCTL2 FIN3
GND
VDD33
5
4
3
2
1
PAD25 PAD29 PCBEX1 PDEVSELX PPAR
AG
GND
PAD24 PAD28 PCBEX2
VDD33
PCLK
AF
PAD13
PAD18
PAD23 VDD33 PCBEX3
PSTOPX
PRSTX
AE
GND
PREQX
AD
PIRDYX
PINTA
AC
FIN0
FIN6 FIN12 FRXCTL1
GND
PAD6
PAD12
VDD33
PAD22 PAD27 PSERRX
FOUT6 FOUT12 FTXCTL0
FIN1
FIN7 FIN13 FRXCTL2
PAD1
PAD5
PAD11
PAD17
PAD21
FOUT7 FOUT13 FTXCTL1
FIN2
FIN8 FIN14 FRXCTL6
PAD0
PAD4
PAD10
PAD16
PAD20 PAD26
PAD31
GND
PIDSEL
SIDA
PAD30
VDDT
SICL
AA
PPERRX
PCBEX0 PTRDYX
AB
GND
VDD33
GND
VDD
GND
VDD
GND
SPCK
SPLD
SPDI
SPDO
GND
XPUHOT
TA21
TA20
Y
GND
VDD
GND
VDD
GND
VDDT
TA19
TA18
TA17
TA16
VDDT
TA15
TA14
TA13
W
GND
VDD
GND
VDD
GND
VDD
GND
TA12
TA11
VDDT
TA10
TA9
TA8
GND
TA7
V
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
TA6
TA5
TA4
TA3
TA2
TA1
TA0
TCE3X
U
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
TCE2X
TCE1X
TCE0X
TPAR3
GND
TPAR2
TPAR1
TPAR0
T
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
TWE3X
TWE2X
TWE1X TWE0X TCLKI
TD63
TD62
TD61
R
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
TD60
TD59
GND
TD58
TD57
TD56
VDDT
TD55
P
MD62
VDD33
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
TD54
TD53
TD52
TD51
TD50
TD49
TD48
TD47
N
MD68
MD69
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
TD46
TD45
TD44
TD43
VDDT
TD42
TD41
TD40
M
MD75
MD76
MD77
VDD33
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
TD39
TD38
TD37
TD36
TD35
TD34
TD33
TD32
L
MD81
VDD33
MD82
MD83
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
TD31
TD30
VDDT
TD29
TD28
TD27
GND
TD26
K
GND
MD87
MD88
MD89
MD90
VDD33
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
TD25
TD24
TD23
TD22
GND
TD21
TD20
TD19
J
MD93
VDD33
MD94
MD95
MD96
MD97
GND
VDD33
GND
VDD
GND
VDD33
GND
VDD
GND
VDD
GND
TD18
TD17
TD16
TD15
VDDT
TD14
TD13
TD12
H
VDD33
MD99
MD100
MD101
GND
MD102
MD103
VDD33
GND
VDD33
GND
VDD33
GND
VDD33
GND VDDT
GND
VDDT
TD11
TD10
GND
TD9
TD8
TD7
VDDT
TD6
G
MD104
MD105
MD106
MD107
MD108
MD109
MD110
MD111
MBA0
MA3
MA8
CCLK0
SCLKX
SCLK
QA14
QA9
QA3
QARDY
QACLKO
TD5
TD4
TD3
TD2
TD1
TD0
QD5
QD0
F
E
MD112
MD113
MD114
GND
MD115
MD116
MD117
MD118
MBA1
MA4
MA9
CCLK1
CCLK2
CCLK3
QA15
QA10
QA4
QWEX
QACLKI
QD30
QD25
QD22
QD17
GND
QD9
QD6
QD1
E
D
MD119
GND
MD120
MD121
MD122
VDD33
MD123
MD124
GND
MA5
MA10
CPREF
JSE
VDD33
QA16
QA11
QA5
QA0
GND
QD31
QD26
VDDT
QD18
QD14
QD10
GND
QD2
D
C
MD125
MD126
MD127
VDD33
MD128
MD129 MDECC8 MDECC7
MA0
MA6
MA11
JTDI
JSO5
JTDO
JSO0
QA12
QA6
QA1
QDPL
QDQPAR
QD27
QD23
QD19
VDDT
QD11
QD7
QD3
C
B
MDECC6
MDECC2 MDECC1
MA1
VDD33
JTCK
GND
JHIGHZ
JSO3
JSO1
GND
QA7
VDDT
QDPH
QBCLKO
QD28
GND
QD20
QD15
QD12
VDDT
QD4
B
A
MDECC0 MDCLK
MDQML
MDQM
MA2
MA7
JTMS
JSO4
JSO2
QA13
QA8
QA2
QNQRDY
QBCLKI
QD29
QD24
QD21
QD16
QD13
QD8
21
20
19
18
17
14
13
12
11
10
9
8
7
6
5
4
3
2
VDD33 MDECC5 MDECC4 MDECC3
26
MCSX
MCASX
25
24
GND
MRASX MWEX
23
22
JTRSTX JCLKBYP
16
15
PGNTX PFRAMEX
GND
GND VDD33
27
C3ENPA1-DS/D REV 03
18
A
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Pinout Diagram
Figure 3 Pin Locations (Bottom View)
1
7
8
9
10
11
24
25
26
27
AG
PPAR PDEVSELX PCBEX1 PAD29 PAD25 PAD19
PAD15
PAD9
FRXCLK
FIN15
FIN9
FIN3 FTXCTL2 FOUT14 FOUT8 FOUT2 FOUT0 CP6_5 CP6_0 CP5_1
CP4_2 CP3_5 CP2_6
CP2_2
CP1_3
CP0_6
CP0_0
AG
AF
PCLK
PAD14
PAD8
PAD3
VDD33
FIN10
FIN4 FTXCTL6
CP4_3
CP3_0
CP2_3
CP1_4
VDD33
CP0_1
AF
VDD33
3
4
5
PCBEX2 PAD28 PAD24
6
GND
12
13
14
GND
15
16
17
18
19
20
FOUT9 FOUT3 FOUT1 VDD33 CP6_1 CP5_2
21
22
GND
23
AE
PRSTX PSTOPX
PCBEX3 VDD33 PAD23 PAD18
PAD13
PAD7
PAD2
FRXCTL0 FIN11
FIN5 FTXCLK FOUT15 FOUT10 FOUT4 CP7_3 CP6_6 CP6_2 CP5_3
CP4_4 CP3_6 CP3_1
VDD33
CP1_5
CP1_0
CP0_2
AE
AD
PREQX
GND
PSERRX PAD27 PAD22 VDD33
PAD12
PAD6
GND
FRXCTL1 FIN12
FIN6
FIN0
CP5_4
CP4_5 VDD33 CP3_2
CP2_4
CP1_6
GND
CP0_3
AD
AC
PINTA
PIRDYX
PPERRX
PAD21 PAD17
PAD11
PAD5
PAD1
FRXCTL2 FIN13
FIN7
FIN1
FTXCTL0 FOUT12 FOUT6 CP7_5 CP7_1 CP6_3 CP5_5
CP4_6 CP4_0 CP3_3
GND
CP2_0
CP1_1
CP0_4
AC
PAD26 PAD20 PAD16
PAD10
PAD4
PAD0
FRXCTL6 FIN14
FIN8
FIN2
FTXCTL1 FOUT13 FOUT7 CP7_6 CP7_2 CP6_4 CP5_6
CP5_0 CP4_1 CP3_4
CP2_5
CP2_1
CP1_2
CP0_5
AB
AB
Freescale Semiconductor, Inc...
2
PTRDYX PCBEX0
PAD31
GND
VDD33 FOUT11 FOUT5 CP7_4 CP7_0
GND
VDD33
GND
VDD33
GND
VDD33
GND
VDD33
MD5
MD4
GND
MD3
MD2
MD1
VDD33
MD0
AA
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MD12
MD11
MD10
MD9
GND
MD8
MD7
MD6
Y
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
MD19
MD18
MD17
MD16
VDD33
MD15
MD14
MD13
W
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MD25
MD24
VDD33
MD23
MD22
MD21
GND
MD20
V
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
U
TCE2X
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MD40
MD39
MD38
MD37
GND
MD36
MD35
MD34
T
TWE3X
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
R
TD59
TD60
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MD54
MD53
GND
MD52
MD51
MD50
VDD33
MD49
P
TD52
TD53
TD54
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
N
TD43
TD44
TD45
TD46
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MD69
MD68
MD67
MD66
VDD33
MD65
MD64
MD63
M
TD35
TD36
TD37
TD38
TD39
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
MD77
MD76
MD75
MD74
MD73
MD72
MD71
MD70
L
TD27
TD28
TD29
VDDT
TD30
TD31
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
MD83
MD82
VDD33
MD81
MD80
MD79
GND
MD78
K
TD20
TD21
GND
TD22
TD23
TD24
TD25
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
MD90
MD89
MD88
MD87
GND
MD86
MD85
MD84
J
TD12
TD13
TD14
VDDT
TD15
TD16
TD17
TD18
GND
VDD
GND
VDD
GND
VDD33
GND
VDD
GND
VDD33
GND
MD97
MD96
MD95
MD94
VDD33
MD93
MD92
MD91
H
G
TD6
VDDT
TD7
TD8
TD9
GND
TD10
TD11
VDDT
GND
VDDT
GND
VDD33
GND
VDD33
GND
VDD33
GND
VDD33 MD103
MD102
GND
MD101
MD100
MD99
VDD33
MD98
G
F
QD0
QD5
TD0
TD1
TD2
TD3
TD4
TD5
QACLKO QARDY
QA3
QA9
QA14
SCLK
SCLKX CCLK0
MA8
MA3
MBA0
MD111
MD110 MD109 MD108
MD107
MD106 MD105
MD104
F
E
QD1
QD6
QD9
GND
QD17
QD22
QD25
QD30
QACLKI
QWEX
QA4
QA10
QA15
CCLK3
CCLK2 CCLK1
MA9
MA4
MBA1
MD118
MD117 MD116 MD115
GND
MD114 MD113
MD112
E
D
QD2
GND
QD10
QD14
QD18
VDDT
QD26
QD31
GND
QA0
QA5
QA11
QA16
VDD33
JSE
CPREF MA10
MA5
GND
MD124
MD123 VDD33 MD122
MD121
MD120
MD119
D
C
QD3
QD7
QD11
VDDT
QD19
QD23
QD27
QDQPAR QDPL
QA1
QA6
QA12
JSO0
JTDO
JSO5
JTDI
MA11
MA6
MA0 MDECC7 MDECC8 MD129 MD128
VDD33
MD127 MD126
MD125
C
B
QD4
VDDT
QD12
QD15
QD20
GND
QD28
QBCLKO QDPH
VDDT
QA7
GND
JSO1
JSO3
JHIGHZ
GND
JTCK
VDD33
QD8
QD13
QD16
QD21
QD24
QD29
QBCLKI QNQRDY
QA2
QA8
QA13
JSO2
JSO4 JCLKBYPJTRSTX JTMS
2
3
4
5
6
7
10
11
12
13
AA
SICL
VDDT
PAD30
SIDA
PIDSEL
Y
TA20
TA21
XPUHOT
GND
SPDO
SPDI
SPLD
W
TA13
TA14
TA15
VDDT
TA16
TA17
V
TA7
GND
TA8
TA9
TA10
U
TCE3X
TA0
TA1
TA2
TA3
T
TPAR0
TPAR1
TPAR2
GND
R
TD61
TD62
P
TD55
N
VDD33
GND
SPCK
GND
VDD
GND
TA18
TA19
VDDT
GND
VDDT
TA11
TA12
GND
TA4
TA5
TA6
TPAR3 TCE0X TCE1X
TD63
TCLKI TWE0X TWE1X TWE2X
VDDT
TD56
TD57
TD58
GND
TD47
TD48
TD49
TD50
TD51
M
TD40
TD41
TD42
VDDT
L
TD32
TD33
TD34
K
TD26
GND
J
TD19
H
A
1
GND PFRAMEX PGNTX
8
9
VDD33 GND
14
15
16
17
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GND
MA1 MDECC1 MDECC2 GND MDECC3 MDECC4 MDECC5 VDD33 MDECC6
B
MA7
MA2
MDQM
A
18
19
20
MDQML MWEX MRASX MCASX
21
22
23
24
MCSX MDCLK MDECC0
25
26
27
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30
CHAPTER 2: SIGNAL DESCRIPTIONS
Freescale Semiconductor, Inc...
Pin Descriptions Grouped
by Function
The C-3e NP pins are categorized in groups, reflecting interfaces to the chip:
•
•
•
•
•
•
•
•
•
•
Clock Signals
CP Interface Signals
Executive Processor System Interface Signals
Fabric Processor Interface Signals
BMU SDRAM Interface Signals
TLU SRAM Interface Signals
QMU SRAM (Internal Mode) Interface Signals
QMU to Q-5/Q-3 (External Mode) Interface Signals
Power Supply Signals
Test Signals
Pins conform to Joint Electronic Devices Engineering Council (JEDEC) standards.
LVTTL and LVPECL
Specifications
C-3e NP pins are the following types:
•
Low Voltage TTL-Compatible (LVTTL). The C-3e NP’s LVTTL pins conform to the JEDEC
JESD8-B specification.
•
Low Voltage Positive Emitter Coupled Logic (LVPECL).
All of the signals in the following tables in this chapter denote whether the individual
signal is an Input (I), Output (O), both Input and Output (I/O), or power (P). In addition, a
PU, PD, and nc are used. The PU indicates that an internal resistor will pullup the pad if
left unconnected. PD indicates an internal pulldown resistor. NC means the pad is to be
left unconnected.
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Pin Descriptions Grouped by Function
Clock Signals
31
Table 6 describes the C-3e NP clock signals.
Freescale Semiconductor, Inc...
Table 6 Clock and Reference Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
SCLK*
SCLKX*
F14
F15
1
1
LVPECL
LVPECL
I
I
Core Clock Rate (Differential)
CCLK0
F16
1
LVTTL
IPD
Programmable CP Clock Input
CCLK1
E16
1
LVTTL
IPD
Programmable CP Clock Input
CCLK2
E15
1
LVTTL
IPD
Programmable CP Clock Input
CCLK3
E14
1
LVTTL
IPD
Programmable CP Clock Input
CPREF†
D16
1
LVPECL
IPD
Reference
TOTAL
*
†
CP Interface Signals
7
SCLK and SCLKX must not be AC-coupled.
If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must
be wired to an external reference, as specified in Table 34 on page 73. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected.
The C-3e NP’s 8 external CPs support various network physical interfaces, providing a
serial interface to the PHY layer. Interfaces are configured via bits in the C-3e NP register
set. Many interfaces are possible by programming the configuration registers. CPs can be
used individually or in a cluster (four CPs) to implement the various interfaces.
Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven
physical I/O pins associated with each CP. All pins are capable of receiving data, with some
configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can
be configured as differential pairs for LVPECL compatibility.
In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally
configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four
CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for
receive and four for transmit) or four CPs that share the transmit and receive functions for
non-wire speed applications.
During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial
Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the
SDPs, with each getting access to the necessary I/O pins.
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CHAPTER 2: SIGNAL DESCRIPTIONS
The signals for the following CP physical interfaces are included in this section:
Freescale Semiconductor, Inc...
•
•
•
•
•
•
C3ENPA1-DS/D REV 03
DS1/T1 Framer Interface Configuration
10/100 Ethernet (RMII) Configuration
Gigabit Ethernet (GMII) Configuration
Gigabit Ethernet and Fibre Channel TBI Configuration
SONET OC-3 Transceiver Interface Configuration
SONET OC-12 Transceiver Interface Configuration
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Pin Descriptions Grouped by Function
33
Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters)
Freescale Semiconductor, Inc...
CP CLUSTER 1
CP CLUSTER 2
SIGNAL
PIN #
SIGNAL
PIN #
CP0_0
AG27
CP4_0
AC22
CP0_1
AF27
CP4_1
AB22
CP0_2
AE27
CP4_2
AG21
CP0_3
AD27
CP4_3
AF21
CP0_4
AC27
CP4_4
AE21
CP0_5
AB27
CP4_5
AD21
CP0_6
AG26
CP4_6
AC21
CP1_0
AE26
CP5_0
AB21
CP1_1
AC26
CP5_1
AG20
CP1_2
AB26
CP5_2
AF20
CP1_3
AG25
CP5_3
AE20
CP1_4
AF25
CP5_4
AD20
CP1_5
AE25
CP5_5
AC20
CP1_6
AD25
CP5_6
AB20
CP2_0
AC25
CP6_0
AG19
CP2_1
AB25
CP6_1
AF19
CP2_2
AG24
CP6_2
AE19
CP2_3
AF24
CP6_3
AC19
CP2_4
AD24
CP6_4
AB19
CP2_5
AB24
CP6_5
AG18
CP2_6
AG23
CP6_6
AE18
CP3_0
AF23
CP7_0
AD18
CP3_1
AE23
CP7_1
AC18
CP3_2
AD23
CP7_2
AB18
CP3_3
AC23
CP7_3
AE17
CP3_4
AB23
CP7_4
AD17
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)
Freescale Semiconductor, Inc...
CP CLUSTER 1
CP CLUSTER 2
SIGNAL
PIN #
SIGNAL
PIN #
CP3_5
AG22
CP7_5
AC17
CP3_6
AE22
CP7_6
AB17
DS1/T1 Framer Interface Configuration
Table 8 describes the serial framer interface signals. For each CP (0-7), you can implement
one serial Framer interface.
Table 8 DS1/T1 Framer Interface Signals
SIGNAL NAME*
PIN #†
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
CPn_1
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7
Table 7
Table 7
Table 7
Table 7
Table 7
Table 7
1
1
1
1
1
1
1
7
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
OPD
IPU
OPD
OPU
IPD
IPU
ncPU
TCLK
RCLK
TData
TFrame
RData
RFrame
nc
Transmit Clock (1.544MHz)
Receive Clock (1.544MHz)
Transmit Data
Transmit Frame Synchronization
Receive Data
Receive Frame Synchronization
nc
TOTAL PINS
*
†
n can be from 0 to 7. See Table 7.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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Pin Descriptions Grouped by Function
35
10/100 Ethernet (RMII) Configuration
Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Freescale Semiconductor, Inc...
Table 9 10/100 Ethernet Signals
SIGNAL NAME*
PIN #
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
CPn_1
Table 7
Table 7
1
1
LVTTL
LVTTL
OPD
IPU
REF_CLK
CRS_DV
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7
Table 7
Table 7
Table 7
Table 7
1
1
1
1
1
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
OPD
OPU
IPD
IPU
OPU
TXD(0)
TXD(1)
RXD(0)
RXD(1)
TX_EN
Transmit and Receive Clock (50MHz)
Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
Transmit Data 0 (first on wire)
Transmit Data 1 (second on wire)
Receive Data 0 (first on wire)
Receive Data 1 (second on wire)
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
TOTAL PINS
*
7
n can be from 0 to 7. See Table 7.
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CHAPTER 2: SIGNAL DESCRIPTIONS
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Gigabit Ethernet (GMII) Configuration
Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways:
•
Use one CP cluster when density is more important than wire-speed performance
because you can then implement up to four Gigabit Ethernet ports per C-3e NP.
•
Use two CP clusters for wire-speed performance and additional processing power. You
can implement up to two Gigabit Ethernet ports per C-3e NP.
Table 10 lists the possible CP cluster combinations you can use and Figure 4 shows receive
and transmit pin configurations by cluster. Table 11 lists the signals and pinouts for
Gigabit Ethernet (GMII).
Table 10 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel
*
CLUSTER
SINGLE CLUSTER MODE (TBI OR GMII)
TWO CLUSTER MODE (GMII)*
0
Port 1 Tx and Rx
Port 1 Tx
1
Port 2 Tx and Rx
Port 1 Rx
The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive
or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3
transmits.
Figure 4 GMII/TBI Transmit and Receive Pin Configurations
Two Cluster Mode
Pin Configuration
Single Cluster Mode
Pin Configuration
Tx
Cluster
0
Rx
Tx
Cluster
1
Rx
} Port 1
} Port 2
Tx
Cluster
0
nc
Tx
Cluster
1
nc
Rx
}
Port 1
Cluster
2
Cluster
2
NOTE: Cluster 2 & 3 are Internal Loopback Only.
Cluster
3
Rx
NOTE: Cluster 2 & 3 are Internal Loopback Only.
Cluster
3
nc = not connected
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Pin Descriptions Grouped by Function
37
Freescale Semiconductor, Inc...
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME*
PIN #†
CPn_0
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
Table 7 1
LVTTL
OPD
T_CLK
GMII Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
CPn_1
Table 7 1
LVTTL
IPU
TCLKI
MII transmit clock. Transmit data aligned to this clock input from
phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
CPn_2
Table 7 1
LVTTL
OPD
TXD(0)
Transmit Data (byte-wide data, least significant bit)
CPn_3
Table 7 1
LVTTL
OPU
TXD(1)
Transmit Data
CPn_4
Table 7 1
LVTTL
OPD
TXD(2)
Transmit Data
CPn_5
Table 7 1
LVTTL
OPU
TXD(3)
Transmit Data
CPn_6
Table 7 1
LVTTL
OPU
TX_EN
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
CPn+1_0
Table 7 1
nc
ncPD nc
nc
CPn+1_1
Table 7 1
LVTTL
IPU
COL
Collision. Asserted when both RX_DV and TX_EN are valid during
half duplex operation.
CPn+1_2
Table 7 1
LVTTL
OPD
TXD(4)
Transmit Data
CPn+1_3
Table 7 1
LVTTL
OPU
TXD(5)
Transmit Data
CPn+1_4
Table 7 1
LVTTL
OPD
TXD(6)
Transmit Data
CPn+1_5
Table 7 1
LVTTL
OPU
TXD(7)
Transmit Data (byte-wide receive data, most significant bit)
CPn+1_6
Table 7 1
LVTTL
OPU
TX_ER
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes
transmission of the designated “bad code” in lieu of the normal
encoded data on the twisted pair data.
CPn+2_0
Table 7 1
nc
ncPD nc
nc
CPn+2_1
Table 7 1
LVTTL
IPU
RCLK
Receive Clock (125MHz)
CPn+2_2
Table 7 1
LVTTL
IPD
RXD(0)
Receive Data (byte-wide receive data, least significant bit)
CPn+2_3
Table 7 1
LVTTL
IPU
RXD(1)
Receive Data
CPn+2_4
Table 7 1
LVTTL
IPD
RXD(2)
Receive Data
CPn+2_5
Table 7 1
LVTTL
IPU
RXD(3)
Receive Data
CPn+2_6
Table 7 1
LVTTL
IPU
RX_DV
Receive Data Valid. Indicates that there is a receive frame in progress
and that the data present on the RXD signals is valid.
CPn+3_0
Table 7 1
nc
ncPD nc
nc
CPn+3_1
Table 7 1
LVTTL
IPU
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a
non-idle condition is detected on the receive data stream. CRS is
deasserted when an end of frame or idle condition is detected.
CRS
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CHAPTER 2: SIGNAL DESCRIPTIONS
Freescale Semiconductor, Inc...
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
SIGNAL NAME*
PIN #†
CPn+3_2
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
Table 7 1
LVTTL
IPD
RXD(4)
Receive Data
CPn+3_3
Table 7 1
LVTTL
IPU
RXD(5)
Receive Data
CPn+3_4
Table 7 1
LVTTL
IPD
RXD(6)
Receive Data
CPn+3_5
Table 7 1
LVTTL
IPU
RXD(7)
Receive Data (most significant bit)
CPn+3_6
Table 7 1
LVTTL
IPU
RX_ER
Receive Error Detected. Indicates that there has been an error
received in the receive frame.
28
TOTAL PINS
*
†
TOTAL
n can be 0, or 4.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
Gigabit Ethernet and Fibre Channel TBI Configuration
1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same
way as Gigabit Ethernet (GMII). Table 10 shows the possible CP pin combinations you can
use and Figure 4 shows receive and transmit pin configurations by cluster. Table 12 shows
the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.
The unused pins for the two cluster configurations should be wired down using a resistor.
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example
SIGNAL NAME*
PIN #†
CPn_0
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
Table 7 1
LVTTL
OPD
TCLK
Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
CPn_1
Table 7 1
nc
ncPU
nc
nc
CPn_2
Table 7 1
LVTTL
OPD
TXD(9)
Transmit Data (ten bits wide, last on wire)
CPn_3
Table 7 1
LVTTL
OPU
TXD(8)
Transmit Data
CPn_4
Table 7 1
LVTTL
OPD
TXD(7)
Transmit Data
CPn_5
Table 7 1
LVTTL
OPU
TXD(6)
Transmit Data
CPn_6
Table 7 1
LVTTL
OPU
TXD(1)
Transmit Data
CPn+1_0
Table 7 1
nc
ncPD
nc
nc
CPn+1_1
Table 7 1
nc
ncPU
nc
nc
CPn+1_2
Table 7 1
LVTTL
OPD
TXD(5)
Transmit Data
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TOTAL
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Pin Descriptions Grouped by Function
39
Freescale Semiconductor, Inc...
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME*
PIN #†
CPn+1_3
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
Table 7 1
LVTTL
OPU
TXD(4)
Transmit Data
CPn+1_4
Table 7 1
LVTTL
OPD
TXD(3)
Transmit Data
CPn+1_5
Table 7 1
LVTTL
OPU
TXD(2)
Transmit Data
CPn+1_6
Table 7 1
LVTTL
OPU
TXD(0)
Transmit Data (ten bits wide, first on wire)
CPn+2_0
Table 7 1
nc
ncPD
nc
nc
CPn+2_1
Table 7 1
LVTTL
IPU
RCLK
Receive Clock (62.5 MHz)
CPn+2_2
Table 7 1
LVTTL
IPD
RXD(9)
Receive Data (ten bits wide, last on wire)
CPn+2_3
Table 7 1
LVTTL
IPU
RXD(8)
Receive Data
CPn+2_4
Table 7 1
LVTTL
IPD
RXD(7)
Receive Data
CPn+2_5
Table 7 1
LVTTL
IPU
RXD(6)
Receive Data
CPn+2_6
Table 7 1
LVTTL
IPU
RXD(1)
Receive Data
CPn+3_0
Table 7 1
nc
ncPD
nc
nc
CPn+3_1
Table 7 1
LVTTL
IPU
RCLKN
Receive Clock Inverted
CPn+3_2
Table 7 1
LVTTL
IPD
RXD(5)
Receive Data
CPn+3_3
Table 7 1
LVTTL
IPU
RXD(4)
Receive Data
CPn+3_4
Table 7 1
LVTTL
IPD
RXD(3)
Receive Data
CPn+3_5
Table 7 1
LVTTL
IPU
RXD(2)
Receive Data
CPn+3_6
Table 7 1
LVTTL
IPU
RXD(0)
Receive Data (ten bits wide, first on wire)
TOTAL PINS
*
†
TOTAL
28
n can be 0, or 4.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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CHAPTER 2: SIGNAL DESCRIPTIONS
SONET OC-3 Transceiver Interface Configuration
Table 13 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each
CP (0-15), you can implement a single OC-3 interface.
Freescale Semiconductor, Inc...
Table 13 OC-3 Signals
SIGNAL NAME*
PIN #†
TOTAL
TYPE
CPn_0
Table 7
1
CPn_1
Table 7
CPn_2
LABEL
SIGNAL DESCRIPTION
LVPECL IPD
RCLK_H
Receive Clock noninverted side of pair (155.52MHz)
1
LVPECL IPU
RCLK_L
Receive Clock inverted side of pair (155.52MHz)
Table 7
1
LVPECL OPD
TXD_H
Transmit Data noninverted side of pair
CPn_3
Table 7
1
LVPECL IPU
TXD_L
Transmit Data inverted side of pair
CPn_4
Table 7
1
LVPECL IPD
RXD_H
Receive Data noninverted side of pair
CPn_5
Table 7
1
LVPECL IPU
RXD_L
Receive Data inverted side of pair
CPn_6
Table 7
1
LVPECL IPU
SIGNAL_DET
A light level above a certain threshold is present at the optical
receiver - single ended LVPECL.
TOTAL PINS
*
†
I/O
7
n can be from 0 to 7.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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Pin Descriptions Grouped by Function
41
SONET OC-12 Transceiver Interface Configuration
SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a
CP within a cluster spends half its time performing receive functions, and the other half
performing transmit functions. Table 14 shows a CP Cluster configured for one OC-12
interface.
Freescale Semiconductor, Inc...
Table 14 OC-12 Signals Example
SIGNAL NAME*
PIN #†
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
Table 7
1
LVTTL
OPD
TCLK
Deskewed Transmit Clock (77.76MHz). This clock is used to
synchronize the transmit data.
CPn_1
Table 7
1
LVTTL
IPU
TCLKI
Transceiver Transmit Clock. This clock sets the frequency of the
transmit data and is typically sourced by the PHY chip.
CPn_2
Table 7
1
LVTTL
OPD
TXD(0)
Transmit Data (byte-wide data, least significant bit)
CPn_3
Table 7
1
LVTTL
OPU
TXD(1)
Transmit Data
CPn_4
Table 7
1
LVTTL
OPD
TXD(2)
Transmit Data
CPn_5
Table 7
1
LVTTL
OPU
TXD(3)
Transmit Data
CPn_6
Table 7
1
LVTTL
OPU
00F
Out of Frame
CPn+1_0
Table 7
1
nc
ncPD
nc
nc
CPn+1_1
Table 7
1
nc
ncPU
nc
nc
CPn+1_2
Table 7
1
LVTTL
OPD
TXD(4)
Transmit Data
CPn+1_3
Table 7
1
LVTTL
OPU
TXD(5)
Transmit Data
CPn+1_4
Table 7
1
LVTTL
OPD
TXD(6)
Transmit Data
CPn+1_5
Table 7
1
LVTTL
OPU
TXD(7)
Transmit Data (byte-wide data, most significant bit)
CPn+1_6
Table 7
1
nc
ncPU
nc
nc
CPn+2_0
Table 7
1
nc
ncPD
nc
nc
CPn+2_1
Table 7
1
LVTTL
IPU
RCLK
Receive Clock (77.76MHz)
CPn+2_2
Table 7
1
LVTTL
IPD
RXD(0)
Receive Data (byte-wide receive data, least significant bit)
CPn+2_3
Table 7
1
LVTTL
IPU
RXD(1)
Receive Data
CPn+2_4
Table 7
1
LVTTL
IPD
RXD(2)
Receive Data
CPn+2_5
Table 7
1
LVTTL
IPU
RXD(3)
Receive Data
CPn+2_6
Table 7
1
LVTTL
IPU
FP
Frame Synchronization Pulse. This is valid during the third A2 of
the receive SONET frame.
CPn+3_0
Table 7
1
nc
ncPD
nc
nc
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CHAPTER 2: SIGNAL DESCRIPTIONS
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Table 14 OC-12 Signals Example (continued)
SIGNAL NAME*
PIN #†
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn+3_1
Table 7
1
nc
ncPU
nc
nc
CPn+3_2
Table 7
1
LVTTL
IPD
RXD(4)
Receive Data
CPn+3_3
Table 7
1
LVTTL
IPU
RXD(5)
Receive Data
CPn+3_4
Table 7
1
LVTTL
IPD
RXD(6)
Receive Data
CPn+3_5
Table 7
1
LVTTL
IPU
RXD(7)
Receive Data (most significant bit)
CPn+3_6
Table 7
1
nc
ncPU
nc
nc
TOTAL PINS
*
†
28
n can be 0, or 4.
Reference Table 7 for pin numbers for a different cluster.
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Pin Descriptions Grouped by Function
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Executive Processor
System Interface Signals
43
The XP’s system interface manages the supervisory controls for the network interfaces, as
well as the set of pins that provide interfaces to other components in the system that are
not memories or network interfaces. It is also the primary interface used for initializing the
C-3e NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM
interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCI Specification revision 2.1. Table 15 describes
the PCI signals.
Table 15 PCI Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
PAD0 - PAD31
AB9, AC9, AE9, AF9, AB8, AC8,
AD8, AE8, AF8, AG8, AB7, AC7,
AD7, AE7, AF7, AG7, AB6, AC6,
AE6, AG6, AB5, AC5, AD5, AE5,
AF5, AG5, AB4, AD4, AF4, AG4,
AA3, AB3,
32
PCI
I/O
Multiplexed Address/Data Bus. These signals are
multiplexed address and data bits. The C-3e NP
receives addresses as target and drives addresses as
master. It drives the data and receives read data as
master.
PCBEX0 - PCBEX3
AB2, AG3, AF3, AE3
4
PCI
I/O
Command byte enables. These signals are
multiplexed command and byte enabled signals.
The C-3e NP receives byte enables as target and drives
byte enables as master.
PPAR
AG1
1
PCI
I/O
Parity. This signal carries even parity for AD and CBE#
pins. It has the same receive and drive characteristics
as the address and data bus, except that it is one PCI
cycle later.
PFRAMEX
AA7
1
PCI
I/O
Cycle frame
PTRDYX
AB1
1
PCI
I/O
Target ready for data transfer
PIRDYX
AC2
1
PCI
I/O
Initiator ready for data transfer
PSTOPX
AE2
1
PCI
I/O
Target transaction stop request
PDEVSELX
AG2
1
PCI
I/O
Target device selected
PPERRX
AC3
1
PCI
I/O
Bus parity error
PSERRX
AD3
1
PCI
I/O
System error
PCLK
AF1
1
IPD
I
Bus clock
PRSTX
AE1
1
PCI
I
Bus reset
PREQX
AD1
1
PCI
O
Initiator bus request (arbitration)
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CHAPTER 2: SIGNAL DESCRIPTIONS
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Table 15 PCI Signals (continued)
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
PGNTX
AA8
1
IPD
I
Initiator bus grant (arbitration)
PIDSEL
AA5
1
PCI
I
Initialization device select
PINTA
AC1
1
PCI
O
Interrupt
50
TOTAL PINS
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following
formats:
•
An 8bit data format followed by an acknowledge bit, which supports transfers at up to
400kbps (low speed).
•
a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports
transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols.
Which of the two data rates used is selected by the state of the PROM interface’s SPLD
signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low
speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is
selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a
transmitter.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor,
to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
of the devices connected to the bus must have either an open-drain or open-collector in
order to perform the wired-AND function required for its arbitration mechanism.
Table 16 Serial Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SICL
AA1
1
LVTTL
IPD/O Serial Clock line
SIDA
AA4
1
LVTTL
IPD/O Serial Data line
TOTAL PINS
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2
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Pin Descriptions Grouped by Function
45
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-3e NP to communicate
through external logic to PROM. The PROM clock is 1/2 to 1/16 the core clock rate.The
maximum PROM size addressable is 4MBytes, and must use a “by 16” part. The PROM
signals are listed in Table 17.
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Table 17 PROM Interface Signals
SIGNAL
NAME
PIN #
TOTAL TYPE
I/O
SIGNAL DESCRIPTION
SPDO
Y5
1
LVTTL
O
Serial Data Out
SPDI
Y6
1
LVTTL
IPD
Serial Data In
SPLD
Y7
1
LVTTL
O
When load is asserted on a positive clock
edge, the external logic performs a parallel
load. On each positive clock edge when
load is de-asserted, the shift registers shift.
When the PROM interface is idle:
• if SPLD is asserted HI it indicates low
speed serial protocol,
•
SPCK
TOTAL PINS
Y8
1
LVTTL
O
if asserted LOW it indicates MDIO serial
protocol.
Clock
4
Figure 5 shows the connections between the PROM Interface and external board logic.
The application is required to provide an external shift register with parallel-in and
parallel-out capabilities, and a parallel load register. Both devices should be
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
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CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 5 PROM Interface Diagram
21
C-3e Network Processor
0
PROM_ADDR<21:1>
External Logic
CE
SPDO
21
21
6
1
0
Freescale Semiconductor, Inc...
SPDI
15
31
16
PROM _H_Word
21
6 0
21
External Shift
Register
0
Internal Shift
Register
15
0
PROM_ADDR<21:1>
CE
PROM _LO_Word
1
21
16
PROM _Return_Data
PROM Clock Gen.
PROM
SPCLK
PROM Sequencer SPLD
PROM_Data
The PROM interface operates in the following manner (Note that two accesses are
piplined together to execute one 32-bit fetch). The steps are shown in Figure 6.
1 The PROM_ADDR is loaded into the network processor internal shift register.
2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register.
4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit
PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift
register.
5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register and the first PROM_DATA into the external shift register.
6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network
processor internal shift register.
7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network
processor PROM_RETURN_DATA register and the second PROM_DATA into the
external shift register.
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Pin Descriptions Grouped by Function
8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the
network processor internal shift register.
9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the
network processor PROM_RETURN_DATA register.
Freescale Semiconductor, Inc...
Figure 6 PROM Interface Timing Outline
XP PROM Interface outline
`
SPLD
SPDTO
`
A1
`
A2
SPDTI
`
‘
A3
A4
A5
D1
D2
D3
XP PROM Interface detail
1
2
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
SPCLK
SPLD
A1
SPDTO
x
1
A A A A A A A A A A A A
20 19 18 17 16 15 14 13 12 11 10 9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A2
A CE
0
The PROM_ADDR is loaded into the
C-5's internal shift register.
The PROM_ADDR is shifted into
the external shift register.
(SPCLK Rising Edge used for shifting)
2
3
A3
A4
5
The PROM_ADDR is loaded into the
external presentation register.
4
The PROM_DATA is
presenting.
The PROM_DATA is loaded into the
external shift register.
D1
x
SPDTI
6
D D D D D D D
15 14 13 12 11 10 9
D
8
D
7
D
6
D
5
D D
4 3
D
2
D
1
D2
D
0
x
x
x
x
x
x
The PROM_DATA is shifted into the C-5's
Internal shift register.
8
7
9
The PROM_DATA is loaded into the C-5's
internal PROM_RETURN_DATA register.
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CHAPTER 2: SIGNAL DESCRIPTIONS
General System Interface Signal
Table 18 provides the signal for the Executive Processor reset power status and I/O clock.
The C-3e NP can be powered up with the XP either running or with the XP in reset mode
similar to the CPs. When the XP remains in reset mode, an external host can be used to
control the initialization of the C-3e NP.
Freescale Semiconductor, Inc...
Table 18 General System Interface Signal
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
XPUHOT
Y3
1
LVTTL
IPD
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low
equals reset and High equals active. During normal operation, this is an
external interrupt.
TOTAL PINS
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Pin Descriptions Grouped by Function
Fabric Processor Interface
Signals
49
The FP has logical signal interfaces: a receive data interface and a transmit data interface,
each with its own control, data, and clock signals. The interface has the following
characteristic:
Freescale Semiconductor, Inc...
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core
C-3e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to
125MHz.
FRXCLK and FTXCLK can be independent of each other; typically they have the same
frequency, but are allowed to be skewed relative to each other.
Each data bus can be configured for widths of 8 (data bits 7:0 are used), or 16 (bits 15:0). In
8bit mode, data bits 15:8 are unused.
Table 19 Fabric Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
FIN0 - FIN15
AD13, AC13, AB13, AG12, AF12, AE12, AD12,
AC12, AB12, AG11, AF11, AE11, AD11, AC11,
AB11, AG10
16
LVTTL
IPD
Fabric Data Bus In
FOUT0 - FOUT15
AG17, AF17, AG16, AF16, AE16, AD16, AC16,
AB16, AG15, AF15, AE15, AD15, AC15, AB15,
AG14, AE14
16
LVTTL
O
Fabric Data Bus Out
FRXCLK
AG9
1
LVTTL
IPD
Receive Clock
FTXCLK
AE13
1
LVTTL
IPD
Transmit Clock
FRXCTL0 - FRXCTL2 & AE10, AD10, AC10, AB10
FRXCTL6
4
LVTTL
IPD, O Receive Control Signals
FTXCTL0 - FRXCTL2 & AC14, AB14, AG13, AF13
FTXCTL6
4
LVTTL
IPD, O Transmit Control Signals
TOTAL PINS
42
The following tables list the Fabric Interface pin mappings:
•
•
Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 20
Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 21
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 20 Utopia1*, 2*, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping
Freescale Semiconductor, Inc...
RECEIVE SIGNALS
*
TRANSMIT SIGNALS
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
FRXCTL0
Output
RxEnb*
Pullup or No
Connection
FTXCTL0
Output
TxEnb*
Pullup or No
Connection
FRXCTL1
Input
RxClav
FTXCTL1
Input
TxClav
FRXCTL2
Input
RxSOC
FTXCTL2
Output
TxSOC
FRXCTL6
Input
RxPrty
FTXCTL6
Output
TxPrty
Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low.
Table 21 Utopia1*, 2*, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
*
TRANSMIT SIGNALS
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
FRXCTL0
Input
TxEnb*
Pullup
FTXCTL0
Input
RxEnb*
Pullup
FRXCTL1
Output
TxClav
No Connection
FTXCTL1
Output
RxClav
No Connection
FRXCTL2
Input
TxSOC
FTXCTL2
Output
RxSOC
FRXCTL6
Input
TxPrty
FTXCTL6
Output
RxPrty
Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low.
When configuring two C-3e network processors back-to-back using the Fabric Port, set
up the transmit side of each C-3e network processor in Utopia ATM mode and the receive
side of each C-3e network processor in Utopia PHY mode.
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Pin Descriptions Grouped by Function
BMU SDRAM Interface
Signals
51
The BMU and SDRAM interface signals are described in Table 22.
The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines
and all 12 address lines must be connected to the SDRAM in order for the BMU to be able
to read and write external SDRAM properly.
Freescale Semiconductor, Inc...
Table 22 BMU SDRAM Interface Signals
SIGNAL NAME
PIN #
TOTAL
MD0 - MD129
AA27, AA25, AA24, AA23, AA21,
130
AA20, Y27, Y26, Y25, Y23, Y22, Y21,
Y20, W27, W26, W25, W23, W22,
W21, W20, V27, V25, V24, V23, V21,
V20, U27, U26, U25, U24, U23, U22,
U21, U20, T27, T26, T25, T23, T22,
T21, T20, R27, R26, R25, R24, R23,
R22, R21, R20, P27, P25, P24, P23,
P21, P20, N27, N26, N25, N24, N23,
N22, N21, N20, M27, M26, M25,
M23, M22, M21, M20, L27, L26, L25,
L24, L23, L22, L21, L20, K27, K25,
K24, K23, K21, K20, J27, J26, J25,
J23, J22, J21, J20, H27, H26, H25,
H23, H22, H21, H20, G27, G25, G24,
G23, G21, G20, F27, F26, F25, F24,
F23, F22, F21, F20, E27, E26, E25,
E23, E22, E21, E20, D27, D25, D24,
D23, D21, D20, C27, C26, C25, C23,
C22
TYPE
I/O
SIGNAL DESCRIPTION
LVTTL
IPD/O Data Lines In
MDECC0 - MDECC8 A27, B20, B21, B23, B24, B25, B27,
C20, C21
9
LVTTL
IPD/O Stored as data, ECC bits
MA0 - MA11
C19, B19, A19, F18, E18, D18, C18,
A18, F17, E17, D17, C17
12
LVTTL
OPD
Address Outputs: A0-A11 are sampled during the
ACTIVE command and READ/WRITE to select one
location out of the memory array in the respective
bank. The address inputs also provide the
op-code during a LOAD MODE REGISTER
command
MBA0 - MBA1
F19, E19
2
LVTTL
OPD
Bank Address Outputs: BA0 and BA1 define which
bank the ACTIVE, READ, WRITE or PRECHARGE
command is being applied
MCASX
A24
1
LVTTL
OPD
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered.
NOTE: MCSX is considered part of the command
code.
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CHAPTER 2: SIGNAL DESCRIPTIONS
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Table 22 BMU SDRAM Interface Signals (continued)
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
MRASX
A23
1
LVTTL
OPD
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
MWEX
A22
1
LVTTL
OPD
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
MCSX
A25
1
LVTTL
OPD
Chip Select: MCSX enables (registered LOW) and
disables (registered HIGH) the command decoder.
All commands are masked when MCSX is
registered HIGH. MCSX provides the external bank
selection on systems with multiple banks. MCSX is
considered part of the command code.
MDQM
MDQML
A20
A21
1
1
LVTTL
LVTTL
OPD
OPD
Input/Output Mask: MDQM is an input mask
signal for write accesses and an output enable
signal for read accesses. Input data is masked
when MDQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a high Z
state (two-clock latency) when MDQM is sampled
HIGH during the READ cycle.
NOTE: MDQML is an identical copy of MDQM
used to drive the loading on SDRAM
configurations with 2 DQM pins.
MDCLK
A26
1
LVTTL
IPD
Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of the MDCLK. MDCLK also increments the
internal burst counter and controls the output
registers.
TOTAL PINS
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Pin Descriptions Grouped by Function
TLU SRAM Interface
Signals
53
The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 125MHz
using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to
64Mbits. The TLU SRAM interface signals are described in Table 23.
Freescale Semiconductor, Inc...
Table 23 TLU SRAM Interface Signals
SIGNAL NAME
PIN #
TYPE
I/O
TD0 - TD63
F3, F4, F5, F6, F7, F8, G1, G3, G4, G5, G7, G8, H1, H2, 64
H3, H5, H6, H7, H8, J1, J2, J3, J5, J6, J7, J8, K1, K3,
K4, K5, K7, K8, L1, L2, L3, L4, L5, L6, L7, L8, M1, M2,
M3, M5, M6, M7, M8, N1, N2, N3, N4, N5, N6, N7,
N8, P1, P3, P4, P5, P7, P8, R1, R2, R3
TOTAL
LVTTL
IPD/O TLU Memory Data
SIGNAL DESCRIPTION
TA0 - TA21
U2, U3, U4, U5, U6, U7, U8, V1, V3, V4, V5, V7, V8,
W1, W2, W3, W5, W6, W7, W8, Y1, Y2
22
LVTTL
OPD
TPAR0 - TPAR3
T1, T2, T3, T5
4
LVTTL
IPD/O Word Data Parity (i.e. TPAR0 across
TD15:0)
TCE0X - TCE3X
T6, T7, T8, U1
4
LVTTL
OPD
TLU Memory Chip Enable
TWE0X - TWE3X
R5, R6, R7, R8
4
LVTTL
OPD
TLU Memory Write Enable
TCLKI
R4
1
LVTTL
IPD
TLU Clock Input
TLU Memory Address
99
TOTAL PINS
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CHAPTER 2: SIGNAL DESCRIPTIONS
QMU SRAM (Internal
Mode) Interface Signals
The QMU signals are described in Table 24.
Freescale Semiconductor, Inc...
Table 24 QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
QA0 - QA16
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12,
E12, D12, C12, A12, F13, E13, D13
17
LVTTL
O
Address [16:0]
QD0 - QD31
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, 32
D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7,
C7, B7, A7, E8, D8
LVTTL
IPD/O Data
QDQPAR
C8
1
LVTTL
IPD
nc
QARDY
F10
1
LVTTL
IPD
nc
QNQRDY
A9
1
LVTTL
IPD
nc
QWEX
E10
1
LVTTL
O
Write Enable
QBCLKO
B8
1
LVTTL
O
nc
QBCLKI
A8
1
LVTTL
IPD
nc
QACLKO
F9
1
LVTTL
O
nc
QACLKI
E9
1
LVTTL
IPD
Input Clock
QDPL
C9
1
LVTTL
IPD/O Data Parity Low
QDPH
B9
1
LVTTL
IPD/O Data Parity High
TOTAL PINS
C3ENPA1-DS/D REV 03
59
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Pin Descriptions Grouped by Function
QMU to Q-5/Q-3 (External
Mode) Interface Signals
55
The QMU to Q-5/Q-3 signals are described in Table 25.
Freescale Semiconductor, Inc...
Table 25 QMU to Q-5/Q-3 (External Mode) Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
QA0 - QA15
D10, C10, A10, F11, E11, D11, C11, B11, A11,
F12, E12, D12, C12, A12, F13, E13
16
LVTTL
O
Enqueue Data [8:23]
QA16
D13
1
LVTTL
O
Enqueue Parity
QD0 - QD23
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3,
B3, A3, D4, B4, A4, E5, D5, C5, B5, A5, E6, C6
24
LVTTL
IPD
Dequeue Data [0:23]
QD24 - QD31
A6, E7, D7, C7, B7, A7, E8, D8
8
LVTTL
IPD
Enqueue Data [0:7]
QDQPAR
C8
1
LVTTL
IPD
Dequeue Parity
QARDY
F10
1
LVTTL
IPD
Dequeue Ack Ready
QNQRDY
A9
1
LVTTL
O
Enqueue Ready
QWEX
E10
1
LVTTL
O
Dequeue Ready
QBCLKO
B8
1
LVTTL
O
Output ClockB
QBCLKI
A8
1
LVTTL
IPD
Input ClockB
QACLKO
F9
1
LVTTL
O
Output ClockA
QACLKI
E9
1
LVTTL
IPD
Input ClockA
QDPL
C9
1
LVTTL
O
Dequeue Ack [0]
QDPH
B9
1
LVTTL
O
Dequeue Ack [1]
59
TOTAL PINS
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56
CHAPTER 2: SIGNAL DESCRIPTIONS
Power Supply Signals
Power supply, and ground signals are described in Table 26.
Freescale Semiconductor, Inc...
Table 26 Power Supply Signals
SIGNAL NAME
PIN #
VDD
TYPE
SIGNAL DESCRIPTION
H10, H12, H16, J11, J13, J15, J17, K10, K12, K14, K16, 57
K18, L11, L13, L15, L17, M10, M12, M14, M16, M18,
N11, N13, N15, N17, P10, P12, P14, P16, P18, R11,
R13, R15, R17, T10, T12, T14, T16, T18, U11, U13, U15,
U17, V10, V12, V14, V16, V18, W11, W13, W15, W17,
Y10, Y12, Y14, Y16, Y18
P
Core Supply Voltage (1.1V Input)
VDD33
B18, B26, C24, D14, D22, G13, G15, G17, G19, G26,
40
H14, H18, H24, J19, K22, L19, M24, N19, P26, R19,
U19, V22, W19, W24, AA9, AA11, AA13, AA15, AA17,
AA19, AA26, AD6, AD14, AD22, AE4, AE24, AF2,
AF10, AF18, AF26
P
I/O Supply Voltage (3.3V Input)
GND
B6, B12, B16, B22, D2, D9, D19, D26, E4, E24, G6, G10, 117
G12, G14, G16, G18, G22, H9, H11, H13, H15, H17,
H19, J4, J10, J12, J14, J16, J18, J24, K2, K9, K11, K13,
K15, K17, K19, K26, L10, L12, L14, L16, L18, M9, M11,
M13, M15, M17, M19, N10, N12, N14, N16, N18, P6,
P9, P11, P13, P15, P17, P19, P22, R10, R12, R14, R16,
R18, T4, T9, T11, T13, T15, T17, T19, T24, U10, U12,
U14, U16, U18, V2, V9, V11, V13, V15, V17, V19, V26,
W10, W12, W14, W16, W18, Y4, Y9, Y11, Y13, Y15,
Y17, Y19, Y24, AA6, AA10, AA12, AA14, AA16, AA18,
AA22, AC4, AC24, AD2, AD9, AD19, AD26, AF6, AF14,
AF22
P
Ground
VDDT
B2, B10, C4, D6, G2, G9, G11, H4, J9, K6, L9, M4, N9,
P2, R9, U9, V6, W4, W9, AA2
P
TLU and QMU I/O supply (3.3V)
TOTAL PINS
C3ENPA1-DS/D REV 03
TOTAL
20
234
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Pin Descriptions Grouped by Function
Test Signals
57
Test signals are described in Table 27.
Freescale Semiconductor, Inc...
Table 27 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
JTCK
B17
1
LVTTL
IPD
Test Clock
JTMS
A17
1
LVTTL
IPD
Test Mode Select. High selects modes
as defined in the IEEE 1149.1 JTAG
specification.
JTRSTX
A16
1
LVTTL
IPD
Test Reset (low active)
JTDI
C16
1
LVTTL
IPD
Test Data In
JTDO
C14
1
LVTTL
O
Test Data Out
JHIGHZ
B15
1
LVTTL
IPD
Turns off all output drivers when High
JCLKBYP
A15
1
LVTTL
IPD
1X or 2X Clock Mode Select. Low
selects 1X, High selects 2X.
JSE
D15
1
LVTTL
IPD
Scan Enable. High enables scan test.
JS00-JS05
C13, B13, A13, B14, A14, C15
6
LVTTL
O
Scan Out Pins
14
TOTAL PINS
During JTAG, SCLK and SCLKX must remain as differential inputs.
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58
CHAPTER 2: SIGNAL DESCRIPTIONS
Signals Grouped by Pin
Number
The C-3e NP signals are listed by pin number in Table 28.
Table 28 Signals Listed by Pin Number
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
Freescale Semiconductor, Inc...
A 1-27
A1
Not present
A9
QNQRDY
A17
JTMS
A25
MCSX
A2
QD8
A10
QA2
A18
MA7
A26
MDCLK
A3
QD13
A11
QA8
A19
MA2
A27
MDECC0
A4
QD16
A12
QA13
A20
MDQM
A5
QD21
A13
JS02
A21
MDQML
A6
QD24
A14
JS04
A22
MWEX
A7
QD29
A15
JCLKBYP
A23
MRASX
A8
QBCLKI
A16
JTRSTX
A24
MCASX
B 1-27
B1
QD4
B9
QDPH
B17
JTCK
B25
MDECC5
B2
VDDT
B10
VDDT
B18
VDD33
B26
VDD33
B3
QD12
B11
QA7
B19
MA1
B27
MDECC6
B4
QD15
B12
GND
B20
MDECC1
B5
QD20
B13
JS01
B21
MDECC2
B6
GND
B14
JS03
B22
GND
B7
QD28
B15
JHIGHZ
B23
MDECC3
B8
QBCLKO
B16
GND
B24
MDECC4
C 1-27
C3ENPA1-DS/D REV 03
C1
QD3
C9
QDPL
C17
MA11
C25
MD127
C2
QD7
C10
QA1
C18
MA6
C26
MD126
C3
QD11
C11
QA6
C19
MA0
C27
MD125
C4
VDDT
C12
QA12
C20
MDECC7
C5
QD19
C13
JS00
C21
MDECC8
C6
QD23
C14
JTDO
C22
MD129
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Signals Grouped by Pin Number
59
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
C7
QD27
C15
JS05
C23
MD128
C8
QDQPAR
C16
JTDI
C24
VDD33
PIN
FUNCTION
Freescale Semiconductor, Inc...
D 1-27
D1
QD2
D9
GND
D17
MA10
D25
MD120
D2
GND
D10
QA0
D18
MA5
D26
GND
D3
QD10
D11
QA5
D19
GND
D27
MD119
D4
QD14
D12
QA11
D20
MD124
D5
QD18
D13
QA16
D21
MD123
D6
VDDT
D14
VDD33
D22
VDD33
D7
QD26
D15
JSE
D23
MD122
D8
QD31
D16
CPREF
D24
MD121
E 1-27
E1
QD1
E9
QACLKI
E17
MA9
E25
MD114
E2
QD6
E10
QWEX
E18
MA4
E26
MD113
E3
QD9
E11
QA4
E19
MBA1
E27
MD112
E4
GND
E12
QA10
E20
MD118
E5
QD17
E13
QA15
E21
MD117
E6
QD22
E14
CCLK3
E22
MD116
E7
QD25
E15
CCLK2
E23
MD115
E8
QD30
E16
CCLK1
E24
GND
F 1-27
F1
QD0
F9
QACLKO
F17
MA8
F25
MD106
F2
QD5
F10
QARDY
F18
MA3
F26
MD105
F3
TD0
F11
QA3
F19
MBA0
F27
MD104
F4
TD1
F12
QA9
F20
MD111
F5
TD2
F13
QA14
F21
MD110
F6
TD3
F14
SCLK
F22
MD109
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60
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
F7
TD4
F15
SCLKX
F23
MD108
F8
TD5
F16
CCLK0
F24
MD107
PIN
FUNCTION
Freescale Semiconductor, Inc...
G 1-27
G1
TD6
G9
VDDT
G17
VDD33
G25
MD99
G2
VDDT
G10
GND
G18
GND
G26
VDD33
G3
TD7
G11
VDDT
G19
VDD33
G27
MD98
G4
TD8
G12
GND
G20
MD103
G5
TD9
G13
VDD33
G21
MD102
G6
GND
G14
GND
G22
GND
G7
TD10
G15
VDD33
G23
MD101
G8
TD11
G16
GND
G24
MD100
H 1-27
H1
TD12
H9
GND
H17
GND
H25
MD93
H2
TD13
H10
VDD
H18
VDD33
H26
MD92
H3
TD14
H11
GND
H19
GND
H27
MD91
H4
VDDT
H12
VDD
H20
MD97
H5
TD15
H13
GND
H21
MD96
H6
TD16
H14
VDD33
H22
MD95
H7
TD17
H15
GND
H23
MD94
H8
TD18
H16
VDD
H24
VDD33
J 1-27
C3ENPA1-DS/D REV 03
J1
TD19
J9
VDDT
J17
VDD
J25
MD86
J2
TD20
J10
GND
J18
GND
J26
MD85
J3
TD21
J11
VDD
J19
VDD33
J27
MD84
J4
GND
J12
GND
J20
MD90
J5
TD22
J13
VDD
J21
MD89
J6
TD23
J14
GND
J22
MD88
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Signals Grouped by Pin Number
61
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
J7
TD24
J15
VDD
J23
MD87
J8
TD25
J16
GND
J24
GND
PIN
FUNCTION
Freescale Semiconductor, Inc...
K 1-27
K1
TD26
K9
GND
K17
GND
K25
MD79
K2
GND
K10
VDD
K18
VDD
K26
GND
K3
TD27
K11
GND
K19
GND
K27
MD78
K4
TD28
K12
VDD
K20
MD83
K5
TD29
K13
GND
K21
MD82
K6
VDDT
K14
VDD
K22
VDD33
K7
TD30
K15
GND
K23
MD81
K8
TD31
K16
VDD
K24
MD80
L 1-27
L1
TD32
L9
VDDT
L17
VDD
L25
MD72
L2
TD33
L10
GND
L18
GND
L26
MD71
L3
TD34
L11
VDD
L19
VDD33
L27
MD70
L4
TD35
L12
GND
L20
MD77
L5
TD36
L13
VDD
L21
MD76
L6
TD37
L14
GND
L22
MD75
L7
TD38
L15
VDD
L23
MD74
L8
TD39
L16
GND
L24
MD73
M 1-27
M1
TD40
M9
GND
M17
GND
M25
MD65
M2
TD41
M10
VDD
M18
VDD
M26
MD64
M3
TD42
M11
GND
M19
GND
M27
MD63
M4
VDDT
M12
VDD
M20
MD69
M5
TD43
M13
GND
M21
MD68
M6
TD44
M14
VDD
M22
MD67
M7
TD45
M15
GND
M23
MD66
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62
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
M8
TD46
M16
VDD
M24
VDD33
PIN
FUNCTION
Freescale Semiconductor, Inc...
N 1-27
N1
TD47
N9
VDDT
N17
VDD
N25
MD57
N2
TD48
N10
GND
N18
GND
N26
MD56
N3
TD49
N11
VDD
N19
VDD33
N27
MD55
N4
TD50
N12
GND
N20
MD62
N5
TD51
N13
VDD
N21
MD61
N6
TD52
N14
GND
N22
MD60
N7
TD53
N15
VDD
N23
MD59
N8
TD54
N16
GND
N24
MD58
P 1-27
P1
TD55
P9
GND
P17
GND
P25
MD50
P2
VDDT
P10
VDD
P18
VDD
P26
VDD33
P3
TD56
P11
GND
P19
GND
P27
MD49
P4
TD57
P12
VDD
P20
MD54
P5
TD58
P13
GND
P21
MD53
P6
GND
P14
VDD
P22
GND
P7
TD59
P15
GND
P23
MD52
P8
TD60
P16
VDD
P24
MD51
R 1-27
C3ENPA1-DS/D REV 03
R1
TD61
R9
VDDT
R17
VDD
R25
MD43
R2
TD62
R10
GND
R18
GND
R26
MD42
R3
TD63
R11
VDD
R19
VDD33
R27
MD41
R4
TCLKI
R12
GND
R20
MD48
R5
TWE0X
R13
VDD
R21
MD47
R6
TWE1X
R14
GND
R22
MD46
R7
TWE2X
R15
VDD
R23
MD45
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Signals Grouped by Pin Number
63
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
R8
TWE3X
R16
GND
R24
MD44
PIN
FUNCTION
Freescale Semiconductor, Inc...
T 1-27
T1
TPAR0
T9
GND
T17
GND
T25
MD36
T2
TPAR1
T10
VDD
T18
VDD
T26
MD35
T3
TPAR2
T11
GND
T19
GND
T27
MD34
T4
GND
T12
VDD
T20
MD40
T5
TPAR3
T13
GND
T21
MD39
T6
TCE0X
T14
VDD
T22
MD38
T7
TCE1X
T15
GND
T23
MD37
T8
TCE2X
T16
VDD
T24
GND
U 1-27
U1
TCE3X
U9
VDDT
U17
VDD
U25
MD28
U2
TA0
U10
GND
U18
GND
U26
MD27
U3
TA1
U11
VDD
U19
VDD33
U27
MD26
U4
TA2
U12
GND
U20
MD33
U5
TA3
U13
VDD
U21
MD32
U6
TA4
U14
GND
U22
MD31
U7
TA5
U15
VDD
U23
MD30
U8
TA6
U16
GND
U24
MD29
V 1-27
V1
TA7
V9
GND
V17
GND
V25
MD21
V2
GND
V10
VDD
V18
VDD
V26
GND
V3
TA8
V11
GND
V19
GND
V27
MD20
V4
TA9
V12
VDD
V20
MD25
V5
TA10
V13
GND
V21
MD24
V6
VDDT
V14
VDD
V22
VDD33
V7
TA11
V15
GND
V23
MD23
V8
TA12
V16
VDD
V24
MD22
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64
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
Freescale Semiconductor, Inc...
W 1-27
W1
TA13
W9
VDDT
W17
VDD
W25
MD15
W2
TA14
W10
GND
W18
GND
W26
MD14
W3
TA15
W11
VDD
W19
VDD33
W27
MD13
W4
VDDT
W12
GND
W20
MD19
W5
TA16
W13
VDD
W21
MD18
W6
TA17
W14
GND
W22
MD17
W7
TA18
W15
VDD
W23
MD16
W8
TA19
W16
GND
W24
VDD33
Y 1-27
Y1
TA20
Y9
GND
Y17
GND
Y25
MD8
Y2
TA21
Y10
VDD
Y18
VDD
Y26
MD7
Y3
XPUHOT
Y11
GND
Y19
GND
Y27
MD6
Y4
GND
Y12
VDD
Y20
MD12
Y5
SPDO
Y13
GND
Y21
MD11
Y6
SPDI
Y14
VDD
Y22
MD10
Y7
SPLD
Y15
GND
Y23
MD9
Y8
SPCK
Y16
VDD
Y24
GND
AA 1-27
C3ENPA1-DS/D REV 03
AA1
SICL
AA9
VDD33
AA17
VDD33
AA25
MD1
AA2
VDDT
AA10
GND
AA18
GND
AA26
VDD33
AA3
PAD30
AA11
VDD33
AA19
VDD33
AA27
MD0
AA4
SIDA
AA12
GND
AA20
MD5
AA5
PIDSEL
AA13
VDD33
AA21
MD4
AA6
GND
AA14
GND
AA22
GND
AA7
PFRAMEX
AA15
VDD33
AA23
MD3
AA8
PGNTX
AA16
GND
AA24
MD2
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Signals Grouped by Pin Number
65
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
Freescale Semiconductor, Inc...
AB 1-27
AB1
PTRDYX
AB9
PAD0
AB17
CP7_6
AB25
CP2_1
AB2
PCBEX0
AB10
FRXCTL6
AB18
CP7_2
AB26
CP1_2
AB3
PAD31
AB11
FIN14
AB19
CP6_4
AB27
CP0_5
AB4
PAD26
AB12
FIN8
AB20
CP5_6
AB5
PAD20
AB13
FIN2
AB21
CP5_0
AB6
PAD16
AB14
FTXCTL1
AB22
CP4_1
AB7
PAD10
AB15
FOUT13
AB23
CP3_4
AB8
PAD4
AB16
FOUT7
AB24
CP2_5
AC 1-27
AC1
PINTA
AC9
PAD1
AC17
CP7_5
AC25
CP2_0
AC2
PIRDYX
AC10
FRXCTL2
AC18
CP7_1
AC26
CP1_1
AC3
PPERRX
AC11
FIN13
AC19
CP6_3
AC27
CP0_4
AC4
GND
AC12
FIN7
AC20
CP5_5
AC5
PAD21
AC13
FIN1
AC21
CP4_6
AC6
PAD17
AC14
FTXCTL0
AC22
CP4_0
AC7
PAD11
AC15
FOUT12
AC23
CP3_3
AC8
PAD5
AC16
FOUT6
AC24
GND
AD 1-27
AD1
PREQX
AD9
GND
AD17
CP7_4
AD25
CP1_6
AD2
GND
AD10
FRXCTL1
AD18
CP7_0
AD26
GND
AD3
PSERRX
AD11
FIN12
AD19
GND
AD27
CP0_3
AD4
PAD27
AD12
FIN6
AD20
CP5_4
AD5
PAD22
AD13
FIN0
AD21
CP4_5
AD6
VDD33
AD14
VDD33
AD22
VDD33
AD7
PAD12
AD15
FOUT11
AD23
CP3_2
AD8
PAD6
AD16
FOUT5
AD24
CP2_4
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66
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
Freescale Semiconductor, Inc...
AE 1-27
AE1
PRSTX
AE9
PAD2
AE17
CP7_3
AE25
CP1_5
AE2
PSTOPX
AE10
FRXCTL0
AE18
CP6_6
AE26
CP1_0
AE3
PCBEX3
AE11
FIN11
AE19
CP6_2
AE27
CP0_2
AE4
VDD33
AE12
FIN5
AE20
CP5_3
AE5
PAD23
AE13
FTXCLK
AE21
CP4_4
AE6
PAD18
AE14
FOUT15
AE22
CP3_6
AE7
PAD13
AE15
FOUT10
AE23
CP3_1
AE8
PAD7
AE16
FOUT4
AE24
VDD33
AF 1-27
AF1
PCLK
AF9
PAD3
AF17
FOUT1
AF25
CP1_4
AF2
VDD33
AF10
VDD33
AF18
VDD33
AF26
VDD33
AF3
PCBEX2
AF11
FIN10
AF19
CP6_1
AF27
CP0_1
AF4
PAD28
AF12
FIN4
AF20
CP5_2
AF5
PAD24
AF13
FTXCTL6
AF21
CP4_3
AF6
GND
AF14
GND
AF22
GND
AF7
PAD14
AF15
FOUT9
AF23
CP3_0
AF8
PAD8
AF16
FOUT3
AF24
CP2_3
AG 1-27
C3ENPA1-DS/D REV 03
AG1
PPAR
AG9
FRXCLK
AG17
FOUT0
AG25
CP1_3
AG2
PDEVSELX
AG10
FIN15
AG18
CP6_5
AG26
CP0_6
AG3
PCBEX1
AG11
FIN9
AG19
CP6_0
AG27
CP0_0
AG4
PAD29
AG12
FIN3
AG20
CP5_1
AG5
PAD25
AG13
FTXCTL2
AG21
CP4_2
AG6
PAD19
AG14
FOUT14
AG22
CP3_5
AG7
PAD15
AG15
FOUT8
AG23
CP2_6
AG8
PAD9
AG16
FOUT2
AG24
CP2_2
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JTAG Support
JTAG Support
The C-3e NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All
required public instructions are implemented, as well as some optional instructions. This
section contains information regarding the pinout, instructions, identification codes, and
boundary scan cell types.
Pinout
Freescale Semiconductor, Inc...
67
JTAG Data Registers
The C-3e NP uses the standard JTAG pins including the optional test reset pin. Table 27
describes the pins and their functions.
The C-3e NP contains the standard internal registers as specified in IEEE 1149.1. These
registers are described in Table 29.
Table 29 JTAG Internal Register Descriptions
REGISTER NAME
REGISTER LENGTH
DESCRIPTION
Bypass
1
Standard JTAG bypass register
Boundary
1549
Boundary Scan Register
Device Identification
32
Standard JTAG IDCODE Register
Boundary Scan Restriction
SCLK/SCLKX inputs must not toggle when exercising the boundary scan function for JTAG.
Boundary Scan Cell Types
The C-3e NP boundary scan register contains only two cell types. All input cells are observe
only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE
1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in
Figure 8.
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CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 7 Observe-Only Cell
To next cell
From System Pin
To System Logic
Freescale Semiconductor, Inc...
G1
1D
C1
Clock DR
From last cell
Shift DR
0
1
Figure 8 Cell Design That Can Be Used for Both Input and Output Pins
Node
To next cell
Shift DR
To/From
System Pin
G1
0
1
From/To
System
G1
0
1
From last cell
C3ENPA1-DS/D REV 03
1D
C1
Clock DR
1D
C1
Update DR
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JTAG Support
IDcode Register
69
The C-3e NP implements a standard 32bit JTAG identification register. Table 30 lists the
value of the code for full identification and its sub-components.
Freescale Semiconductor, Inc...
Table 30 JTAG Identification Code and Its Sub-components
FIELD NAME
WIDTH
BIT POSITIONS
BINARY VALUE
Version
4
31-28
0000
Part Number
16
27-12
0000_0000_0010_0001
Manufacturer Identity
11
11-1
001_1001_0110
LSB
1
0
1
The concatenated 32bit value is hexidecimal 0002132d.
JTAG Instruction Register
The C-3e NP contains a 4bit instruction register. Table 31 lists the instructions that are
supported.
Table 31 Instruction Register Instructions
INSTRUCTION MNEMONIC SELECTED REGISTER
INSTRUCTION OPCODE
Extest
Boundary Scan
0000
Idcode
Identification Register
0001
Sample/Preload
Boundary Scan
0010
Highz
Bypass Register
0011
Clamp
Bypass Register
0100
Bypass
Bypass Register
0101
Reserved*
Bypass Register
0110
Reserved*
Bypass Register
0111
Bypass
Bypass Register
1000
Bypass
Bypass Register
1001
Bypass
Bypass Register
1010
Bypass
Bypass Register
1011
Bypass
Bypass Register
1100
Bypass
Bypass Register
1101
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 31 Instruction Register Instructions (continued)
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*
Boundary Scan
Description Language
INSTRUCTION MNEMONIC SELECTED REGISTER
INSTRUCTION OPCODE
Bypass
Bypass Register
1110
Bypass
Bypass Register
1111
There are two reserved instructions intended for Motorola Corporation’s internal
use. These should not be programmed by users.
In order to simplify board test, Motorola Corporation has provided a boundary scan
description language (BSDL) file (c3e.bsdl) in the Motorola web site that describes the
complete set of instructions, boundary scan order, and identification code value in an
industry standard format.
http://www.motorola.com/networkprocessors
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C3ENPA1-DS/D
Chapter 3
Rev 03
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ELECTRICAL SPECIFICATIONS
Absolute Maximum
Ratings
Table 32 lists the absolute maximum ratings for the C-3e network processor. Stresses
beyond those listed may cause permanent damage to the device. These are stress ratings
only and do not imply that operation under any conditions other than those listed under
“Recommended Operating Conditions” (Table 33) is possible.
Exposure to conditions beyond Table 32 can:
•
•
Reduce device reliability
Result in premature device failure, even with no immediate sign of failure
Prolonged exposure to conditions at or near the absolute maximum ratings could also
result in reduced useful life and reliability of the C-3e NP.
Table 32 C-3e Network Processor Absolute Maximum Ratings
*
PARAMETER
MIN
MAX
UNIT
VDD33/VDDT Supply Voltage (3.3V input)*
-0.5
+5
V
VDD Supply Voltage (1.1V input)*
-0.5
+2.2
V
Voltage on any pin
-0.5
VDD33 + 0.5
V
Static Discharge Voltage
2000/500
Storage Temperature
-40
+125
°C
Absolute Maximum Junction Temperature
-40
+125
°C
V
Voltages are relative to Ground
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Recommended Operating
Conditions
The recommended operating conditions describe an environment the C-3e NP network
processor is expected to encounter during normal operation. Table 33 delineates the
recommended operating parameters for the C-3e NP.
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Table 33 C-3e Network Processor Recommended Operating Conditions
PARAMETER
MIN
NOMINAL
MAX
UNIT
VDD33 Supply Voltage
3.135
3.3
3.465
V
VDDT Supply Voltage
3.135
3.3
3.465
V
VDD Supply Voltage
1.04
1.2
1.16
V
IDD33 - VDD33 Supply Current
0.6
A
IDD - VDD Supply Current
5.0
A
125
°C
Tj Junction Temperature
C3ENPA1-DS/D REV 03
-40
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DC Characteristics
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DC Characteristics
73
The DC electrical characteristics define the input operating conditions for proper
operation and the output responses to applied DC signals and switch characteristics over
specified voltage and temperature ranges. The DC electrical characteristics are specified
within the recommended operating conditions including operating temperature and power
supply range as stated in this data sheet. Table 34 outlines the C-3e NP DC characteristics.
Table 34 C-3e Network Processor DC Characteristics
PARAMETER*
MIN
MAX
UNIT
LVTTL Input High Voltage
2.0
VDD33+.3
V
LVTTL Input Low Voltage
-0.3
0.8
V
LVTTL Output High Voltage
2.4
LVTTL Output Low Voltage
*
NOTES
V
@IOH = -2mA
0.4
V
@IOL = +2mA
VIN = 0V or VDD33
LVTTL Input Current
-100
+100
µA
LVPECL Input High Voltage
VDD33 -1.165
VDD33+.3V
V
LVPECL Input Low Voltage
-0.3
VDD33 -1.475
V
LVPECL Output High Voltage
VDD33 -1.025
VDD33 -0.60
V
Load = 50ohm to
VDD33 - 2V
LVPECL Output Low Voltage
VDD33 -2.20
VDD33 -1.620
V
Load = 50ohm to
VDD33 - 2V
LVPECL Input Current
-100
+100
µA
CPREF
VDD33 -1.38
VDD33 -1.26
V
Single-ended LVPECL
reference
All voltages are relative to Ground unless otherwise indicated.
Each control input pin has a capacitance associated with it. The capacitance at the control
input is due to the package and the input circuitry connected to the pin. Capacitance is
based on these conditions: TA = 25°C; VDD33 = 3.3V; f = 1MHz. Table 35 provides
capacitance data.
Table 35 C-3e Network Processor Capacitance Data
PARAMETER
TYPICAL
UNIT
All Pins
5
pF
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Power Sequencing
It is intended that the VDD33/VDDT and VDD rails are sequenced to their final value
together for most applications. VDD33 and VDDT must be above VDD at all times. VDD
must be brought to its final value within 100ms of sequencing on VDD33 and VDDT.
Freescale Semiconductor, Inc...
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-3e NP. Figure 9
indicates the relationship between the clocks and PRSTX. There is no requirement that the
asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be
asserted within 100µs of power initiation. Typically, reset is held low during power
initiation.
Figure 9 Bringup Clock Timing Diagram
VDD, VDD33,
VDDT
≤100µs
PRSTX
) (
³1ms
TCLKI, PCLK,
SCLK, SCLKX,
MDCLK, FTXCLK,
FRXCLK
C3ENPA1-DS/D REV 03
³100µs
) (
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Power and Thermal Characteristics
Power and Thermal
Characteristics
75
Table 36 provides the derived power and thermal characteristics for the production
version of the C-3e NP.
Freescale Semiconductor, Inc...
Table 36 C-3e Network Processor Power and Thermal Characteristics
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
Power Dissipation, PD
2.5
5.5
7.5
W
180MHz core clock
See Note below
125
oC
See Note below
Maximum Junction
Temperature, TJ
Thermal Resistance, junction
to case, θJC
<0.1
oC/W
See Note below
Thermal Resistance, junction
to printed circuit board, θJB
5.5
oC/W
See Note below
Table 36 note: Power dissipation values assume the following conditions:
Thermal Management
Information
•
•
•
•
BMU memory operating at 125MHz
•
•
“Minimum” PD based on idle condition (clocks running and no programs executing)
•
“Maximum” PD based on maximum consumption for any high-bandwidth
communications application executing on all CPs, FP, and XP
TLU memory operating at 125MHz
QMU operating at 150MHz
VDD = 1.1V, VDD33/VDDT = 3.3V, TJ at approximately 50°C for typical values. VDD and
VDD33/VDDT are 5% higher for maximum values
“Typical” PD based on test application that implements Fast Ethernet forwarding
actively running on all CPs
This section provides thermal management information for the ceramic ball grid array
(CBGA) package for air-cooled applications. Proper thermal control design is primarily
dependent on the system-level design—the heat sink, airflow, and thermal interface
material. To reduce the die-junction temperature, heat sinks may be attached to the
package by several methods—spring clip to holes in the printed-circuit board or package,
and mounting clip and screw assembly (refer to Figure 10); however, due to the potential
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
large mass of the heat sink, attachment through the printed circuit board is suggested. If a
spring clip is used, the spring force should not exceed 5.5 pounds.
Figure 10 Package Cross Section View with Serveral Heat Sink Options
Freescale Semiconductor, Inc...
Heat Sink
Heat Sink Clip
Thermal Interface Material
CBGA Package
Printed Circuit Board
Internal Package Conduction Resistance
For the exposed-die packaging technology the intrinsic conduction thermal resistance
paths are as follows:
•
•
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
The die junction-to-ball thermal resistance
Figure 11 depicts the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.
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Power and Thermal Characteristics
77
Figure 11 Package with Heat Sink Mounted to the Printed Circuit Board
Radiation
External Resistance
Convection
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Heat Sink
Thermal Interface Material
Die/Package
Internal Resistance
Die Junction
Package/Leads
Printed Circuit Board (PCB)
External Resistance
Radiation
Convection
Heat generated on the active side of the chip is conducted through the silicon, then
through the heat sink attach material (or thermal interface material), and finally to the
heat sink where it is removed by convection.
Because the silicon thermal resistance is quite small, for a first-order analysis, the
temperature drop in the silicon may be neglected. Thus, the thermal interface material
and the heat sink conduction/convective thermal resistances are the dominant terms.
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T j = T a + T r + (θjc + θint + θsa ) x P d
where:
T j is the die-junction temperature
T a is the inlet cabinet ambient temperature
T r is the air temperature rise within the computer cabinet
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
θjc is the junction-to-case thermal resistance
θint is the adhesive or interface material thermal resistance
θsa is the heat sink base-to-ambient thermal resistance
P d is the power dissipated by the device
Freescale Semiconductor, Inc...
During operation, the die-junction temperatures (T j ) should be maintained less than the
value specified in Table 36. The temperature of the air cooling the component greatly
depends upon the ambient inlet air temperature and the air temperature rise within the
electronic cabinet. An electronic cabinet inlet-air temperature (T a ) may range from 30° to
40°C. The air temperature rise within a cabinet (T r ) may be in the range of 5° to 10°C. The
thermal resistance of the thermal interface material (θint ) is typically about 1.5°C/W. For
example, assuming a T a of 30°C, a T r of 5°C, a CBGA package θjc = 0.1, and a maximum
power consumption (P d ) of 7.5 W, the following expression for T j is obtained:
Die-junction temperature: T j = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa ) x 7.5 W
For this example, a θsa value of 10.4°C/W or less is required to maintain the die junction
temperature below the maximum value of Table 36.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are
a common figure-of-merit used for comparing the thermal performance of various
microelectronic packaging technologies, one should exercise caution when only using
this metric in determining thermal management because no single parameter can
adequately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power
consumption, a number of factors affect the final operating die-junction
temperature—airflow, board population (local heat flux of adjacent components), heat
sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology,
system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for
today's microelectronic equipment, the combined effects of the heat transfer
mechanisms (radiation, convection,and conduction) may vary widely. For these reasons,
we recommend using conjugate heat transfer models for the board, as well as
system-level designs.
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AC Timing Specifications
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AC Timing Specifications
79
AC timing specifications consist of input requirements and output responses. The input
requirements include setup and hold times, pulse widths, and high and low times. The
output responses include delays from clock to signal. The AC timing specifications are
defined separately for each interface to the C-3e NP.
See Figure 12. Output timing specifications for LVTTL pins are given with a 20pF load on
the output. Other loads can be simulated with the IBIS model available from Motorola.
The LVPECL driver is specified into a 50Ω load terminated to a (VDD33 - 2V) reference.
Figure 12 Test Loading Conditions
LVTTL
DUT
20pF
VDD33
+2V
LVPECL
DUT
50Ω
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Clock Timing
Specifications
The system clock timing is shown in Figure 13 and described in Table 37.
Figure 13 System Clock Timing Diagram
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
Freescale Semiconductor, Inc...
SCLK
SCLKX
Tsc
Tsh
Tsl
CCLKn
TccN
Tcch
Tccl
Table 37 System Clock Timing Description
*
†
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
COMMENT
Tsc
System Cycle Time
3.76
ns
180MHz core clock
Tsh
Sys Clk High Pulse
45
55
Duty cycle*
Tsl
Sys Clk Low Pulse
45
55
Duty cycle*
Tcc0
CCLK0 Cycle Time
6.43
ns
†
Tcc1
CCLK1 Cycle Time
6.43
ns
†
Tcc2
CCLK2 Cycle Time
6.43
ns
†
Tcc3
CCLK3 Cycle Time
6.43
ns
†
Tcch
CCLKm High Time
40%
60%
% cycle pulse is high
Tccl
CCLKm Low Time
40%
60%
% cycle pulse is low
Pulse duty cycle measured at crossing voltage of SCLK/SCLKX
The frequencies specified for CCLK0 - CCLK3 allow full flexibility for the C-3e NP. It is also possible to use one
or more CCLKn inputs for other frequencies; contact your Motorola representative for more information.
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AC Timing Specifications
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CP Timing Specifications
81
This section describes the timing for the following CP interfaces:
•
•
•
•
•
DS1/DS3
10/100 Ethernet
Gigabit Ethernet
OC-3
OC-12
DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in Figure 14 and described in Table 38.
Figure 14 DS1/DS3 Ethernet Timing Diagram
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
CPn_0 (TCLK)
Tcdt
CPn_2/3 (Tx)
Tcdo
Cycle 2
Cycle 3
Cycle 5
Cycle 4
CPn_1 (RCLK)
Tcdr
CPn_4/5 (Rx)
Tcds
Tcdh
Table 38 DS1/DS3 Ethernet Timing Description
SYMBOL
PARAMETER
Tcdt
DS1/DS3 Transmit Cycle Time
Tcdo
DS1/DS3 Output Time
Tcdr
DS1/DS3 Receive Cycle Time
MIN
TYP
MAX
647/22.4
3.0/3.0
ns
400/15.0
647/22.4
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UNIT
ns
ns
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82
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Freescale Semiconductor, Inc...
Table 38 DS1/DS3 Ethernet Timing Description (continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tcds
DS1/DS3 Setup Time
2.0
ns
Tcdh
DS1/DS3 Hold Time
0
ns
10/100 Ethernet Timing Specifications
The 10/100 Ethernet interface timing is shown in Figure 15 and described in Table 39.
Figure 15 10/100 Ethernet Timing Diagram
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
CPn_0 (TCLK)
Tcet
CPn_2/3/6 (Tx)
Tceo
CPn_1/4/5 (Rx)
Tces
Tceh
Table 39 10/100 Ethernet Timing Description
*
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
TYP
MAX
Tcet
Transmit Cycle Time*
Tceo
Output Time
3.0
Tces
Setup Time
2.0
ns
Tceh
Hold Time
0
ns
20
UNIT
ns
15.0
ns
STD/Fast Ethernet
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AC Timing Specifications
83
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in
Table 40. The TBI interface timing is shown in Figure 16 and described in Table 41.
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
Freescale Semiconductor, Inc...
GMII / TBI Tx
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
CPn_0 (TCLK)
Tcgt
CPn_2-6 (Tx)
CPn+1_2-6 (Tx)
Tcgo
MII Tx
Cycle 1
Cycle 2
Cycle 3
MII CPn_1 (TCLKI)
Tcmt
MII CPn_2-6 (Tx)
Tcmo
TBI Rx
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 3
Cycle 4
Cycle 5
CPn+2_1 (RCLK)
CPn+3_1 (RCLKN)
Tctr
Tctd
CPn+2_2-6 (Rx)
CPn+3_2-6 (Rx)
Tcts
GMII/MII Rx
Cycle 1
Tcth
Cycle 2
CPn+2_1 (RCLK)
Tcgr
CPn+2_2-6 (Rx)
CPn+3_1-6 (Rx)
Tcgs
Tcgh
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84
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Freescale Semiconductor, Inc...
Table 40 Gigabit GMII/MII Ethernet Interface Timing Description
SYMBOL
GIGABIT
PARAMETER
Tcgt
Transmit Cycle Time, GMII
Tcgo
Output Time, GMII
Tcgr
Receive Cycle Time
Tcgs
Setup Time
2.0
ns
Tcgh
Hold Time
0.0
ns
Tcmt
Transmit Cycle Time, MII
Tcmo
Output Time, MII
MIN
TYP
MAX
UNIT
8.0
COMMENT
ns
3.0
6.0
ns
8.0
ns
40/400
2
ns
12
100BaseT/10BaseT
ns
Table 41 Gigabit TBI Interface Timing Description
*
C3ENPA1-DS/D REV 03
SYMBOL
TBI
PARAMETER
Tctt
Transmit Cycle Time
Tcto
Output Time
Tctr
Receive Cycle Time
Tctd
Rclk/Rclkn Deviation
Tcts
Setup Time
2.0
ns
Tcth
Hold Time
0.0
ns
MIN
TYP
MAX
TOL
8.0
3.0
UNIT
ns
6.0*
ns
16.0
ns
1.0
ns
For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns.
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AC Timing Specifications
85
OC-3 Timing Specifications
The OC-3 interface timing is shown in Figure 17 and described in Table 42.
Figure 17 OC-3 Timing Diagram
Cycle 2
Freescale Semiconductor, Inc...
Cycle 1
Cycle 3
Cycle 4
Cycle 5
CPn_2
Tc3t
CPn_3
Tc3i
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn_0
CPn_1
Tc3r
Tc3d
CPn_4
Tc3s
Tc3h
Tc3s
Tc3h
CPn_5
Table 42 OC-3 Timing Description
*
SYMBOL
PARAMETER
MIN
TYP
MAX
Tc3t
OC-3 Transmit Cycle Time
Tc3i
OC-3 Pulse Width
2.0
ns
Tc3r
OC-3 Receive Cycle Time*
6.0
ns
Tc3d
OC-3 Clock Duty Cycle
40
Tc3s
OC-3 Setup Time
2.0
ns
Tc3h
OC-3 Hold Time
0.0
ns
6.43
UNIT
ns
60
%
155.52MHz
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86
CHAPTER 3: ELECTRICAL SPECIFICATIONS
OC-12 Timing Specifications
The OC-12 interface timing is shown in Figure 18 and described in Table 43.
Figure 18 OC-12 Timing Diagram
Cycle 2
Freescale Semiconductor, Inc...
Cycle 1
Cycle 3
Cycle 4
Cycle 5
CPn_1 (TCLKI)
Tc12i
Tc12d
CPn_0 (TCLK)
Tc12t
CPn+1_2-5 (Tx)
Tc12o
Cycle 2
Cycle 1
Cycle 3
CPn_1 (RCLK)
Tc12r
CPn+2_2-6 (Rx)
CPn+3_2-5 (Rx)
Tc12s
Tc12h
Table 43 OC-12 Timing Description
*
†
‡
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
TYP
MAX
Tc12i
OC-12 Transmit Cycle Time*
Tc12d
OC-3 Clock Duty Cycle
Tc12t
OC-12 Transmit Cycle Time†
Tc12o
OC-12 Output Time‡
3.0
Tc12r
OC-12 Receive Cycle Time
12.0
Tc12s
OC-12 Setup Time
2.0
ns
Tc12h
OC-12 Hold Time
0.0
ns
12.86
40
ns
60
12.86
%
ns
10.0
12.86
UNIT
ns
ns
Input from PHY
Output from C-3e NP
Aligned to TCLK
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AC Timing Specifications
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Executive Processor
Timing Specifications
87
The XP timing specifications include:
•
•
•
•
PCI Timing Specifications
MDIO Serial Interface Timing Specifications
Low Speed Serial Interface Timing Specifications
PROM Interface Timing Specifications
PCI Timing Specifications
The PCI timing is shown in Figure 19 and described in Table 44.
Figure 19 PCI Timing Diagram
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
PCLK
Tpc
PAD/P_ctl
(output)
Tpao
Tpaz
Tpav
PAD/P_ctl
(input)
Tpas
Tpah
Tpgs
Tpgh
Tpis
Tpih
PGNTX
(input)
PIDSEL
(input)
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Freescale Semiconductor, Inc...
Table 44 PCI Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tpc
PCI Cycle Time*
15.0
ns
Tpas
PAD/P_ctl† Setup
3.0
ns
Tpah
PAD/P_ctl Hold
0.0
ns
Tpao
PAD/P_ctl Output
2.0
6.0
ns
Tpaz
PAD/P_ctl Clk to Tri‡
2.0
6.0
ns
Tpav
PAD/P_ctl Clk to Driven‡
2.0
6.0
ns
Tpgs
PGNTX Setup
5.1
ns
Tpgh
PGNTX Hold
0.0
ns
Tpis
PIDSEL Setup
3.0
ns
Tpih
PIDSEL Hold
0.0
ns
PRSTX**
ns
PINTA**
ns
*
66MHz PCI
P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX,
PSTOPX, PDEVSELX, PPERRX, PSERRX
‡ Not fully tested, values based on design/characterization.
** Asynchronous
†
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AC Timing Specifications
89
MDIO Serial Interface Timing Specifications
The MDIO serial interface timing is shown in Figure 20 and described in Table 45.
Figure 20 MDIO Serial Interface Timing Diagram
Freescale Semiconductor, Inc...
Cycle 2
Cycle 3
Cycle 4
SICL
Tsic
SIDA
(output)
Tsods
Tsodh
SIDA
(input)
Tsids
Table 45 MDIO Serial Interface Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
Tsic
SICL Cycle Time
40
ns
Tsids
SIDA Input Setup
10
ns
Tsidh
SIDA Input Hold
0.0
ns
Tsods
SIDA Output Setup
10
ns
Tsodh
SIDA Output Hold
10
ns
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90
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in Figure 21 and described in Table 46.
Freescale Semiconductor, Inc...
Figure 21 Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
SICL
Tslss
Tslhs
Tslhd
Tslsd
Tslc
Tslb
Tslst
SIDA
Table 46 Low Speed Serial Interface Timing Description
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
Tslc
SICL Cycle Time
2500
MAX
ns
Tslss
Set-up Time for Repeated START Condition
600
ns
Tslhs
Hold Time START Condition
600
ns
Tslsd
Data Set-up Time
250
ns
Tslhd
Data Hold Time
0.0
ns
Tslst
Set-up Time for STOP Condition
600
ns
Tslb
Bus Free Time Between a STOP and START Condition
1250
ns
Cmax
Capacitive load for each line of the bus
400
UNIT
pF
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AC Timing Specifications
91
PROM Interface Timing Specifications
The PROM interface timing is shown in Figure 22 and described in Table 47.
Figure 22 PROM Interface Timing Diagram
Freescale Semiconductor, Inc...
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
SPCK
Tspc
SPDI
Tspis
Tspih
SPLD
Tsplo
SPDO
Tspdo
Table 47 PROM Interface Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
Tspc
SPCK Cycle Time
40.0
ns
Tspis
SPDI Setup
10.0
ns
Tspih
SPDI Hold
0.0
ns
Tsplo
SPLD Output
Tsc
Tsc + 3.0
ns
Tspdo
SPDO Output
Tsc
Tsc + 3.0
ns
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UNIT
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92
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Fabric Processor Timing
Specifications
The FP timing specifications are shown in Figure 23 and described in Table 48.
Figure 23 Fabric Processor Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Freescale Semiconductor, Inc...
FRXCLK
Tfrc
FRXCTL
(output)
Tfrco
Tfrcv
Tfrcz
FRXCTL
(input)
Tfrcs
Tfrch
Tfrds
Tfrdh
FINn
FTXCLK
Tftc
FTXCTL
(output)
Tftco
Tftcv
Tftcz
FTXCTL
(input)
Tftcs
Tftch
FOUTn
Tftdo
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AC Timing Specifications
93
Freescale Semiconductor, Inc...
Table 48 Fabric Processor Timing Description
*
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tfrc
FRX Cycle Time
8.0
ns
Tfrcs
FRXCTL Setup
4.0
1.5
ns
Tfrch
FRXCTL Hold
0.0
ns
Tfrco
FRXCTL Output
1.0
4.0
ns
Tfrcz
FRXCTL Clk to Tri*
1.0
4.0
ns
Tfrcv
FRXCTL Clk to Driven*
1.0
4.0
ns
Tfrds
FIN Setup
4.0
1.5
ns
Tfrdh
FIN Hold
0.0
ns
Tftc
FTX Cycle Time
8.0
ns
Tftcs
FTXCTL Setup
4.0
1.5
ns
Tftch
FTXCTL Hold
0.0
ns
Tftco
FTXCTL Output
1.0
4.0
ns
Tftcz
FTXCTL Clk to Tri*
1.0
4.0
ns
Tftcv
FTXCTL Tri to Driven*
1.0
4.0
ns
Tftdo
FOUT Output
1.0
4.0
ns
COMMENT
Utopia2 Mode
All other modes
Utopia2 Mode
All other modes
Utopia2 Mode
All other modes
Not fully tested, values based on design/characterization.
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94
CHAPTER 3: ELECTRICAL SPECIFICATIONS
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BMU Timing
Specifications
The BMU timing specifications are shown in Figure 24 and described in Table 49.
The BMU synchronous DRAM interface is PC100-compliant and designed to work with
industry standard SDRAM components with 12 or fewer address lines. The information
below is intended to provide the output, setup, and hold data required to design this
interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 24 BMU Timing Diagram
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
MDCLK
Tmc
M_ctl
Tmco
MAn
Tmao
MDn
(output)
Tmdo
Tmdv
Tmdz
MDn
(input)
Tmds
Tmdh
Table 49 BMU Timing Description
*
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tmc
BMU Cycle Time
8.0
Tmco
BMU Ctrl Output
0.8
3.9
ns
Tmao
BMU Addr Output
0.8
3.9
ns
Tmds
BMU Data Setup
0.5
ns
Tmdh
BMU Data Hold
1.1
ns
Tmdo
BMU Data Output
0.8
4.5
ns
Tmdz
BMU Data Clk to Tri*
0.8
4.5
ns
Tmdv
BMU Data Clk to Driven*
0.8
4.5
ns
ns
Not fully tested, values based on design/characterization.
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AC Timing Specifications
95
Table 50 Signal Groups in BMU Timing Diagrams
INCLUDED SIGNALS
Control (M_ctl)
MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM, MDQML
Address (MAn)
MA0 - MA11
Data (MDn)
MD0 - MD129, MDECC0 - MDECC8
Freescale Semiconductor, Inc...
SIGNAL GROUP
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96
CHAPTER 3: ELECTRICAL SPECIFICATIONS
TLU Timing Specifications
The TLU timing specifications are shown in Figure 25 and described in Table 51.
Figure 25 TLU Timing Diagram
Cycle 2
Cycle 1
Cycle 3
Cycle 4
Cycle 5
Freescale Semiconductor, Inc...
TCLKI
Ttc
T_ctl
Ttco
TAn
Ttao
TDn
(output)
Ttdo
Ttdv
Ttdz
TDn
(input)
Ttds
Ttdh
Table 51 TLU Timing Description
*
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Ttc
TLU Cycle Time
8.0
Ttco
TLU Ctrl Output
0.8
3.9
ns
Ttao
TLU Addr Output
0.8
3.9
ns
Ttds
TLU Data Setup
1.0
ns
Ttdh
TLU Data Hold
1.2
ns
Ttdo
TLU Data Output
0.8
4.2
ns
Ttdz
TLU Data Clk to Tri*
0.8
4.2
ns
Ttdv
TLU Data Clk to Driven*
0.8
4.2
ns
ns
Not fully tested, values based on design/characterization.
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AC Timing Specifications
97
Table 52 Signal Groups in TLU Timing Diagrams
INCLUDED SIGNALS
Control (T_ctl)
TCE0X - TCE3X, TWE0X - TWE3X
Address (TAn)
TA0 - TA21
Data (TDn)
TD0 - TD63, TPAR0-3
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SIGNAL GROUP
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98
CHAPTER 3: ELECTRICAL SPECIFICATIONS
QMU SRAM (Internal
Mode) Timing
Specifications
The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and
described in Table 53.
Figure 26 QMU SRAM (Internal Mode) Timing Diagram
Cycle 2
Freescale Semiconductor, Inc...
Cycle 1
Cycle 3
Cycle 4
Cycle 5
QACLKI
Tqc
Q_ctl
Tqco
QAn
Tqao
QDn
(output)
Tqdo
Tqdv
Tqdz
QDn
(input)
Tqds
Tqdh
Table 53 QMU SRAM (Internal Mode) Timing Description
C3ENPA1-DS/D REV 03
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
COMMENT
Tqc
QMU Cycle Time
6.7
Tqco
QMU Ctrl Output
0.8
4.4
ns
Loading is 50Ω
transmission line.
Tqao
QMU Addr Output
0.8
4.4
ns
Loading is 50Ω
transmission line.
Tqds
QMU Data Setup
0.8
ns
Tqdh
QMU Data Hold
0.8
ns
Tqdo
QMU Data Output
0.9
ns
4.4
ns
Loading is 50Ω
transmission line.
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AC Timing Specifications
99
Freescale Semiconductor, Inc...
Table 53 QMU SRAM (Internal Mode) Timing Description (continued)
*
SYMBOL
PARAMETER
Tqdz
Tqdv
MIN
TYP
MAX
UNIT
QMU Data Clk to Tri* 0.9
4.4
ns
QMU Data Clk to
Driven*
4.4
ns
0.9
COMMENT
Not fully tested, values based on design/characterization.
Table 54 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
Control (Q_ctl)
QWEX
Address (QAn)
QA0-QA16
Data (QDn)
QD0-QD31, QDPL, QDPH
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100
CHAPTER 3: ELECTRICAL SPECIFICATIONS
QMU to Q-5/Q-3 (External
Mode) Timing
Specifications
The QMU to Q-5/Q-3 (External Mode) timing specifications are shown in Figure 27 and
describded in Table 55.
Figure 27 QMU to Q-5/Q-3 (External Mode) Timing Diagram
Cycle 2
Cycle 1
Freescale Semiconductor, Inc...
Tqec
QACLKI
Tqep
Tqep
QBCLKI
Tqec
DQDATA
Tqeh
Tqes
Tqeh
Tqes
Tqec
QACLKO
Tqep
Tqep
QBCLKO
Tqec
NQDATA
Tqeomax
Tqeomax
Tqeomin
Tqeomin
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AC Timing Specifications
101
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Table 55 QMU to Q-5/Q-3 (External Mode) Timing Description
SYMBOL
PARAMETER
MIN
Tqec
QMU External Cycle Time
Tqep
TYP
MAX
UNIT
COMMENT
10.0
ns
QACLKO/QBCLKO
derived from
QACLKI/QBCLKI
QMU CLKA-CLKB delta
between rising edges
4.8
ns
Tqes
QMU Input Data Setup
0.6
ns
Tqeh
QMU Input Data Hold
0.8
ns
Tqeo
QMU Data Output
-.85
1.3
ns
Determines valid time
for data from each clock
rising edge
Table 56 Signal Groups in QMU to Q-5/Q-3 (External Mode) Timimg Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
Input Clocks (QnCLKI)
QACLKI, QBCLKI
Output Clocks (QnCLKO)
QACLKO, QBCLKO
Input Data (DQDATA)
QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR
Output Data (NQDATA)
QA0-16, QWEX, QD24-31
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
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102
C3ENPA1-DS/D REV 03
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C3ENPA1-DS/D
Chapter 4
Rev 03
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MECHANICAL SPECIFICATIONS
Package Views
The C-3e network processor is an 728 pin (27 pins x 27 pins) Ball Grid Array (BGA) package
as shown in the following illustrations. Table 57 defines the package measurements.
Figure 28 C-3e Network Processor BGA Package Side View
A4 A2
A3
A
A1
Seating Plane
HiTCE: Green ceramic is thermally matched to FR4 circuit board.
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104
CHAPTER 4: MECHANICAL SPECIFICATIONS
Figure 29 C-3e Network Processor BGA Package (Bottom View)
D
D1
e
Freescale Semiconductor, Inc...
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
E1
b
1
C3ENPA1-DS/D REV 03
E
2
3
4 5
6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
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Package Views
105
Figure 30 C-3e Network Processor BGA (Top View)
Probe Pad
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Die
Optional
Capacitor
Pads
1.65
0.7
Optional
Capacitor
Pads
1.70
18ARS10518D001
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CHAPTER 4: MECHANICAL SPECIFICATIONS
Package Measurements
Table 57 defines the C-3e NP package measurements, providing nominal, minimum, and
maximum sizes where appropriate.
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Table 57 Package Measurements (Reference Figure 28, Figure 29 and Figure 30 for Symbols)
SYMBOL
DEFINITION
NOM. (MM)
MIN. (MM)
MAX. (MM)
A
Overall
3.11
2.83
3.39
A1
Ball height
0.70
0.6
0.8
A2
C4 and Die
0.86
A3
Body thickness
1.55
1.41
1.69
A4
Capacitor pad
D
Body size
29.00
D1
Ball footprint (X)
26.00
E
Body size
29.00
E1
Ball footprint (Y)
26.00
e
Ball pitch
1.00
b
Ball diameter
0.70
0.6
28.80
29.20
28.80
29.20
At Motorola’s discretion up to fourteen (14) capacitors may or may not be attached on
the top of the package.
Marking Codes
Table 58 explains the marking on the C-3e NP.
Table 58 C-3e Network Processor Marking Codes
MARKING (EXPLANATION OF CODES)
C3ENPA1-DS/D REV 03
Top
Logo/Part#/Date Code
Bottom
N/A
Pin 1 Marking
Chamfered Corner
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Reflow
Reflow
107
Typical Reflow Profile for the C-3e Switch Module comprises:
1 Follow the guidelines recommended by your solder paste supplier.
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Flux requirements must be met for best solderability.
2 The temperature profile should be carefully characterized to ensure uniform
temperature across the board and package.
Solder ball voiding may be affected by ramp rates and dwell times below and above
liquids.
3 A nitrogen atmosphere is not required, but will make the process more robust. It can
make a difference for marginally solderable PC board pads.
4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can
be used.
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CHAPTER 4: MECHANICAL SPECIFICATIONS
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C3ENPA1-DS/D REV 03
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INDEX
Channel Processors 22
Channel Processors Physical Interface Signals and Pins
Grouped by Clusters 33
Clock and Reference Signals 31
Clock Signals 31
Clock Timing Specifications 80
Configuration
10/100 Ethernet (RMII) 35
DS1/T1 Framer Interface 34
FibreChannel TBI 38
Gigabit Ethernet 38
Gigabit Ethernet (GMII) 36
SONET OC-12 Transceiver Interface 41
SONET OC-3 Transceiver Interface 40
Configurations
GMII/TBI Transmit and Receive Pin 36
CP Timing Specifications 81
Symbols
10/100 Ethernet (RMII) Configuration 35
10/100 Ethernet Signals 35
10/100 Ethernet Timing Description 82
10/100 Ethernet Timing Diagram 82
10/100 Ethernet Timing Specifications 82
A
Absolute Maximum Ratings 71
AC Timing Specifications 79
B
Block Diagram, C-3e Network Processor 20
BMU SDRAM Interface Signals 51
BMU Signal Groups 95
BMU Timing Description 94
BMU Timing Diagram 94
BMU Timing Specifications 94
Boundary Scan Cell Types 67
Boundary Scan Description Language 70
Bringup Clock Timing Diagram 74
Buffer Management Unit 24
D
C
C-3e Network Processor Absolute Maximum Ratings 71
C-3e Network Processor BGA Package, Bottom View 104
C-3e Network Processor BGA Package, Side View 103
C-3e Network Processor Capacitance Data 73
C-3e Network Processor DC Characteristics 73
C3e Network Processor Power and Thermal Characteristics 75
C-3e NP Channel Processors 22
Channel Processor Interface Signals 31
Data Registers
JTAG 67
DC Characteristics 73
Description
Functional 19
Description Language
Boundary Scan 70
Descriptions
Signal 27
Diagram
10/100 Ethernet Timing 82
BMU Timing 94
Bringup Clock Timing 74
DS1/DS3 Ethernet Timing 81
Fabric Processor Timing 92
Gigabit Ethernet (TBI) Timing 83
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INDEX
Low Speed Serial Interface Timing 90
MDIO Serial Interface Timing 89
OC-3 Timing 85
PCI Timing 87
Pinout 28
PROM Interface 46
PROM Interface Timing 91
QMU Timing 98
Signal Groups in BMU Timing 95
Signal Groups in QMU Timing 99
Signal Groups in TLU Timing 97
System Clock Timing 80
TLU Timing 96
Diagram, Block
C-3e Network Processor 20
DS1/DS3 Ethernet Timing Description 81
DS1/DS3 Ethernet Timing Diagram 81
DS1/DS3 Timing Specifications 81
DS1/T1 Framer Interface Configuration 34
DS1/T1 Framer Interface Signals 34
G
General System Interface Signal 48
Gigabit Ethernet (GMII) Configuration 36
Gigabit Ethernet (GMII) Signals
One Cluster Example 37
Gigabit Ethernet (TBI) Timing Description 84, 84
Gigabit Ethernet (TBI) Timing Diagram 83
Gigabit Ethernet and FibreChannel TBI Configuration 38
Gigabit Ethernet and FibreChannel TBI Signals
Example 38
Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 83
GMII/TBI Transmit and Receive Pin Configurations 36
I
IDcode Register 69
Instruction Register Instructions 69
J
E
Electrical Specifications 71
Absolute Maximum Ratings 71
Executive Processor 23
PCI 23
PROM Interface 24
Serial Bus Interface 23
System Interface Signals 43
System Interfaces 23
Executive Processor Timing Specifications 87
F
Fabric Interface Pin Mapping
Utopia2/Utopia3 ATM Mode 50
Utopia2/Utopia3 PHY Mode 50
Fabric Processor 24
Fabric Processor Interface Signals 49
Fabric Processor Timing Description 93
Fabric Processor Timing Diagram 92
Fabric Processor Timing Specifications 92
Functional Description 19
C3ENPA1-DS/D REV 03
JTAG Data Registers 67
JTAG Identification Code and Its Sub-components 69
JTAG Instruction Register 69
JTAG Internal Register Descriptions 67
JTAG Support
Pinouts 67
L
Low Speed Serial Interface Timing Description 90
Low Speed Serial Interface Timing Diagram 90
Low Speed Serial Interface Timing Specifications 90
LVPECL Specifications 30
LVTTL Specifications 30
M
MDIO Serial Interface Timing Description 89
MDIO Serial Interface Timing Diagram 89
MDIO Serial Interface Timing Specifications 89
Measurements
C-3e Network Processor 106
Mechanical Specifications 103
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INDEX
Miscellaneous Test Signals for JTAG, Scan, and Internal Test
Routines 57
Queue Management Unit 26
R
O
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Recommended Operating Conditions 72
Register
IDcode 69
JTAG Instruction 69
OC-12 Signals 41
OC-12 Timing Description 86
OC-12 Timing Specifications 86
OC-3 Signals 40
OC-3 Timing Description 85
OC-3 Timing Diagram 85
OC-3 Timing Specifications 85
Operating Conditions, Recommended 72
S
P
Package Measurements 106
PCI Signals 43
PCI Timing Description 88
PCI Timing Diagram 87
PCI Timing Specifications 87
Pin Descriptions
Grouped by Function 30
Pin Locations 28
Pin Number Signals Groups 58
Pinout Diagram 28
Power Sequencing 74, 75
Power Supply Signals 56
Processor, Executive 23
Processor, Fabric 24
PROM Interface Diagram 46
PROM Interface Signals 45
PROM Interface Timing Description 91
PROM Interface Timing Diagram 91
PROM Interface Timing Outline 47
PROM Interface Timing Specifications 91
Q
QMU Signal Groups 99
QMU SRAM (Internal Mode) Timing Diagram 98
QMU SRAM Interface Signals 54, 55
QMU Timing Description 98
QMU Timing Specifications 98
QMU to Q-5/Q-3 (External Mode) Timing Diagram 100
Serial Interface Signals 44
Serial Port Signals 44
Signal
General System Interface 48
Signal Descriptions 27
Signal Summary 27
Signals
10/100 Ethernet 35
BMU SDRAM Interface 51
Channel Processor Interface 31
Clock 31
Clock and Reference 31
DS1/T1 Framer Interface 34
Fabric Processor Interface 49
Grouped by Pin Number 58
OC-12 41
OC-3 40
PCI 43
Power Supply 56
PROM Interface 45
QMU SRAM Interface 54, 55
Serial Interface 44
Serial Port 44
Test 57
TLU SRAM Interface 53
SONET OC-12 Transceiver Interface Configuration 41
SONET OC-3 Transceiver Interface Configuration 40
Specifications
10/100 Ethernet Timing 82
AC Timing 79
BMU Timing 94
Clock Timing 80
CP Timing 81
DS1/DS3 Timing 81
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INDEX
Electrical 71
Executive Processor Timing 87
Fabric Processor Timing 92
Gigabit GMII Ethernet, TBI and MII Interface Timing
Specification 83
Low Speed Serial Interface Timing 90
MDIO Serial Interface Timing 89
Mechanical 103
OC-12 Timing 86
OC-3 Timing 85
PCI Timing 87
PROM Interface Timing 91
QMU Timing 98
TLU Timing 96
XP Timing 87
System Clock Timing Description 80
System Clock Timing Diagram 80
System Interfaces
Executive Processor 23
Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test
Routines 57
Timing Outline
PROM Interface 47
TLU Signal Groups 97
TLU SRAM Interface Signals 53
TLU Timing Description 96
TLU Timing Diagram 96
TLU Timing Specifications 96
Transceiver Interface Configuration
SONET OC-12 41
SONET OC-3 40
Transmit and Receive Pin Combinations for Gigabit Ethernet and
FibreChannel 36
U
Utopia2/Utopia3 ATM Mode, C-3e Network Processor to Fabric
Interface Pin Mapping 50
Utopia2/Utopia3 PHY Mode, C-3e Network Processor to Fabric
Interface Pin Mapping 50
T
Table Lookup Unit 25
Test Signals 57
C3ENPA1-DS/D REV 03
X
XP Timing Specifications 87
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Motorola, Inc. C-Port Family of Network Processors
120 Water Street, No. Andover, MA 01845 Voice: (978) 773-2300 FAX: (978) 773-2301
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