CAT93C46/56/57/66/86 "GREEN" PACKAGES -Lead free 1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM FEATURES ■ High speed operation: ■ Power-up inadvertant write protection ■ 1,000,000 Program/erase cycles – 93C56/57/66: 1MHz – 93C46/86: 3MHz ■ 100 year data retention ■ Low power CMOS technology ■ Commercial, industrial and automotive ■ 1.8 to 6.0 volt operation temperature ranges ■ Selectable x8 or x16 memory organization ■ Sequential read (except CAT93C46) ■ Self-timed write cycle with auto-clear ■ Program enable (PE) pin (CAT93C86 only) ■ Hardware and software write protection ■ Available in new lead-free packages DESCRIPTION The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46/56/ 57/66/86 are manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages. PIN CONFIGURATION DIP Package (P, L) CS SK 1 2 8 7 DI DO 3 4 6 5 VCC NC (PE*) VCC NC (PE*) CS ORG GND TSSOP Package (U,Y) SOIC Package (J,W) SOIC Package (S,V) SOIC Package (K,X) SK 1 2 8 7 3 4 6 5 ORG GND DO DI CS SK 1 2 8 7 DI DO 3 4 6 5 VCC CS NC (PE*) SK ORG DI GND DO 1 2 8 7 3 4 6 5 VCC NC (PE*) ORG GND CS SK DI DO *Only For 93C86 1 2 3 4 8 7 6 5 VCC NC (PE*) ORG GND 93C46/56/57/66/86 F01 PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 6.0V Power Supply GND Ground ORG Memory Organization NC No Connection PE* Program Enable Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization. © 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice. BLOCK DIAGRAM VCC ORG GND MEMORY ARRAY ORGANIZATION ADDRESS DECODER DATA REGISTER OUTPUT BUFFER DI CS PE* SK MODE DECODE LOGIC CLOCK GENERATOR DO 93C46/56/57/66/86 F02 Doc. No. 1023, Rev. D 93C46/56/57/66/86 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias .................. -55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts Latch-Up JEDEC Standard 17 100 mA ILTH (3)(4) Typ Max Units D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol Parameter Test Conditions ICC1 Power Supply Current (Operating Write) ICC2 Max Units fSK = 1MHz VCC = 5.0V 3 mA Power Supply Current (Operating Read) fSK = 1MHz VCC = 5.0V 500 µA ISB1 Power Supply Current (Standby) (x8 Mode) CS = 0V ORG=GND 10 µA ISB2(5) Power Supply Current (Standby) (x16Mode) CS=0V ORG=Float or VCC 0 µA ILI Input Leakage Current VIN = 0V to VCC 1 µA ILO Output Leakage Current (Including ORG pin) VOUT = 0V to VCC, CS = 0V 1 µA VIL1 Input Low Voltage 4.5V≤VCC<5.5V -0.1 0.8 V VIH1 Input High Voltage 2 VCC+1 V VIL2 Input Low Voltage 0 VCCX0.2 V VIH2 Input High Voltage VCCX0.7 VCC+1 V VOL1 Output Low Voltage 4.5V≤VCC<5.5V 0.4 V VOH1 Output High Voltage IOL = 2.1mA IOH = -400µA VOL2 Output Low Voltage 1.8V≤VCC<2.7V VOH2 Output High Voltage IOL = 1mA IOH = -100µA 1.8V≤VCC<2.7V Min Typ 2.4 V 0.2 VCC-0.2 V V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Standby Current (ISB2)=0µA (<900nA) for 93C46/56/57/66, (ISB2)=2µA for 93C86. Doc. No. 1023, Rev. D 2 93C46/56/57/66/86 PIN CAPACITANCE Symbol COUT (3) CIN(3) Test Conditions OUTPUT CAPACITANCE (DO) INPUT CAPACITANCE (CS, SK, DI, ORG) Min Typ Max Units VOUT=0V 5 pF VIN=0V 5 pF INSTRUCTION SET Instruction Device Type READ ERASE WRITE EWEN EWDS ERAL WRAL Start Opcode Bit Address x8 x16 Data x8 x16 PE(2) Comments 93C46 93C56(1) 93C66 93C57 93C86 1 1 1 1 1 10 10 10 10 10 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 Read Address AN–A0 93C46 93C56(1) 93C66 93C57 93C86 1 1 1 1 1 11 11 11 11 11 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 Clear Address AN–A0 93C46 93C56(1) 93C66 93C57 93C86 1 1 1 1 1 01 01 01 01 01 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 93C46 93C56 93C66 93C57 93C86 1 1 1 1 1 00 00 00 00 00 11XXXXX 11XXXX 11XXXXXXX 11XXXXXX 11XXXXXXX 11XXXXXX 11XXXXXX 11XXXXX 11XXXXXXXXX 11XXXXXXXX Write Enable 93C46 93C56 93C66 93C57 93C86 1 1 1 1 1 00 00 00 00 00 00XXXXX 00XXXX 00XXXXXXX 00XXXXXX 00XXXXXXX 00XXXXXX 00XXXXXX 00XXXXX 00XXXXXXXXX 00XXXXXXXX Write Disable 93C46 93C56 93C66 93C57 93C86 1 1 1 1 1 00 00 00 00 00 10XXXXX 10XXXX 10XXXXXXX 10XXXXXX 10XXXXXXX 10XXXXXX 10XXXXXX 10XXXXX 10XXXXXXXXX 10XXXXXXXX Clear All Addresses 93C46 93C56 93C66 93C57 93C86 1 1 1 1 1 00 00 00 00 00 01XXXXX 01XXXX 01XXXXXXX 01XXXXXX 01XXXXXXX 01XXXXXX 01XXXXXX 01XXXXX 01XXXXXXXXX 01XXXXXXXX X I D7-D0 D7-D0 D7-D0 D7-D0 D7-D0 D15-D0 D15-D0 D15-D0 D15-D0 D15-D0 Write Address AN–A0 I X X I D7-D0 D7-D0 D7-D0 D7-D0 D7-D0 D15-D0 D15-D0 D15-D0 D15-D0 D15-D0 Write All Addresses I Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands. (2) Applicable only to 93C86 (3) This parameter is tested initially and after a design or process change that affects the parameter. 3 Doc. No. 1023, Rev. D 93C46/56/57/66/86 A.C. CHARACTERISTICS (93C56/57/66) Limits VCC = 1.8V-6V* VCC = 2.5V-6V Max Min Min tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns VIL = 0.45V tDIS DI Setup Time 400 200 100 ns VIH = 2.4V tDIH DI Hold Time 400 200 100 ns CL = 100pF tPD1 Output Delay to 1 1 0.5 0.25 µs VOL = 0.8V tPD0 Output Delay to 0 1 0.5 0.25 µs tHZ(1) Output Delay to High-Z 400 200 100 ns VOH = 2.0v CL = 100pF tEW Program/Erase Pulse Width 10 10 10 ms tCSMIN Minimum CS Low Time 1 0.5 0.25 µs tSKHI Minimum SK High Time 1 0.5 0.25 µs tSKLOW Minimum SK Low Time 1 0.5 0.25 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency DC Min 0.5 250 DC 500 DC Max Test SYMBOL PARAMETER 1 Max VCC = 4.5V-5.5V UNITS Conditions 0.25 µs 1000 kHz CL = 100pF * Preliminary data for 93C56/57/66 A.C. CHARACTERISTICS (93C46/86) Limits VCC = 1.8V-6V* VCC = 2.5V-6V Max Min Min tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns VIL = 0.45V tDIS DI Setup Time 200 100 50 ns VIH = 2.4V tDIH DI Hold Time 200 100 50 ns CL = 100pF tPD1 Output Delay to 1 1 0.5 0.15 µs VOL = 0.8V tPD0 Output Delay to 0 1 0.5 0.15 µs tHZ(1) Output Delay to High-Z 400 200 100 ns VOH = 2.0v CL = 100pF tEW Program/Erase Pulse Width 5 5 5 ms tCSMIN Minimum CS Low Time 1 0.5 0.15 µs tSKHI Minimum SK High Time 1 0.5 0.15 µs tSKLOW Minimum SK Low Time 1 0.5 0.15 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency DC Min 0.5 500 DC 1000 DC NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1023, Rev. D 4 Max Test SYMBOL PARAMETER 1 Max VCC = 4.5V-5.5V UNITS 0.1 µs 3000 kHz Conditions CL = 100pF 93C46/56/57/66/86 DEVICE OPERATION the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The CAT93C46/56(57)66/86 is a 1024/2048/4096/ 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46/56/ 57/66/86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions for 93C46; seven 10-bit instructions for 93C57; seven 11-bit instructions for 93C56 and 93C66; seven 13-bit instructions for 93C86; control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions for 93C46; seven 11-bit instructions for 93C57; seven 12-bit instructions for 93C56 and 93C66: seven 14-bit instructions for 93C86; control the reading, writing and erase operations of the device. The CAT93C46/56/57/66/86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. Instructions, addresses, and write data are clocked into Figure 1. Sychronous Data Timing tSKLOW tSKHI tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0,tPD1 DO tCSMIN DATA VALID 93C46/56/57/66/86 F03 Figure 2a. Read Instruction Timing (93C46) SK tCS CS STANDBY AN DI DO 1 1 AN–1 A0 0 HIGH-Z tPD0 tHZ HIGH-Z 0 DN DN–1 D1 D0 93C46/56/57/66/86 F04 5 Doc. No. 1023, Rev. D 93C46/56/57/66/86 the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/ /7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86) (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Note: This note is applicable only to 93C86. The Write, Erase, Write all and Erase all instructions require PE=1. If PE is left floating, 93C86 is in Program Enabled mode. For Write Enable and Write Disable instruction PE=don’t care. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/busy status of the CAT93C46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C46/ 56/57/66/86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1) After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the CAT93C46/56/66/86 will automatically increment to Figure 2b. Read Instruction Timing (93C56/57/66/86) SK 1 1 1 1 1 AN AN–1 1 1 1 1 1 1 1 1 1 1 CS Don't Care DI 1 1 A0 0 HIGH-Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCS AN DI 1 0 AN-1 A0 DN D0 1 tSV DO STANDBY STATUS VERIFY CS tHZ BUSY HIGH-Z READY HIGH-Z tEW 93C46/56/57/66/86 F05 Doc. No. 1023, Rev. D 6 93C46/56/57/66/86 Erase Erase All Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/ busy status of the CAT93C46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/busy status of the CAT93C46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase/Write Enable and Disable Write All The CAT93C46/56/57/66/86 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46/56/57/66/86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/ busy status of the CAT93C46/56/57/66/86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Note 1: This note is applicable only to the CAT93C46. After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the self-timed high voltage cycle. This is important because if the CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Figure 4. Erase Instruction Timing SK STATUS VERIFY CS AN DI 1 1 tCS A0 AN-1 STANDBY 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW 93C46/56/57/66/86 F06 7 Doc. No. 1023, Rev. D 93C46/56/57/66/86 Figure 5. EWEN/EWDS Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE=11 DISABLE=00 93C46/56/57/66/86 F07 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS DI 1 0 0 0 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW 93C46/56/57/66/86 F08 Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS DI 1 0 0 0 DN 1 D0 tSV tHZ DO BUSY READY HIGH-Z tEW 93C46/56/57/66/86 F09 Doc. No. 1023, Rev. D 8 93C46/56/57/66/86 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 93C46 Product Number 93C46: 1K 93C56: 2K 93C57: 2K 93C66: 4K 93C86: 16K Suffix S I Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C) E = Extended (-40˚C to + 125˚C) Package P = PDIP S = SOIC (JEDEC) J = SOIC (JEDEC) K = SOIC (EIAJ) U = TSSOP M= MSOP** L = PDIP (Lead free) V = SOIC, JEDEC (Lead free) W= SOIC, JEDEC (Lead free) X = SOIC, EIAJ (Lead free) Y = TSSOP (Lead free) -1.8 TE13 Tape & Reel TE13: 2000/Reel Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V) Notes: (1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) 9 Doc. No. 1023, Rev. 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Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 1023 D 08/28/02 Final