Revised December 2001 CD4047BC Low Power Monostable/Astable Multivibrator General Description The CD4047B is capable of operating in either the monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor (between pins 2 and 3) to determine the output pulse width in the monostable mode, and the output frequency in the astable mode. Astable operation is enabled by a high level on the astable input or low level on the astable input. The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components. A frequency twice that of Q is available at the Oscillator Output; a 50% duty cycle is not guaranteed. Monostable Multivibrator Features ■ Positive- or negative-edge trigger ■ Output pulse width independent of trigger pulse duration ■ Retriggerable option for pulse width expansion ■ Long pulse widths possible using small RC components by means of external counter provision ■ Fast recovery time essentially independent of pulse width ■ Pulse-width accuracy approaching 100% maintained at Monostable operation is obtained when the device is triggered by LOW-to-HIGH transition at + trigger input or HIGH-to-LOW transition at − trigger input. The device can be retriggered by applying a simultaneous LOW-to-HIGH transition to both the + trigger and retrigger inputs. ■ Free-running or gatable operating modes A high level on Reset input resets the outputs Q to LOW, Q to HIGH. ■ Good astable frequency stability duty cycles Astable Multivibrator Features ■ 50% duty cycle ■ Oscillator output available typical= ±2% + 0.03%/°C @ 100 kHz frequency= ±0.5% + 0.015%/°C @ 10 kHz deviation (circuits trimmed to frequency VDD = 10V ±10%) Features ■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VDD (typ.) Applications ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS • Frequency discriminators • Timing circuits • Time-delay applications Special Features ■ Low power consumption: special CMOS oscillator configuration ■ Monostable (one-shot) or astable (free-running) operation • Envelope detection • Frequency multiplication • Frequency division ■ True and complemented buffered outputs ■ Only one external R and C required Ordering Code: Order Number Package Number Package Description CD4047BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4047BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS005969 www.fairchildsemi.com CD4047BC Low Power Monostable/Astable Multivibrator October 1987 CD4047BC Connection Diagram Pin Assignments for SOIC and DIP Top View Function Table To VDD Function Terminal Connections Output Pulse To VSS From Input Pulse To Typical Output Period or Pulse Width Astable Multivibrator Free-Running 4, 5, 6, 14 7, 8, 9, 12 10, 11, 13 tA(10, 11) = 4.40 RC True Gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13 tA (13) = 2.20 RC Complement Gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13 Positive-Edge Trigger 4, 14 5, 6, 7, 9, 12 8 10, 11 Negative-Edge Trigger 4, 8, 14 5, 7, 9, 12 6 10, 11 Retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11 Monostable Multivibrator External Countdown (Note 1) 14 5, 6, 7, 8, 9, 12 Figure 1 Figure 1 Note 1: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3. Typical Implementation of External Countdown Option tEXT = (N − 1) tA + (tM + tA/2) FIGURE 1. www.fairchildsemi.com 2 tM (10, 11) = 2.48 RC Figure 1 CD4047BC Block Diagram Logic Diagram *Special input protection circuit to permit larger input-voltage swings. 3 www.fairchildsemi.com CD4047BC Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 3) (Note 3) −0.5V to +18VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5V to VDD +0.5VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −40°C to +85°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) Note 3: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15VDC Input Voltage (VIN) DC Electrical Characteristics (Note 3) Symbol IDD VOL VOH VIL VIH IOL IOH Parameter Quiescent Device Current LOW Level Output Voltage HIGH Level Output Voltage LOW Level Input Voltage Min Max 25°C Min Typ 85°C Max Min Max Units VDD = 5V 20 20 150 µA VDD = 10V 40 40 300 µA VDD = 15V 80 80 600 µA |IO| < 1 µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V |IO| < 1 µA VDD = 5V 4.95 4.95 5 4.95 V VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 VDD = 5V, VO = 0.5V or 4.5V 14.95 1.5 15 2.25 14.95 1.5 V 1.5 V VDD = 10V, VO = 1V or 9V 3.0 4.5 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 VDD = 10V, VO = 1V or 9V 7.0 7.0 5.5 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V LOW Level Output Current VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level Output Current VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 HIGH Level Input Voltage (Note 4) IIN −40°C Conditions Input Current mA VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10−5 0.3 1.0 µA Note 4: IOH and IOL are tested one output at a time. www.fairchildsemi.com V 4 (Note 5) TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise specified. Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tTHL, tTLH tWL, tWH tRCL, tFCL CIN Typ Max Propagation Delay Time Astable, Parameter VDD = 5V 200 400 ns Astable to Osc Out VDD = 10V 100 200 ns VDD = 15V 80 160 ns VDD = 5V 550 900 ns VDD = 10V 250 500 ns VDD = 15V 200 400 ns VDD = 5V 700 1200 ns VDD = 10V 300 600 ns VDD = 15V 240 480 ns VDD = 5V 300 600 ns VDD = 10V 175 300 ns VDD = 15V 150 250 ns VDD = 5V 300 600 ns VDD = 10V 125 250 ns ns Astable, Astable to Q, Q + Trigger, − Trigger to Q + Trigger, Retrigger to Q Reset to Q, Q Transition Time Q, Q, Osc Out Minimum Input Pulse Duration Conditions Min Units VDD = 15V 100 200 VDD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns Any Input VDD = 5V 500 1000 ns VDD = 10V 200 400 ns VDD = 15V 160 320 ns + Trigger, Retrigger, Rise and VDD = 5V 15 µs Fall Time VDD = 10V 5 µs VDD = 15V 5 µs 7.5 pF Average Input Capacitance Any Input 5 Note 5: AC Parameters are guaranteed by DC correlated testing. 5 www.fairchildsemi.com CD4047BC AC Electrical Characteristics CD4047BC Typical Performance Characteristics Typical Q, Q, Osc Out Period Accuracy vs Supply Voltage (Astable Mode Operation) f Q, Q R Typical Q, Q, Pulse Width Accuracy vs Supply Voltage Monostable Mode Operation C tM R C 22k 10 pF A 2 µs 100 kHz 22k 100 pF B 7 µs 22k 100 pF 10 kHz 220k 100 pF C 60 µs 220k 100 pF D 1 kHz 220k 1000 pF D 550 µs 220k 1000 pF E 100 Hz 2.2M 1000 pF E 5.5 ms 2.2M 1000 pF A 1000 kHz B C Typical Q, Q and Osc Out Period Accuracy vs Temperature Astable Mode Operation f Q, Q R 22k 10 pF Typical Q and Q Pulse Width Accuracy vs Temperature Monostable Mode Operation tM C R C 22k 10 pF A 2 µs 100 kHz 22k 100 pF B 7 µs 22k 100 pF 10 kHz 220k 100 pF C 60 µs 220k 100 pF 1 kHz 220k 1000 pF D 550 µs 220k 1000 pF A 1000 kHz B C D Note: Minimum Value of R: 10 K Ω Maximum Value of R: 1 Meg Ω Minimum Value of C for Astable Mode: 100 pF Minimum Value of C for Monostable Mode: 1000 pF www.fairchildsemi.com 6 22k 10 pF CD4047BC Typical Performance Characteristics (Continued) Timing Diagrams Astable Mode Monostable Mode Retrigger Mode 7 www.fairchildsemi.com CD4047BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 8 CD4047BC Low Power Monostable/Astable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com