LM98555 CCD Driver General Description The LM98555 is a highly integrated driver circuit intended for CCD driving applications. It combines 25 drivers of varying drive strengths into one chip to provide a complete CCD driving solution. Due to this one-chip integration, optimal skew control is achieved for this demanding application. Features n All CCD drivers integrated into one package n High strength drivers designed specifically for CCD loads n Ability to scale clock driver strength n Skew specifications guaranteed n Separate input and output power supplies n CMOS process technology n 64-pin TSSOP package with extended power handling capability Key Specifications Supply Voltage Maximum Output Skew Inputs 3.0 to 5.5V Drivers 4.5 to 5.8V Between P1A and P2A outputs Maximum Power Dissipation 0.5 ns 2.0W Functional Description 20126401 FIGURE 1. Functional Block Diagram TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201264 www.national.com LM98555 CCD Driver February 2006 LM98555 Ordering Information Commercial Temperature Range NS Package LM98555CCMH 64-Pin Exposed Pad TSSOP Connection Diagram 20126402 FIGURE 2. TSSOP Package Pinout www.national.com 2 LM98555 Pin Descriptions Symbol Pin Type Description 8 Input CMOS logic input for the P2B driver. RSIN 9 Input CMOS logic input for the RS driver. CPIN 10 Input CMOS logic input for the CP driver. P1AIN 15 Input CMOS logic input for the P1A ganged (8) driver set. P2AIN 18 Input CMOS logic input for the P2A ganged (8) driver set. SHIN 21 Input CMOS logic input for the SH ganged (3) driver set. AFEIN 22 Input CMOS logic input for the AFE driver. MCLIN 23 Input CMOS logic input for the MCL driver. SHDIN 24 Input CMOS logic input for the SHD driver. SHDOUT 28 Output; Low-Strength Driver output for the SHDIN input signal. MCLOUT 30 Output; Low-Strength Driver output for the MCLIN input signal. AFEOUT 31 Output; Low-Strength Driver output for the AFEIN input signal. CPOUT 2 Output; Low-Strength Driver output for the CPIN input signal. Typically used to drive the Clamp Gate input of the CCD. RSOUT 3 Output; Low-Strength Driver output for the RSIN input signal. Typically used to drive the Reset Gate input of the CCD. P2BOUT 5 Output; Low-Strength Driver output for the P2BIN input signal. P2AOUT0 47 P2AOUT1 46 P2AOUT2 43 Output; TRI-STATE ® ; High-Strength P2AOUT3 42 Ganged driver outputs for the P2AIN input. Typically the user may join together these outputs to drive the φ2 clock input of the CCD. Some of these outputs may be disabled using the EN(1:0) inputs - see the Functional Description section. P2AOUT4 39 P2AOUT5 38 P2AOUT6 35 P2AOUT7 34 P1AOUT0 50 P1AOUT1 51 P1AOUT2 54 Output; TRI-STATE; High-Strength P1AOUT3 55 Ganged driver outputs for the P1AIN input. Typically the user may join together these outputs to drive the φ1 clock input of the CCD. Some of these outputs may be disabled using the EN(1:0) inputs - see the Functional Description section. P1AOUT4 58 P1AOUT5 59 P1AOUT6 62 P1AOUT7 63 Output; Low-Strength Ganged driver outputs for the SHIN input signal. Typically used to drive the Shift Gate input of the CCD. Driver inputs P2BIN Driver Outputs SHOUT0 26 SHOUT1 27 SHOUT2 6 Logic Inputs EN0 11 EN1 12 Input Driver enable control. Some of the P1A and P2A drivers can be disabled using these inputs. See the Functional Description section. 3 www.national.com LM98555 Pin Descriptions Symbol Pin (Continued) Type Description Power & Ground Pins VDDI 14 16 20 Power VDD for pre-drivers. VDDO 1 7 29 32 37 40 45 49 53 57 60 Power VDD for final-stage driver. GNDI 13 17 19 Ground Ground connection for all circuitry other than the Final-Stage Drivers. GNDO 4 25 33 36 41 44 48 52 56 61 64 Ground Ground connection for the Final-Stage Drivers. www.national.com 4 Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage −0.5V to 6.2V Package Power Rating at 25˚C (Note 2) Voltage on Any Input or Output Pin +3.0V to +5.5V Supply Voltage VDDO +4.5V to +5.8V 0 to 70˚C Operating Frequency −0.5V to VDD+0.5V 30 MHz Power Dissipation (Note 3) 2.0W 25 mA DC Package Input Current Storage Temperature Supply Voltage VDDI Ambient Temperature (TA) 2.0 Watts DC Input Current at Any Pin LM98555 Absolute Maximum Ratings (Note 1) 50 mA −65˚C to +150˚C Package Thermal Resistances Lead temperature (Soldering, 10 sec.) 300˚C ESD Susceptibility θJ-A (Note 4) Package Human Body Model 2000V Machine Model θJ-PAD (Thermal Pad) 64-Lead Exposed Pad TSSOP 36.8˚C / W 6.2˚C / W 200V DC Electrical Characteristics The following specifications apply for GND = 0V, VDDI = 3.3V, VDDO = 5.0V, unless noted otherwise. Boldface limits apply for TA= TMIN to TMAX; all other limits TA= 25˚C Symbol II VIT Parameter Conditions Min Typical Max Units Logic 1 Input Current VI = VDDI -1 0.004 1 µA Logic 0 Input Current VI = GNDI -1 0.006 1 µA Input Threshold VDDI = 3.3V 1.41 1.57 1.75 V 100 mV 100 mV 6.1 9.9 Ω 10.2 17.4 Ω Input Threshold VDDI = 5.0V Input Threshold Hysteresis VDDI = 3.3V -72 ∆VIT Input Threshold Variation Between P1A, P2A inputs -100 RO Output Impedance P1A and P2A Outputs ILOAD = 525 mA 2.48 RO = (VDDO - VO)/IOH or 11 V RO = VO/IOL RO Output Impedance All Other Outputs ILOAD = 280 mA RO = (VDDO - VO)/IOH or RO = VO/IOL AC Electrical Characteristics The following specifications apply for GND = 0V, VDDI = 3.3V, VDDO = 5.0V, unless noted otherwise. Boldface limits apply for TA= TMIN to TMAX; all other limits TA= 25˚C Symbol Parameter Conditions Min Typical Max Units 3.06 4.6 6.55 ns tPHL Prop Delay: High-to-Low P1A and P2A Outputs CL = 220 pF, RL = 10Ω (Note 5) tPHL Prop Delay: High-to-Low CP, RS, P2B Outputs CL = 82 pF, RL = 10Ω (Note 5) (Note 7) tPLH Prop Delay: Low-to-High P1A and P2A Outputs CL = 220 pF, RL = 10Ω (Note 6) tPLH Prop Delay: Low-to-High CP, RS, P2B Outputs CL = 82 pF, RL = 10Ω (Note 6) (Note 7) 4.2 tSKEW Prop Delay Skew High-to-Low Between any P1A or P2A Outputs on a Single Unit CL = 220 pF, RL = 10Ω 109 387 157 490 Prop Delay Skew Low-to-High 4.1 3.38 4.9 ns 6.68 ns ns ps Important Note: Not all drivers can be loaded to the highest specified load at the same time without violating the maximum power dissipation limit. The system design must guarantee that the maximum power dissipation specification is never exceeded. 5 www.national.com LM98555 AC Electrical Characteristics (Continued) Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: Package power rating assumes the exposed thermal pad is soldered to the printed circuit board as recommended, with significant heat spreading provided by vias to internal or bottom heat dissipation planes or pad. If this is not the case, then the package power rating should be reduced. See the Thermal Guidelines in the applications section for more information. Note 3: This is the power dissipated on-chip due to all currents flowing through the device - both DC and AC. This operating condition will be violated if all driver outputs are fully loaded and operating at the same time at the rated FMAX. The system design must constrain the chip’s operating conditions (loads, power supply, number of parallel drivers enabled, frequency of operation) to make certain that this limit is never exceeded. Note 4: Package thermal resistance for junction to ambient is based on a 5.5 inch by 3 inch, 4 layer printed circuit board, with thermal vias connecting the heat sinking pad to a full internal ground plane. Tests were done in still air, with a power dissipation of 2.0 W, at an ambient temperature of 22˚C. Note 5: Propagation Delay High-to-Low with output low trigger voltage at VDDO*0.75. Note 6: Propagation Delay Low-to-High with output high trigger voltage at VDDO*0.25. Note 7: Typical values determined from characterization testing only. Not production tested or guaranteed. Test Conditions 20126403 FIGURE 3. AC Test Conditions www.national.com 6 LM98555 Application Information The LM98555 is a fully integrated clock driver/buffer for high speed CCD applications. It provides high performance low impedance drivers, with optimized low skew performance of the P1 and P2 outputs. Enable inputs allow use of two, four, six, or all eight P1 and P2 drivers to optimize the amount of drive for the application. The 64 pin thermally enhanced TSSOP provides excellent power handling through the use of an exposed heat transfer pad on the underside of the package. THERMAL GUIDELINES The LM98555’s maximum power dissipation limit, shown in the Operating Conditions section, must be strictly adhered to. The product’s multiple high-strength drivers, with their ability to drive a wide-range of loads, make it possible to be within spec on each output and yet violate the aggregate maximum power dissipation limit for the total product. Special caution must be paid to this by limiting the chip’s operating conditions (loads, power supply, number of parallel drivers enabled, frequency of operation) to make certain that the maximum power dissipation limit is never exceeded. Thermal characterization of the device has been done to provide reference points under specific conditions. θ junction to ambient was measured using a 5.5 inch by 3 inch, 4 layer PCB. The thermal contact pad on the board was connected using vias to a full ground plane on one of the internal layers. The recommended thermal pad is shown in Figure 4. 20126406 FIGURE 4. Exposed Pad Land Pattern The vias shown provide a path for heat to flow from the pad to a heat sinking or dissipating area of the printed circuit board. The following figures show several typical examples of how this can be done, and illustrate how heat is conducted away from the IC to larger areas where it is dissipated. 20126407 FIGURE 5. 4 Layer PCB - Example 1 20126409 FIGURE 6. 4 Layer PCB - Example 2 20126408 FIGURE 7. 2 Layer PCB In multi-layer board applications, one or more internal planes are usually dedicated as a ground plane. Connecting the thermal pad to this ground plane with vias will usually provide adequate heat management. In 2 layer boards, it is 7 www.national.com LM98555 Application Information used in series with each output to provide good matching to the trace characteristic impedance. The resistors should be located as close as possible to each output pin. If multiple outputs will be combined to drive a single load pin, the output signals should be combined after the termination resistors. This will provide the best summing of adjacent outputs. The combined signal should then pass through an EMI type ferrite bead. This component can be selected to change the bandwidth or shape of the clocking signal to achieve the best CCD transfer efficiency. Several other techniques will also help maintain signal quality, and minimize timing differences between critical signals. Vias should not be used for critical timing signals. These can add impedance discontinuities that will affect the waveform quality. Traces should have gradual bends and avoid sharp changes in direction that can also introduce impedance discontinuities. (Continued) important to provide a large heat spreading pad on the opposite side of the board. The vias will provide a good thermal connection between the pad under the IC, and the heat spreading pad on the bottom of the board. Thermal modelling can be done using the θ junction to pad information provided, to calculate the required area of copper based on the ambient temperature of the system, and the calculated amount of thermal dissipation in the LM98555. POWER DISSIPATION The amount of power dissipated in the device can be determined by considering the following factors: • Power dissipated delivering energy to the load capacitance • Power dissipated delivering energy to parasitic capacitance • Power dissipated due to leakage in the IC SELECTIVE DRIVER ENABLING With the Enable pins, the user has the capability to enable only the drivers that are required for the application, thus eliminating unnecessary outputs switching. The following table shows the details. The amount of power dissipated due to leakage is very small in this CMOS device. Most of the power will be due to the load capacitance being switched, with a small additional amount caused by the parasitic capacitance of the output circuitry, output pins, and PCB traces. A typical parasitic capacitance would be on the order of 5 pF. Since the load capacitance will be on the order of 100 pF or more, this usually dominates the power dissipation calculation. The following equation can be used to calculate the power dissipation due to capacitive switching of the loads: P = Sum[Output Frequency x Load Capacitance x Output Voltage Squared] (summed for all outputs) EN1 EN0 INPUT SIGNALS Care should be taken to match the trace lengths between timing signals that require low skew. Usually, the P1A and P2A signals will be the most critical. In some applications, the timing of P2B with respect to P1A and P2A can also be important, and that input trace should also be carefully designed. Trace shape and width should also be carefully controlled. The trace geometry will determine the characteristic impedance of each trace. The impedance should be set to give reasonable immunity to noise coupling into the trace. With a known trace impedance, the signals can be terminated using a series resistor at the source that is equal to the characteristic impedance. This will provide a signal with minimum overshoot and ringing, and will contribute to better performance of the final signal reaching the CCD. 0 P1Aout(1:0) and P2Aout(1:0) are enabled; all others disabled. 0 1 P1Aout(3:0) and P2Aout(3:0) are enabled; all others disabled. 1 0 P1Aout(5:0) and P2Aout(5:0) are enabled; all others disabled. 1 1 All P1Aout and P2Aout drivers are enabled. Note: The disabled drivers’ outputs are in TRI-STATE. POWER AND GROUND - PLANES VERSUS BUSES The best performance will be achieved by using planes rather than traces for power and ground. Planes provide lower electrical and thermal impedance. Ground bounce and ringing are reduced, electromagnetic emissions are minimized and the best thermal performance will be realized. A single common ground plane should be used for all power and signal domains. Another circuit board layer can be used to provide power to the various circuitry. Different power buses can be provided by isolated planes within this layer of the circuit board. EMI MANAGEMENT Good EMI control will be achieved by addressing the following items: • Provide proper source termination of output signals OUTPUT CONNECTIONS AND LOADING EXAMPLES The LM98555 can be used with a wide variety of different CCD sensors. The P1Aoutx and P2Aoutx outputs can be selectively enabled to provide 2, 4, 6, or 8 drivers. This allows the available drive strength to be optimized for the sensor and application. Connecting multiple outputs together in parallel as shown in the typical application circuit provides lower drive impedance as needed to suit the load being driven. When driving smaller loads, lower switching noise will be generated if the minimum necessary outputs are enabled and used. The output signal traces should also be designed for a known impedance. Source terminating resistors should be www.national.com Driver-set State 0 • • • • • 8 Limit length of output traces Ensure adequate power supply decoupling Provide power and ground planes as much as possible Provide common ground plane for all signals, especially between LM98555 outputs and load CCD Enable and use the minimum number of outputs needed LM98555 CCD Driver Physical Dimensions inches (millimeters) unless otherwise noted 64-TSSOP NS Package Number MXD64A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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