ETC DDX4100

DDX-4100
DDX Multichannel
Digital Audio Processor
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
SOURCE-TO-SPEAKER INTEGRATED
DIGITAL AUDIO SOLUTION w/DDX-2060
Power IC’s
DIGITAL PREAMP FUNCTIONS:
•
Digital Volume Control
•
Bass and Treble
•
Parametric EQ on each Channel
•
Bass Management for LFE Channel
•
Soft Mute
•
Automatic mute for Zero Inputs
4+1 CHANNELS DDX PROCESSING
STEREO S/PDIF INPUT INTERFACE
4 CHANNEL PROGRAMMABLE SERIAL
INPUT INTERFACE
6 CHANNEL PROGRAMMABLE SERIAL
OUTPUT INTERFACE
Intel AC’97 LINK (rev.2.1) INPUT INTERFACE
for AUDIO AND CONTROL
AUTOMATIC INPUT SAMPLING
FREQUENCY DETECTION AND SAMPLE
RATE CONVERTER
I2C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
EXTERNAL INPUT CLOCK OR BUILT-IN
XTAL OSCILLATOR
DIGITAL GAIN CONTROL; UP TO 24dB @
0.75dB/STEP
GENERAL DESCRIPTION
The DDX-4100 Digital Audio Processor is a single
chip device for implementing complete digital
solutions for audio amplification. In conjunction with
multiple DDX-2060 Power IC’s, the solution provides
a full digital, multi-channel, high quality, power
processing chain without the need of Digital-to-Analog
converters between the DSP and power amplifier.
The device supports two input configurations, AC’97
input mode or IIS/SPDIF input mode, with the
selection made via a dedicated pin (AC97_MODE
pin).
The AC’97 input mode can be configured to work in
either a ‘Fully Compliant’ mode or a ‘Proprietary’
mode. The selection of this compliance mode is made
in a Vendor Reserved register. The ‘Fully Compliant’
mode conforms to rev 2.1 of AC’97 specification. The
‘Proprietary’ mode enables additional features not
found in the ‘Fully Compliant’ mode. The link supports
up to 6 input channels with discrete sampling
frequencies of 44.1, 48, 88.2, or 96 kHz.
DDX-4100 BLOCK DIAGRAM
LRCK1/SYNC
3
BICKI/BIT CL
4
SDI 1/AC97 OUT
SDI 2/AC97 IN
RXP
RXN
1
2
18
19
SA
SCL
SDA
11
10
9
2
2
IS
IC
ROM
S/PDI
SRC
DDX
RAM
AC’97
PowerDown
PLL
7
14
XTI
15
XTO
43
CKOUT
129 Morgan Drive, Norwood MA 02062
voice: (888) 3APOGEE fax: (781) 440-9528
Copyright Apogee Technology, Inc 2000, 2001
(All Rights Reserved)
LEFT A
LEFT B
28
27
34
33
RIGHT A
24
RIGHT B
SLEFT A
SLEFT B
SRIGHT A
23
22
SRIGHT B
21
LFE B
36
40
LRCK0
37
SDO 1
38
39
SDO 2
35
EAPD
DSP
I2S
RESET
30
29
LFE A
BICKO
SDO 3
44
PWDN
1
www.apogeeddx.com
December 2001
DOC # 04010001-05
DDX-4100
GENERAL DESCRIPTION (continued)
In the IIS/SPDIF mode, a stereo S/PDIF and a 4 channel three-wire programmable serial input interface
support any sampling frequency in the continuous range from 32 to 96 KHz. The programmable serial
interface supports up to four channels including the standard IIS protocol. Operation of the S/PDIF or the
IIS inputs is mutually exclusive.
An embedded high quality sample rate converter (SRC) re-samples input data at the internal fixed
sampling frequency of 48 kHz for DSP operations. The DSP is a 20 x 20 bit core audio processor
performing several user controlled parametric algorithms, among them are static equalization, Bass,
Treble, Volume control and more. The DSP operates at 49.152MHz (1024xfs). This frequency is
generated by an internal PLL with programmable multiplication factor (x2 or x8) in conjunction with the
built-in oscillator or an external clock input.
The device includes 5 channels of Direct Digital Amplification (DDX™), providing PWM output signals
used to directly drive external high efficiency class-D power bridge stages (DDX-2060). Additionally, a
programmable 6-channel digital output interface (supporting IIS standard protocol) is embedded for
applications with standard audio D/A converters. The output sampling frequency is fixed at 48 kHz when
the interface operates as a master. An over-sampling clock (256xfs or 512xfs) is provided for external
D/A converters.
An IIC interface allows programming of internal algorithms and control registers via an external controller.
Arbitration logic handles access conflicts to embedded control registers (which may occur as a
consequence of simultaneous access to control registers by Aclink, IIC and DSP blocks).
LRCKO
EAPD
SLEFT_A
41 40
SDO_1
GND_5
42
SDO_2
VDD_5
43
39 38
37
36
35
34
SDO_3
CKOUT
44
SCKO
PWDN
PIN CONNECTION (Top View)
4
30
LEFT_A
VDD_1
5
29
LEFT_B
GND_1
6
28
RIGHT_A
RESET
7
27
RIGHT_B
AC97_MODE
8
26
VDD_3
SDA
9
25
GND_3
SCL
10
24
SRIGHT_A
SA
11
23
SRIGHT_B
15 16
17 18
RXP
14
VCC
13
GND_2
12
19
20
21
22
LFE_A
GND_4
BICKI/BIT_CLK
LFE_B
31
VSS
3
RXN
VDD_4
LRCKI/SYNC
XTO
SLEFT_B
32
XTI
33
2
VDD_2
1
SDI_2/SDATA_IN
TEST_MODE
SDI_1/SDATA_OUT
2
Details and Specifications are subject to change without notice
DDX-4100
PIN FUNCTION
PIN
NAME
1
SDl_1/SDATA_
OUT
2
SDl_2/SDATA_I
N
3
LRCKI/SYNC
TYPE
I
I/O
I/O
4
5
6
7
BICKI/BIT_CLK
VDD_1
GND_1
RESET
I/O
8
AC97_Mode
I
9
10
11
12
SDA
SCL
SA
N/C
I/O
I
I
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VDD_2
XTI
XTO
GND_2
VCC
RXP
RXN
VSS
LFE_B
LFE_A
SRIGHT_B
SRIGHT_A
GND_3
VDD_3
RIGHT_B
RIGHT_A
LEFT_B
LEFT_A
GND_4
VDD_4
SLEFT_B
SLEFT_A
EAPD
36
37
38
39
40
41
42
43
44
LRCKO
SDO_1
SDO_2
SDO_3
BICKO
GND_5
VDD_5
CKOUT
PWDN
I
I
O
I
I
O
O
O
O
O
O
O
O
O
O
O
I/O
O
O
O
I/O
O
I
Table1
DESCRIPTION
Input I2S Serial Data 1/AC97 Output Data
(I2S mode maps to L,R DDX)
Input I2S Serial Data 2/AC97 Input Data
(I2S mode maps to LS,RS DDX)
Input I2S Left/Right Clock/AC97 Synch.
Clock
Input I2S Serial Clock/AC97 Bit Clock
Digital Supply Voltage
Digital Ground
Global Reset (Active Low) This pin
is sensed only after 2 clock cycles
AC97 Enable/Disable (1=AC97;
0=I2S/SPDIF)
I2C Serial Data
I2C Serial Clock
Select Address (I2C/AC97)
Connect to ground or Leave open
Digital Supply Voltage
Crystal Oscillator Input (Clock Input)
Crystal Oscillator Output Do Not Load
Digital Ground
Analog Supply Voltage
S/PDIF receiver positive (L,R DDX)
S/PDIF receiver negative (L,R DDX)
Analog Ground
Pwm LFE (subwoofer) channel output (B)
Pwm LFE (subwoofer) channel output (A)
Pwm Surround right channel output (B)
Pwm Surround right channel output (A)
Digital Ground
Digital Supply Voltage
Pwm Right channel output (B)
Pwm Right channel output (A)
Pwm Left channel output (B)
Pwm Left channel output (A)
Digital Ground
Digital Supply Voltage
Pwm Surround Left channel output (B)
Pwm Surround Left channel output (A)
External Amplifier Power down (Active
Low)
I2S Left/Right Clock
I2S Serial Data 1 Output (L,R)
I2S Serial Data 2 Output (LS,RS)
I2S Serial Data 3 Output (C,SUB)
I2S Serial Clock
Digital Ground
Digital Supply Voltage
Clock Output (256fs or 512fs)
Device Power down (Active Low)
OUTPUT DRIVE
2mA
2mA
4mA
CMOS Schmitt
In Pull-Up
CMOS Schmitt
In Pull-Down
2mA
CMOS In PullDown
Analog IN
Analog In
Analog In
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
2mA
2mA
2mA
2mA
4mA
8mA
CMOS In PullUp
3
Details and Specifications are subject to change without notice
DDX-4100
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Power Supply
Vi
Voltage on input pins
Vo
Voltage on output pins
Tstg
Storage Temperature
Ta
Ambient operating temperature
Value
-0.3 to 4
-0.3 to VDD+0.3
-0.3 to VDD+0.3
-40 to +150
-20 to +85
Unit
V
V
V
°C
°C
Value
85
Unit
°C/W
THERMAL DATA
Symbol
Parameter
Rθj-a
Thermal resistance Junction to Ambient
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
VDD
Power Supply Voltage
Tj
Operation Junction Temperature
Value
3.0 to 3.6V
-20 to 125 °C
ELECTRICAL CHARACTERISTICS (VDD= 3.3±0.3V; Ta=0 to 70°C; unless otherwise specified)
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Iil
Low Level Input Current
Vi – 0V
-10
Without pull-up/dn device
Iih
High Level Input Current
Vi – VDD = 3.6V
-10
Without pull-up/dn device
Vesd
Electrostatic Protection
Leakage < 1µA
2000
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test
Condition
Vil
Low Level Input Voltage
Vih
High Level Input Voltage
Vol
Low Level Output
IoI = X mA
Voltage
Voh
High Level Output
Voltage
Ipu
Pull-up current
Vi = 0V;
VDD = 3.3V
Rpu
Equivalent Pull-up
resistance
Tr
Reset Active Time
Tck
Master Clock Period
Typ.
Min.
Max.
10
Unit
µA
10
µA
1
V
2
Typ.
Max.
Unit
Note
0.2*VDD
V
V
V
3
V
3
µA
4
0.8*VDD
0.4*VDD
0.85*VDD
-26
-66
Note
1
-125
50
kohm
2*Tck
20.345
ns
ns
Note 1: See Table 1 for input pins with pull-up/dn
Note 2: Human Body Model
Note 3: X is the source/sink current under worst-case conditions and is reflected in the name of the I/O cell according
to the drive capability, see Table 1 for values.
Note 4: Min condition: VDD = 2.7V; Max condition: VDD = 3.6 V
DIGITAL CHARACTERISTICS – S/PDIF RECEIVER (RXP, RXN pins only)
Symbol
Parameter
Test Condition
Min. Typ.
Vth
Vhyst
Differential input voltage
Input Hysteresis
200
50
Max.
Unit
Note
mV
mV
4
Details and Specifications are subject to change without notice
DDX-4100
2.0
AC’97 REGISTER BANK OVERVIEW
The AC’97 interface is compliant with ‘Audio Codec ’97 – Revision 2.1’ specification in terms of the
protocol used. All of the registers described in this specification, including Standard, Vendor Reserved
and Extended Audio (AC’97 2.0) registers, are available in the device, however, only relevant registers
(which are described in paragraph 12, Register Summary) are implemented.
2.1
Reading AC’97 Registers
The AC’97 register bank is implemented as a contiguous RAM space, from a DSP point of view, as the
result of a read operation the content of the RAM itself will be returned. This should be followed as the
general rule, but in some cases an alternate approach is required. The following is a list of the registers
and bits where an alternate approach is required;
•
CodecID_0, CodecID_1:
These two bits are bits D14 and D15 of registers 28h (Extended Audio ID) and 3Ch (Extended
Modem ID). When a read operation of these registers is performed the returned value is dependent
on the status of the SA pin: CodecID_0 reports the status of SA pin, CodecID_1 always reports 0.
Other bits of these registers return the related RAM register contents. Also note that the status of the
SA pin is not readable by the DSP.
•
PR4
Bit D12 of register 26h (Power down, ctrl/start) is used to set the AC’97 D_CLK and SDATA_IN signal
to a low state. In response to a warm reset the status of this bit is set back to its default 0 value. In
response to a read request the actual value of this signal is returned, not the RAM content. Due to
this, the RAM register content can be inconsistent.
•
Regs. 2Ch, 2Eh and 30h (Audio Sample Rate Control):
These three registers are used to setup the sample rate when the Variable Rate Mode is enabled. In
response to a read request on one of these registers, the actual value returned can be either BB80h
or AC44h, depending on the status of an internal hardware signal. The status of this signal is updated
every time a write operation into one of these registers is performed.
Using the AC97_FC_MODE configuration bit the interface can be configured in Fully Compliant mode
(default). In this mode the value returned as a response to a read operation will be properly masked in
order to set ‘reserved’ bits to 0, per the specification. This operation is performed on all registers
including the Standard or Extended Audio address space. If the Full-Compliant mode is not selected the
full 16 bits of data from the corresponding RAM register will be returned with no further manipulation.
If an odd-addressed register reading operation is performed the following scheme is adopted:
•
•
•
Slot 0:
Slot 1 (address):
Slot 2 (data):
report valid bit set to 1 for both slot 1 and slot 2
report the odd address
report all 0s
2.2 Writing AC’97 Registers
When a write operation into one of the available AC’97 registers is performed the entire 16 bit data word
is written into the addressed RAM register (also reserved bits are passed through). Some bits of some
registers may have corresponding hardware registers (Flip-Flops), used to control the internal status of
the device. In this case the value of the FF is also updated every time a write to the related RAM register
is performed. The status of the FF’s are reset to their default values after either a hardware or software
reset (writing to reg. 00h) request has been issued; in which case the DSP will also have to reload the
RAM register contents.
Some registers have a different behavior from the one depicted above and are summarized below.
5
Details and Specifications are subject to change without notice
DDX-4100
•
Regs. 7Ch and 7Eh:
These are the Vendor ID1 and ID2 registers. Any write request to one of these will be ignored.
•
Regs. 28h:
The ‘Extended Audio ID Register’ is read only. Therefore, any write request will be ignored.
•
Regs. 26h:
When a write request is issued the actual data written into the RAM register is
“xxxxxxxxxxxx1110’, where ‘x’ represents the incoming data.
•
Regs. 2Ah:
When a write request is issued the actual data written into the RAM register is
‘xxxxxx0111xxxxxx’, where ‘x’ represents the incoming data.
•
Regs. 32h and 34h:
Any write request into one of these sample rate registers will result in the value BB80h written into
the corresponding RAM register.
3.0 I2S INPUT INTERFACE CONFIGURATION
To configure the I2S input interface the Configuration Register B (CRB) is used. Using the three
I2S1_Align_x bits, one of the seven configuration modes can be selected. Table 2 describes each of
them.
Table 2
Mode
# of Slots
W. Length
Alignment
Delay Slot
Notes
0
32
24
Left
No
1
32
24
Left
Yes
2
32
16
Right
No
MSb first only
3
32
24
Right
No
4
24
24
Left
No
Slave only
5
Not Valid
Not Valid
Not Valid
Not Valid
Reserved, do not use
6
24
16
Right
No
MSb first only. Slave only
7
24
24
Right
No
Slave only
By default the standard I2S input interface slave is provided (mode 1 in bits D0, D1,and D2 of register
CRB, I2SS_BICK_POL = 1 and I2SI_LRCK_Pol = 0)
3.0 I2S Input switching characteristics (10pF load, Fsm = 32 to 96kHz)
Refer to Figure 1.
BICKI FREQUENCY (master mode)
BICKI FREQUENCY (slave mode)
BICKI pulse width low (T0) (slave mode)
BICKI pulse width high (T0) (slave mode)
BICKI active to LRCKI edge delay (T2)
BICKI active to LRCKI edge delay (T3)
SDI valid to BICKI active setup (T4)
BICKI active to SDI hold time (T5)
BICKI falling to LRCKI edge (T6) (master mode)
BICKI falling to LRCKI edge (T6) (master mode)
3.072MHz
6.4MHz max.
40ns min.
40ns min.
20ns min.
20ns min.
20ns min.
20ns min.
3ns min.
9ns max.
6
Details and Specifications are subject to change without notice
DDX-4100
T2
T3
LRCKI
T1
T6
T0
BICKI
T4
SDI
T5
Figure 1: Input switching characteristics
4.0 I2S OUTPUT INTERFACE CONFIGURATION
To configure the I2S output interface the Configuration Register B (CRB) is used. Using the three
I2SO_Align_x bits one of the seven configuration modes can be selected. Table 3 describes each of
them.
Table 3
Mode
# of Slots
W. Length
Alignment
Delay Slot
Notes
0
32
24
Left
No
1
32
24
Left
Yes
2
32
16
Right
No
MSb first only
3
32
24
Right
No
4
24
24
Left
No
Slave only
5
Not Valid
Not Valid
Not Valid
Not Valid
Reserved, do not use
6
24
16
Right
No
MSb first only. Slave only
7
24
24
Right
No
Slave only
By default the standard I2S output interface master is provided (mode 1 in bits D8, D9 and D10 of register
CRB, I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register).
4.1 I2S Input switching characteristics (10pF load, Fsm = 48kHz) Refer to Figure 2
BICKO Frequency (master mode)
BICKO Frequency (slave mode)
BICKO pulse width low (T0) (slave mode)
BICKO pulse width high (T0) (slave mode)
BICKO active to LRCKO edge delay (T2)
BICKO active to LRCKO edge delay (T3)
SDO valid to BICKO active setup (T4)
BICKO active to SDO hold time (T5)
BICKO falling to LRCKO edge (T6) (master mode)
BICKO falling to LRCKO edge (T6) (master mode)
BICKO falling to SDO edge (T7) (master mode)
BICKO falling to SDO edge (T7) (master mode)
BICKO falling to SDO edge (T7) (slave mode)
BICKO falling to SDO edge (T7) (slave mode)
64*Fsm
64*Fsm
40ns min.
40ns min.
20ns min.
20ns min.
20ns min.
20ns min.
2ns min.
8ns max.
2ns min.
8ns max.
6ns min.
17ns max.
7
Details and Specifications are subject to change without notice
DDX-4100
T2
T3
LRCKO
T1
T6
T0
BICKO
T4
SDO
T5
T7
Figure 2: I2S Input switching characteristics
5.0 SAMPLE RATE CONVERTER
The sample rate converter re-samples the selected input data source in order to send to the DSP an
audio stream with a fixed frequency of 48 KHz. Figure 1 shows the basic architecture.
Interpolation
FIR x2
DA TA_IN
2 x Fs
Fs
Interpolation
FIR x2
Anti-A lias
FILT
4xFs or 2xFs
Sinc 6
Async.
DA TA_OUT
48KH z
Fs
Thresh.
Se lector
LRCK_IN
DRLL
RA TIO
Figure 3: Sample Rate Converter
The threshold selector block makes the selection between a X2 Fir interpolation and direct anti-aliasing
Filter on the input data automatically. If the input sampling frequency, (measured by DRLL), is higher
than the SRC threshold (see Table 5 in section 12.9), the direct initializing filter is selected, otherwise if
the input frequency is lower than the SRC threshold, the X2 FIR filter is added to the data path. A 1kHz
hysteresis is fixed around the SRC threshold nominal values of Table 5 section 12.9, to prevent unstable
settings.
8
Details and Specifications are subject to change without notice
DDX-4100
6.0 DAP INPUT STAGE
The device provides three mutually exclusive input interfaces: I2S, S/PDIF and AC’97. Their
configuration is shown in Figure 4.
I2C
I2S_SPDIF_Sel
LRCK
I2S
SRC_Bypass
SRC
S/PDIF
DSP
YRAM
AC97
AC97_Sel
LEFT
LEFT
RIGHT
RIGHT
SL/CENTER
PLL_Factor
PLL_Bypass
YRA
DDX
SL/CENTER
SR
S
CENTE
CENTE
LF
LFE
PLL
MCK
I2S
LRCK
/1024
XTI
/2 or /8
CK_OUT
Figure 4: DAP Input Stage
6.1
Input from I2S
Using this input interface a maximum of 4 channels can be sent to the DSP. This I/F can be configured
as either master or slave. When the master the sampling frequency is fixed to 48 kHz, the SRC can be
by passed using the SRC_Bypass configuration bit. If slave operation is selected the full range between
32kHz and 96kHz is supported but the SRC must always be in the processing path (no bypass). In order
to select this interface the AC97_Mode pin must be tied to GND and the I2S_SPDIF_Sel must be 0.
The DDX-4100 includes a double-buffering feature to adapt the phase of the incoming serial data to the
internal data frame. Double-buffering is enabled by setting Bit D1 in the Configuration Register A,
address 0x5B. Enabling this function requires that the incoming data rate is exactly equal to the internal
data rate, e.g. for a synchronous application using an ADC. If the nominal data input frequency and the
internal data frequency are not exactly the same, this function will not properly work and samples will be
lost causing performance degradation. It is not recommended to use this feature when the SRC is
enabled.
Input Rate : | L0 | R0 | L1 | R1 | L2 | R2 | ...
Output Rate : |
|
| L0 | R0 | L1 | R1 | L2 | R2 | ...
6.2
Input from S/PDIF
This interface is compliant with the AES/EBU IEC 958, S/PDIF and EIA CP-340/1201 professional and
consumer standards. The full range from 32 kHz up to 96 kHz is supported but the SRC bypass option
must be switched off. Using the SPDIF_Mode bit this interface can be configured as a digital or an
analog input. If the analog mode is selected the line receiver can decode differential as well as single
9
Details and Specifications are subject to change without notice
DDX-4100
ended inputs. The receiver consists of a differential input Schmitt Trigger comparator with 50mV of
hysteresis to prevent noise from corrupting the recovered data. The minimum input signal is 200 mV. If
the digital mode is selected only single ended operation is supported; the input signal must comply with
the input voltage specifications in DC ELECTRICAL CHARACTERISTICS. In order to select this interface
the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel must be 1.
6.3
Input from AC’97
To select this interface the AC97_MODE pin must be tied to VDD (I2S_SPDIF_Sel is don’t care). The
AC’97 interface can be configured either as the primary or secondary device using the external
configuration pin SA. This interface supports four discrete sampling frequencies, according to the
Variable and Double Rate Audio Codec ’97 specification. Table 6 summarizes the slot usage for each
one of these frequencies and Table 7 summarizes the different input configurations
Freq.
Slot 3
Slot4
Slot 6
Slot 7
Table 6
Slot 8 Slot 9
48
44.1
88.2*
Left
Left
Left
Right
Right
Right
Center
Surr.L
Surr.L
Surr.R
Surr.R
96
Left
Right
Slot 10
Slot 11
Slot 12
Center
Left (n+1)
Right (n +1)
Center
Left (n+1)
Right (n+1)
Center
(n+1)
Center
(n+1)
LFE
*Slots 3, 4 and 6 are always requested. Slots 10, 11, and 12 are requested only when needed
Input from
Channels
I2S (Master)
I2S (Slave)
S/PDIF
AC’97
AC’97
AC’97
AC’97
4
4
2
6
3
4
3
Table 7
Available Freq.
Bypass
(KHz)
48
Yes
32..96
No
32..96
No
48
Yes*
96
No
44.1 (VRA)
No
88.2 (VRA)
No
Notes
Bypass is user selectable
Left, Right, SL, SR, Center, LFE
Left, Right, Center
Left, Right, SL, SR
Left, Right, Center
*In this configuration the BYPASS is always active, regardless of the state (status) of SRC_Bypass bit in reg. 5Ah
7.0
PLL
To generate the required internal 49.152 MHz clock a low-jitter PLL has been included in the device. It
can be configured to work with a multiplication factor of either x8 or x2, in order to fit an external
frequency reference of 6.144 MHz or 24.576 MHz respectively. To select the multiplication factor the
PLL_Factor bit is used. Using PLL_Bypass bit the PLL section can be bypassed, allowing direct
connection of the internal clock to the XTI pin. When this option is selected the PLL is automatically
powered-down and an external frequency of 49.152 MHz needs to be provided to the device. .
8.0
POWER DOWN MANAGEMENT
The power down capability and its logic behavior is shown in Figure 3 – Powerdown management. There
are three powerdown requests that are external to the device that will cause a power down condition:
•
External PWDN pin – this signal will turn-off the device, which will enter the power down mode (all
the device clocks are stopped). The device will exit this state as soon as the PWDN pin is deasserted.
10
Details and Specifications are subject to change without notice
DDX-4100
•
PR5 bit (reg. 26h, bit D13) – Setting this bit will cause a partial power down of the device, with all
the clocks suspended except those that are required to keep the AC97 and I2C cells alive. In this
way, using either of these input interfaces makes it possible to resume from this state simply by
resetting the PR5 bit.
•
EAPD bit (reg. 26h, bit D15) – The External Amplifier Power Down bit controls the state of the
related pin (EAPD), which in turn, is used to switch off the external power device.
DSP
Requests
LR
LFE
SL
LR: Reg 02h bit 15
LFE: reg 36h bit 15
SR: reg 39h bit 07
SL: reg 38h bit 15
SR
EAPD pin
(active LOW)
EAPD
reg 26h, bit 15
Chip
powerdown
PWDN
Internal CK
Disable
reg 7EFh, bit 0
PR5
reg 26h, bit 13
Figure 6: Power Down Management
To avoid any extraneous noise while switching between the various powerdown modes, a masking
technique has been adopted to drive the actual controlling signals. As shown in Figure 3 a powerdown
request will instruct the DSP to perform a volume fade-out and MUTE of all channels. The external power
device will also be turned off (via the EAPD pin) not only as a consequence of an EAPD request, but also
as a consequence of a PR5 or PWDN request, preventing any possible noise.
9.0
BASS MANAGEMENT AND EQ
The DDX-4100 has the ability to redirect sound to the SBW,(subwoofer), channel and to pass each
channel through a 4 stage cascaded 2nd order IIR filter. With the combination of the DDX
gain/compressor (CRA register bits 2-3) a dynamic EQ can be implemented. Additionally, a special SideFiring sound can be achieved by enabling this feature available with the ready-made filter topology on the
surround channels.
11
Details and Specifications are subject to change without notice
DDX-4100
L
LR Filter
L
C
Phantom
(IIS C)
R
LR Filter
R
LS
Sur Filter
LS
RS
Sur Filter
RS
Scale
RS
Scale
LS
Scale
R
Scale
C
Scale
L
+
SBW
Filter
LFE
SBW
Sca
le
Figure 7: Bass Redirection
9.1
Bass Redirection
There is an option to redirect each input channel to the SBW output channel. The scaling factor of each
channel can be set with values between 0 (no redirection) to – 1 (full redirection). See Paragraph 10 for
more information about setting the scaling factor registers. This redirection takes place when bit D0 of the
Bass Management Register (add. 72h) is set (see section 12.12).
Together with the static EQ option, described in the following section, and by setting the appropriate
filters, a full bass management solution is available. Note that C and LFE channels are available only with
six channel AC97 input. Four channel I2S INPUT has only L, R, LS and RS. Two channel S/PDIF input
has only L and R.
9.2
Input
Static EQ
Scale in
Factor
Biquad0
Biquad1
Biquad2
Biquad3
Output
Figure 8: Static EQ Biquads
Each channel has a 4-stage cascaded filter of 2nd order bi-quad sections. Each filter’s coefficients are
user definable (see paragraph 10.0). The coefficients for the Left and Right channels are common, as
are the coefficients for the surrounds. There is also an input-scaling factor for each channel, which can
be set with values from 0 to –1. The scaling factor must be set to an appropriate value to prevent the
filters from saturating.
The Static EQ filters are activated by the Static EQ and Side Firing registers (address 70h, see section
12.11).
12
Details and Specifications are subject to change without notice
DDX-4100
9.3 Surround Side Firing
Instead of the normal filters described in the previous section above, a special topology is available for
the surround channels:
Left Surround
Input
Left Surround
Output
Scale
in
Right Surround
Input
Scale
in
biquad
biquad
biquad
biquad
biquad
biquad
biquad
biquad
+
and Phase
Inverting
Right Surround
Output
+
Figure 6
Figure 9: Side Firing connections for Surround channels
By designing appropriate filters, special surround sound can be achieved where surround speakers are
located next to the front speakers and rotated to the sides. By setting Static EQ and Side Firing (address
70h, section 12.11), this Side Firing topology is enabled.
10.0 EQ AND BASS MANAGEMENT COEFFICIENT HANDLING
In order to implement the Static EQ filters and the Bass management, a RAM space for user coefficients
has been included in this device. Beginning with address 240h (YRAM), there are 69 x 20 bit registers
available for this purpose. To read or write into these registers the application software must follow an
indirect addressing approach. As shown in Figure 8, there are two AC’97 dedicated registers, (4 x 8 bit
registers for I2C addressing), to access the coefficient table. In register 78h (78h + 79h in I2C addressing)
the 16 low bits of the coefficient are stored either by the user for a write operation, or by the internal logic
for a read operation. The upper 4 bits are stored in the lowest nibble of register 7Ah (7Bh in I2C
addressing). The address of the coefficient on which the R/W operation must be performed is stored in
the high byte of register 7Ah. The address is derived by adding the coefficient index to the base location
40h.
To select between Read or Write operation the ‘R’ bit in register 7Ah (7Bh in I2C addressing) must be
properly setup. The actual read/write operation will start after register 7Ah (7Bh in I2C addressing) has
been written. The following explains this in more detail:
Coefficient registers usage
AC’97
78h
7
8
7Ah
h
I2C
78h
79h
7Ah
7Bh
Bit 15
Bit 0
Coefficient (15..0)
Coeff. Address (8 bits)
R-x-x-x
Coefficient (19..16)
R: set this bit to 1 for reading, 0 for writing a coefficient.
13
Details and Specifications are subject to change without notice
DDX-4100
10.1 Reading a Coefficient Value
Depending on the bus used to read the coefficient, the following steps must be executed:
•
•
Reading from AC’97
o Write 8 bit INDEX 40h and R/W bit at AC’97 address 7Ah
o Read 16 lower data bits at AC’97 address 78h
o Read 4 upper data bits at AC’97 address 7Ah
Reading From I2C
o Write 8 bit address at I2C address 7Ah coefficient INDEX + 40h
o Write R/W bit at I2C address 7Bh
o Read 8 middle data bits at I2C address 78h
o Read 8 lower data bits at I2C address 79h
o Read 4 upper data bits at I2C address 7Bh
10.2 Writing a Coefficient Value
Depending on the bus used to write the coefficient, the following steps must be followed:
•
Writing from AC’97
o Write 16 lower bit data at AC’97 address 78h
o Write 8 bit INDEX 40h and R/W bit and 4 upper data bits at AC’97 address 7Ah
•
Writing from I2C
o Write 8 middle data bits at I2C address 78h
o Write 8 lower data bits at I2C address 79h
o Write 8 bit address at I2C address 7Ah coeff INDEX +40h
o Write 4 upper data bits and R/W bit at I2C address 7Bh
14
Details and Specifications are subject to change without notice
DDX-4100
10.3 Coefficient Map
Index
(decimal)
0
Index
(hex)
0h
Coefficient
Default Value
LR00(b2)
00000h
1
1h
LR01(b0-1)
00000h
***
***
****
***
4
4h
LR04 (b1/2)
00000h
5
5h
LR10(b2)
00000h
***
***
***
***
19
20
13h
14h
LR34(b1/2)
SUR00
00000h
00000h
***
***
***
***
39
40
27h
28h
SUR34
SBW00(b2)
00000h
00032h
41
29h
SBW01(b0-1)
80032h
42
2Ah
SBW02(a2)
7C7Eah
43
2bh
SBW03(a1/2)
81C6Fh
44
2Ch
SBW04(b1/2)
00032h
45
2dh
SBW10
00000h
***
***
***
***
59
60
3bh
3Ch
SBW34
-scale_in LR
00000h
80000h
61
3dh
-scale in SUR
80000h
62
3Eh
-scale in SBW
80000h
63
3Fh
-scale_L – SBW
C0000h
64
40h
-scale_R – SBW
C0000h
65
41h
-scale_LS – SBW
C0000h
66
42h
-scale_RS – SBW
C0000h
67
43h
-scale_C – SBW
C0000h
68
44h
-scale_LFE – SBW
80000h
20 LR Filter
Coef
20 Surrounds
filter coef
20 SBW filter
coef
3 scale in
factors
6 SBW
redirection
factors
15
Details and Specifications are subject to change without notice
DDX-4100
Filter coefficients:
CHx0 = b2
CHx1 = (b0)-1
CHx2 = a2
CHx3 = (a1)/2
CHx4 = (b1)/2
Where the CH stands for LR, SUR or SBW and x stands for the filter number (0 thru 3). The filter
equation is Yn = Xn+((b0)-1)* Xn + 2 *((b1)/2) *Xn – 1 + b2 *Xn – 2 – 2 * ((a1)/2) *Yn – 1 – a2 *Yn – 2 =
= b0 *Xn + b1 *Xn – 1 + b2 *Xn – 2 – a1 *Yn – 1 – a2 *Yn – 2
The coefficient registers are 20 bits wide and should be in the range (-1 to 1) (80000h to 7ffffh).
Scaling factor registers:
• For the filters Xn = - (-scale_in) *CHn, where CHn is the value before scaling and Xn is the input to
the filter.
• For the SBW redirection SBWn = S (-scale_CH) *CHn
• The scaling factor registers are 20 bits wide and should be in the range (-1 to 0) (80000h to
000000h).
• SBW redirection: - 1 for maximum redirection and 0 for no redirection.
• Filter scaling: -1 for maximum input and 0 for no input to filter.
11.0
I2C BUS SPECIFICATION
The DDX-4100 supports the I2C protocol. This protocol defines any device that sends data on to the bus
as a transmitter and any device that reads the data as a receiver. The device that controls the data
transfer is known as the master and the other as the slave. The master always starts the transfer and
provides the serial clock for synchronization. The DDX-4100 is always a slave device in all of its
communications.
16-bit registers are addressed as two 8-bit registers. The high byte has an even address, while the low
byte has an odd address. For example, reading from register 02 (16-bit) means read register 02 (High
Byte) and 03 (Low Byte) for I2C.
11.1
COMMUNICATION PROTOCOL
11.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock
is high is used to identify a START or STOP condition.
11.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
stable in the high state. A START condition must precede any command for data transfer.
11.1.3 Stop Condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A STOP condition terminates communication between DDX-4100 and the bus master.
16
Details and Specifications are subject to change without notice
DDX-4100
11.1.4 Data Input
During the data input the DDX-4100 samples the SDA signal on the rising edge of clock SCL. For correct
device operation the SDA signal must be stable during the rising edge of the clock and the data can
change only when the SCL line is low.
11.2 DEVICE ADDRESSING
To start communication between the master and the DDX-4100, the master must initiate with a start
condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the
device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In
the DDX-4100 the I2C interface has two device addresses depending on the SA pin configuration,
0011110 when SA = 0, and 0011111 when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write
mode. After a START condition the DDX-4100 identifies on the bus the device address and if a match is
found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device
identification byte is the internal space address.
11.3
WRITE OPERATION (see fig. 16)
Following the START condition the master sends a device select code with the RW bit set to 0. The
DDX-4100 acknowledges this and the writes for the byte of internal address. After receiving the internal
byte address the DDX-4100 again responds with an acknowledgement.
11.3.1 Byte Write
In the byte write mode the master sends one data byte, this is acknowledged by the DDX-4100. The
master then terminates the transfer by generating a STOP condition.
11.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. The master generating a STOP condition
terminates the transfer.
Write Mode Sequence
ACK
BYTE
WRITE
DEV-ADDR
START
ACK
SUB-ADDR
RW
STOP
ACK
MULTIBYTE
WRITE
DEV-ADDR
START
ACK
DATA IN
ACK
SUB-ADDR
RW
ACK
DATA IN
ACK
DATA IN
STOP
17
Details and Specifications are subject to change without notice
DDX-4100
Figure 10 Read Mode Sequence
ACK
CURRENT
ADDRESS
READ
NO ACK
DEV-ADDR
START
DATA
RW
STOP
ACK
RANDOM
ADDRESS
READ
DEV-ADDR
START
ACK
DEV-ADDR
RW
START
RW= ACK
HIGH
SEQUENTIAL
CURRENT
READ
ACK
SUB-ADDR
RW
ACK
DEV-ADDR
NO ACK
DATA
STOP
ACK
DATA
DATA
NO ACK
DATA
START
STOP
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
ACK
SUB-ADDR
DEV-ADDR
RW
START
12.0
REGISTER SUMMARY
12.1
Reset Register (address 00h)
D15
0
D14
0
D13
0
ACK
D12
0
D11
0
D10
0
ACK
ACK
DATA
DATA
NO ACK
DATA
RW
D9
0
D8
0
STOP
D7
1
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
Writing any value to this register performs a register reset, which causes all registers to revert to their
default values. Reading this register returns 00E4h as it is the ID code of the part and it’s 3D Stereo
Enhancement type (see AC’97 revision 2.1 specification, section 6.3.1).
12.2
LR Volume Register (address 02h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mute
ML6
ML5
ML4
ML3
ML2
ML1
ML0
X
MR6
MR5
MR4
MR4
MR2
MR1
MR0
This register manages the stereo (both right and left channels) output signal volume. The MSB of the
register is the mute bit. ML6 through ML0 set the left channel level, MR6 though MR0 set the right
channel. There are two options: ‘Full Compliance’ operating mode (bit D0 in the CRA register, address
5Ah, is set to ‘0’) only 6 bits are active (Mx0 to Mx5) and each step corresponds to 1.5dB. In ‘Proprietary”
mode (bit D1 in the CRA register is set to ‘1’), Mx0 to Mx6 can have the values between 0h to 68h (110
1000) and each step corresponds to 1dB. Greater values are undefined.
The default value is 8000h (1000 0000 0000 0000), which corresponds to 0dB attenuation.
‘Full Compliance Mode’
Mute
0
0
0
1
Mx6 – Mx0
X00 0000
X01 1111
X11 1111
xxx xxxx
Function
0 dB Attenuation
46.5dB Attenuation
94.5dB Attenuation
∞dB Attenuation
18
Details and Specifications are subject to change without notice
DDX-4100
Proprietary Mode’
Mute
0
0
0
Mx6 – Mx0
000 0000
001 1111
011 1111
***
110 0001
110 0010
110 0011
110 0100
110 0101
110 0110
110 0111
110 1000
xxx xxxx
0
0
0
0
0
0
0
0
1
Function
0 dB Attenuation
31dB Attenuation
63dB Attenuation
***
97dB Attenuation
99dB Attenuation
100dB Attenuation
102dB Attenuation
104dB Attenuation
107dB Attenuation
111dB Attenuation
∞dB Attenuation
∞db Attenuation
12.3 Tone Control Register (address 08h)
D15
X
D14
X
D13
X
D12
X
D11
BA3
D10
BA2
D9
BA1
D8
BA0
D7
X
D6
X
D5
X
D4
X
D3
TR3
D2
TR2
D1
TR1
D0
TR0
This register supports tone controls (bass and treble). Writing a 0000h corresponds to +12dB of gain.
The frequencies (from which gains are measured) are 160Hz for Bass and 5,000Hz for Treble. The
default value is 0F0Fh, which corresponds to bass and treble bypass. The tone feature is implemented
only on the L and R front channel.
TR3… TR0 or BA3… BA0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Function
+12dB of gain
+10dB of gain
+8dB of gain
+6 dB of gain
+4dB of gain
+2 dB of gain
+1dB of gain
0dB of gain
-1dB of gain
-2dB of gain
-4dB of gain
-6dB of gain
-8dB of gain
-10dB of gain
-12dB of gain
Bypass
The tone control in the DDX-4100 is implemented in such a manner that boosting can create clipping of
the audio regardless of the volume setting. This is because the Bass/Treble boost occurs before the
volume control. Meaning, for example, if the bass boost is set at +8dB then any low-frequency program
material recorded above -8dBFS will clip within the bass boost processing. Implementing attenuation
prior to the DDX-4100 can solve this problem. Many audio decoding ICs provide a volume control that
can accomplish this. An attenuation of -12dB should be implemented in the decoding IC. Therefore no
clipping will take place in either the bass or treble boost regardless of the setting. Volume is controlled
normally using the DDX-4100, except when maximum DDX-4100 volume(0dB) is reached. The
attenuation in the decoder IC will then have to be decreased from -12dB to 0dB in the appropriate volume
step size to obtain maximum gain through the system. This implementation will only create signal clipping
once maximum output has been reached. Therefore it will clip like any other amplifier regardless of the
bass/treble settings
19
Details and Specifications are subject to change without notice
DDX-4100
Bass
/
Treble
PreScale
Volume
Biquads
Figure 11: Digital Audio Signal Flow
12.4 Power-down Ctrl/Status Register (PCSR) (address 26h)
D15
EAPD
D14
D13
PR5
D12
PR4
D11
D10
BIT
D12
R/W
R/W
RST
0
NAME
PR4
D13
R/W
0
PR5
D15
R/W
1
EAPD
D9
D8
D7
D6
D5
D4
D3
1
D2
1
D1
1
D0
0
DESCRIPTION
Setting this bit to 1 the BIT_Clk and the SDATA_IN signal
will be fixed to the digital low level. To resume the normal
operation either a hardware reset or a softReset must be
performed.
In order to set the device in a power-down-like condition
this bit must be set to 1. This will stop the device internal
clock: only the PL and AC’97, I2C clocks will still be
running. The DSP starts the power-down sequence
(volume fade-out and MUTE).
The value of this bit is checked by the DSP in order to
recognize an external power amplifier power-down
request. As a consequence the DSP starts the powerdown sequence (volume fade-out and MUTE).
NOTE: Bit D0, D3 will be masked to show the value before writing into the RAM register, other bits will simply pass through.
12.5
D15
0
Extended Audio ID Register (address 28h) AC’97 Only
D14
ID0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
1
D7
1
D6
1
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
The Extended Audio ID is a read-only register that identifies which extended audio features are supported
(see AC’97 revision 2.1 specification, section A2.1). The extended features supported are Variable Rate
PCM Audio (VRA), Double rate PCM Audio (DRA), PCM Center (CDAC), PCM Surround (SDAC) and
PCM LFE (LDAC).
Code ID0, at D14, reports the status of the SA pin. Code ID1, at D15, always reports 0. Hence, the
configurations are primary (00) if SA pin is 0 or Secondary (01) if SA pin is 1.
20
Details and Specifications are subject to change without notice
DDX-4100
12.6
D15
•
•
Extended Audio Status and Control Register (address 2Ah) AC’97 Only
D14
D13
D12
D11
D10
D9
0
D8
1
D7
1
D6
1
D5
D4
D3
D2
D1
DRA
D0
VRA
VRA = 1 enables Variable Rate Audio mode (sample rate control register and SLOTREQ signaling)
DRA = 1 enables Double Rate Audio mode
Bits D9 – D6 are read only status of the extended audio feature readiness. When a write request is
issued the actual data written into the RAM register is ‘xxxxxx0111xxxxxx’.
For more details refer to AC’97 rev 2.1, section A2.2
12.7
Audio Sample Rate Control Registers (address 2Ch – 34h) AC’97 Only
D15
SR15
D14
SR14
D13
SR13
D12
SR12
D11
SR11
D10
SR10
D9
SR9
D8
SR8
D7
SR7
D6
SR6
D5
SR5
D4
SR4
D3
SR3
D2
SR2
D1
SR1
D0
SR0
In VRA mode, two frequencies are supported 48000 (BB80h) Hz and 44100 (AC44h) Hz. If one of these
values is written to the 2Ch register, that value will be echoed back when read, otherwise the closest
(higher in case of a tie) sample rate supported is returned. The content of the 2Eh and 30h register is
copied from the 2Ch register.
If the Double Rate Audio (DRA) mode is active, the sample rate programmed will be multiplied by 2x. For
example: When running at 88.2KHz, the DRA bit will be programmed to 1, and the sample rate
programmed would be 44.100KHz.
The default value after a cold or warm register reset for these registers is 48kHz, (BB80h). The content of
the sample rate register (32h and 34h) stays always at BB80h.
12.8
D15
Mute
Mute
6-Channel Volume Control Register (address 36h – 38h)
D14
LFE
6
LSR
6
D13
LFE
5
LSR
5
D12
LFE
4
LSR
4
D11
LFE
3
LSR
3
D10
LFE
2
LSR
2
D9
LFE
1
LSR
1
D8
LFE
0
LSR
0
D7
Mute
Mute
D6
CNT
6
RSR
6
D5
CNT
5
RSR
5
D4
CNT
4
RSR
4
D3
CNT
3
RSR
3
D2
CNT
2
RSR
2
D1
CNT
1
RSR
1
D0
CNT
0
RSR
0
These read/write registers control the output volume of the optional six I2S PCM channels, and values
written to the fields behave the same as the Play Master Volume Register (Index 02h), which offers
attenuation but no gain. There is an independent mute (1=on) for each channel.
The default value after reset for this register (8080h) corresponds to 0dB attenuation with mute on.
12.9 Configuration Register A (CRA): address 5Ah
D15
SRC_
ByPass
D14
DRLL
_dBg
D13
SRC_
THR_1
D12
SRC_
THR_0
D11
SPDIF
_Mode
D10
I2S_SP
Dif_Set
D9
MCKOU
T_Mode
D8
PLL_
Bypass
D7
PLL_
Factor
D6
DDX_P
WrMode
D5
DDX_
ZD
Enable
D4
DDX
_Rst
D3
DDX
Gain_
1
D2
DDX
Gain_
0
D1
I2SI
Dbuff
Mode
D0
AC97
FC
Mode
21
Details and Specifications are subject to change without notice
DDX-4100
BIT
D0
R/W
R/W
RST
0
NAME
AC97_FC_Mode
D1
R/W
0
I2SI_DBUFF_Mode
D2
R/W
0
DDX_Gain_0
D3
R/W
0
DDX_Gain_1
D4
R/W
1
DDX_Rst
D5
R/W
1
DDX_ZD_Enable
D6
R/W
1
DDX_PwrMode
D7
R/W
0
PLL_Factor
D8
R/W
1
PLL_Bypass
D9
R/W
0
MCKOUT_Mode
D10
R/W
0
I2S_SPDIF_Sel
D11
R/W
0
SPDIF_Mode
D12
R/W
1
SRC_THR_0
D13
R/W
0
SRC_THR_1
D14
R/W
0
DRLL_dbg
D15
R/W
0
SRC_Bypass
DESCRIPTION
AC’97 Full Compliant Mode (0 to enable). When in
FC mode any read of registers will return only valid
bits: bits marked as ‘reserved’ by AC’97 v2.0
specification will return 0, regardless of the RAM
contents.
Enable Double Buffer mode for the I2S input
interface (write 1 to enable this option). This is
recommended ONLY if this interface is operated in
SYNC mode (SRC bypassed).
DDX Gain setting (LSb/MSb). These two bits will
set the DDX stage gain and the compression as
shown in Table 4.
DDX Reset (active high)
DDX Zero Detect Feature. If this bit is 1 the
feature is enabled.
DDX Power Mode. (1 = Fixed for DDX-2060).
PLL factor (x2 or x8). It should be used according
to the input frequency provided to the device: 1
(x8) when 6.144MHz is provided, 0 (x2) when
24.576MHz is provided.
PLL Bypass. Setting this bit to 0 will bypass the
PLL; internal master clock will be directly
connected to XTI pin.
MCKOut Mode: 12.288 MHz (1) or 24.576MHz (0).
I2S – S/PDIF Selector. Select the input source: set
to 0 for I2S input, 1 for S/PDIF input.
S/PDIF Mode. Set to 0 to select Analog mode, 1
to select Digital mode.
Sample Rate threshold (LSb/MSb). These bits are
used to select the threshold frequency enabling the
SRC anti-alias filter.
Table 5 shows the threshold selections.
DRLL Debug Mode. This bit is used for a test
mode. Set to 0 for normal operation.
SRC Bypass. Setting this bit to 1 the SRC block
can be bypassed and the selected input I/F is
directly connected to the DSP.
Note: In TEST_MODE – PLL_Bypass = 0
Table 4 DDX Gain
DDX_GAIN_0
0
0
1
1
DDX_GAIN_1
0
1
0
1
DDX Gain
1x
2x
2x
3x
DDX Compression
NO
NO
YES
YES
22
Details and Specifications are subject to change without notice
DDX-4100
DDX Gain Compression
Since a full-scale output of the GC/Vol block is mapped to full output modulation, any signal exceeding
0dBFS at the output of the GC/Vol block will clip. The purpose of the compression algorithm is to reduce
the gain of the system when 0dBFS has been exceeded. This eliminates clipping, thus performing an
output limiting function. This yields constant output once the gained input exceeds 0dBFS.
With DDX_GAIN_0 set to 1, the output of the GC/Vol block is compared to a threshold set just below
0dBFS. When the GC/Vol exceeds this threshold the system gain is reduced following a set time constant
at a set gain reduction rate. The gain reduction is stored as a variable. If the subsequent output of GC/Vol
remains below a lower threshold for a set time, the gain is increased following another set time, at a set
gain rate. Thus, seven constants determine the attack, release and limiting characteristics of the
compression algorithm. These constants have been tuned for the lowest perceived audio distortion when
reducing the dynamic range of a recording due to 0dBFS being exceeded.
LIMITER
GAIN/VOLUME
INPUT
RMS
+
OUTPUT
GAIN
SATURATION
ATTENUATION
Figure 12 Gain Limiter
Table 5 SRC Threshold
SRC_THR_0
0
0
1
1
SRC_THR_1
0
1
0
1
Threshold Frequency
INACTIVE
58.875 to 61.125kHz
78.973 to 81.000kHz
Always active
12.10 Configuration Register B (CRB) (address 5Ch)
D15
I2SO_
MSbLSb
D14
I2SO_
LRCK_
Master
D13
I2SO_
LRCK_
Pol
D12
I2SO_
BCK_
Master
D11
I2SO_
BICK
_Pol
D10
I2SO_
Align
_2
D9
I2SO_
Align
_1
D8
I2SO_
Align
_0
D7
I2SI_
MSbLSb
D6
I2SI_
LRCK
_Master
D5
I2SI_
LRCL
_Pol
D4
I2SI_
BCK
_Master
D3
I2SI_
BICK
_Pol
D2
I2SI_
Align
_2
D1
I2SI_
Align
_1
D0
I2SI_
Align
_0
23
Details and Specifications are subject to change without notice
DDX-4100
BIT
D0
D1
D2
R/W
R/W
R/W
R/W
RST
1
0
0
NAME
I2SI_Align _0
I2SI_Align_1
I2SI_Align_2
D3
R/W
1
I2SI_BICK_Pol
D4
R/W
0
I2SI_BCK_Master
D5
R/W
0
I2SI_LRCK_Pol
D6
R/W
0
I2SI_LRCK_Master
D7
R/W
1
I2SO_MSbLSb
D8
R/W
1
I2SO_Align_0
D9
R/W
0
I2SO_Align_1
D10
R/W
0
I2SO_Align_2
D11
R/W
1
I2SO_BICK_Pol
D12
R/W
1
I2SO_BCK_Master
D13
R/W
0
I2SO_LRCK_Pol
D14
R/W
1
I2SO_LRCK_Master
D15
R/W
1
I2SO_MSbLSB
DESCRIPTION
I2S (Input) Alignment. Using these bits the word
alignment can be adjusted with respect to the LRCK
edges. Please refer to the related paragraph for more
details. The default value is mode 1.
I2S (Input) BICK Polarity. This bit should be configured
according to the serial protocol used. In order to
sample incoming data on the rising edge (data
changes on the falling edge) this bit should be set to 1.
Set to 0 to reverse the sampling edge.
I2S (Input) Master/Slave Selection. The I2S input
interface can be configured as either master or slave:
if the master mode is selected (1) the BICK line will be
an output (64 x 48KHz fixed). Otherwise (0) slave
mode is selected and this line is an input.
I2S (Input) LRCK Polarity. Set to 0 to receive LEFT
samples when LRCK is low, 1 otherwise
I2S (Input) Master/Slave Selection. The I2S input
interface can be configured as either master or slave:
if the master mode is selected (1) the LRCK line will be
an output (48KHz fixed). Otherwise (0) slave mode is
selected and this line is an input (continuous frequency
between 32KHz and 96KHz).
I2S (Input) MSb/LSb Selection. Use this bit to select
how the sample word is received by the I2S input
interface: set to 0 to configure as LSb first, 1 MSb first.
I2S (Output) Alignment. Using these bits the word
alignment can be adjusted with respect to the LRCK
edges. The default value is mode 1.
I2S (Output) BICK Polarity. This bit should be
configured according to the used serial protocol. In
order to sample out coming data on the rising edge
(data changes on the falling edge) this bit should be
set to 1. Set to 0 to reverse the sampling edge.
I2S (Output) Master/Slave Selection. The I2S output
interface can be configured as either master or slave:
if the master mode is selected (1) the BICK line will be
an output (64 x 48kHz). Otherwise (0) slave mode is
selected and this line is an input.
I2S (Output) LRCK Polarity. Set to 0 to transmit LEFT
samples when LRCK is low, 1 otherwise.
I2S (Output) Master/Slave Selection. The I2S output
interface can be configured as either master or slave: if
the master mode is selected (1) the LRCK line will be
an output. Otherwise (0) slave mode is selected and
this line is an input. In any case the frequency is fixed
at 48kHz
I2S (Output) MSb/LSb Selection. Use this bit to select
how the sample word is transmitted by the I2S output
interface: set to 0 to configure as LSb first 1, MSb first.
2
2
NOTE: Power-on default values will configure serial input interface as I S Slave and the output interface as I S Master.
24
Details and Specifications are subject to change without notice
DDX-4100
12.11 Phantom Center Register (address 60h) (AC’97 only)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Phantom
Setting bit D0=1 enables the Phantom Center Channel in AC’97 operation. When enabled, the content of
the center channel is split and added to the L and R channels. Default setting is 0h.
12.12 Static EQ and Side Firing Register (address 70h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
EQ1
D0
EQ0
D1
D0
Bass
Mng
This register controls the activation of the Static EQ and the Side Firing surround sound.
EQ1
EQ0
Result
0
0
EQ off (default)
0
1
EQ enabled
1
x
Side Firing + EQ
For more information on setting EQ parameters, see Paragraph 9.2
12.13 Bass Management Register (address 72h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
Setting bit D0=1 activates the Bass Management. For more information on Bass Management, See
Paragraph 9.1. Default setting is 0h.
12.14 Bypass Register (address 74h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bypass
Setting bit D0=1 bypasses the DSP block. All channels are bypassed and output equal to input,
regardless of all other algorithm register settings (Volume, Tone, Phantom, EQ). Default is 0h.
12.15 BIST and Status Register (BASR): (address 76h)
D15
DSP_
BIST_
START
D14
DSP_
BIST_
RUNNIN
G
D13
DSP_
BIST_
STOP
D12
DSP_
RAM
D11
X
D10
X
D9
SRC_
SPRAM
_2
D8
SRC_
SPRAM
_1
D7
DDX_
DPRAM
D6
DDX_
SPRAM
_3
D5
DDX_
SPRAM
_2
D4
DDX_
SPRAM
_1
D3
BIST
_STOP
D2
BIST
_START
D1
SPDIF_
STATUS
D0
SRC_
STATUS
25
Details and Specifications are subject to change without notice
DDX-4100
BIT
D0
I/F
R
DSP
D1
R
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
W
R
R
R
R
R
R
R
R/W
R/W
R
D12
D13
D14
D15
R
R
R
W
R
R
R
R
RST
1
NAME
SRC_Status
1
SPDIF_Status
0
0
0
0
0
0
0
0
1
0
AC3_AMEN
CH1_AMEN
DESCRIPTION
When 0, the digital PLL in the SRC is
LOCKED. When 1 the digital PLL is OUT of
LOCK
When 1, the SPDIF interface is out of lock.
When 0 the interface is locked to the SPDIF
stream input.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Enable auto-muting if AC3 frame header found
Enable auto-muting if no CH1_STATUS bit
found
Reserved
Reserved
Reserved
Reserved
0
0
0
0
12.16 Coefficient Handling Registers (address 78h – 7Ah)
D15 D14 D13 D12
C15 C14 C13 C12
AD7 AD6 AD5 AD4
See Paragraph 10
D11
C11
AD3
D10
C10
AD2
D9
C9
AD1
D8
C8
AD0
D7
C7
R/W
D6
C6
D5
C5
D4
C4
D3
C3
C19
D2
C2
C18
D1
C1
C17
D0
C0
C16
12.17 Vendor ID Register (address 7Ch – 7Eh) (AC’97 only)
D15
0
0
D14
1
1
D13
0
0
D12
0
0
D11
0
1
D10
0
0
D9
0
1
D8
1
0
D7
0
REV7
D6
1
REV6
D5
0
REV5
D4
0
REV4
D3
1
REV3
D2
1
REV2
D1
0
REV1
D0
0
REV0
These registers are specific vendor identification for the DDX4100. Microsoft’s Plug and Play Vendor ID
code is “ALJ”. The REV7 0 field is for the Vendor Revision number. These are read only registers, any
request to one of these will be ignored.
26
Details and Specifications are subject to change without notice
DDX-4100
mm
DIM.
MIN.
TYP.
A
inch
MA X.
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
C
0.09
0.15
0.002
0.006
1.40
1.45
0.053
0.05 5
0.057
0.37
0.45
0.012
0.01 4
0.018
0.20
0.004
0.008
12.00
0.47 2
D1
10.00
0.394
D3
8.00
0.31 5
e
0.80
0.031
E
12.00
0.47 2
E1
10.00
0.394
E3
8.00
0.31 5
L1
K
0.45
0.60
1.00
0.75
OUTLINE AND
ME CHANICAL DATA
0.063
D
L
MA X.
0.018
0.02 4
0.03 9
0.030
TQF P44 (10 x 10)
(min.), 3.5° (typ.), 7 (max.)
Information furnished in this publication is believed to be accurate and reliable. However, Apogee
Technology, Inc. assumes no responsibility for its use, or for any infringements of patents or other rights
of third parties that may result from its use. Specifications in this publication are subject to change without
notice. This publication supersedes and replaces all information previously supplied.
27
Details and Specifications are subject to change without notice