STMICROELECTRONICS STA326

STA326
2.1 HIGH EFFICIENCY
DIGITAL AUDIO SYSTEM
1
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FEATURES
Wide supply voltage range (10-36V)
3 Power Output Configurations
– 2x30W + 1x60W, 8Ω+4Ω @ 10% THD
– 2x60W, 8Ω @ 10% THD
– 1x120W, 4Ω @ 10% THD
Power SO-36 Package
2.1 Channels of 24-Bit DDX®
100dB SNR and Dynamic Range
32kHz to 192kHz Input Sample Rates
Digital Gain/Attenuation +48dB to -80dB in
0.5dB steps
4 x 22-bit User Programmable Biquads (EQ) per
Channel
I2C Control
2-Channel I2S Input Data Interface
Individual Channel and Master Gain/
Attenuation
Individual Channel and Master Soft and Hard
Mute
Individual Channel Volume and EQ Bypass
Bass/Treble Tone Control
Dual Independent Programmable Limiters/
Compressors
Automodes™
– 31 Preset EQ Curves
– 15 Preset Crossover Settings
– Auto Volume Controlled Loudness
– 3 Preset Volume Curves
– 2 Preset Anti-Clipping Modes
– Preset Nighttime Listening Mode
– Preset TV AGC
Input and Output Channel Mapping
AM Noise Reduction and PWM Frequency
Shifting Modes
Soft Volume Update and Muting
Auto Zero Detect and Invalid Input Detect
Muting
Over Current and over-temperature protection
with programmable recovery
Thermal warning indicator with programmable
auto output power reduction
Selectable De-emphasis
May 2006
Figure 1. Package
PowerSO36 (Slug up)
Table 1. Order Codes
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2
Part Number
Package
STA326
PowerSO36 (Slug up)
STA32613TR
Tape & Reel
Post-EQ User Programmable Mix with default
2.1 Bass Management settings
Variable Max Power Correction for lower fullpower THD
4 Output Routing Configurations
Selectable Clock Input Ratio
96kHz Internal Processing Sample Rate, 24 to
28-bit precision
QXpander
Video Application: 576 fs input mode suporting
DESCRIPTION
The STA326 is an integrated solution of digital audio processing, digital amplifier control, and DDXPower Output Stage, thereby creating a high-power single-chip DDX® solution comprising of highquality, high-efficiency, all digital amplification.
The STA326 can be configured via digital control
to operate in several output modes providing up to
2.1 channels of power output to speakers.
This device is capable to deliver up to 2x30W +
1x60W in 2.1 mode or 2x60W in stereo mode.
The IC can also be configured as a single
paralelled full-bridge capable of high-current operation and 1x120W output.
Also provided in the STA326 are a full assortment
of digital processing features. This includes up to
4 programmable 28-bit biquads (EQ) per channel,
and bass/treble tone control. Automodes™ enable
a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes Auto
Rev. 2
1/43
STA326
Volume loudness, preset volume curves, preset EQ settings, etc. New advanced AM radio inerference reduction modes.
The serial audio data input interface accepts all possible formats, including the popular I2S format.
Three channels of DDX® processing are provided. This high quality conversion from PCM audio to DDX's
patented tri-state PWM switching waveform provides over 100dB SNR and dynamic range.
Figure 2.
SDA
SCL
I 2C
System Control
LRCKI
Serial Data
Input,
Channel
Mapping &
Resampling
BICKI
SDI_12
OUT1A
Audio EQ, Mix,
Crossver,
Volume, Limiter
Processing
DDX ®
Processing
Quad
Half-Bridge
Power Stage
OUT1B
OUT2A
OUT2B
EAPD
System Timing
PLL
TWARN
FAULT
Power-Down
CLK
Figure 3. Channel Signal Flow Diagram through the Digital Core
I 2S
Input
Channel
Mapping
Re-sampling
EQ
Processing
Mix
Crossover
Filter
Volume
Limiter
4X
Interp
DDX®
DDX
Output
2.1 EQ Processing
Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block.
In this block, upto 4 user-defined Biquads can be appplied to each of the two channels.
Pre-scaling, dc-blocking high-pass, de-emphasis, bass, and tone control filters can also be applied based
on various configuration parameter settings.
The entire EQ block can be bypassed for all channels simulatneously by setting the DSPB bit to '1'. And
the CxEQBP bits can be used to bypass the EQ functionality on a per channel basis. Figure below shows
the internal signal flow through the EQ block.
2.2 Mix Processing
The Post-EQ Mix block takes the two channel outputs from the EQ block and outputs three channels of
data. By default, Channels 1 and 2 outputs are essentially pass-through of Channels 1 and 2 inputs coming from the EQ block. An additional channel is created as a result of a sum & mix of the two input channels. See Figure 30. By default, this 3rd channel of data is an equal mix of channel 1 and 2 data. Normally
this third channel will be used as the subwoofer in the 2.1 configuration. An additional filtering stage is
found after the mix block in order to implement crossover filtering. The crossover filters can be automatically configured from the AutoMode Crossover (XO) bits or these filters can be manually programmed for
any type and frequency crossover.
2/43
STA326
2.3 Output Mode Configurations
Figure 4. Channel Signal Flow through the EQ Block
Re-sampled
Input
Pre
Scale
High-Pass
Filter
If HPB = 0
BQ#1
BQ#2
BQ#3
BQ#4
4 Biquads
User defined if AMEQ = 00
P reset EQ if AMEQ = 01
Auto Loudness if AMEQ = 10
DeEmphasis
Bass
Filter
If DEMP = 1
T reble
Filt er
To
Mix
If CxT CB = 0
BT C: Bass Boost /Cut
T T C: T reble Boost/Cut
If DSPB = 0 & CxEQB = 0
Figure 5. 2-Channel (Full-bridge) Power, OCFG(1…0) = 00
Half
Bridge
OUT1A
Channel 1
Half
Bridge
Half
Bridge
Half
Bridge
OUT1B
OUT2A
Channel 2
OUT2B
Figure 6. - 2.1-Channel Power Configuration OCFG(1…0) = 01
Half
Bridge
Half
Bridge
Half
Bridge
Channel 1
OUT1A
Channel 2
OUT1B
OUT2A
Channel 3
Half
Bridge
OUT2B
Figure 7. 1-Channel Mono-Parallel Configuration, OCFG(1…0) = 11
OUT1A
Half
Bridge
Half
Bridge
OUT1B
Channel 3
Half
Bridge
Half
Bridge
OUT2A
OUT2B
3/43
STA326
3
Pin Function and Specifications
Figure 8. Pin Connection (Top view)
VCCSign
36
1
N.C.
VSS
35
2
N.C.
VDD
34
3
OUT2B
GND
33
4
VCC2B
BICKI
32
5
N.C.
LRCKI
31
6
GND2B
SDI
30
7
GND2A
VDDA
29
8
VCC2A
GNDA
28
9
OUT2A
XTI
27
10
OUT1B
PLL FILTER
26
11
VCC1B
RES
25
12
GND1B
SDA
24
13
GND1A.
SCL
23
14
N.C.
RESET
22
15
VCC1A
CONFIG
21
16
OUT1A
VL
20
17
GNDCLEAN
VDD REG
19
18
GND REG
D04AU1540
Table 2. Pin Function
Pin
1, 2, 5, 14
3
4
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
4/43
Type
O
I/O
I/O
I/O
I/O
O
O
I/O
I/O
I/O.
I/O
O
I/O
I/O
I/O
I/O
I
I
I
I/O
RES
I
I
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
Name
N.C.
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
GNDCLEAN
GNDREG
VREG1
VL
CONFIG
RESET
SCL
SDA
Reserved
PLL FILTER
XTI
GNDA
VDDA
SDI_12
LRCKI
BICKI
GND
VDD
VSS
VCCSIGN
Description
Not Connected
Output half bridge 2B
Positive supply
Negative Supply
Negative Supply
Positive supply
Output half bridge 2A
Output half bridge 1B
Positive supply
Negative Supply
Negative Supply
Positive supply
Output half bridge 1A
Logic reference ground
Substrate ground
Internal +5V regulator voltage
Digital Supply 3.3V
Configuration pin (mono parallel)
Reset
I²C Serial Clock
I²C Serial Data
This pin must be connected to GND
Connection to PLL filter
PLL Input Clock
Analog Ground
Analog Supply 3.3
I²S Serial Data Channels 1 & 2
I²S Left/Right Clock,
I²S Serial Clock
Digital Ground
Digital Supply 3.3V
Internal - 5V (Relative to Vcc)
Internal signal supply
STA326
Table 3. Absolute Maximum Ratings
Symbol
Parameter
VDD3
3.3V Digital Power Supply
VDDA
3.3V Analog Power Supply
Value
Unit
-0.5 to 4
V
-0.5 to 4
V
Vi
Voltage on input pins
-0.5 to (VDD+0.5)
V
Vo
Voltage on output pins
-0.5 to (VDD+0.5)
V
Tstg
Storage Temperature
-40 to +150
°C
Tamb
Ambient Operating Temperature
-20 to +85
°C
Tj
Operating Junction Temperature
0 to +150
°C
DC Supply Voltage
40
V
Maximum voltage on pins 20
5.5
V
VCC
VMAX
Table 4. Thermal Data
Symbol
Rthj-case
Parameter
Min
Typ
Max
Unit
2.5
°C/W
Thermal resistance Junction to case (thermal pad)
Thermal Shut-down Junction Temperature
150
°C
TWARN
Thermal Warning Temperature
130
°C
Th-SD
Thermal Shut-down Hysteresis
25
°C
Value
Unit
3.0 to 3.6
V
Tj-SD
Table 5. Recommended Dc Operating Conditions
Symbol
VDD3
4
Parameter
I/O Power Supply
Electrical Characteristcs
(VDD3 = 3.3V ± 0.3V; Tamb = 25°C; unless otherwise specified)
4.1 GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Iil
Low Level Input no pull-up
Max.
Unit
Note
Vi = 0V
Test Condition
Min.
Typ.
1
µA
1
Iih
High Level Input no pull-down
Vi = VDD3
2
µA
1
IOZ
Tristate output leakage without
pullup/down
Vi = VDD3
2
µA
1
Vesd
Electrostatic Protection
Leakage < 1µA
V
2
2000
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin.
Note 2: Human Body Model
4.2 DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
0.8
V
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
2.0
V
Schmitt Trigger Hysteresis
0.4
V
Vhyst
Vol
Low Level Output
IoI = 2mA
Voh
High Level Output
Ioh = -2mA
0.15
VDD -0.15
V
V
5/43
STA326
4.3 POWER ELECTRICAL CHARACTERISTCS
(VL = 3.3V; Vcc = 30V; Tamb = 25°C unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
200
270
mΩ
50
µA
RdsON
Power Pchannel/Nchannel
MOSFET RdsON
Id=1A
Idss
Power Pchannel/Nchannel
leakage Idss
Vcc=35V
gN
Power Pchannel RdsON Matching Id=1A
95
%
gP
Power Nchannel RdsON
Matching
95
%
Id=1A
Dt_s
Low current Dead Time (static)
see test circuit no.1; see fig. 1
20
ns
td ON
Turn-on delay time
Resistive load
10
100
ns
td OFF
Turn-off delay time
Resistive load
100
ns
tr
Rise time
Resistive load
25
ns
tf
Fall time
Resistive load; as fig. 1
25
ns
VCC
Supply voltage operating voltage
IVCC-
Supply Current from Vcc in
PWRDN
PWRDN = 0
Supply current from Vcc in Tristate
Vcc=30V; Tri-state
22
mA
IVCC
Supply current from Vcc in
operation
(both channel switching)
Input pulse width = 50% Duty;
Switching Frequency = 384Khz;
No LC filters;
80
mA
Iout-sh
Overcurrent protection threshold
(short circuit current limit)
6
A
7
V
PWRDN
IVCC-hiz
VUV
tpw-min
Po
Po
Po
THD+N
SNR
η
6/43
10
4
Undervoltage protection threshold
V
3
mA
Output minimum pulse width
No Load
Output Power
(Full-bridge mode)
THD = 10%
RL = 4Ω; VS = 17V
RL = 8Ω; VS = 32V
30
60
W
W
Output Power
(Binary half-bridge mode)
THD = 1%
RL = 4Ω; VS = 17V
RL = 8Ω; VS = 32V
25
46
W
W
Mono mode output power
THD = 10%
RL = 4Ω; VS = 32V
60
120
W
W
0.07
%
Total Harmonic Distortion + Noise Po = 1 Wrms
70
36
150
ns
Po = 40 Wrms
0.1
Signal to Noise Ratio
A-Weighted
DDX® Mode
99
dB
Signal to Noise Ratio,
Binary Half-Bridge Mode
Binary Mode
A-Weighted
92
dB
Efficiency
DDX® Mode
89
%
Binary
87
%
STA326
5
FUNCTIONAL DESCRIPTION
5.1 PIN DESCRIPTION
5.1.1 OUT1A, 1B, 2A & 2B (Pins 16, 10, 9 & 3)
Output Half Bridge PWM Outputs 1A, 1B, 2A & 2B provide the inputs signals to the speaker devices.
Half Bridge Power Outputs 1A, 1B, 2A & 2B deliver audio power to the speaker loads. Using DDX stereo
configuration mode, outputs 1A (+) and 1B (-) comprise Channel 1 and outputs 2A (+) and 2B (-) comprise
Channel 2. Using binary 2.1 channel configuration mode, output 1A is for Channel 1 and output 1B is for
Channel 2 and outputs 2A (+) and 2B (-) comprise Channel 3. Using DDX mono-high power output mode
(Config connected to VREG1), outputs 1A and 1B are shorted (+) and outputs 2A and 2B are shorted (-)
comprising a single BTL output with twice output current capability for Channel 3.
5.1.2 RESET (Pin 22)
Driving RESET low sets all outputs low and returns all register settings to their defaults. The reset is asynchronous to the internal clock.
5.1.3 I2C Signals (Pins 23 & 24)
The SDA (I2C Data) and SCL (I2C Clock) pins operate per the I2C specification. See Section 4.0. Fastmode (400kB/sec) I2C communication is supported.
5.1.4 GNDA & VDDA: Phase Locked Loop Power (Pins 28-29)
The phase locked loop power is applied here. This +3.3V supply must be well bypassed and filtered for
noise immunity. The audio performance of the device is critically dependent upon the PLL circuit.
5.1.5 CLK: Master Clock In (Pin 27)
This is the master clock in required for the operation of the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256*Fs) for
a 48kHz sample rate, which is the default at power-up. Care must be taken to avoid over-clocking the
device i.e provide the device with the nominally required system clock; otherwise, the device may not properly operate or be able to communicate.
5.1.6 FILTER_PLL: PLL Filter (Pin 26)
PLL Filter connects to external filter components for PLL loop compensation. Refer to the schematic diagram for the recommended circuit.
5.1.7 BICKI: Bit Clock In (Pin 32)
The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64*Fs, for example using I2S serial format.
5.1.8 SDI_12: Serial Data Input (Pin 30)
PCM audio information enters the device here. Six format choices are available including I2S, left- or rightjustified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
5.1.9 CONFIG: Configuration input (Pin 21)
The configuration input pin is normally connected to ground. Using the mono-high power BTL configuration requires the CONFIG input pin be shorted to VREG1.
5.1.10 LRCKI: Left/Right Clock In (Pin 31)
The Left/Right clock input is for data word framing. The clock frequency will be at the input sample rate Fs.
5.2 AUDIO PERFORMANCE
TBD
7/43
STA326
6
STA326 I2C BUS SPECIFICATION
The STA326 supports the I2C protocol. This protocol defines any device that sends data on to the bus as
a transmitter and any device that reads the data as a receiver. The device that controls the data transfer
is known as the master and the other as the slave. The master always starts the transfer and provides
the serial clock for synchronization. The STA326 is always a slave device in all of its communications.
6.1 COMMUNICATION PROTOCOL
6.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock
is high is used to identify a START or STOP condition.
6.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
stable in the high state. A START condition must precede any command for data transfer.
6.1.3 Stop Condition
STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A STOP condition terminates communication between STA326 and the bus master.
6.1.4 Data Input
During the data input the STA326 samples the SDA signal on the rising edge of clock SCL. For correct
device operation the SDA signal must be stable during the rising edge of the clock and the data can
change only when the SCL line is low.
6.2 DEVICE ADDRESSING
To start communication between the master and the STA326, the master must initiate with a start condition. Following this, the master sends 8-bits (MSB first) onto the SDA line corresponding to the device
select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In
the STA326 the I2C interface uses a device addresse of 0x34 or 0011010x.
The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write
mode. After a START condition the STA326 identifies the device address on the bus. If a match is found,
it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device
identification byte is the internal space address.
6.3 WRITE OPERATION
Following the START condition the master sends a device select code with the RW bit set to 0. The
STA326 acknowledges this and then the master writes the internal address byte.
After receiving the internal byte address the STA326 again responds with an acknowledgement.
6.3.1 Byte Write
In the byte write mode the master sends one data byte. This is acknowledged by the STA326. The master
then terminates the transfer by generating a STOP condition.
6.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. Sequential data byte writes will be written
to sequential addresses within the STA326.
The master generating a STOP condition terminates the transfer.
8/43
STA326
6.4 READ OPERATION
6.4.1 Current Address Byte Read
Following the START condition the master sends a device select code with the RW bit set to 1. The
STA326 acknowledges this and then responds by sending one byte of data. The master then terminates
the transfer by generating a STOP condition.
6.4.1.1Current Address Multi-byte Read
The multi-byte read modes can start from any internal address. Sequential data bytes will be read from
sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
6.4.2 Random Address Byte Read
Following the START condition the master sends a device select code with the RW bit set to 0. The
STA326 acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA326 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA326
acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
6.4.2.1Random Address Multi-byte Read
The multi-byte read modes could start from any internal address. Sequential data bytes will be read from
sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
6.5 Write Mode Sequence
Figure 9. I2C Write Procedure
ACK
DEV-ADDR
BYTE
WRITE
ACK
DATA IN
RW
START
STOP
ACK
MULTIBYTE
WRITE
ACK
SUB-ADDR
DEV-ADDR
START
ACK
ACK
SUB-ADDR
ACK
DATA IN
DATA IN
STOP
RW
6.6 Read Mode Sequence
Figure 10. I2C Read Procedure
ACK
CURRENT
ADDRESS
READ
DEV-ADDR
START
NO ACK
DATA
RW
STOP
ACK
RANDOM
ADDRESS
READ
DEV-ADDR
START
SEQUENTIAL
CURRENT
READ
ACK
ACK
SUB-ADDR
RW
RW= ACK
HIGH
DEV-ADDR
DEV-ADDR
START
NO ACK
DATA
RW
ACK
STOP
ACK
DATA
DATA
NO ACK
DATA
START
STOP
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
ACK
ACK
SUB-ADDR
RW
DEV-ADDR
START
ACK
DATA
RW
ACK
DATA
NO ACK
DATA
STOP
9/43
STA326
7
REGISTER DESCRIPTION
Table 6. Register Summary
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x1F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
10/43
Name
ConfA
ConfB
ConfC
ConfD
ConfE
ConfF
Mmute
Mvol
C1Vol
C2Vol
C3Vol
Auto1
Auto2
Auto3
C1Cfg
C2Cfg
C3Cfg
Tone
L1ar
L1atrt
L2ar
L2atrt
Cfaddr2
B1cf1
B1cf2
B1cf3
B2cf1
B2cf2
B2cf3
A1cf1
A1cf2
A1cf3
A2cf1
A2cf2
A2cf3
B0cf1
B0cf2
B0cf3
Cfud
MPCC1
MPCC2
RES
RES
FDRC1
FDRC2
Status
D7
FDRB
C2IM
D6
TWAB
C1IM
CSZ4
ZDE
ZCE
PWDN
D5
TWRB
DSCKE
CSZ3
DRC
DCCV
ECLE
D4
IR1
SAIFB
CSZ2
BQL
PWMS
LDTE
D3
IR0
SAI3
CSZ1
PSL
AME
BCLE
D2
MCS2
SAI2
CSZ0
DSPB
RES
IDE
D1
MCS1
SAI1
OM1
DEMP
MPC
OCFG1
MV7
C1V7
C2V7
C3V7
AMPS
XO3
MV6
C1V6
C2V6
C3V6
XO2
MV5
C1V5
C2V5
C3V5
AMGC1
XO1
C1OM1
C2OM1
C3OM1
TTC3
L1A3
L1AT3
L2A3
L2AT3
CFA7
C1B23
C1B15
C1B7
C2B23
C2B15
C2B7
C3B23
C3B15
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
C1OM0
C2OM0
C3OM0
TTC2
L1A2
L1AT2
L2A2
L2AT2
CFA6
C1B22
C1B14
C1B6
C2B22
C2B14
C2B6
C3B22
C3B14
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C5B6
C1LS1
C2LS1
C3LS1
TTC1
L1A1
L1AT1
L2A1
L2AT1
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
C2B5
C3B21
C3B13
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C5B5
MV4
C1V4
C2V4
C3V4
AMGC0
XO1
PEQ4
C1LS0
C2LS0
C3LS0
TTC0
L1A0
L1AT0
L2A0
L2AT0
CFA4
C1B20
C1B12
C1B4
C2B20
C2B12
C2B4
C3B20
C3B12
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
MV3
C1V3
C2V3
C3V3
AMV1
AMAM2
PEQ3
C1BO
C2BO
C3BO
BTC3
L1R3
L1RT3
L2R3
L2RT3
CFA3
C1B19
C1B11
C1B3
C2B19
C2B11
C2B3
C3B19
C3B11
C3B3
C4B19
C4B11
C4B3
C5B19
C5B11
C5B3
MV2
C1V2
C2V2
C3V2
AMV0
AMAM1
PEQ2
C1VBP
C2VBP
C3VBP
BTC2
L1R2
L1RT2
L2R2
L2RT2
CFA2
C1B18
C1B10
C1B2
C2B18
C2B10
C2B2
C3B18
C3B10
C3B2
C4B18
C4B10
C4B2
C5B18
C5B10
C5B2
MV1
C1V1
C2V1
C3V1
AMEQ1
AMAM0
PEQ1
C1EQBP
C2EQBP
D0
MCS0
SAI0
OM0
HPB
MPCV
OCFG0
MMute
MV0
C1V0
C2V0
C3V0
AMEQ0
AMAME
PEQ0
C1TCB
C2TCB
MPCC15
MPCC7
RES
RES
FDRC15
FDRC7
PLLUL
MPCC14
MPCC6
RES
RES
FDRC14
FDRC6
MPCC13
MPCC5
RES
RES
FDRC13
FDRC5
MPCC12
MPCC4
RES
RES
FDRC12
FDRC4
MPCC11
MPCC3
RES
RES
FDRC11
FDRC3
MPCC10
MPCC2
RES
RES
FDRC10
FDRC2
BTC1
L1R1
L1RT1
L2R1
L2RT1
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C2B1
C3B17
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
WA
MPCC9
MPCC1
RES
RES
FDRC9
FDRC1
FAULT
BTC0
L1R0
L1RT0
L2R0
L2RT0
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C2B0
C3B16
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
MPCC8
MPCC0
RES
RES
FDRC8
FDRC0
TWARN
MME
SVE
EAPD
STA326
7.1 CONFIGURATION REGISTER A (Address 00h)
D7
D6
D5
D4
D3
D2
D1
D0
FDRB
TWAB
TFRB
IR1
IR0
MCS2
MCS1
MCS0
0
1
1
0
0
0
1
1
7.1.1
Master Clock Select
BIT
0
R/W
R/W
RST
1
NAME
MCS0
1
2
R/W
R/W
1
0
MCS1
MCS2
DESCRIPTION
Master Clock Select: Selects the ratio between the input
I2S sample frequency and the input clock.
The STA326 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, and 96kHz. Therefore the
internal clock will be:
■
32.768Mhz for 32kHz
■
45.1584Mhz for 44.1khz, 88.2kHz, and 176.4kHz
49.152Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs).
The correlation between the input clock and the input sample rate is determined by the status of the MCSx
bits and the IR (Input Rate) register bits. The MCSx bits determine the PLL factor generating the internal
clock and the IR bit determines the oversampling ratio used internally.
■
Table 7. IR and MCS Settings for Input Sample Rate and Clock Rate
Input Sample Rate
fs (kHz)
IR
32, 44.1, 48
88.2, 96
176.4, 192
00
01
1X
7.1.2
BIT
4...3
MCS(2..0)
000
768fs
384fs
384fs
001
512fs
256fs
256fs
010
384fs
192fs
192fs
011
256fs
128fs
128fs
100
128fs
64fs
64fs
101
576fs
x
x
Interpolation Ratio Select
R/W
R/W
RST
00
NAME
IR (1...0)
DESCRIPTION
Interpolation Ratio Select: Selects internal interpolation ratio based
on input I2S sample frequency
The STA326 has variable interpolation (re-sampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (passthrough) or provides a down-sample by a factor of 2.
The IR bits determine the re-sampling ratio of this interpolation.
Table 8. IR bit settings as a function of Input Sample Rate
Input Sample Rate Fs (kHz)
IR (1,0)
32
44.1
48
88.2
96
176.4
192
00
00
00
01
01
10
10
1st Stage Interpolation Ratio
2 times over-sampling
2 times over-sampling
2 times over-sampling
Pass-Through
Pass-Through
Down-sampling by 2
Down-sampling by 2
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STA326
7.1.3
Thermal Warning Recovery Bypass
BIT
R/W
RST
NAME
5
R/W
1
TWRB
DESCRIPTION
Thermal-Warning Recovery Bypass:
0 – Thermal warning Recovery enabled
1 – Thermal warning Recovery disabled
If the Thermal Warning Adjustment is enabled (TWAB=0), then the Thermal Warning Recovery will determine if the adjustment is removed when Thermal Warning is negative. If TWRB=0 and TWAB=0, then
when a thermal warning disappears the gain adjustment determined by the Thermal Warning PostScale(default = -3dB) will be removed and the gain will be added back to the system. If TWRB=1 and
TWAB=0, then when a thermal warning disappears the Thermal Warning Post-Scale gain adjustment will
remain until TWRB is changed to zero or the device is reset.
7.1.4
Thermal Warning Adjustment Bypass
BIT
R/W
RST
NAME
6
R/W
1
TWAB
DESCRIPTION
Thermal-Warning Adjustment Bypass:
0 – Thermal warning adjustment enabled
1 – Thermal warning adjustment disabled
The on-chip STA326 Power Output block provides feedback to the digital controller using inputs to the
Power Control block. The TWARN input is used to indicate a thermal warning condition. When TWARN
is asserted (set to 0) for a period greater than 400ms, the power control block will force an adjustment to
the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning
volume adjustment is applied, whether the gain is reapplied when TWARN is de-asserted is dependent
on the TWRB bit.
7.1.5
Fault Detect Recovery Bypass
BIT
R/W
RST
NAME
7
R/W
0
FDRB
DESCRIPTION
Fault Detector Recovery Bypass:
0 – Fault Detector Recovery enabled
1 – Fault Detector Recovery disabled
The DDX Power block provides feedback to the digital controller using inputs to the Power Control block.
The FAULT input is used to signal a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt automatic recovery from the fault by asserting the tristate signal in a sequence to reset the fault and retest the fault status. The sequence period can range
from 0.1 milliseconds to 1 second as defined by the Fault-Detect Recovery Constant register (FDRC registers 29-2Ah). This sequence is repeated for as long as the fault condition exists. This feature is enabled
by default but can be disabled by setting the FDRB control bit to 1. If Fault-Detect Recovery is disabled
(not recommended), an output stage FAULT will cause a shut-down condition, which must be reset either
by toggling the external reset pin or via a VCC power cycle to the IC.
7.2 CONFIGURATION REGISTER B (Address 01h)
D7
D6
D5
D4
D3
D2
D1
D0
C1IM
C1IM
DSCKE
SAIFB
SAI3
SAI2
SAI1
SAI0
1
0
0
0
0
0
0
0
7.2.1
Serial Audio Input Interface Format
BIT
R/W
RST
NAME
3…0
R/W
0000
SAI (3...0)
12/43
DESCRIPTION
Serial Audio Input Interface Format: Determines the interface format of
the input serial digital audio interface.
STA326
7.3 Serial Data Interface
The STA326 serial audio input was designed to interface with standard digital audio components and to
accept a number of serial data formats. The STA326 always acts as a slave when receiving audio input
from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/
right clock LRCKI (pin 33), serial clock BICKI (pin 31), and serial data 1 & 2 SDI12 (pin 32).
The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (Configuration Register B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSBFirst. Available formats are shown in Figure 11 and the tables that follow.
Figure 11. General Serial Input and Output Formats
2
IS
Left
LRCLK
Right
SCLK
MSB
SDATA
LSB
MSB
LSB
MSB
Left Justified
Left
LRCLK
Right
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
Right Justified
Left
LRCLK
Right
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First.
Table 10 below lists the serial audio input formats supported by STA326 as related to BICKI = 32/48/64fs,
where the sampling rate fs = 32/44.1/48/88.2/96/176.4/192 kHz.
Table 9. First Bit Selection Table
SAIFB
Format
0
MSB-First
1
LSB-First
Note: Serial input and output formats are specified distinctly.
13/43
STA326
Table 10. Supported Serial Audio Input Formats
BICKI
SAI (3...0)
SAIFB
Interface Format
32fs
1100
X
I2S 15bit Data
1110
X
Left/Right-Justified 16bit Data
0100
X
I2S 23bit Data
0100
X
I2S 20bit Data
1000
X
I2S 18bit Data
0100
0
MSB First I2S 16bit Data
1100
1
LSB First I2S 16bit Data
0001
X
Left-Justified 24bit Data
0101
X
Left-Justified 20bit Data
1001
X
Left-Justified 18bit Data
1101
X
Left-Justified 16bit Data
0010
X
Right-Justified 24bit Data
0110
X
Right-Justified 20bit Data
1010
X
Right-Justified 18bit Data
1110
X
Right-Justified 16bit Data
0000
X
I2S 24bit Data
0100
X
I2S 20bit Data
1000
X
I2S 18bit Data
0000
0
MSB First I2S 16bit Data
1100
1
LSB First I2S 16bit Data
0001
X
Left-Justified 24bit Data
0101
X
Left-Justified 20bit Data
1001
X
Left-Justified 18bit Data
1101
X
Left-Justified 16bit Data
0010
X
Right-Justified 24bit Data
0110
X
Right-Justified 20bit Data
1010
X
Right-Justified 18bit Data
1110
X
Right-Justified 16bit Data
48fs
64fs
Table 11. Serial Input Data Timing characteristics (Fs = 32 to 192kHz)
BICKI FREQUENCY (slave mode)
12.5MHz max.
BICKI pulse width low (T0) (slave mode)
40 ns min.
BICKI pulse width high (T1) (slave mode)
40 ns min.
BICKI active to LRCKI edge delay (T2)
20 ns min.
BICKI active to LRCKI edge delay (T3)
20 ns min.
SDI valid to BICKI active setup (T4)
20 ns min.
BICKI active to SDI hold time (T5)
20 ns min.
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STA326
Figure 12.
T2
T3
LRCKI
T1
T0
BICKI
T4
SDI
T5
7.3.1
Delay Serial Clock Enable
BIT
R/W
RST
NAME
5
R/W
0
DSCKE
7.3.2
DESCRIPTION
Delay Serial Clock Enable:
0 – No serial clock delay
1 – Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
Channel Input Mapping
BIT
R/W
RST
NAME
DESCRIPTION
6
R/W
0
C1IM
0 – Processing channel 1 receives Left I2S Input
1 – Processing channel 1 receives Right I2S Input
7
R/W
1
C2IM
0 – Processing channel 2 receives Left I2S Input
1 – Processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input
Mapping registers. This allows for flexibility in processing. The default settings of these registers map
each I2S input channel to its corresponding processing channel.
7.4 CONFIGURATION REGISTER C (Address 02h)
D7
7.4.1
D6
D5
D4
D3
D2
D1
D0
CSZ4
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
1
0
0
0
0
1
0
DDX® Power Output Mode
BIT
R/W
RST
NAME
1...0
R/W
10
OM (1...0)
DESCRIPTION
DDX Power Output Mode:
Selects configuration of DDX® output.
The DDX® Power Output Mode selects how the DDX® output timing is configured. Different power devices can use different output modes. The DDX-2060/2100/2160 recommended use is OM = 10. When
OM=11 the CSZ bits determine the size of the DDX® compensating pulse.
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STA326
Table 12. DDX® Output Modes
OM (1,0)
Output Stage – Mode
00
Not Used
01
Not Used
10
STA500/505/508
11
Variable Compensation
7.4.2 DDX® Variable Compensating Pulse Size
The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact
Apogee applications for support when deciding this function.
7.4.3
DDX® Variable Compensating Pulse Size
BIT
R/W
RST
NAME
6...2
R/W
10000
CSZ (4...0)
DESCRIPTION
Compensating Pulse Size Select
The DDX® variable compensating pulse size is not recommended to be used except in special circumstances . Contact STMicroelectronics applications for support when deciding this function.
Table 13. DDX® Compensating Pulse
CSZ (4…0)
Compensating Pulse Size
00000
0 Clock period Compensating Pulse Size
00001
1 Clock period Compensating Pulse Size
…
…
10000
16 Clock period Compensating Pulse Size
…
…
11111
31 Clock period Compensating Pulse Size
7.5 Configuration Register D (Address 03h)
D7
D6
D5
D4
D3
D2
D1
D0
MME
ZDE
DRC
BQL
PSL
DSPB
DEMP
HPB
0
0
0
0
0
0
0
0
7.5.1
High-Pass Filter Bypass
BIT
R/W
RST
NAME
0
R/W
0
HPB
DESCRIPTION
High-Pass Filter Bypass Bit.
0 – AC Coupling High Pass Filter Enabled
1 – AC Coupling High Pass Filter Disabled
The STA326 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of
this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker
damage.
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STA326
7.5.2
De-Emphasis
BIT
R/W
RST
NAME
1
R/W
0
DEMP
DESCRIPTION
De-emphasis:
0 – No De-emphasis
1 – De-emphasis
By setting this bit to HIGH, or one (1), de-emphasis will implemented on all channels. DSPB (DSP Bypass,
Bit D2, CFA) bit must be set to 0 for De-emphasis to function.
7.5.3
DSP Bypass
BIT
R/W
RST
NAME
2
R/W
0
DSPB
DESCRIPTION
DSP Bypass Bit:
0 – Normal Operation
1 – Bypass of EQ and Mixing Functionality
Setting the DSPB bit bypasses all the EQ and Mixing functionality of the STA326 Core.
7.5.4
Post-Scale Link
BIT
R/W
RST
NAME
3
R/W
0
PSL
DESCRIPTION
Post-Scale Link:
0 – Each Channel uses individual Post-Scale value
1 – Each Channel uses Channel 1 Post-Scale value
Post-Scale functionality is an attenuation placed after the volume control and directly before the conversion to PWM. Post-Scale can also be used to limit the maximum modulation index and therefore the peak
current. A setting of 1 in the PSL register will result in the use of the value stored in Channel 1 post-scale
for all three internal channels.
7.5.5
Biquad Coefficient Link
BIT
R/W
RST
NAME
4
R/W
0
BQL
DESCRIPTION
Biquad Link:
0 – Each Channel uses coefficient values
1 – Each Channel uses Channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM
space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
7.5.6
Dynamic Range Compression/Anti-Clipping Bit
BIT
R/W
RST
NAME
5
R/W
0
DRC
DESCRIPTION
Dynamic Range Compression/Anti-Clipping
0 – Limiters act in Anti-Clipping Mode
1 – Limiters act in Dynamic Range Compression Mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in
anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.
7.5.7
Zero-Detect Mute Enable
BIT
R/W
RST
NAME
6
R/W
1
ZDE
DESCRIPTION
Zero-Detect Mute Enable: Setting of 1 enables the automatic zerodetect mute
Setting the ZDE bit enables the zero-detect automatic mute. When ZDE=1, the zero-detect circuit looks
17/43
STA326
at the input data to each processing channel after the channel-mapping block. If any channel receives
2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.
7.5.8
Sub-Mix Enable
BIT
R/W
RST
NAME
7
R/W
0
SME
DESCRIPTION
Sub-Mix Enable:
0 - Sub Mix into Left/Right Disabled
1 - Sub Mix into Left/Right Enabled
Setting the SME bit enables a scaled-mix of the content from the Sub channel (i.e. channel 3) into the main
Left & Right channels (i.e. channels 1 & 2). The Sub-Mix resides post-volume & gain compression processing.
7.6 CONFIGURATION REGISTER E (ADDRESS 04H)
D7
D6
D5
D4
D3
D2
D1
D0
SVE
ZCE
RES
PWMS
AME
RES
MPC
MPCV
0
0
0
0
0
0
0
0
7.6.1
Max Power Correction Variable
BIT
R/W
RST
NAME
DESCRIPTION
0
R/W
0
MPCV
Max Power Correction Variable:
0 – Use Standard MPC Coefficient
1 – Use MPCC bits for MPC Coefficient
By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the
MPCC registers (address 0x27-0x28) it becomes possible to adjust the THD at maximum unclipped power
to a lower value for a particular application.
7.6.2
Max Power Correction
BIT
R/W
RST
NAME
7
R/W
1
MPC
DESCRIPTION
Max Power Correction:
0 – MPC Disabled
1 – MPC Enabled
Setting the MPC bit corrects the STA500/505/508 power device at high power. This mode will lower the
THD+N of a full STA500 DDX® system at maximum power output and slightly below.
7.6.3
Noise Shaper BandWidth Selection
BIT
R/W
RST
NAME
2
R/W
0
NSBW
DESCRIPTION
Noise Shaper BandWidth Select
0 – 4th Order Noise Shaper
1 – 3rd Order Noise Shaper
DDXi-2101 provides the ability to the user to select two types of noise-shaper order. This facilitates the
user to essentially make the appropriate bandwidth selection for their design thereby achieving optimal
noise performance. It is recommended to set NSBW = '1' when the device is initialized via I2C.
18/43
STA326
7.6.4
AM Mode Enable
BIT
R/W
RST
NAME
3
R/W
0
AME
DESCRIPTION
AM Mode Enable:
0 – Normal DDX® operation.
1 – AM reduction mode DDX® operation.
The STA326 features a DDX® processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when DDX® is operating in a device with an
active AM tuner. The SNR of the DDX® processing is reduced to ~83dB in this mode, which is still greater
than the SNR of AM radio.
7.6.5
PWM Speed Mode
BIT
R/W
RST
NAME
4
R/W
0
PWMS
DESCRIPTION
PWM Speed Selection: Normal or Odd
Table 14. PWM Output Speed Selections
PWMS (1...0)
7.6.6
PWM Output Speed
0
Normal Speed (384kHz) All Channels
1
Odd Speed (341.3kHz) All Channels
Zero-Crossing Volume Enable
BIT
R/W
RST
NAME
6
R/W
1
ZCE
DESCRIPTION
Zero-Crossing Volume Enable:
1 – Volume adjustments will only occur at digital zero-crossings
0 – Volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible.
7.6.7
Soft Volume Update Enable
BIT
R/W
RST
NAME
7
R/W
1
SVE
DESCRIPTION
Soft Volume Enable:
1 – Volume adjustments will use soft volume
0 – Volume adjustments will occur immediately
The STA326 includes a soft volume algorithm that will step through the intermediate volume values at a
predetermined rate when a volume change occurs. By setting SVE=0 this can be bypassed and volume
changes will jump from old to new value directly. This feature is only available if individual channel volume
bypass bit is set to ‘0’.
7.7 Configuration Register F (Address 05h)
D7
D6
D5
D4
D3
D2
D1
D0
EAPD
PWDN
ECLE
RES
BCLE
IDE
OCFG1
OCFG0
0
1
0
1
1
1
1
0
19/43
STA326
7.7.1
Output Configuration Selection
BIT
R/W
RST
NAME
1…0
R/W
00
OCFG
(1…0)
DESCRIPTION
Output Configuration Selection
00 – 2-channel (Full-bridge) Power, 1-channel DDX is default
Table 15. Output Configuration Selections
OCFG (1...0)
00
01
10
11
7.7.2
BIT
2
Output Power Configuration
2 Channel (Full-Bridge) Power, 1 Channel DDX:
1A/1B ◊ 1A/1B
2A/2B ◊ 2A/2B
2(Half-Bridge).1(Full-Bridge) On-Board Power:
1A ◊ 1A
Binary
2A ◊ 1B
Binary
3A/3B ◊ 2A/2B Binary
Reserved
1 Channel Mono-Parallel:
3A ◊ 1A/1B
3B ◊ 2A/2B
Invalid Input Detect Mute Enable
R/W
R/W
RST
1
NAME
IDE
DESCRIPTION
Invalid Input Detect Auto-Mute Enable:
0 – Disabled
1 – Enabled
Setting the IDE bit enables this function, which looks at the input I2S data and clocking and will automatically mute all outputs if the signals are perceived as invalid.
7.7.3
Binary Clock Loss Detection Enable
BIT
R/W
RST
NAME
5
R/W
1
BCLE
DESCRIPTION
Binary Output Mode Clock Loss Detection Enable
0 – Disabled
1 – Enabled
Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when
input clocking is lost.
7.7.4
Auto-EAPD on Clock Loss Enable
BIT
R/W
RST
NAME
7
R/W
0
ECLE
DESCRIPTION
Auto EAPD on Clock Loss
0 – Disabled
1 – Enabled
When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.
7.7.5
Powerdown
BIT
R/W
RST
NAME
6
R/W
1
PWDN
DESCRIPTION
Software Power Down:
0 – Powerdown mode operation (auto soft-mute enabled)
1 – Normal Operation
If the powerdown bit is set low, a powerdown sequence is initiated resulting in a soft mute of all the channels and PWM outputs are damped.
20/43
STA326
7.7.6
External Amplifier Power Down
BIT
R/W
RST
NAME
7
R/W
0
EAPD
DESCRIPTION
External Amplifier Power Down:
0 – External Power Stage Power Down Active
1 – Normal Operation
EAPD is used to actively power down a connected DDX® Power device. This register has to be written to
1 at start-up to enable the DDX® power device for normal operation.
7.8 VOLUME CONTROL
7.8.1
Master Controls
7.8.1.1Master Mute Register (Address 06h)
D7
D6
D5
D4
D3
D2
D1
D0
MMUTE
0
7.8.1.2Master Volume Register (Address 07h)
D7
D6
D5
D4
D3
D2
D1
D0
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
1
1
1
1
1
1
1
1
Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.
7.8.2
Channel Controls
7.8.2.1Channel 1 Volume (Address 08h)
D7
D6
D5
D4
D3
D2
D1
D0
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0
1
1
0
0
0
0
0
7.8.2.2Channel 2 Volume (Address 09h)
D7
D6
D5
D4
D3
D2
D1
D0
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0
1
1
0
0
0
0
0
7.8.2.3Channel 3 Volume (Address 0Ah)
D7
D6
D5
D4
D3
D2
D1
D0
C3V7
C3V6
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
0
1
1
0
0
0
0
0
7.8.3 Volume Description
The volume structure of the STA326 consists of individual volume registers for each of the three channels
and a master volume register, and individual channel volume trim registers. The channel volume settings
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STA326
are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed. The individual
channel volumes are adjustable in 0.5dB steps from +48dB to -80 dB. The master volume control is normally mapped to the master volume of the system. The values of these two settings are summed to find
the actual gain/volume value for any given channel.
When set to 1, the Master Mute will mute all channels, whereas the individual channel mutes (CxM) will
mute only that channel. Both the Master Mute and the Channel Mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing
rate (~96kHz). A “hard mute” can be obtained by commanding a value of all 1’s (FFh) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than –100dB will be muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates will
occur immediately.
The STA326 also features a soft-volume update function that will ramp the volume between intermediate
values when the value is updated, when SVE = 1 (configuration register E). This feature can be disabled
by setting SVE = 0.
Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects
the volume setting, the master volume setting will not affect that channel. Also, master soft-mute will not
affect the channel if CxVBP = 1.
Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel
Table 16. Master Volume Offset as a function of MV (7..0).
MV (7..0)
Volume Offset from Channel Value
00000000 (00h)
0dB
00000001 (01h)
-0.5dB
00000010 (02h)
-1dB
…
…
01001100 (4Ch)
-38dB
…
…
11111110 (FEh)
-127dB
11111111 (FFh)
Hard Master Mute
Table 17. Channel Volume as a function of CxV (7..0)
22/43
CxV (7..0)
Volume
00000000 (00h)
+48dB
00000001 (01h)
+47.5dB
00000010 (02h)
+47dB
…
…
01100001 (5Fh)
+0.5dB
01100000 (60h)
0dB
01011111 (61h)
-0.5dB
…
…
11111110 (FEh)
-79.5 dB
11111111 (FFh)
Hard Channel Mute
STA326
7.9 AUTOMODE REGISTERS
7.9.1
Register – AutoModes EQ, Volume, GC (Address 0Bh)
D7
D6
D5
D4
D3
D2
D1
D0
AMPS
AMGC1
AMGC0
AMV1
AMV0
AMEQ1
AMEQ0
1
0
0
0
0
0
0
Table 18. AutoMode EQ
AMEQ (1,0)
Mode (Biquad 1-4)
00
User Programmable
01
Preset EQ – PEQ bits
10
Auto Volume Controlled Loudness Curve
11
Not used
By setting AMEQ to any setting other than 00 enables AutoMode EQ. When set, biquads 1-4 are not user
programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used
the pre-scale value for channels 1-2 becomes hard-set to –18dB.
Table 19. AutoMode Volume
AMV (1,0)
Mode (MVOL)
00
MVOL 0.5dB 256 Steps (Standard)
01
MVOL Auto Curve 30 Steps
10
MVOL Auto Curve 40 Steps
11
MVOL Auto Curve 50 Steps
Table 20. AutoMode Gain Compression/Limiters
AMGC (1...0)
7.9.2
Mode
00
User Programmable GC
01
AC No Clipping
10
AC Limited Clipping (10%)
11
DRC Nighttime Listening Mode
AMPS – AutoMode Auto Prescale
BIT
R/W
RST
NAME
0
R/W
0
AMPS
DESCRIPTION
AutoMode Pre-Scale
0 – -18dB used for Pre-scale when AMEQ /= 00
1 – User Defined Pre-scale when AMEQ /= 00
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STA326
7.9.3
Register – AutoMode AM/Pre-Scale/Bass Management Scale (Address 0Ch)
D7
D6
D5
D4
D3
D2
D1
D0
XO3
XO2
XO1
XO0
AMAM2
AMAM1
AMAM0
AMAME
0
0
0
0
0
0
0
0
7.9.3.1AutoMode AM Switching Enable
BIT
R/W
RST
NAME
0
R/W
0
AMAME
3…1
R/W
000
AMAM (2…0)
DESCRIPTION
AutoMode AM Enable
0 – Switching Frequency Determined by PWMS Setting
1 – Switching Frequency Determined by AMAM Settings
AM Switching Frequency Setting
Default: 000
Table 21. AutoMode AM Switching Frequency Selection
AMAM (2..0)
48kHz/96kHz Input Fs
44.1kHz/88.2kHz Input Fs
000
0.535MHz – 0.720MHz
0.535MHz – 0.670Mhz
001
0.721MHz – 0.900MHz
0.671MHz – 0.800MHz
010
0.901MHz – 1.100MHz
0.801MHz – 1.000MHz
011
1.101MHz – 1.300MHz
1.001MHz – 1.180MHz
100
1.301MHz – 1.480MHz
1.181MHz – 1.340Mhz
101
1.481MHz – 1.600MHz
1.341MHz – 1.500MHz
110
1.601MHz – 1.700MHz
1.501MHz – 1.700MHz
When DDX® is used concurrently with an AM radio tuner, it is advisable to use the AMAM bits to automatically adjust the output PWM switching rate dependent upon the specific radio frequency that the tuner is
receiving. The values used in AMAM are also dependent upon the sample rate determined by the ADC
used.
7.9.3.2AutoMode Crossover Setting
BIT
R/W
RST
NAME
7…4
R/W
0
XO (3…0)
DESCRIPTION
AutoMode Crossover Frequency Selection
000 – User Defined Crossover coefficients are used
Otherwise – Preset coefficients for the crossover setting desired
The XO bits are used to either select one of the 15 preset crossover frequency settings or enable the user
to implement custom crossover filters. The preset crossover settings signify the crossover frequency selected for the 2nd order low pass and 1st order high pass filters used on the processing channels. If a different crossover frequency, other than those available, is desired, then the user needs to set XO = 000
and design custom high-pass and low-pass filters. These filters should then be written to the device coefficient RAM using the I2C communication. Please refer to section 8.6.
Table 22. Crossover Frequency Selection
XO (2..0)
0000
0001
0010
0011
0100
0101
0110
0111
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Bass Management - Crossover Frequency
User
80 Hz
100 Hz
120 Hz
140 Hz
160 Hz
180 Hz
200 Hz
STA326
Table 22. Crossover Frequency Selection (continued)
XO (2..0)
1000
1001
1010
1011
1100
1101
1110
1111
7.9.4
Bass Management - Crossover Frequency
220 Hz
240 Hz
260 Hz
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
Register - Preset EQ Settings (Address 0Dh)
D7
D6
D5
D4
PEQ4
0
D3
PEQ3
0
D2
PEQ2
0
D1
PEQ1
0
D0
PEQ0
0
Table 23. Preset EQ Selection
PEQ (3..0)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Setting
Flat
Rock
Soft Rock
Jazz
Classical
Dance
Pop
Soft
Hard
Party
Vocal
Hip-Hop
Dialog
Bass-Boost #1
Bass-Boost #2
Bass-Boost #3
Loudness 1 (least boost)
Loudness 2
Loudness 3
Loudness 4
Loudness 5
Loudness 6
Loudness 7
Loudness 8
Loudness 9
Loudness 10
Loudness 11
Loudness 12
Loudness 13
Loudness 14
Loudness 15
Loudness 16 (most boost)
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STA326
7.10 Channel Configuration Registers
7.10.1 Channel 1 Configuration (Address 0Eh)
D7
D6
D5
D4
D3
D2
D1
D0
C1OM1
C1OM0
C1LS1
C1LS0
C1BO
C1VBP
C1EQBP
C1TCB
0
0
0
0
0
0
0
0
7.10.2 Channel 2 Configuration (Address 0Fh)
D7
D6
D5
D4
D3
D2
D1
D0
C2OM1
C2OM0
C2LS1
C2LS0
C2BO
C2VBP
C2EQBP
C2TCB
0
0
0
0
0
0
0
0
D1
D0
7.10.3 Channel 3 Configuration (Address 10h)
D7
D6
D5
D4
D3
D2
C3OM1
C3OM0
C3LS1
C3LS0
C3BO
C3VBP
0
0
0
0
0
0
EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the
prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in
any combination) are bypassed for that channel.
CxEQBP:
– 0 Perform EQ on Channel X – normal operation
– 1 Bypass EQ on Channel X
Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given
channel the two filters that tone control utilizes are bypassed.
CxTCB:
– 0 Perform Tone Control on Channel x – (default operation)
– 1 Bypass Tone Control on Channel x
Each channel can be configured to output either the patented DDX PWM data or standart binary PWM
encoded data. By setting the CxBO bit to ‘1’, each channel can be individually controlled to be in binary
operation mode.
Also, there is the capability to map each channel independently onto any of the two limiters available within
the STA326 or even not map it to any limiter at all (default mode).
Table 24. Channel Limiter Mapping Selection
CxLS (1,0)
Channel Limiter Mapping
00
Channel has limiting disabled
01
Channel is mapped to limiter #1
10
Channel is mapped to limiter #2
Each PWM Output Channel can receive data from any channel output of the volume block. Which channel
a particular PWM output receives is dependent upon that channel’s CxOM register bits.
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STA326
Table 25. Channel PWM Output Mapping
CxOM (1...0)
PWM Output From
00
Channel 1
01
Channel 2
10
Channel 3
11
Not used
7.11 Tone Control (Address 11h)
D7
D6
D5
D4
D3
D2
D1
D0
TTC3
TTC2
TTC1
TTC0
BTC3
BTC2
BTC1
BTC0
0
1
1
1
0
1
1
1
Table 26. Tone Control Boost/Cut Selection
BTC (3...0)/TTC (3...0)
Boost/Cut
0000
-12dB
0001
-12dB
…
…
0111
-4dB
0110
-2dB
0111
0dB
1000
+2dB
1001
+4dB
…
…
1101
+12dB
1110
+12dB
1111
+12dB
7.12 DYNAMICS CONTROL
7.12.1 Limiter 1 Attack/Release Threshold (Address 12h)
D7
D6
D5
D4
D3
D2
D1
D0
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
0
1
1
0
1
0
1
0
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STA326
7.12.2 Limiter 1 Attack/Release Threshold (Address 13h)
D7
D6
D5
D4
D3
D2
D1
D0
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
0
1
1
0
1
0
0
1
7.12.3 Limiter 2 Attack/Release Rate (Address 14h)
D7
D6
D5
D4
D3
D2
D1
D0
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
0
1
1
0
1
0
1
0
7.12.4 Limiter 2 Attack/Release Threshold (Address 15h)
D7
D6
D5
D4
D3
D2
D1
D0
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
0
1
1
0
1
0
0
1
7.12.5 Dynamics Control Description
The STA326 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce
the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively
reduce the dynamic range for a better listening environment (such as a night-time listening mode, which
is often needed for DVDs.) The two modes are selected via the DRC bit in Configuration Register D, bit
5 address 0x03. Each channel can be mapped to Limiter1, Limiter2, or not mapped.
If a channel is not mapped, that channel will clip normally when 0 dB FS is exceeded. Each limiter will
look at the present value of each channel that is mapped to it, select the maximum absolute value of all
these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the
mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers. When the Attack Thesehold has been
exceeded, the limiter, when active, will automatically start reducing the gain. The rate at which the gain
is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for
that limiter. The gain reduction occurs on a peak-detect algorithm.
The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The
output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to
the release threshold, determined by the Release Threshold register.
When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent
upon the Release Rate register. The gain can never be increased past its set value and therefore the
release will only occur if the limiter has already reduced the gain. The release threshold value can be used
to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release
threshold is set relative to the maximum volume setting plus the attack threshold.
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STA326
Figure 13. - Basic Limiter and Volume Flow Diagram
Limiter
RMS
Gain/Volume
Input
Output
Gain
Attenuation
Table 27. Limiter Attack Rate Selection
LxA (3...0)
Attack Rate dB/ms
0000
3.1584
0001
Saturation
Table 28. Limiter Release Rate Selection
LxR (3...0)
Release Rate dB/ms
0000
0.5116
2.7072
0001
0.1370
0010
2.2560
0010
0.0744
0011
1.8048
0011
0.0499
0100
1.3536
0100
0.0360
0101
0.9024
0101
0.0299
0110
0.4512
0110
0.0264
0111
0.2256
0111
0.0208
1000
0.1504
1000
0.0198
1001
0.1123
1001
0.0172
1010
0.0902
1010
0.0147
1011
0.0752
1011
0.0137
1100
0.0645
1100
0.0134
1101
0.0564
1101
0.0117
1110
0.0501
1110
0.0110
1111
0.0451
1111
0.0104
Fast
Slow
Fast
Slow
29/43
STA326
7.12.6 Anti-Clipping Mode
7.12.7 Dynamic Range Compression Mode
Table 29. Limiter Attack
Threshold Selection (AC-Mode)
Table 31. Limiter Attack Threshold Selection
(DRC-Mode).
LxAT (3...0)
AC (dB relative to FS)
LxAT (3...0)
DRC (dB relative to Volume)
0000
-12
0000
-31
0001
-10
0001
-29
0010
-8
0010
-27
0011
-6
0011
-25
0100
-4
0100
-23
0101
-2
0101
-21
0110
0
0110
-19
0111
+2
0111
-17
1000
+3
1000
-16
1001
-15
1010
-14
1011
-13
1100
-12
1101
-10
1110
-7
1111
-4
1001
+4
1010
+5
1011
+6
1100
+7
1101
+8
1110
+9
1111
+10
Table 32. Limiter Release Threshold Selection
(DRC-Mode).(
Table 30. Limiter Release
Threshold Selection (AC-Mode).
30/43
LxRT (3...0)
DRC (db relative to Volume
+ LxAT)
-∞
0000
-∞
0001
-29dB
0001
-38dB
0010
-20dB
0010
-36dB
0011
-16dB
0011
-33dB
0100
-14dB
0100
-31dB
0101
-12dB
0101
-30dB
0110
-10dB
0110
-28dB
0111
-8dB
0111
-26dB
1000
-7dB
1000
-24dB
1001
-6dB
1001
-22dB
1010
-5dB
1010
-20dB
1011
-4dB
1011
-18dB
1100
-3dB
1100
-15dB
1101
-2dB
1101
-12dB
1110
-1dB
1110
-9dB
1111
-0dB
1111
-6dB
LxRT (3...0)
AC (dB relative to FS)
0000
STA326
8
USER PROGRAMMABLE PROCESSING
8.1 EQ - BIQUAD EQUATION
The biquads use the equation that follows. This is diagrammed in Figure 14 below.
Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2]
= b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2]
where Y[n] represents the output and X[n] represents the input. Multipliers are 28-bit signed fractional
multipliers, with coefficient values in the range of 800000h (-1) to 7FFFFFh (0.9999998808).
Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner:
– CxHy0 = b1/2
– CxHy1 = b2
– CxHy2 = -a1/2
– CxHy3 = -a2
– CxHy4 = b0/2
The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in
the fourth biquad for channel 3
Figure 14. - Biquad Filter
b0 /2
Z
2
+
-1
Z -1
b1 /2
2
+
-a1 /2
2
Z -1
Z -1
b2
+
-a2
8.2 PRE-SCALE
The Pre-Scale block which precedes the first biquad is used for attenuation when filters are designed that
boost frequencies above 0dBFS. This is a single 28-bit signed multiplier, with 800000h = -1 and 7FFFFFh
= 0.9999998808. By default, all pre-scale factors are set to 7FFFFFh.
8.3 POST-SCALE
The STA326 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this
multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the post-scale link bit.
8.4 MIX/BASS MANAGEMENT
The STA326 provides a post-EQ mixing block per channel. Each channel has 2 mixing coefficients, which
are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block.
These coefficients are accessible via the User Controlled Coefficient RAM described below. The mix coefficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (8388608) are used used to provide three channels of output from two channels of filtered input.
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STA326
Table 33. Mix/Bass Management Block Diagram
Channel #1
from EQ
C1MX1
+
Channel #2
from EQ
High-Pass
XO
Filter
Channel#1
to GC/Vol
C1MX2
C2MX1
+
High-Pass
XO
Filter
Channel#2
to GC/Vol
C2MX2
C3MX1
+
Low-Pass
XO
Filter
Channel#3
to GC/Vol
C3MX2
User-defined Mix Coefficients
Crossover Frequency determined
by XO setting.
User-defined when XO = 000
After a mix is achieved, STA326 also provides the capability to implement crossver filters on all channels
corresponding to 2.1 bass management solution. Channels 1-2 use a 1st order high-pass filter and channel 3 uses a 2nd order low-pass filter corresponding to the setting of the XO bits of I2C register 0Ch. If XO
= 000, user specified crossover filters are used.
By default these coefficients correspond to pass-through. However, the user can write these coefficients
in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd
order crossover filters. This output is then passed on to the Volume/Limiter block.
8.5 Calculating 24-Bit Signed Fractional Numbers from a dB Value
The pre-scale, mixing, and post-scale functions of the STA326 use 24-bit signed fractional multipliers to
attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to
+1. It is possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the
equations below.
– Non-Inverting Phase Numbers 0 to +1 :
– Coefficient = Round(8388607 * 10^(dB/20))
– Inverting Phase Numbers 0 to -1 :
– Coefficient = 16777216 - Round(8388607 * 10^(dB/20))
As can be seen by the preceding equations, the value for positive phase 0dB is 0x7FFFFF and the value
for negative phase 0dB is 0x800000.
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STA326
8.6 USER DEFINED COEFFICIENT RAM
8.6.1
Coefficient Address Register 1 (Address 16h)
D7
D6
D5
D4
D3
D2
D1
D0
CFA7
CFA6
CFA5
CFA4
CFA3
CFA2
CFA1
CFA0
0
0
0
0
0
0
0
0
8.6.2
Coefficient b1Data Register Bits 23...16 (Address 17h)
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
8.6.3
Coefficient b1Data Register Bits 15...8 (Address 18h)
D7
D6
D5
D4
D3
D2
D1
D0
C1B15
C1B14
C1B13
C1B12
C1B11
C1B10
C1B9
C1B8
0
0
0
0
0
0
0
0
8.6.4
Coefficient b1Data Register Bits 7...0 (Address 19h)
D7
D6
D5
D4
D3
D2
D1
D0
C1B7
C1B6
C1B5
C1B4
C1B3
C1B2
C1B1
C1B0
0
0
0
0
0
0
0
0
8.6.5
Coefficient b2 Data Register Bits 23...16 (Address 1Ah)
D7
D6
D5
D4
D3
D2
D1
D0
C2B23
C2B22
C2B21
C2B20
C2B19
C2B18
C2B17
C2B16
0
0
0
0
0
0
0
0
8.6.6
Coefficient b2 Data Register Bits 15...8 (Address 1Bh)
D7
D6
D5
D4
D3
D2
D1
D0
C2B15
C2B14
C2B13
C2B12
C2B11
C2B10
C2B9
C2B8
0
0
0
0
0
0
0
0
8.6.7
Coefficient b2 Data Register Bits 7...0 (Address 1Ch)
D7
D6
D5
D4
D3
D2
D1
D0
C2B7
C2B6
C2B5
C2B4
C2B3
C2B2
C2B1
C2B0
0
0
0
0
0
0
0
0
8.6.8
Coefficient a1 Data Register Bits 23...16 (Address 1Dh)
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
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8.6.9
1.1.9Coefficient a1 Data Register Bits 15...8 (Address 1Eh)
D7
D6
D5
D4
D3
D2
D1
D0
C3B15
C3B14
C3B13
C3B12
C3B11
C3B10
C3B9
C3B8
0
0
0
0
0
0
0
0
8.6.10 Coefficient a1 Data Register Bits 7...0 (Address 1Fh)
D7
D6
D5
D4
D3
D2
D1
D0
C3B7
C3B6
C3B5
C3B4
C3B3
C3B2
C3B1
C3B0
0
0
0
0
0
0
0
0
8.6.11 Coefficient a2 Data Register Bits 23...16 (Address 20h)
D7
D6
D5
D4
D3
D2
D1
D0
C4B23
C4B22
C4B21
C4B20
C4B19
C4B18
C4B17
C4B16
0
0
0
0
0
0
0
0
8.6.12 Coefficient a2 Data Register Bits 15...8 (Address 21h)
D7
D6
D5
D4
D3
D2
D1
D0
C4B15
C4B14
C4B13
C4B12
C4B11
C4B10
C4B9
C4B8
0
0
0
0
0
0
0
0
8.6.13 Coefficient a2 Data Register Bits 7...0 (Address 22h)
D7
D6
D5
D4
D3
D2
D1
D0
C4B7
C4B6
C4B5
C4B4
C4B3
C4B2
C4B1
C4B0
0
0
0
0
0
0
0
0
8.6.14 Coefficient b0 Data Register Bits 23...16 (Address 23h)
D7
D6
D5
D4
D3
D2
D1
D0
C5B23
C5B22
C5B21
C5B20
C5B19
C5B18
C5B17
C5B16
0
0
0
0
0
0
0
0
8.6.15 Coefficient b0 Data Register Bits 15...8 (Address 24h)
D7
D6
D5
D4
D3
D2
D1
D0
C5B15
C5B14
C5B13
C5B12
C5B11
C5B10
C5B9
C5B8
0
0
0
0
0
0
0
0
8.6.16 Coefficient b0 Data Register Bits 7...0 (Address 25h)
D7
D6
D5
D4
D3
D2
D1
D0
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
C5B0
0
0
0
0
0
0
0
0
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STA326
8.6.17 Coefficient Write Control Register (Address 26h)
D7
D6
D5
D4
D3
D2
D1
D0
RA
R1
WA
W1
0
0
0
0
Coefficients for EQ, Mix and Scaling are handled internally in the STA326 via RAM. Access to this RAM
is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. First register contains the coefficient base address, five sets of three registers store the values of the
24-bit coefficients to be written or that were read, and one contains bits used to control the read or write
of the coefficient (s) to RAM. The following are instructions for reading and writing coefficients.
8.7 Reading a coefficient from RAM
■
write 8-bits of address to I2C register 16h
■
write ‘1’ to bit R1 (D2) of I2C register 26h
■
read top 8-bits of coefficient in I2C address 17h
■
read middle 8-bits of coefficient in I2C address 18h
■
read bottom 8-bits of coefficient in I2C address 19h
8.8 Reading a set of coefficients from RAM
■
write 8-bits of address to I2C register 16h
■
write ‘1’ to bit RA (D3) of I2C register 26h
■
read top 8-bits of coefficient in I2C address 17h
■
read middle 8-bits of coefficient in I2C address 18h
■
read bottom 8-bits of coefficient in I2C address 19h
■
read top 8-bits of coefficient b2 in I2C address 1Ah
■
read middle 8-bits of coefficient b2 in I2C address 1Bh
■
read bottom 8-bits of coefficient b2 in I2C address 1Ch
■
read top 8-bits of coefficient a1 in I2C address 1Dh
■
read middle 8-bits of coefficient a1 in I2C address 1Eh
■
read bottom 8-bits of coefficient a1 in I2C address 1Fh
■
read top 8-bits of coefficient a2 in I2C address 20h
■
read middle 8-bits of coefficient a2 in I2C address 21h
■
read bottom 8-bits of coefficient a2 in I2C address 22h
■
read top 8-bits of coefficient b0 in I2C address 23h
■
read middle 8-bits of coefficient b0 in I2C address 24h
■
read bottom 8-bits of coefficient b0 in I2C address 25h
8.9 Writing a single coefficient to RAM
■
write 8-bits of address to I2C register 16h
■
write top 8-bits of coefficient in I2C address 17h
■
write middle 8-bits of coefficient in I2C address 18h
■
write bottom 8-bits of coefficient in I2C address 19h
■
write 1 to W1 bit in I2C address 26h
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STA326
8.10 Writing a set of coefficients to RAM
■
write 8-bits of starting address to I2C register 16h
■
write top 8-bits of coefficient b1 in I2C address 17h
■
write middle 8-bits of coefficient b1 in I2C address 18h
■
write bottom 8-bits of coefficient b1 in I2C address 19h
■
write top 8-bits of coefficient b2 in I2C address 1Ah
■
write middle 8-bits of coefficient b2 in I2C address 1Bh
■
write bottom 8-bits of coefficient b2 in I2C address 1Ch
■
write top 8-bits of coefficient a1 in I2C address 1Dh
■
write middle 8-bits of coefficient a1 in I2C address 1Eh
■
write bottom 8-bits of coefficient a1 in I2C address 1Fh
■
write top 8-bits of coefficient a2 in I2C address 20h
■
write middle 8-bits of coefficient a2 in I2C address 21h
■
write bottom 8-bits of coefficient a2 in I2C address 22h
■
write top 8-bits of coefficient b0 in I2C address 23h
■
write middle 8-bits of coefficient b0 in I2C address 24h
■
write bottom 8-bits of coefficient b0 in I2C address 25h
write 1 to WA bit in I2C address 26h
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients
corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects.
When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (e.g.
0, 5, 10, 15, …, 45 decimal), and the STA326 will generate the RAM addresses as offsets from this base
value to write the complete set of coefficient data.
■
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STA326
Table 34. RAM Block for Biquads, Mixing, and Scaling
Index (Decimal)
Index (Hex)
Coefficient
Default
0
00h
C1H10 (b1/2)
000000h
1
01h
C1H11 (b2)
000000h
2
02h
C1H12 (a1/2)
000000h
3
03h
C1H13 (a2)
000000h
4
04h
C1H14 (b0/2)
400000h
5
05h
C1H20
000000h
…
…
…
…
19
13h
Channel 1 – Biquad 4
C1H44
400000h
20
14h
Channel 2 – Biquad 1
C2H10
000000h
21
15h
C2H11
000000h
…
…
…
…
39
27h
C2H44
400000h
40
28h
C12H0 (b1/2)
000000h
Channel 1 – Biquad 1
Channel 1 – Biquad 2
…
…
Channel 2 – Biquad 4
2nd
High-Pass
Order Filter
For XO = 000
41
29h
C12H1 (b2)
000000h
42
2Ah
C12H2 (a1/2)
000000h
43
2Bh
C12H3 (a2)
000000h
44
2Ch
C12H4 (b0/2)
400000h
45
2Dh
C12L0 (b1/2)
000000h
46
2Eh
C12L1 (b2)
000000h
47
2Fh
C12L2 (a1/2)
000000h
48
30h
C12L3 (a2)
000000h
49
31h
C12L4 (b0/2)
400000h
50
32h
Channel 1 – Pre-Scale
C1PreS
7FFFFFh
51
33h
Channel 2 – Pre-Scale
C2PreS
7FFFFFh
52
34h
Channel 1 – Post-Scale
C1PstS
7FFFFFh
53
35h
Channel 2 – Post-Scale
C2PstS
7FFFFFh
54
36h
Channel 3 – Post-Scale
C3PstS
7FFFFFh
55
37h
Thermal Warning – Post Scale
TWPstS
5A9DF7h
56
38h
Channel 1 – Mix 1
C1MX1
7FFFFFh
57
39h
Channel 1 – Mix 2
C1MX2
000000h
58
3Ah
Channel 2 – Mix 1
C2MX1
000000h
59
3Bh
Channel 2 – Mix 2
C2MX2
7FFFFFh
60
3Ch
Channel 3 – Mix 1
C3MX1
400000h
61
3Dh
Channel 3 – Mix 2
C3MX2
400000h
62
3Eh
UNUSED
63
3Fh
UNUSED
Low-Pass 2nd Order Filter
For XO = 000
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STA326
8.11 Variable Max Power Correction (Address 27h-28h):
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place
of the default coefficient when MPCV = 1.
Table 35.
D7
D6
D5
D4
D3
D2
D1
D0
MPCC15
MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0
0
1
0
1
1
0
1
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
1
1
0
0
0
0
0
0
8.12 Fault Detect Recovery (Address 2Bh-2Ch):
FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE
output will be immediately asserted low and held low for the time period specified by this constant. A constant value of 0001h in this register is ~.083ms. The default value of 000C specifies ~.1mSec.
Table 36.
D7
D6
D5
D4
D3
D2
D1
D0
FRDC15
FDRC14
FDRC13
FDRC12
FDRC11
FDRC10
FDRC9
FDRC8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
FDRC7
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FDRC0
0
0
0
0
1
1
0
0
Figure 15.
OUTY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTY
INY
M57
+
-
gnd
38/43
R 8Ω
V67 =
vdc = Vcc/2
D02AU1448
STA326
9
SCHEMATIC DIAGRAMS
Table 37. Component Selection Table 1
Load
Inductor
Capacitor
4Ω
10uH
1.0uF
6Ω
15uH
470nF
8Ω
22uH
470nF
Load
Inductor
Capacitor
4Ω
22uH
680nF
6Ω
33uH
470nF
8Ω
47uH
390nF
Table 38. Component Selection Table 2
Figure 16. Schematic Diagram for 2(Half-bridge).1(Full-bridge)-channel On-board Power.
39/43
STA326
Figure 17. Schematic Diagram for 2-channel (Full-bridge) Power.
Figure 18. Schematic Diagram for 1-channel Mono-Parallel Power..
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STA326
Figure 19. PowerSO36 Slug Up Mechanical Data & Package Dimensions
DIM.
A
A2
A4
A5
a1
b
c
D
D1
D2
E
E1
E2
E3
E4
e
e3
G
H
h
L
N
s
MIN.
3.25
3.1
0.8
mm
TYP.
MAX.
3.43
3.2
1
MIN.
0.128
0.122
0.031
-0.040
0.38
0.32
16
9.8
0.0011
0.008
0.009
0.622
0.37
14.5
11.1
2.9
6.2
3.2
0.547
0.429
0.2
0.030
0.22
0.23
15.8
9.4
5.8
2.9
0.8
OUTLINE AND
MECHANICAL DATA
-0.0015
0.015
0.012
0.630
0.38
0.039
0.57
0.437
0.114
0.244
1.259
0.228
0.114
0.65
11.05
0
15.5
MAX.
0.135
0.126
0.039
0.008
1
13.9
10.9
inch
TYP.
0.026
0.435
0.075
15.9
1.1
1.1
10˚
8˚
0
0.61
0.031
0.003
0.625
0.043
0.043
10˚
8˚
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
7183931 D
41/43
STA326
Table 39. Revision History
42/43
Date
Revision
Description of Changes
July 2005
1
First Issue
May 2006
2
Changed from preliminary data to maturity.
STA326
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