ETC DRM034

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PC CAN
Interface
Designer Reference
Manual
HCS12
Microcontrollers
DRM034/D
Rev. 0, 03/2003
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PC_CAN Interface
Reference Design
Designer Reference Manual — Rev 0
by: Jaromir Chocholac
Zdenek Kaspar
TU682
Czech Systems Laboratories
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Revision history
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
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The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Revision history
Date
Revision
Level
January,
2003
1.0
Description
Initial release
Designer Reference Manual
Page
Number(s)
N/A
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Designer Reference Manual — PC_CAN
List of Sections
Section 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Section 2. Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Section 3. Hardware Description . . . . . . . . . . . . . . . . . . . 19
Section 4. Software Module Descriptions. . . . . . . . . . . . 33
Appendix A. Bill of Materials and Schematics . . . . . . . . 73
Appendix B. Source Code Files . . . . . . . . . . . . . . . . . . . . 81
Appendix C. Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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List of Sections
Designer Reference Manual
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Designer Reference Manual — PC_CAN
Table of Contents
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Section 1. Introduction
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2
Application intended functionality . . . . . . . . . . . . . . . . . . . . . . . 13
1.3
Benefits of our solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Section 2. Quick Start
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
PC_CAN Interface Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4
MCU Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Section 3. Hardware Description
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
PC_CAN Interface Reference Design Architecture . . . . . . . . . 25
3.5
The Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.7
Board Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.8
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Section 4. Software Module Descriptions
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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Table of Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3
Project Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Appendix A. Bill of Materials and Schematics
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
A.2
PC_CAN Interface Bill of Materials. . . . . . . . . . . . . . . . . . . . . . 74
A.3
PC_CAN Interface Schematics. . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix B. Source Code Files
B.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
B.2
CAN_master.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
B.3
CAN_master.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.4
rti.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
B.5
rti.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
B.6
spi.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
B.7
spi.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
B.8
s12_regs.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
B.9
s12_regs.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
B.10 MC9S12DP256_RAM.prm . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
B.11 MC9S12DP256_FLAT.prm. . . . . . . . . . . . . . . . . . . . . . . . . . .119
Appendix C. Glossary
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Designer Reference Manual — PC_CAN
List of Figures
Figure
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2-1
2-2
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
A-1
A-2
A-3
A-4
Title
Page
PC_CAN Interface Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jumper JP6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PC_CAN Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . 20
Board Component Side Layout. . . . . . . . . . . . . . . . . . . . . . . . . 29
Board Solder Side Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Analog Configuration word composition . . . . . . . . . . . . . . . . . . 60
Digital Inputs word composition . . . . . . . . . . . . . . . . . . . . . . . .60
Digital Outputs word composition . . . . . . . . . . . . . . . . . . . . . . . 60
Analog Configuration byte composition . . . . . . . . . . . . . . . . . . 60
rxCANProcess() function flowchart. . . . . . . . . . . . . . . . . . . . . . 62
nodeIDProcess() function flowchart . . . . . . . . . . . . . . . . . . . . . 64
analogConfigProcess() function flowchart . . . . . . . . . . . . . . . . 66
Black box demo scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
rtiISR() function flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MODULE BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
RS232. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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List of Figures
Designer Reference Manual
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Designer Reference Manual — PC_CAN
List of Tables
Table
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3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
A-1
Title
Page
MC9S12DP256 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . 32
List of application events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SPI modules usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SCI modules usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
msCAN modules usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Memory usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
List of message types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Messages description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Black Box module connection. . . . . . . . . . . . . . . . . . . . . . . . . . 67
PC_CAN Interface Bill of materials. . . . . . . . . . . . . . . . . . . . . . 74
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List of Tables
Designer Reference Manual
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Designer Reference Manual — PC_CAN
Section 1. Introduction
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1.1 Contents
1.2
Application intended functionality . . . . . . . . . . . . . . . . . . . . . . . 13
1.3
Benefits of our solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Application intended functionality
This reference design of the PC_CAN Interface provides an RS232 to
CAN bus interface for industrial automation purpose. The reference
design demonstrates the ability of HCS12 MCU family to control analog
devices trough the CAN bus. The CAN interface is compatible to ISO
11898 and allow maximum data transfer rate of 1 Mbit/s.
The PC_CAN Interface software was designed with embedded demo
application software (PC master). The PC master software is used to
control and observe application variables. This tool allows the remote
control of an application from a user-friendly graphical environment,
running on a PC. It also enables the real-time display of application
variables, in both textual and graphical form.
1.3 Benefits of our solution
The PC_CAN Interface can be used as a hardware platform for high
level communication protocol software development. In addition, the
PC_CAN Interface enables the implementation and testing of user
software.
With the embedded demo application software this interface allows the
remote control of an application from a user-friendly graphical
environment, running on a PC.
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Introduction
Designer Reference Manual
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Designer Reference Manual — PC_CAN
Section 2. Quick Start
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
PC_CAN Interface Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4
MCU Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Introduction
This section describes the main procedures required to set up and start
the PC_CAN Interface Reference Design. The document also describes
the specific steps and provides additional reference information.
The PC_CAN Interface Reference Design is distributed with embedded
demo application software (PC Master). The PC Master software is used
to control and observe application variables. This tool allows the remote
control of an application from a user-friendly graphical environment,
running on a PC. It also enables the real-time display of application
variables, in both textual and graphical form.
The PC_CAN Interface Reference Design is initially delivered with the
embedded application PC Master software for use it in the Industrial
CAN I/O Module kit. The application software is placed in the flash
memory, then if needed, the interface can be reprogrammed for any
other application.
For more details about the Industrial CAN I/O Module kit, refer to
“Industrial CAN I/O Module - Design Reference Manual”.
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Quick Start
2.3 PC_CAN Interface Setup
Generally, the PC_CAN Interface Reference Design does not need any
setup. The Interface is distributed without Fault Tolerant CAN Interface
MC33388, so Jumpers JP1, JP2, JP3, JP4, JP5 must be closed. The
standard option of Interface is supplied from the CAN bus 24V power
supply, and pins 1 and 2 of JP8 must be closed. See Figure 2-1.
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The interface provides a 3-pole solder Jumper (JP6) for possible
configuration of the CAN speed. See Figure 2-2. Each Interface is
distributed with the CAN speed set to 500 kbps as default.
NOTE:
The CAN speed configuration is not supported in the distributed version
of software.
RS232
Connector
JP8
JP3
JP2
JP5
CAN
Connector
BDM
Connector
JP1
Figure 2-1. PC_CAN Interface Setup
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Quick Start
MCU Flash Programming
Figure 2-2. Jumper JP6
2.4 MCU Flash Programming
In order to allow the possibility of downloading software into the
application flash memory, Jumper JP5 must be open during the
programming process. In that case, the MCU’s reset pin is connected to
Vdd1 through pull up resistor R15, and the MCU is not affected by the
reset signal from SBC. For more details refer to datasheet “MC33989/D”.
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Designer Reference Manual — PC_CAN
Section 3. Hardware Description
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1
PC_CAN Interface Reference Design . . . . . . . . . . . . . . . . . 20
3.3.2
MC9S12DP256 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.3
MC33989 System Basis Chip. . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.4
MC33388 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.5
PC_CAN Interface Reference Design Functionality. . . . . . . 25
3.4
PC_CAN Interface Reference Design Architecture . . . . . . . . . 25
3.4.1
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.2
The CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.3
The RS232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5
The Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.7
Board Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.7.1
CAN Control Connector - J2. . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.2
RS232 Connector - J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.3
BDM Connector - J3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Introduction
This reference design of the PC_CAN Interface Reference Design
provides CAN- RS232 gateway for industrial automation purposes.
Besides this, the PC_CAN Interface Reference Design can be used as
a hardware platform for high level communication protocol software
development. In addition to that, the PC_CAN Interface Reference
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Hardware Description
MCU
CAN Transceiver
SBC
MC33989
CAN MODULE
CAN
RS232 Level
Converter
SCI
HCS12
RS232
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Design enables the implementation and testing of user software. For this
purpose, the board is equipped with a Background Debug Mode (BDM)
interface for reprogramming and debugging. The module contains a
MCU controller with CAN and RS232 transceivers. The CAN interface is
compatible to ISO 11898 and allows a maximum data transfer rate of 1
Mbit/s. The block diagram of the module can be seen in Figure 3-1.
Power
Figure 3-1. PC_CAN Interface Block Diagram
The reference design is based on CAN transceiver (PC33989 or
MC33388). The application is supported by HCS12 MCU.
3.3 Technical Data
This section provides technical data for both the PC_CAN Interface
Reference Design itself, as well as for the individual Motorola devices
used in the Interface.
3.3.1 PC_CAN Interface Reference Design
•
CAN Interface
– Compatible to ISO 11898
– Programmable speed (set up by coding switch)
125kbps, 250kbps, 500kbps and 1Mbps
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Hardware Description
Technical Data
•
Power Supply
– 24V/40mA
3.3.2 MC9S12DP256 Processor
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The control unit of the PC_CAN Interface Reference Design is the
MC9S12DP256 microcontroller unit (MCU). It is a 16-bit device
composed of a STAR12 CPU processing unit and standard on-chip
peripherals.
System resource mapping, clock generation, interrupt control and bus
interfacing are managed by the System Integration Module (SIM). The
MC9S12DP256 has full 16-bit data paths throughout. However, the
external bus can also operate in an 8-bit narrow mode, allowing an
interface to 8-bit wide memory for lower cost systems. The inclusion of
a PLL circuit allows power consumption and performance to be adjusted
to suit the operational requirements.
3.3.2.1 Features
•
16-bit STAR12 CPU
– Upwardly compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to
M68HC11
– 20-bit ALU
– Instruction pipe
– Enhanced indexed addressing
•
Multiplexed External Bus
•
Memory
– 256K byte Flash EEPROM
– 4.0K byte EEPROM
– 12.0K byte RAM
•
Two 8 channel Analog-to-Digital Converters
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Hardware Description
– 10-bit resolution
•
Five 1M bit per second, CAN 2.0 A, B software compatible
modules
– Four receive and three transmit buffers
– Flexible identifier filter, programmable as 2 x 32 bit, 4 x 16 bit
or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
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– Low-pass filter wake-up function
– Loop-back for self test operation
– Time-stamping capabilities for network synchronization
•
8 channel IC/OC Enhanced Capture Timer
•
Byte Data Link Controller (BDLC)
•
Inter-IC Bus (IIC)
•
8 PWM channels with programmable period and duty cycle
– Standard 8-bit 8-channel, 16-bit 4-channel, or any combination
of 8/16 bit
– Separate control for each pulse width and duty cycle
– Left-aligned or center-aligned outputs
– Programmable clock select logic, with a wide range of
frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
•
Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Three synchronous Serial Peripheral Interfaces (SPI)
•
SIM (System integration module)
– CRG (low current oscillator, PLL, reset, clocks, COP
watchdog, real time interrupt, clock monitor)
– MEBI (Multiplexed External Bus Interface)
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Hardware Description
Technical Data
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
•
112-Pin LQFP package or 80-Pin QFP package
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– 50 MHz CPU equivalent to 25MHz bus operation
– 2.25 to 2.75V Digital Supply Voltage, generated using an
internal voltage regulator
– 4.75V to 5.25V Analog and I/O Supply Voltage
3.3.3 MC33989 System Basis Chip
The MC33989 is a System Basis Chip (SBC) with high speed CAN
transceiver, primarily dedicated to automotive applications. It combines
Can high speed physical interface with one fully protected voltage
regulator (5V output) with 200mA total output current capability. As the
regulator supplies the CAN module, 120mA is available at the Vdd1
external pin for outside the circuit. In addition to that, it includes the
following functions:
– Driver for external path transistor for V2 regulator function.
– Reset, programmable watchdog function, INT
– 4 operational modes
– Programmable wake up input, and cyclic sense wake up
The device has four modes of operation: the stand-by mode, normal
mode, stop and sleep modes. All modes are controlled by the SPI.
3.3.3.1 Features
•
Nominal DC operating voltage from 5.5 to 27V, extended range
down to 4.5V
•
40V maximum transient voltage
•
High speed 1MBaud CAN physical interface
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•
Four operational modes (normal, stand-by, stop and sleep mode)
•
Low stand-by current consumption in stop and sleep modes
•
Low drop voltage regulator, current limitation, over temperature
detection, monitoring and reset function
•
Control circuitry for external bipolar ballast transistor for high
flexibility in choice of peripheral voltage and current supply
•
Four external high voltage wake-up inputs, associated with HS1
Vbat switch
•
150mA output current capability for HS1 Vbat switch, allowing
drive of external switches pull up resistors, or relays
•
Vsup failure detection
•
Programmable software time out and window Watchdog
•
Safe mode with separate outputs for Watchdog time out and
Reset
•
Wake up capabilities (four wake up inputs, programmable cyclic
sense, forced wake up, CAN interface and SPI)
•
Interface with MCU through SPI
3.3.4 MC33388 CAN Interface
The MC33388 is a Fault Tolerant CAN physical interface device. It
operates in differential mode, allowing ground shifts of up to 1.5V,
reducing RFI disturbances. It offers very low standby current in sleep
and standby mode operation, and supports communication speeds of up
to 125kBauds.
It is fully protected against harsh environments, and the driver is able to
detect fault conditions, automatically switching into the appropriate
default mode. Under fault condition, it continuously monitors bus
failures, in order to switch the bus operation back to normal as soon as
the faults disappear.
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PC_CAN Interface Reference Design Architecture
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3.3.4.1 Features
•
Very low sleep/standby current (15mA typical)
•
Baud rate from 10 kBaud up to 125kBauds
•
Automatic switching to single wire mode in the case of bus failure,
and return to differential mode if bus failure disappears
•
Supports one wire transmission modes with ground offset up to
1.5V
•
Internal bus driver slope control function to minimize RFI
•
Bus line short-circuit protected to battery, VDD and ground
•
Bus line protected against transients
•
Thermal protection of bus line drivers
•
Supports unshielded twisted pair bus
•
An unpowered node does not disturb the bus lines
•
Wake-up capability triggered from bus message and wake-up
input pin
•
Wake-up pin with dual edges sensitivity
•
Battery fail flag reported on NERR output
•
Ambient temperature range from -40°C to 125°C.
3.3.5 PC_CAN Interface Reference Design Functionality
The PC_CAN Interface Reference Design is dedicated for use in the
Industrial Automation market.
3.4 PC_CAN Interface Reference Design Architecture
Schematics of the PC_CAN Interface Reference Design are provided in
Appendix A. Bill of Materials and Schematics. The PC_CAN
Interface Reference Design block diagram can be seen in Figure A-1
The PC_CAN Interface Reference Design creates a gateway between
CAN bus and RS232 interface.
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The board is logically divided into the following three basic blocks:
•
Microcontroller
•
CAN Interface
•
RS232 Interface
3.4.1 Microcontroller
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A Motorola 16-bit MC9S12DP256 microcontroller unit (MCU) is the main
component (U3) of the Interface. You can find more details about the
microcontroller in section 3.3.2. The schematic diagram can be seen in
Figure A-4.
The PC_CAN Interface Reference Design uses one of five CAN
modules (CAN0) built into the MCU. The module is a communication
controller implementing the CAN 2.0 A/B protocol as defined in the
BOSCH specification. It is the specific implementation of the Motorola
Scalable CAN (MSCAN). The MSCAN uses 2 external pins, 1 input
(RxCAN0) and 1 output (TxCAN0). The signal, named SS_CAN, is
assigned to the CAN transceiver chip control.
The SPI module allows full-duplex, synchronous, and serial
communication between the MCU and peripheral devices. The PC_CAN
Interface Reference Design uses one of three SPI modules (SPI0) built
into the MCU. When the SPI system is enabled, the four associated SPI
port pins are dedicated to the SPI function as:
•
Serial clock (SCK)
•
Master out/slave in (MOSI)
•
Master in/slave out (MISO)
•
Slave select (see NOTE)
The SPI can be configured to operate as a master or as a slave. The
master mode must be selected for the SPI0 module, because only a
master SPI module can initiate transmissions.
NOTE:
During an SPI transmission, data is transmitted (shifted out serially) and
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PC_CAN Interface Reference Design Architecture
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received (shifted in serially) simultaneously. The serial clock (SCK)
synchronizes shifting and sampling of the information on the two serial
data lines (MOSI, MISO). A slave select line allows selection of an
individual slave SPI device; slave devices that are not selected do not
interfere with SPI bus activities. The MCU uses signal SS_CAN for the
selection of an slave SPI device - SBC (U2).
The board provides an jumper switch (JP6), for configuring the CAN
speed. The CAN speed setup signals are connected to port P, pins PP0
and PP1. The weight meaning of the JP6 positions is determined by
software. For more details see section 2.3.
Single-wire communication with host development system is done
through the Background Debug Mode (BDM) system, implemented in
on-chip hardware. Connection to the target system is made through the
standard six pins BDM Connector (J3). For details see section 3.7.3.
3.4.2 The CAN Interface
Each CAN station is connected physically to the CAN bus lines through
a transceiver chip. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective
CAN or defective stations. There are two possible options for the CAN
transceiver on the board. One of them is to use Fault Tolerant CAN
Interface MC33388; the other one is to use the high speed CAN
transceiver part of the MC33989 SBC device. The standard option is to
use the CAN transceiver part of the MC33989 device, as MC33388 is not
populated on the board. The MC33388 was designed on the board
mainly for development purposes. The schematic diagram of the CAN
interface can be seen in Figure A-2.
3.4.3 The RS232 Interface
The PC_CAN Interface module provides an RS-232 interface for
connection to a PC, or a similar host. Refer to the RS232 schematic
diagram in Figure A-3. The RS-232 level converter (U4) transforms the
SCI +5V signal levels to RS-232 compatible signal levels, and connects
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to the host’s serial port via connector J1. See block diagram Figure A-1.
The connector is arranged as a DCE port. Flow control is not provided.
3.5 The Power Supply
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The power supply is designed to meet all the power supply needs of
PC_CAN Interface Reference Design. To distribute a power dissipation
on the interface board, a two stage power supply was designed.
See Figure A-1 and Figure A-2
The linear voltage regulator (U5) converts an input power supply of 24V
into a board supply of 12V (VBat).
The SBC chip is supplied from the on board supply through pin Vsup,
and in turn, creates a 5V power supply (VDD)through the Vdd1
regulator.
VDD has an output current capability of up to 200mA, and supplies the
CAN module, leaving 120mA available for the microcontroller and
RS232 converter supply. The Vdd1 regulator includes voltage
monitoring circuitry with a reset function.
3.6 Board Layout
Detailed layout plans of the PC_CAN Interface Reference Design
boards, with the names of all components, are shown in this section.
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Hardware Description
Board Layout
Figure 3-2. Board Component Side Layout
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Figure 3-3. Board Solder Side Layout
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Board Connectors
3.7 Board Connectors
This section provides information on the Board connectors pin
assignments and meaning.
Freescale Semiconductor, Inc...
3.7.1 CAN Control Connector - J2
1
V-
+24V power supply return
2
CANL
CAN bus drive low line
3
NC
Not Connected
4
CANH
CAN bus drive high line
5
V+
+24V power supply
3.7.2 RS232 Connector - J1
1
NC
Not Connected
2
RX
RS232 - RX
3
TX
RS232 - TX
4
xxx
Jumper to 6
5
DGND
Digital Ground
6
xxx
Jumper to 4
7
xxx
Jumper to 8
8
xxx
Jumper to 7
9
NC
Not Connected
3.7.3 BDM Connector - J3
Background
Interface
BKGD
1
2
GND
Digital Ground
Not Connected
N.C.
3
4
RESET\
MCU Reset
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Not Connected
N.C
5
6
VDD
+5V Power supply
3.8 Memory Map
Table 3-1 shows the device memory map of the MC9S12DP256 after
reset. Note that after reset the bottom 1k of the EEPROM ($0000 $03FF) is hidden by the register space.
Freescale Semiconductor, Inc...
Table 3-1. MC9S12DP256 Memory Map
From
To
Size
Content
0x0000
0x03FF
1k
REGISTERS
0x0000
0x0FFF
4k
EEPROM
0x1000
0x3FFF
12k
RAM
0x4000
0x7FFF
16k
Fixed Flash
0x8000
0xBFFF
16k
Paged Flash
0xC000
0xFEFF
16k-256b
Fixed Flash
0xFF00
0xFFFF
256bytes
VECTORS
The internal register block, RAM, and EEPROM have default locations
within the 64K byte standard address space, but may be reassigned to
other locations during program execution by setting bits in the mapping
registers. For a detailed description of the MC9S12DP256 memory map,
refer to the MC9S12DP256 Device User Guide, Motorola document
order number 9S12DP256BDGV2/D.
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Section 4. Software Module Descriptions
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4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1
Software Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2
Initialization Routines Basics . . . . . . . . . . . . . . . . . . . . . . . .34
4.2.3
Demo Application Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3
Project Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1
List of the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.2
Utilized Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.3
Project Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.4
Memory Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.4
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4.1
SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.4.2
msCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.3
SCI Module and PC Master software Initialization . . . . . . . . 55
4.4.4
RTI Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4.5
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.2 Introduction
This section of the reference design provides a complete documentation
of the PC_CAN Interface software.
4.2.1 Software Basics
All embedded software of this project was written using the CodeWarrior
for MOTOROLA 8- & 16-Bit MCU version 1.0 by Metrowerks Corporation
(http://www.metrowerks.com).
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The msCAN Driver Software version 1.0 by Metrowerks was used for the
development, as it is an msCAN periphery low level driver. Although this
tool made the development faster and the final source code more
readable, it is assumed that the reader has at least some experience
with Controller Area Network (CAN) connectivity. For CAN 2.0
specification see CAN in Automation (CiA) at http://www.can-cia.de/can/.
The PC Master software is used to control and for visualization of
application variables. This tool allows the remote control of an
embedded application from a PC based graphical environment. It also
enables the real-time display of application variables, in both textual and
graphical form.
Software content of the project can be divided into two basic groups. In
the first group, are all the initialization routines necessary to configure
both the MCU peripherals and all the sub-modules of the system, while
the second part consists of the routines for the PC_CAN Interface demo
application. Therefore, separate descriptions will be given for
initialization routines and for the demo application. The demo application
is enabled when the following symbolic constant is defined in
CAN_master.h file.
#define BLACK_BOX
/* if defined, the Black Box demo application is ON */
4.2.2 Initialization Routines Basics
Here is a list of the routines for the first group, responsible for
initialization and configuration of the PC_CAN Interface. Details about
each item on the list will be given in the Software Implementation
chapters.
•
MOTOROLA Scalable CAN (msCAN) periphery module
initialization (including module addressing, baud-rate selection,
CAN identifiers settings and msCAN message objects definition)
•
Serial Peripheral Interface (SPI) periphery module initialization for
communication with the PC33989 device
•
Configuration of the PC33989 System Basis Chip with High Speed
CAN transceiver, via the SPI channel
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Introduction
•
Serial Communication Interface (SCI) periphery module
initialization for communication with the PC Master software
•
Real Time Interrupt (RTI) module initialization for the demo
application
4.2.3 Demo Application Basics
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The referred demo application is a part of the PC_CAN Interface
Reference Design project, where two kinds of devices are embodied PC_CAN Interface Reference Design and PC_CAN Interface. Thus the
application implementation itself is also divided between these two
devices.
While Software Module Descriptions chapter of this document will
provide information of the software implementation of the PC_CAN
Interface part of the application, for more information about PC_CAN
Interface Reference Design refer to “PC_CAN Interface Reference
Design - Design Reference Manual”.
A detailed introduction to the demo application is given in Section 1.
Quick Start of the PC_CAN Interface Reference Design - Design
Reference Manual. That chapter describes software installation, demo
setup & configuration, and even the PC Master software shared
variables.
NOTE:
Please note that for the PC_CAN Interface Reference Design kit demo
application, both the PC_CAN Interface Reference Design and the
PC_CAN Interface have to be used. However, a standalone PC_CAN
Interface module provides an programmable RS232 / CAN interface
and, in addition, the PC_CAN Interface can be used as a hardware
platform for any other user software development, such as high level
communication protocol implementation and so on.
The aim of the demo application is to show the main features of the
PC_CAN Interface Reference Design (16 digital and 8 analog inputs, 16
digital outputs), together with the utilization of the CAN connectivity. A
simplified description of the PC_CAN Interface part of the application is
that the module enables users to send, through the PC Master software
environment, command messages to the PC_CAN Interface Reference
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Design. It also receives the PC_CAN Interface Reference Designs
status messages and visualizes them for the user. And finally, when the
“Black box” demo application is enabled, its controlling algorithm is
located here as well.
A list of all events of the module can be seen in the following Table 4-1.
.
Freescale Semiconductor, Inc...
Table 4-1. List of application events
Event description
Initiator
Recipient
Change of Analog Inputs block parameters (range, accuracy)
of PC_CAN Interface Reference Design
Superior device
PC_CAN
Interface
Reference
Design
Status of Analog Inputs block values of PC_CAN Interface
Reference Design
PC_CAN
Interface
Reference
Design
Superior device
Set new Digital Outputs values of PC_CAN Interface
Reference Design
Superior device
PC_CAN
Interface
Reference
Design
Status of all Digital values of PC_CAN Interface Reference
Design
PC_CAN
Interface
Reference
Design
Superior device
Change of state of Digital Inputs values of PC_CAN Interface
Reference Design
PC_CAN
Interface
Reference
Design
Superior device
4.3 Project Introduction
This section gives an introduction and description of the software
implementation of the PC_CAN Interface project.
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4.3.1 List of the Project Files
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The Project was written using the Metrowerks CodeWarrior for
MOTOROLA 8- & 16-Bit MCU version 1.0. In this chapter, a list of all
source code files of the CodeWarrior project can be found. It will be
divided into three parts:
•
Project source codes
•
MC9S12DP256 periphery structure
•
msCAN Driver Software routines
4.3.1.1 Project Source Codes
•
master CAN.mcp is a Metrowerks CodeWarrior project file
•
CAN_master.c is a main file of the project containing the
complete initialization, global variables declaration and the main()
routine
•
CAN_master.h is the header file of the CAN_master.c; it
contains all project-related symbolic constants and function style
macros, as well as the structure definitions
•
spi.c and spi.h files consist of Serial Peripheral Interface (SPI)
based routines used for periphery module initialization and
communication with the PC33989 device
•
rti.c and rti.h files contain all Real Time Interrupt (RTI) related
periphery initialization and interrupt service routine (ISR)
•
s12_regs.c and s12_regs.h are files for periphery module
allocation (see 4.3.1.2 MC9S12DP256 Periphery Structure) within
MCU memory
•
MC9S12DP256_FLAT.prm and MC9S12DP256_RAM.prm are
parameter files of the device for RAM and FLASH configuration
4.3.1.2 MC9S12DP256 Periphery Structure
•
s12_atd.h is a header file for Analog to Digital (ATD) register block
•
s12_bdlc.h is a header file for J1850 Byte Data Link Controller
(BDLC)
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NOTE:
•
s12_common.h is a header file for HCS12 common definitions
•
s12_crg.h is a header file of HCS12 Clocks and Reset Generator
(CRG) block
•
s12_eeprom.h is a header file containing EEPROM control
registers block definitions
•
s12_flash.h is a header file for HCS12 Flash control registers
block
•
s12_iic.h is a header file for HCS12 Inter-IC Bus (IIC) register
block
•
s12_mscan.h is a header file for HCS12 Motorola Scalable
(msCAN) register block
•
s12_page.h is a header file for HCS12 Page (MEBI) register block
•
s12_pim.h is a header file for HCS12 Port Integration Module
(PIM) block
•
s12_pwm.h is a header file for HCS12 PWM register block
•
s12_register.h is a header file for HCS12 register block
•
s12_sci.h is a header file containing the HCS12 Serial
Communications Interface (SCI) register block
•
s12_spi.h is a header file containing the HCS12 Serial Peripheral
Interface (SPI) register block definition
•
s12_template.h is a template file of periphery register block
definition
•
s12_timer.h is a header file for HCS12 Timer block
Note that although not all of the MC9S12DP256 periphery modules are
used within the project, all of them are included in the project. Thus they
are available to a developer for immediate use.
4.3.1.3 msCAN Driver Software Routines
As already mentioned, msCAN Driver Software is used in the project,
and thus msCAN low level initialization is eliminated from the project.
The driver itself consists of a couple of source code files (*.c and *.h) and
one object file called msCANs12drv.o, where a key part of the driver
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implementation is carried out. Chapter 4.4.2 covers all the msCAN
related topics to this project.
4.3.1.4 MCU Peripherals Utilized
This section briefly describes all MCU peripheral components used in
the project. It gives an overall summary picture of the necessary MCU
resources.
Freescale Semiconductor, Inc...
A brief description of the SPI modules usage is given in the following
Table 4-2.
Table 4-2. SPI modules usage
SPI
Purpose
ISR
function
SPI0
communication with PC33989 device
-
SPI1
not used
n/a
SPI2
not used
n/a
Usage of SCI modules of the MCU is given in the following table.
Table 4-3. SCI modules usage
NOTE:
SCI
Purpose
ISR
function
SCI0
RS232 communication with PC Master
software
-
SCI1
not used
n/a
SCI0 periphery module is, except for the initialization routine, completely
controlled by embedded part of the PC Master software.
A description of the msCAN modules usage is given in the Table 4-4.
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Table 4-4. msCAN modules usage
msCAN
Purpose
ISR function
msCAN0
demo application CAN connectivity
authority of msCAN
Driver Software
msCAN1
not used
n/a
msCAN2
not used
n/a
msCAN3
not used
n/a
msCAN4
not used
n/a
4.3.2 Utilized Interrupts
All interrupts used within the PC_CAN Interface project are briefly
detailed in Table 4-5.
Table 4-5. Interrupts
Symbolic name
of periphery
ISR function
Type of the
interrupt
Note
RTI
rtiISR()
real time interrupt
n/a
msCAN0 Tx
CAN0_TransmitISR()
msCAN
transmission
authority of
msCAN Driver
Software
msCAN0 Rx
CAN0_ReceiveISR()
msCAN reception
authority of
msCAN Driver
Software
msCAN0 wake-up
CAN0_WakeupISR()
msCAN wake-up
authority of
msCAN Driver
Software
4.3.3 Project Variables
In this section a brief description of the main project variables is given.
The most important variable is called node and is declared as follows:
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volatile sNode node;
/* complete Node information */
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This single structure variable contains complete information of the
device, such as node status (node.state), node identification
(node.nodeID), values of digital inputs and digital outputs (node.digitIn,
node.digitOut), analog input values (node.analog[8]) and configuration
of the analog inputs (node.analogConf[8]). sNode structure is defined as
follows:
typedef struct
{
tU16 value : 10;
tU16 dumb : 5;
tU16 mode : 1;
/* mode = 0 ...
/* mode = 1 ...
} sAnalog;
/* structure of pcAnalog variable word */
/* analog value of ADC */
/* reserved for future */
/* mode configuration of ADC module */
normal voltage measurement according to "range" value */
current loop measurement */
typedef struct
/* structure of pcAnalogConf byte variable */
{
tU08 range : 2;
/* range configuration of ADC module */
tU08 dumb : 5;
/* reserved for future */
tU08 accuracy : 1; /* ADC module accuracy */
/* accuracy = 0 ... 8 bit accuracy */
/* accuracy = 1 ... 10 bit accuracy */
} sAnalogConf;
typedef union
{
tU16
word;
struct
{
tU08
msb;
tU08
lsb;
} byte;
sAnalog
struc;
} uAnalog;
typedef union
{
tU16
word;
struct
{
tU08
msb;
tU08
lsb;
} byte;
} uDigital;
/* union for Analog variable word */
/* access whole word */
/* access byte at a time */
/* access as declared in sAnalog structure */
/* union for Digital variable word */
/* access whole word */
/* access byte at a time */
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typedef struct
{
tU08 state;
/* state = STATE_KO (0)
/* state = STATE_OK (1)
tU08
nodeID;
uDigital
digitIn;
uDigital
digitOut;
uAnalog
analog[8];
sAnalogConf analogConf[8];
} sNode;
NOTE:
/* structure of the node information */
/* node status */
... node is not connected or not ready */
... node is connected */
/* node identification */
/* digital input values */
/* digital output values */
/* union of analog value */
/* analog configuration structure */
For a graphical representation of the key components of sNode structure
type see 4.4.5.2 Message Types Details.
Then there is a considerable number of variables shared with the
Personal Computer application through the PC Master software.
Description of the key ones is made in chapter 1.8 Demo System
Variables Description of the PC_CAN Interface Reference Design Design Reference Manual; below is the listing of them.
/******************************************************************************/
/* G L O B A L
V A R I A B L E S
S H A R E D
F O R
P C
M a s t e r */
/******************************************************************************/
/* variables dedicated for sharing with PC via PC Master */
volatile tU08 pcState;
/* node status */
/* STATE_KO 0x0
state of node is "data are not ready" */
/* STATE_OK 0xFF state of node is "communicating" */
volatile tU08 pcGTWState;
/* gateway status */
/* GTW_CAN_KO
0x1
state of the gateway: CAN failure */
/* GTW_TEMP_WARN 0x2
state of the gateway: Vdd temperature warning */
/* GTW_OK
0xFF state of the gateway: no issues */
volatile tU08 pcNodeID;
/* node identification */
volatile uDigital pcDigitIn;
/* digital input values */
volatile uDigital pcDigitOut;
/* digital output values */
volatile uAnalog pcAnalog[8];
/* array of structure of analog values */
volatile sAnalogConf pcAnalogConf[8]; /* analog configuration structure */
/* variables dedicated for sharing with PC via PC Master for Black Box application */
volatile sPcDemoStatus pcDemoStatus;
/* status of the demo */
volatile tU16 pcAnalogLimit_1;
/* analog limit value for process #1 */
volatile tU16 pcAnalogLimit_2;
/* analog limit value for process #2 */
/* Note that value equal to 1 makes delay 25ms long */
volatile tU16 pcDelayTime_1;
/* delay time value for process #1 */
volatile tU16 pcDelayTime_2;
/* delay time value for process #2 */
volatile tU16 pcAccuracyRange;
/* value for PC Master linear transformation */
/* VALUE_FOR_8BIT
128
value for PC Master transformation */
/* VALUE_FOR_10BIT 512
according to desired ADC accuracy */
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Project Introduction
Structure sPcDemoStatus is defined as follows:
typedef struct
{
tU08 state_1 : 1;
tU08 delay_1 : 1;
Freescale Semiconductor, Inc...
tU08 dumb
: 2;
tU08 state_2 : 1;
tU08 delay_2 : 1;
tU08 dumb2
: 2;
} sPcDemoStatus;
/* structure of pcDemoStatus byte variable */
/* status of first demo LED */
/* 0 - process is stopped
1 - process is started */
/* first demo LED is in delay (while running) */
/* 0 - not delayed, charging
1 - delayed after de-charging */
/* reserved for future */
/* status of second demo LED */
/* 0 - process is stopped
1 - process is started */
/* second demo LED is in delay (while running) */
/* 0 - not delayed, charging
1 - delayed after de-charging */
/* reserved for future */
There are also a couple of symbolic constants (defined in
CAN_master.h), which control the behaviour and configuration of the
application.
•
The demo application is enabled when the BLACK_BOX symbolic
constant is defined in file.
•
When a 16 MHz crystal is utilized in the design, the OSC_16MHZ
symbolic constant has to be defined; for 4 MHz, the OSC_4MHZ
definition should be used.
•
When FAST_CAN_ENABLE symbolic constant is not defined, the
MC33388D Low speed CAN physical line driver (125kbps) is
used, instead of the PC33989 System Basis Chip with High Speed
CAN transceiver.
•
CAN baudrate setting is defined by CAN_SPEED symbolic
constant, valid values are 125, 250 or 500 kbps.
/******************************************************************************/
/*
A P P L I C A T I O N
D E F I N E S
*/
/******************************************************************************/
/* public defines for user's reconfiguration */
#define OSC_16MHZ
/* running on 16Mhz crystal */
//#define OSC_4MHZ
/* running on 4MHz crystal */
#define CAN_SPEED
BAUDRATE_500
/* this defines the CAN baudrate, valid values are 125, 250 and 500 kbps */
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/* note that this settings is valid only when OSC_16MHZ is defined
and SBC MC33989 is connected (FAST_CAN_ENABLE has to be defined) */
#define BLACK_BOX
/* if defined, the Black Box demo application is ON */
#define FAST_CAN_ENABLE /* if defined, PC33989 SBC is used instead of MC33388D */
Freescale Semiconductor, Inc...
NOTE:
Note that the variable (higher) CAN baudrate settings can be used only
when both the PC33989 device is connected and the OSC_16MHZ is
defined (16 MHz crystal connected), otherwise the CAN baudrate is
fixed at 125kbps.
4.3.4 Memory Usage
The following table shows the PC_CAN Interface software memory
usage:
Table 4-6. Memory usage
Type of memory
Total size (B)
Used memory (B)
program flash
40000h
165Ch
data
3000h
419h
4.4 Software Implementation
In this section a complete description of the key software modules for the
reference design is given.
4.4.1 SPI Communication
The SPI communication channel is used for the configuration of the
PC33989 System Basis Chip with High Speed CAN transceiver device.
Description of the SPI module initialization is presented in the next
chapter.
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4.4.1.1 SPI Periphery Module Initialization
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The initialization is implemented in spi0Init() routine of spi.c and is called
from init() function of CAN_master.c file.
There are a couple of key settings of the SPI format. At first, it is
important to set the Master mode of the SPI device to be equal to 1
because only a master SPI device can initiate transmission with
peripherals. SPI format for communication with PC33989 device is 8-bit
long and is configured to transfer the most significant bit first. The SPI
baud rate setting (value of the SPI Serial clock, called SCLK) is set to a
value of 4 MHz. The SPI Clock phase shift bit setting is equal to 1 (the
first SCLK edge is issued at the beginning of the 8-cycle transfer
operation).
For the SPI communication, the pooling approach was chosen so there
is no SPI interrupt enabled.
Here is the complete SPI module initialization, taken from the spi0Init().
spi0.spicr1.bit.lsbf
= 0;
spi0.spicr1.bit.ssoe
=
spi0.spicr1.bit.cpha
=
spi0.spicr1.bit.cpol
=
spi0.spicr1.bit.mstr
=
spi0.spicr1.bit.sptie =
spi0.spicr1.bit.spe
=
spi0.spicr1.bit.spie
=
spi0.spicr2.bit.spc0
/*
/*
/*
/*
/*
/*
lsb first enable bit */
msb bit is transferred first */
0;
slave select output enable */
slave select output is not enabled */
1;
SPI clock phase bit */
first SCLK edge issued at the beginning
of the 8-cycle transfer operation */
0;
/* clock polarity bit */
/* serial clock (SCK) active in high, SCK idles low */
1;
/* master/slave mode select bit */
/* Master mode selected */
0;
/* transmit interrupt enable bit */
/* transmit interrupt disabled, SPI
communication done in pooling style */
1;
/* spi enable bit */
/* enable SPI, SPI port pins are dedicated to SPI module */
0;
/* spi interrupt enable bit */
/* SPI interrupt disabled */
= 0;
/* serial pin control 0 bit */
/* no bidirectional pin configuration of the SPI */
spi0.spicr2.bit.spiswai = 0;
/* SPI stop in wait mode bit */
/* SCLK operates normally in wait mode */
spi0.spicr2.bit.bidiroe = 0;
/* bi-directional mode output enable bit */
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spi0.spicr2.bit.modfen
= 0;
/* output buffer disable in bidirectional mode */
/* mode fault enable bit */
/* disable the MODF error */
/* in order to run the SCLK on 4MHz while 16MHz crystal is connected
(thus 8 MHz Module CLK), SPI module clock divisor has to be 2 */
/* divider is set to 2, so SCLK is 4MHz for 8 MHzModule Clk */
spi0.spibr.bit.spr = 0;
/* baud rate selection */
spi0.spibr.bit.sspr = 0;
/* baud rate pre-selection */
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4.4.1.2 SPI Communication Routine
For SPI communication with a device, the following function is used. It
transmits one byte via the SPI channel. Value to be sent is a composite
of all the function arguments and the received byte is given as a function
return.
/*******************************************************************************
*
* Module: tU08 spi0TxByte (tU08 address, tU08 readWrite, tU08 value)
*
* Description: This is the SPI communication function. It transmit one byte via
*
SPI (address | readWrite | value) and pass the received one as an argument.
*
* Returns: outByte as the SPI received byte
*
* Global Data: None
*
* Arguments: composite of (address | readWrite | value) which is 1B long value
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
tU08 spi0TxByte (tU08 address, tU08 readWrite, tU08 value)
{
tU08 outByte;
while (spi0.spisr.bit.sptef == 0);
clearCSB();
spi0Write(address | readWrite | value);
while (spi0.spisr.bit.spif == 0);
outByte = spi0Read();
while (spi0.spisr.bit.sptef == 0);
setCSB();
return (outByte);
/*
/*
/*
/*
/*
/*
/*
while Tx reg not empty
set "chip select" */
write value to be send
while Rx reg not empty
store status byte */
while Tx reg not empty
unset "chip select" */
*/
*/
*/
*/
}
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4.4.1.3 PC33989 Communication
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For the address structure of the PC33989 System Basis Chip with High
Speed CAN transceiver device, these symbolic constants are defined in
spi.h file:
/* MC33989 addresses used for SPI communication */
#define MCR
0x00
/* Mode control register */
#define RCR
0x20
/* Reset control register */
#define CAN
0x40
/* CAN control register */
#define IOR
0x60
/* I/O control register */
#define WUR
0x80
/* Wake-up input register */
#define TIM
0xA0
/* Timing register */
#define LPC
0xC0
/* Low power mode control register */
#define INTR
0xE0
/* Interrupt register */
/* MC33989 read / write command used for SPI communication */
#define READ
0x00
/* read operation with MC33989 */
#define WRITE
0x10
/* write operation with MC33989 */
Two different types of configuration are presented for two types of the
PC33989 device operation modes:
•
1st variant puts the device into “Normal” mode of operation with
watch-dog running
/* "NORMAL" MODE OF SBC OPERATION */
/* "Normal" mode of operation, watchdog is enabled */
/* Watchdog timeout do push reset pin to low level */
/* configuration of the MC33989 chip for the first time */
tmp = spi0TxByte(TIM, WRITE, 0x3);
/* set no window watchdog with 400ms timing */
/* this watchdog configuration command is necessary, it has to be
called during first 350ms after entering the "Normal request" mode */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(MCR, WRITE, 0x1);
/* set SBC mode to "Normal" */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(RCR, WRITE, 0x0);
/* set Reset mode to "first mode" */
/* SAFE bit = 0 */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(CAN, WRITE, 0x0);
/* set CAN mode to "normal", slew rate 0 */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(INTR, WRITE, 0x3);
/* do not mask CAN failure and VDDTEMP
pre-warning */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
•
2nd variant shows the “Normal debug” initialization, while the
watchdog time-out does not control the Reset pin of PC33989
device
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/* "NORMAL DEBUG" MODE OF SBC OPERATION */
/* "Normal debug" mode of operation, watchdog is disabled */
/* Watchdog time out do not push reset pin to low level */
/* configuration of the MC33989 chip for the first time */
tmp = spi0TxByte(TIM, WRITE, 0x3);
/* set no window watchdog with 400ms timing */
/* this watchdog configuration command is necessary, it has to be
called during first 350ms after entering the "Normal request" mode */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(MCR, WRITE, 0x0);
/* set SBC mode to "Debug" */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(MCR, WRITE, 0x5);
/* set SBC mode to "Normal debug" */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(RCR, WRITE, 0x2);
/* set Reset mode to "safe mode" */
/* SAFE bit = 1 */
/* note that in this mode watchdog time out do not control the reset */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(CAN, WRITE, 0x0);
/* set CAN mode to "normal", slew rate 0 */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(INTR, WRITE, 0x3);
/* do not mask CAN failure and VDDTEMP
pre-warning */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
NOTE:
Note that there has to be at least 20 ms delay between individual
communication with PC33989 device.
For the watch dog service of the System Basis Chip with High Speed
CAN transceiver the following command is used as a part of rti_ISR()
routine of rti.c
#ifdef FAST_CAN_ENABLE
/* SBC watch dog serving */
if (count >= 4)
/* each 100ms */
{
tmp = spi0TxByte(TIM, WRITE, 0x3);
/* set watchdog to 400ms */
/* this command is necessary to serve the SBC watchdog */
count = 0;
}
#endif
The INTB signal of the PC33989 System Basis Chip with High Speed
CAN transceiver is connected to the IRQ pin of the MC9S12DP256.
Thus when the PC33989 is connected, IRQ interrupt should be enabled
in the application. This routine below reads the interrupt status flags of
the PC33989, the active INTB signal indicates either a CAN failure or a
Vddtemp pre-warning of the device.
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Software Implementation
/*******************************************************************************
*
* Module: void IRQ_ISR()
*
* Description: This is the interrupt service routine of the IRQ connected to INTB pin
of SBC.
*
The routine read the status of device when INTB signal of SBC is active.
*
It can indicate the CAN failure and VDDTEMP pre-warning of the device.
*
* Returns: None
*
* Global Data: pcGTWState is a variable shared with PC Master, it indicates the
*
status of GTW: GTW_CAN_KO
0x1 - CAN failure
*
GTW_TEMP_WARN 0x2 - Vdd temperature warning
*
GTW_OK
0xFF - no issues
*
* Arguments: None
*
* Range Issues: IRQ interrupt is enabled only when SBC MC33989 is used.
*
* Special Issues: None
*
*******************************************************************************/
void IRQ_ISR()
{
tU08 tmp;
tmp = spi0TxByte(INTR, READ, 0x3);
/* read interrupt source status,
do not mask CAN failure and VDDTEMP pre-warning */
if (tmp == 0x1)
/* set the state of the gateway to */
pcGTWState = GTW_CAN_KO;
/* CAN failure */
else if (tmp == 0x2)
pcGTWState = GTW_TEMP_WARN; /* Vdd temperature warning */
else
pcGTWState = GTW_OK;
/* no issues */
}
For more information about the device, see PC33989 System Basis Chip
with High Speed CAN transceiver, PC33989/D.
4.4.2 msCAN Module
For the msCAN module, the msCAN Driver Software was successfully
used to create both more readable initialization and application routines,
while rapidly reducing total cycle time.
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NOTE:
The msCAN Driver software may be ordered with the following part
number: “MSCANDRV12” .
msCAN12 Low Level Drivers - Supports Motorola M68HC(S)12
For msCAN support queries, please email: [email protected]
4.4.2.1 msCAN Driver Initialization Introduction
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The driver itself consists of several *.c and *.h files, and
msCANs12drv.o object file, with the main implementation of the driver.
For each key msCAN parameter of the periphery, there is a certain
symbolic constant located in one of its header files. For more
information, see msCAN Driver Software 1.0, User Manual, Metrowerks.
In msCAN0drv.h the following settings related to the msCAN
parameters can be found:
•
Number of Message Buffers for msCAN module 0
•
Clock prescaler for msCAN module 0
•
msCAN module 0 bit timing
•
Message Object Acceptance Filter size for msCAN module 0
•
Message Object Acceptance Code for msCAN module 0
•
Message Object Acceptance Filter Mask for msCAN module 0
In msCAN0ID.h the following settings related to the msCAN message
objects (MO) identifiers can be found:
•
Number of MO identifiers for msCAN module 0
•
Message type (STANDARD or EXTENDED) declaration for each
of MO identifiers
•
all MO identifiers definition
Because of the fact that the application needs to change some of
previously mentioned values during the program run, this small
modification to the msCAN Driver Software code needs to be done:
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•
in msCAN0ID.c file, the M_Identifier[NO_OF_ID_CAN0] variable
has to be placed in RAM to enable the program to change the
message object identifier during the program run; see codelisting
below:
Freescale Semiconductor, Inc...
//const UINT32 M_Identifier_CAN0[NO_OF_ID_CAN0] =
/* in order to change value, this variable has to be placed in RAM */
UINT32 M_Identifier_CAN0[NO_OF_ID_CAN0] =
{
#if (NO_OF_ID_CAN0 > 0)
MO0_IDR_CAN0
#endif
#if (NO_OF_ID_CAN0 > 1)
,MO1_IDR_CAN0
#endif
...
•
similar trick is used in msCANgvlite.c file, with CANBTR0_Def
variable, which has to be placed into RAM as well, to enable the
program to change the CAN baudrate during the program run; see
codelisting below:
// const UINT8 CANBTR0_Def
= CANBTR0_CAN0;
/* in order to change value, this variable has to be placed in RAM */
UINT8 CANBTR0_Def
= CANBTR0_CAN0;
/* note that the default CANBTR0_CAN0 value has to be rewritten before CAN
initialization routine call */
4.4.2.2 msCAN Driver Initialization
In the case that the FAST_CAN_ENABLE (PC33989 connected) and
OSC_16MHZ (running on 16 Mhz) symbolic constants are defined, the
CAN baudrate is defined in msCAN0drv.h according to the user’s
symbolic constant CAN_SPEED defined in CAN_master.h. Otherwise,
the CAN baudrate definition is fixed to value of 125 kbps.
/*****************************************************************************
Define clock prescaler for msCAN module 0: permitted values 1 to 64
msCAN module 0 clock = CLKSRC_CAN0 / PRESCALER_CAN0
CAN bitrate is equal to OSCILATOR / Prescaler / number of time quanta
number of time quanta is equal to 16 clocks/bit = 1 + 15 = 1 + tseg1 + tseg2
TSEG1 = 7 + 4
TSEG2 = 4
#Samp = 3
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SJW = 4
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*******************************************************************************/
/* when low speed CAN MC33388D is used, the baudrate is fixed to 125kbps for
any connected crystal (4 or 16 MHz) */
#ifndef FAST_CAN_ENABLE
#ifdef OSC_4MHZ
#define PRESCALER_CAN0 2
#endif
#ifdef OSC_16MHZ
#define PRESCALER_CAN0 8
#endif
/* 125kbps baudrate with 4MHz crystal */
/* 125kbps baudrate with 16MHz crystal */
#else
/* when SBC PC33989 is used instead of MC33388D and 16MHz crystal is connected,
CAN baudrate is set according to the user's symbolic constant CAN_SPEED */
#ifdef OSC_4MHZ
#define PRESCALER_CAN0 2
/* 125kbps baudrate with 4MHz crystal */
#endif
#ifdef OSC_16MHZ
#define PRESCALER_CAN0 CAN_SPEED
/* baudrate according to the user's symbolic
constant */
#endif
#endif
Message Object Acceptance Filter size for msCAN module 0 is set to be
16 bits long. However Message Object Acceptance Filter Masks of
msCAN module are all set to logical one, which means that all Message
Object Acceptance Code is ignored, and the device receives ALL of the
CAN messages on the network. This configuration can be used knowing
that there is no other traffic on the network.
The application messages are all based on CAN 2.0A 11-bit long
identifiers, therefore, all used Message objects identifiers are set as
STANDARD ones. However, default values of the Message objects
identifiers (defined in msCAN0ID.h) are ignored, because their values
change during the program run. This piece of code, taken from init()
routine, is responsible for the initial message object identifier
adjustments:
/* preset of values - local values which differs from PC Master ones */
node.nodeID = 0;
node.state = STATE_KO; /* set state of node to "data are not ready" */
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/* Set CAN identificators according to: - key message identificators
- desired node ID address */
/* Note this functionality is slightly modified from original msCAN Drv */
shiftedNodeID = pcNodeID << 3;
M_Identifier_CAN0[0] = ((tU32)(CAN_KEYID_MSG_A1 | pcNodeID) << 21);
M_Identifier_CAN0[1] = ((tU32)(CAN_KEYID_MSG_A2 | pcNodeID) << 21);
M_Identifier_CAN0[2] = ((tU32)(CAN_KEYID_MSG_B | pcNodeID) << 21);
M_Identifier_CAN0[3] = ((tU32)(CAN_KEYID_MSG_C | pcNodeID) << 21);
M_Identifier_CAN0[4] = ((tU32)(CAN_KEYID_MSG_D | shiftedNodeID) << 21);
M_Identifier_CAN0[5] = ((tU32)(CAN_KEYID_MSG_E | shiftedNodeID) << 21);
Freescale Semiconductor, Inc...
NOTE:
As a part of the message object identifier, the address of the device is
used in the application. For more information about this topic, see 4.4.5
Application chapter, specially Table 4-7. List of message types.
4.4.2.3 Initialization / Transmission / Reception Using msCAN Driver Software
For the initialization of the msCAN module the following routine of the
msCAN Driver Software is used:
/* CAN init & configuration */
tmp = CAN_Init(FAST, 0);
Next, it is necessary to configure employed message buffers (entities for
handling CAN messages) using CAN_ConfigMB() function, with one
message buffer (MB) for each message type (see Table 4-7). This
configuration consists of assigning the message type (message object
identifier) and a direction of communication (reception or transmission)
for each message buffer.
/* used CAN MO
Rx [letter
0 [A1] ...
1 [A2] ...
2 [B] ...
3 [C] ...
numbers plus letter names:
identifier used in notation]:
first analog status msg - Msg Group 1 with msg group ID = 1000
scnd analog status msg - Msg Group 1 with msg group ID = 1001
digital status msg - Msg Group 1 with msg group ID = 0100
dig input change-of-state msg - Group 1 with msg group ID = 0001
Tx [letter identifier used in notation]:
3 [D] ... configure digital output msg - Msg Group 2 with msg group ID =010
4 [E] ... analog configure msg - Msg Group 2 with msg group ID = 101 */
tmp = CAN_ConfigMB(0, RXDF, 0,
/* analog status msg, part
tmp = CAN_ConfigMB(1, RXDF, 1,
/* analog status msg, part
tmp = CAN_ConfigMB(2, RXDF, 2,
0); /* configure MB 0 to receive, ID = 0 */
1 */
0); /* configure MB 1 to receive, ID = 1 */
2 */
0); /* configure MB 2 to receive, ID = 2 */
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/* digital status msg */
tmp = CAN_ConfigMB(3, RXDF, 3,
/* digital input change of
tmp = CAN_ConfigMB(4, TXDF, 4,
/* configure (set) digital
tmp = CAN_ConfigMB(5, TXDF, 5,
/* configure analog inputs
0); /* configure MB 3 to receive, ID = 3 */
state msg */
0); /* configure MB 4 to transmit, ID = 4 */
outputs msg */
0); /* configure MB 5 to transmit, ID = 5 */
msg */
Freescale Semiconductor, Inc...
For the CAN transmission the following piece of code can be used. It
prepares a two bytes long message in sendData[] buffer and sends it
through message buffer number 4.
tU08 sendData[3];
/* pass data to CAN Tx routine */
sendData[0] = 2;
/* store desired data to sendData */
sendData[1] = node.digitOut.byte.lsb;
sendData[2] = node.digitOut.byte.msb;
tmp = CAN_LoadMB(4, sendData, 0);
/* load buf */
tmp = CAN_TransmitMB(4, 0);
/* send buf */
For the CAN reception the pooling technique is utilized in msCAN
Driver Software. Therefore user code has to periodically check the
status of each message buffer, by calling CAN_CheckStatusMB()
function. When data arrives it can be read using CAN_ReadDataMB()
function. The following demonstration piece of code checks the
message buffers 0 and 1; when status NEWDATA is detected on them,
the message buffer received a CAN message with a valid message
object identifier.
tU08 bufSts[2];
tU08 bufData[9];
/* buffer status of CAN reception */
/* buffer of received CAN message */
tmp = CAN_CheckStatusMB(0, bufSts, 0); /* MB 0 - analog status - part 1 */
if(bufSts[0] == NEWDATA)
/* new data in MB 0? */
{
tmp = CAN_ReadDataMB(0, bufData, 0);
for (i = 0; i < 4; i++)
{
/* write analog value + mode */
node.analog[i].byte.lsb = pcAnalog[i].byte.lsb = bufData[2 * i + 1];
node.analog[i].byte.msb = pcAnalog[i].byte.msb = bufData[2 * i + 2];
}
node.state = pcState = STATE_OK; /* state of node is "communicating" */
}
if(bufSts[1] == NEWDATA)
/* new data in MB 1? */
{
tmp = CAN_ReadDataMB(1, bufData, 0);
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for (i = 0; i < 4; i++)
{
/* write analog value + mode */
node.analog[i+4].byte.lsb = pcAnalog[i+4].byte.lsb = bufData[2*i+1];
node.analog[i+4].byte.msb = pcAnalog[i+4].byte.msb = bufData[2*i+2];
}
node.state = pcState = STATE_OK; /* state of node is "communicating" */
}
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4.4.3 SCI Module and PC Master software Initialization
SCI module is used for the PC Master software communication, thus it
has to be initialized. Initialization itself is a part of init() routine of the
CAN_master.c file. It enables both transmitter and receiver of the
module and sets the SCI baudrate. When running with 16 MHz crystal,
the SCI baudrate is set to 38.400 bps, while for 4 MHz crystal, preset
baudrate is equal to 9.600 bps.
/* SCI0 configuration */
#ifdef OSC_16MHZ
/* Module Clock with EVB = 16 / 2 MHz */
sci0.scibd.word = 0x1A;
/* baudrate is set to 19.200 */
/* 0x0034: BR = 9.600Bd, 0x001A: BR = 19.200Bd, 0x000D: BR = 38.400Bd */
#endif
#ifdef OSC_4MHZ
/* Module Clock on module = 4 / 2 MHz */
sci0.scibd.word = 0x0D;
/* baudrate is set to 9.600 */
/* 0x0034: BR = 2.400Bd, 0x001A: BR = 4.800Bd, 0x000D: BR = 9.600Bd */
#endif
sci0.scicr2.byte = TE | RE; /* set TE, RE */
tmp = sci0.scisr1.byte;
/* clear Status Register */
PC Master software initialization is done simply by calling pcmasterInit()
function, this function is a part of init() routine of the CAN_master.c.
4.4.4 RTI Module
In this chapter Real Time Interrupt (RTI) related routines are explained.
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4.4.4.1 RTI Initialization
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Real time interrupt event is set to interrupt the process 40.7 times per
second (when running on 16 MHz crystal), otherwise it is 15.25 times per
second. Complete initialization routine is given here:
void rtiInit(void)
{
#ifdef OSC_4MHZ
crg.rtictl = 0x73;
#endif
#ifdef OSC_16MHZ
crg.rtictl.byte = 0x75;
/* real time interrupt 15.25 times per second */
/* real time interrupt 40.7 times per second */
/* one tick is circa 25ms */
#endif
crg.crgint.bit.rtie = 1;
/* real time interrupt enable */
}
4.4.4.2 RTI In Application
RTI interrupt service request routine is called rtiISR(). It is assigned for
the “Black box” demo application timing, specifically for the generation of
delays of both analog variables in the “Black box” process.
Moreover, there is also the PC33989 System Basis Chip with High
Speed CAN transceiver watch dog service function calling when the
device is used in the design. For more information, see function header
below and 4.4.1.3 PC33989 Communication chapter.
/*******************************************************************************
*
* Module: void rti_ISR(void)
*
* Description: This routine is the interrupt service routine of the RTI module.
*
When SBC MC33989 is connected, it is used for watch-dog feeding.
*
When "black box" application is enabled, it is used for generation of
*
delay pulses for both analog variables.
*
When running with 4MHz crystal, it interrupt 15.25 times per second
*
When running with 16MHz crystal, it interrupt 40.7 times per second,
*
with one clock tick circa 25ms
*
* Returns: None
*
* Global Data:
*
FAST_CAN_ENABLE is a symbolic constant, if defined the SBC MC33989 (fast CAN
physical *
layer driver) is used, otherwise MC33388D is used as a slow CAN
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physical layer driver
*
BLACK_BOX is a symbolic constant, if defined the "black box" demo application
is enabled
*
status_1, status_2
*
inDelay_1, inDelay_2
*
delayCounter[0] and delayCounter[1]
*
pcDigitOut
*
* Arguments: None
*
*******************************************************************************/
4.4.5 Application
This chapter summarizes the PC_CAN Interface part of the “Black
demo” application for the reference design. Note that the complete
application is running on the PC_CAN Interface Reference Design, as
well as on the PC_CAN Interface device linked with the CAN network.
4.4.5.1 Application Introduction
The application itself is separated into the following tasks, with more
details given in the following chapters.
•
CAN reception and proper handling of all types of status
messages (message buffers 0, 1, 2 and 3).
•
Detection and proper handling of the "user's change to the Node
ID" event. Node ID of the device to be visualized and controlled via
PC Master software screen is one of the project variables, so when
a value (address) is changed, complete information about the new
device has to be read and configuration has to be written to the
new selected network device (PC_CAN Interface Reference
Design).
•
Detection and proper handling of the "user's change to the Analog
channel configuration" event. Analog configuration for each
analog channel is controlled by a couple of project variables
commanded via the PC Master software screen. When change of
state is detected on any of them, a new configuration has to be
written to the actual device (linked with message buffer number 5).
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•
Detection and proper handling of the "user's change to the Digital
output values" event. Digital output is 16 bit long variable; when
any change in this value is detected, a dedicated CAN message
with the actual digital output value is sent (linked with message
buffer number 4) to the actual network device.
•
Routine of the “Black box” demo application implementation.
•
Timing of the “Black box” demo application; it is based on the Real
Time interrupt (RTI) of the MCU.
•
Cyclic calling of the pcmasterRxTxPoll() PC Master software
function, since SCI communication with PC side is done in pooling
fashion.
For the change of state detection of monitored variables, the approach
described below is used. There are two different variables within the
project used for one entity (variable) of the PC_CAN Interface Reference
Design. As an example there are two variables declared for the Node ID
identification - pcNodeID and node.nodeID.
While the first variable is a PC Master software shared variable
(embedded instance of the PC Master software screen variable), the
second is the actual address of the currently connected node. Thus,
when a user’s change has occurred, the values of the described
variables are not identical, and this event is considered as the change of
state.
The same approach is utilized for the detection of a user’s change to
Digital output values and Analog channel configuration, for more
information about used variables, see 4.3.3 Project Variables.
4.4.5.2 Message Types Details
A straightforward structure of the messages, based on the CAN 2.0A
11-bit long identifiers, was created for all events listed in Table 4-1.
Every message type has a definition of its identifier as can be seen in
Table 4-7. Note that the definition of the Group numbers and identifiers
structure are chosen in correspondence with the DeviceNet
specification, release 2.0, Open DeviceNet Vendor Association.
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Table 4-7. List of message types
Message type
Message
buffer number
Complete CAN
identifier
Group
number (of
DeviceNet)
Message
identifier (of
DeviceNet)
Analog Inputs status - part 1
0
01000aaaaaa
1
1000
Analog Inputs status - part 2
1
01001aaaaaa
1
1001
Digital status
2
00100aaaaaa
1
0100
Digital Inputs status change of state
3
00001aaaaaa
1
0001
Digital Output configuration
4
10aaaaaa010
2
010
Analog Inputs configuration
5
10aaaaaa101
2
101
The sign “a” in CAN identifier (message object identifier) definition
stands for one bit of Node Address (NodeID) as mentioned in 4.4.2.2
msCAN Driver Initialization.
Table 4-8. Messages description
Message type
Message
buffer number
Length of the
message [in B]
Content
Analog Inputs status - part 1
0
8
see Figure 4-1
for analog inputs 0 to 3
Analog Inputs status - part 2
1
8
see Figure 4-1
for analog inputs 4 to 7
Digital status
2
2
first dig. inputs (Figure 4-2),
then dig. outputs (Figure 4-3)
Digital Inputs change of state
3
4
see Figure 4-2
Digital Output configuration
4
2
see Figure 4-3
Analog Inputs configuration
5
8
see Figure 4-4
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15
10
14
CSI
9
free
8
2 analog bits
7
0
1
node.Analog[8]
lower 8 bits of analog value
for each analog channel
used with
10 bit accuracy
Analog input
mode
0 - Current
1 - Voltage
Freescale Semiconductor, Inc...
Figure 4-1. Analog Configuration word composition
8
15
7
1
0
node.digitIn
Digital input bits
Figure 4-2. Digital Inputs word composition
8
15
7
1
0
node.digitOut
Digital output bits
Figure 4-3. Digital Outputs word composition
7
accuracy
ATD accuracy
0 - 8bit
1 - 10bit
free
1
0
G
G/2
node.AnalogConfig[8]
for each analog channel
voltage
range
Figure 4-4. Analog Configuration byte composition
4.4.5.3 Main Routine Details
Description of main() routine of the PC_CAN Interface reference design
can be found in this section, its codelisting is as follows.
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void main(void)
{
init();
/* Initialization of periphery modules & variables */
while(1)
{
pcmasterRxTxPoll();
rxCANProcess();
nodeIDProcess();
digitOutProcess();
analogConfigProcess();
#ifdef BLACK_BOX
blackBoxProcess();
#endif
}
NOTE:
/*
/*
/*
/*
/*
PC Master software pooling routine */
CAN reception */
Node ID testing condition */
Digital output testing condition */
Analog configuration testing condition */
/* Black Box Application */
Note that there is also an RTI interrupt service routine involved within this
project main loop.
4.4.5.4 CAN Reception Routine of the Application
The CAN reception handling is carried out in rxCANProcess() routine; its
flowchart is given in Figure 4-5. There are four types of the CAN
messages being received by the PC_CAN Interface device in the “Black
box” application:
•
two analog channel status messages linked with message buffer
0 (for analog channel inputs 0 to 3) and message buffer 1 (for
analog channel inputs 4 to 7)
•
digital status messages linked with message buffer 2
•
and digital inputs change of state messages linked with MB 3
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rxCANProcess() START
CHECK STATUS OF MSG
BUFFER 0
(ANALOG STATUS - part 1)
NEW DATA
IN MB3?
Y
NEW DATA
IN MB0?
UPDATE VALUES IN
Y
node.digitIn and pcDigitIn
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UPDATE VALUES IN
node.analog and pcAnalog
SET “STATE OK” INTO
MODULE STATUS
SET “STATE OK” INTO
MODULE STATUS
CHECK STATUS OF MSG
BUFFER 2
(DIGITAL STATUS)
CHECK STATUS OF MSG
BUFFER 1
(ANALOG STATUS - part 2)
NEW DATA
IN MB2?
Y
NEW DATA
IN MB1?
UPDATE VALUES
Y
IN node.digitIn
UPDATE VALUES IN
node.analog and pcAnalog
USER CHANGED
NODE ADDRESS?
Y
SET “STATE OK” INTO
MODULE STATUS
LOAD ACTUAL DIGITAL
OUTPUT VALUES OF NODE
CHECK STATUS OF MSG
BUFFER 3
(CHANGE OF D. INPUTS)
SET “STATE OK” INTO
MODULE STATUS
END
Figure 4-5. rxCANProcess() function flowchart
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4.4.5.5 Node ID Change Detection Routine
Flowchart of the nodeIDProcess() routine is given in Figure 4-6. This
function checks for a user’s change to the value of pcNodeID (address
of the device which is visualized in the PC Master software
environment).
Freescale Semiconductor, Inc...
When a change is detected, new values are written to all utilized CAN
message object identifiers, since the address is a part of the identifier.
Then it is necessary to write default values to the PC Master software
shared variables (pcDigitIn, pcAnalog[], pcAnalogConf[]) and also to
node.analogConf[] variable. Note that 10 bit accuracy and analog range
0 to 10 V are default analog channels settings of the PC_CAN Interface
Reference Design.
And finally it is necessary to send a respective CAN message containing
analog configuration information (MB 5). Thus:
•
for the analog configuration related variables the CAN message
with new configuration is send to the actual PC_CAN Interface
Reference Design within the nodeIDProcess() routine
•
values of the analog inputs of the actually selected PC_CAN
Interface Reference Design are read (and thus available) as soon
as the CAN message object identifiers are updated and the first
analog status message is received
•
digital output values are read from the actually selected
PC_CAN Interface Reference Design and properly stored into
both node.digitOut and pcDigitOut variables of the PC_CAN
Interface (see Figure 4-5)
•
values of the digital inputs are read as soon as the CAN
message object identifiers are updated and the first digital status
message is received
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nodeIDProcess() START
USER’S CHANGE
OF NODE ID?
Y
BLACK BOX
APPLICATION?
Y
STOP BLACK BOX
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APPLICATION
UPDATE CAN MSG
OBJECT IDENTIFIERS
DEFAULT VALUES TO
pcDigitIn and pcAnalog[]
DEFAULT VALUES FOR
ANALOG CONFIG.
SEND ANALOG CONFIG
MESSAGE (MB5)
END
Figure 4-6. nodeIDProcess() function flowchart
4.4.5.6 Digital Output Transmission
The detection of a user’s change to digital output values of the currently
addressed PC_CAN Interface Reference Design is implemented in
digitOutProcess() routine. This routine compares the values stored in
pcDigitOut and node.digitOut variables. When user changes the digital
output value in the PC Master software screen (value stored in
pcDigitOut variable), a non-equivalency is detected and thus, digital
output configuration CAN message (linked with MB 4) is sent.
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4.4.5.7 Analog Configuration Handling Routine
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The analogConfigProcess() routine is dedicated to the detection of a
user’s change to analog channels configuration of the active PC_CAN
Interface Reference Design. Detection is based on the comparison of
analog channels configuration variables:
NOTE:
•
pcAnalogConf[8].range and node.analogConf[8].range variables
in case of analog channel voltage ranges
•
pcAnalogConf[0].accuracy and node.analogConf[0].accuracy
variables in case of analog channel accuracy
Please note that analog accuracy value cannot be set separately for
analog channels of the ATD module. Thus only
pcAnalogConf[0].accuracy value can be changed by the user, and the
remaining pcAnalogConf[1..7].accuracy values are a copy of
pcAnalogConf[0].
Flowchart of the function is shown in Figure 4-7.
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analogConfigProcess()
ANALOG CONFIG.
CHANGED?
Y
BLACK BOX
APPLICATION?
Y
STOP BLACK BOX
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APPLICATION
UPDATE NEW ANALOG
CONFIGURATION
PREPARE DATA FOR
MSG TRANSMISSION
MODIFY VALUE OF
pcAccuracyRange
SEND ANALOG CONFIG
MESSAGE (MB5)
END
Figure 4-7. analogConfigProcess() function flowchart
4.4.5.8 Black Box Demo Application
The “Black box” demo application is enabled when the BLACK_BOX
symbolic constant is defined in CAN_master.h file.
The aim of the Black Box module is to substitute a controlled device. It
creates two analog channels controlled by two control signals, four
buttons (digital inputs) and four LEDs as digital outputs. For more
information, see 1.5 Black Box chapter of “PC_CAN Interface
Reference Design - Design Reference Manual”.
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Signal connection of the Black Box is shown in Table 4-9.
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Table 4-9. Black Box module connection
Signal name
Type of signal
Purpose
A0
analog
analog process #1
A1
analog
analog process #2
DI0
digital input
“Stop” button of analog process #1
DI1
digital input
“Start” button of analog process #1
DI2
digital input
“Stop” button of analog process #2
DI3
digital input
“Start” button of analog process #2
DO0
digital output
control signal of analog process #1
DO1
digital output
control signal of analog process #2
DO2
digital output
analog process #1 is started LED indication
DO3
digital output
analog process #1 is stopped LED indication
DO4
digital output
analog process #2 is started LED indication
DO5
digital output
analog process #2 is stopped LED indication
In Figure 4-8 a graphical description of the Black box demo application
is given. For more information about used variables, see 4.3.3 chapter.
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pcDemoStatus.delay_x pcDemoStatus.delay_x
in “NO“ state
pcAnalogLimit_x
STOP button #x detected
in “YES” state
analog process #x
value
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time
pcDemoStatus.state_x
pcDemoStatus.state_x
in STARTED state
in STOPPED state
pcDelayTime_x
Symbol “x” is used to specify analog channel 1 and 2
Figure 4-8. Black box demo scheme
The Black box demo application is implemented in blackBoxProcess()
routine. This routine checks the state of connected buttons (Start and
Stop buttons for each analog channel) and controls the analog limits of
both analog channels.
Detection of the Start button of analog channel #1 is as follows; for the
analog channel #2 the implementation is analogous.
/* START button control for process #1 */
if ((node.digitIn.byte.lsb & 0x2) && !(node.digitIn.byte.lsb& 0x1) && (status_1 !=
STARTED))
/* if START1 button not STOP1 button and not started yet */
{
startProcess1();
/* LED and output ctrl */
digitOutProcess();
status_1 = STARTED;
/* set status */
inDelay_1 = NO;
}
Where startProcess1() function style macro is defined as:
#define startProcess1()
periphBitClear(0x8, &pcDigitOut.byte.lsb); \
periphBitSet(0x4, &pcDigitOut.byte.lsb);
\
periphBitSet(0x1, &pcDigitOut.byte.lsb)
/* switch on red LED, switch off green LED and finally switch on the output 1 */
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If Start1 button is pressed and process #1 is not started yet, function
style macro startProcess1() starts the process and updates the LEDs.
Then digitOutProcess() function (see 4.4.5.6) sends the digital output
configuration message to the active PC_CAN Interface Reference
Design, and finally, the flags are set properly.
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For the Stop buttons detection, the technique is similar.
/* STOP button control for process #1 */
if ((node.digitIn.byte.lsb & 0x1)&& !(node.digitIn.byte.lsb & 0x2)&& (status_1 !=
STOPPED))
/* if STOP1 button not START1 button and not stopped yet */
{
stopProcess1();
/* LED and output ctrl */
digitOutProcess();
status_1 = STOPPED;
/* set status */
inDelay_1 = NO;
}
Where stopProcess1() function style macro is defined as:
#define stopProcess1()
periphBitSet(0x8, &pcDigitOut.byte.lsb);
\
periphBitClear(0x4, &pcDigitOut.byte.lsb); \
periphBitClear(0x1, &pcDigitOut.byte.lsb)
/* switch off red LED, switch on green LED and finally switch off the output 1 */
The routine also controls the analog limits of both analog channels, as
they are stored in pcAnalogLimit_1 and pcAnalogLimit_2. The following
piece of code is assigned to perform the control of the analog channel 1
limit.
/* Analog value control - analog process #1 */
if ((inDelay_1 == NO) && (status_1 == STARTED))
/* if not in delay period after de-charging AND if started */
{
if (node.analog[0].struc.value <= pcAnalogLimit_1) /* compare value */
{
periphBitClear(0x1, &pcDigitOut.byte.lsb); /* switch off output */
digitOutProcess();
delayCounter[0] = pcDelayTime_1;
inDelay_1 = YES;
/* set desired delay */
/* set on delay */
}
}
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Condition is tested only when the process is started, and is not in the
delay state. Actual value of analog channel (stored in node.analog[0]
variable) is compared with the limit. When the value reaches the limit,
process control output is switched off, and digital output configuration
message is sent to the active PC_CAN Interface Reference Design.
Finally, the delay counter called delayCounter[0] is filled to the user’s
defined value, stored in pcDelayTime_1, and “process is in delay stage”
flag is set.
Delay timing generation of the Black box application is based on the Real
Time Interrupt module and is described in next chapter.
4.4.5.9 Timing of the Black Box Application
The RTI module interrupt service routine is called rtiISR(). It interrupts
the program execution 40.7 times per second in the case of a 16 MHz
crystal being connected.
The first function of this routine is the watch dog service routine of the
connected PC33989 System Basis Chip with High Speed CAN
transceiver device. For more information, see 4.4.1.3 PC33989
Communication.
The second function is the delay time generation for the demo
application; implementation for the analog process #1 can be seen
below:
#ifdef BLACK_BOX
/* Demo process #1 */
if (status_1 == STARTED)
{
if (delayCounter[0] == 0)
/* if counter is over => */
{
inDelay_1 = NO;
/* set process to NO delayed period */
periphBitSet(0x1, &pcDigitOut.byte.lsb); /* switch on output */
digitOutProcess();
}
if (inDelay_1 == YES) delayCounter[0]--; /* decrement counter */
}
Designer Reference Manual
70
DRM034 — Rev 0
Software Module Descriptions
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Software Module Descriptions
Software Implementation
Freescale Semiconductor, Inc...
The condition is tested only when "Black box" application is enabled, and
when the respective process is started. In the case that process is in the
state of delay generation (see Figure 4-8. Black box demo scheme),
the routine decrements the value of delayCounter[0] variable. And
finally, when counter value equal to 0 is detected, the delay time period
is over and the process shoulb start again. So, the delay flag is cleared,
the process is started, and the proper message is sent to the active
PC_CAN Interface Reference Design. In Figure 4-9, the rtiISR()
flowchart can be seen in the condition where the FAST_CAN_ENABLE
and BLACK_BOX symbolic constants are defined.
DRM034 — Rev 0
MOTOROLA
Designer Reference Manual
Software Module Descriptions
For More Information On This Product,
Go to: www.freescale.com
71
Freescale Semiconductor, Inc.
Software Module Descriptions
rtiISR() INTR SERVICE
CLEAR FLAG
INCREMENT counter
WATCH DOG
SERVICE?
Y
SEND WATCHDOG SERV.
Freescale Semiconductor, Inc...
ANALOG PROCESS #1
PROCESS #1
STARTED?
Y
DELAY COUNT
#1 IS OVER?
Y
SET PROCESS #1 FLAG
inDelay_1 TO NOT IN
DELAY PERIOD
START PROCESS #1
CALL digitOutProcess()
TO SEND DIG. OUTPUTS
CONGIG MESSAGE
FLAG inDelay_1
= YES?
Y
DECREMENT DELAY
COUNTER #1 CALLED
delayCounter[0]
ANALOG PROCESS #2
ANALOG PROCESS #2
EQUAL TO THE
PREVIOUS ONE
END
Figure 4-9. rtiISR() function flowchart
Designer Reference Manual
72
DRM034 — Rev 0
Software Module Descriptions
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Designer Reference Manual — PC_CAN
Appendix A. Bill of Materials and Schematics
Freescale Semiconductor, Inc...
A.1 Contents
A.2
PC_CAN Interface Bill of Materials. . . . . . . . . . . . . . . . . . . . . . 74
A.3
PC_CAN Interface Schematics. . . . . . . . . . . . . . . . . . . . . . . . . 76
DRM034 — Rev 0
MOTOROLA
Designer Reference Manual
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
73
74
Designer Reference Manual
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
1
2
6
3
1
1
1
1
5
1
1
1
1
1
3
1
9
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
18
1
2
C3,C1
C2,C5,C6,C7,C8,C9,C13,
C15,C17,C19,C22,C26,C29,
C30,C31,C32,C33,C36
C4
C11,C10
C12,C16,C18,C20,C21,C25
C14,C27,C28
C23
C24
C35
D1
JP1,JP2,JP3,JP4,JP5
JP8
JP6
J1
J2
J3
L1,L2,L3
Q1
R1,R5,R6,R8,R11,R12,R14,
C0805
C0805
4.7nF
C0805
33pF
C0805
10nF
C0805
22uF/6.3V
AL-elyt
33nF
C0805
3.3 nF
C0805
47uF/6.3V
AL-elyt
MBRS130LT3
SW/Jumper/2
SW/Jumper/3
Jumper
CON/CANNON9/90GM Elektronic
CON/5MOLEX
HEADER 3X2
10uH
Inductor Axial
BC807-40LT1
10K
R0805
47nF
100nF
Item
Quantity Reference
Part
______________________________________________
Bill Of MatePage1
MCSL Roznov
1. maje 1009
756 61 Roznov p.R., Czech Republic, Europe
PC_CAN I/O_1 Revised: Wednesday, June 19, 2002
Revision: 0.1
Farnell - 911-975
GM - 801E099
Farnell-889-714
Fischer elektronik-SL
Farnell - 108-267
Farnell-894-850
Farnell-317-603
Farnell-499-225
Farnell-556-117
Farnell-894-886
Farnell-894-849
Farnell-556-129
OnSemiconductor
Farnell-894-898
Farnell-499-687
Table A-1. PC_CAN Interface Bill of materials
A.2 PC_CAN Interface Bill of Materials
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Bill of Materials and Schematics
DRM034 — Rev 0
MOTOROLA
19
20
21
22
23
24
25
26
27
28
29
2
5
1
1
1
1
1
1
1
1
1
R15,R122
R2,R4
R3,R7,R9,R10,R13
R16
R109
U1
U2
U3
U4
U5
Y1
Box
510R
R0805
33K
R0805
2.7K
R0805
3.3k
R0805
MC33388D
MC33989
MC9S12DP256
MAX202ECSE
MC7812
CRYSTAL-16.0MHz
Freescale Semiconductor, Inc...
MOTOROLA
Farnell - 639-588
Farnell - .465-896
Farnell - 771-302
Farnell - 912-037
Farnell - 911-902
Farnell - 911-914
Motorola
Motorola
Motorola
Maxim
Freescale Semiconductor, Inc.
Bill of Materials and Schematics
PC_CAN Interface Bill of Materials
DRM034 — Rev 0
Designer Reference Manual
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
75
Designer Reference Manual
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
Microcontroller
MICRO
INT
RESET
RxCAN0
TxCAN0
SS_CAN
MOSI
MISO
SCLK
RxD0
TxD0
VDD
VDD
DGND
VDD
SI
SO
SCLK
RS232
INT
RESET
RxCAN
TxCAN
STB
MOSI
MISO
SCLK
VDD
CAN
TXD
RXD
RS232_RS485
RX
TX
DGND
RX
TX
5
9
4
8
3
7
2
6
1
J1
CAN
CANL
CANH
Vbat
JP8
SW/Jumper/3
1
PC_CAN Interface_1
D1
MBRS130LT3
1
2
3
2
VOUT VIN
GND
U5 MC7812
RS232
CON/5MOLEX
5
4
3
2
1
J2
MCSL Roznov
1. maje 1009
756 61 Roznov p.R., Czech Republic, Europe
C36
100nF
Modify Date: Wednesday, July 10, 2002
Sheet
Copyright Motorola 2001
POPI Status:
of
1
4
General Business
Author: Jaromir Chocholac
Size
Rev
Schematic Name: MODULE_BLOCKS
0.1
A
D:\CCWORK\R28107_PLM_VIEW_LATEST\ICONN\IC104 - INDUSTRIAL CAN IO\HW\00147_01\00147_01.DSN
Design File Name:
Title
CANL
V-
CANH
V+
3
CON/CANNON9/90DEG/FEMALE
DGND
Figure A-1. MODULE BLOCKS
WAKEUP
/HRESET
RxCAN
TxCAN
SS_CAN
RX_232
TX_232
VDD
VDD
76
DGND
A.3 PC_CAN Interface Schematics
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Bill of Materials and Schematics
DRM034 — Rev 0
MOTOROLA
MOTOROLA
DGND
CANL
CANH
VDD
Vbat
Vbat
JP4
2
1
DGND
CANL
CANH
VDD
Vbat
10K R12
10K R6
JP1
2
1
R8
C6
100nF
10K
R4
510
R2
510
5 mA - ON
C7
100nF
C3
47nF
C1
47nF
C8
100nF
R13
R9
STB
MOSI
MISO
SCLK
4.7nF
C4
100nF
C2
L3
33K L2
L1
33K
CANL1
CANH1
R7
33K
15 - 25 uA - SLEEP
20 - 40 uA - STBY
300 uA - ON
DRM034 — Rev 0
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
MC33989
WDOGB
CSB
MOSI
MISO
SCLK
GND8
GND7
GND6
GND5
CANL
CANH
L3
L2
L1
U2
RX
TX
Vdd1
Reset
INTB
GND1
GND2
GND3
GND4
V2sns
V2ctrl
Vsup
HS1
L0
7
6
5
1
2
3
4
R3
R5
10k
33k
C5
100nF
PC_CAN Interface_1
33K
Q1
JP5
R122
10k
R11
10K
C35
47uF/6.3V
Vbat
SCLK
MOSI
MISO
RESET
SCLK
MOSI
MISO
TxCAN
RxCAN
INT
STB
MCSL Roznov
1. maje 1009
756 61 Roznov p.R., Czech Republic, Europe
+
JP3
1
2
VDD
Modify Date: Wednesday, June 19, 2002
Sheet
Copyright Motorola 2001
POPI Status:
of
1
4
General Business
Author: Jaromir Chocholac
Size
Rev
Schematic Name: CAN
0.1
A
Design File Name: D:\CCWORK\R28107_PLM_VIEW_LATEST\ICONN\IC104 - INDUSTRIAL CAN IO\HW\00147_01\00147_01.DSN
Title
C9
100nF
R10
STB
TxCAN
RxCAN
INT
JP2
1
1 RxCAN2
2
TxCAN
2
VDD
3
4
INT2
5
6
7
BC807-40LT1
8
3.3k R109
9
10
11
Vbat
12
13
L0
14
MC33388D
BAT WAKE
EN
Vdd
RTH
STB
CANH INH
CANL
TX
RTL
RX
GND NERR
Figure A-2. CAN
28
27
26
25
24
23
22
21
20
19
18
L3 17
L2 16
L1 15
14
10
8
11
12
9
13
U1
R1
10k
2
1
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Bill of Materials and Schematics
PC_CAN Interface Schematics
Designer Reference Manual
77
C32
100nF
C31
100nF
78
C1+
Vcc
V+
GND
C1T1OUT
C2+
R1In
C2R1OUT
VT1IN
T2OUT T2IN
R2IN R2OUT
U4
MAX202ECSE
C33
100nF
1
2
3
4
5
6
7
8
C29
100nF
16
15
14
13
12
11
10
9
Designer Reference Manual
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
PC_CAN Interface_1
TX
RX
DGND
TXD
RXD
VDD
MCSL Roznov
1. maje 1009
756 61 Roznov p.R., Czech Republic, Europe
Modify Date: Wednesday, June 19, 2002
Sheet
2001
Copyright Motorola
POPI Status:
1
4
of
General Business
Author: Jaromir Chocholac
Size
Rev
RS232
Schematic Name:
0.1
A
Design File Name: D:\CCWORK\R28107_PLM_VIEW_LATEST\ICONN\IC104 - INDUSTRIAL CAN IO\HW\00147_01\00147_01.DSN
Title
TX
RX
DGND
TXD
RXD
Figure A-3. RS232
C30
100nF
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Bill of Materials and Schematics
DRM034 — Rev 0
MOTOROLA
MOTOROLA
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
DRM034 — Rev 0
79
Designer Reference Manual
U3
JP6
SW/Jumper/3
1
2
3
Figure A-4. MICROCONTROLLER
36
37
38
39
53
54
55
56
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4//SDI/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PB7/AD7
PB6/AD6
PB5/AD5
PB4/AD4
PB3/AD3
PB2/AD2
PB1/AD1
PB0/AD0
31
30
29
28
27
26
25
24
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
IOC7/PT7
IOC6/PT6
IOC5/PT5
IOC4/PT4
IOC3/PT3
IOC2/PT2
IOC1/PT1
IOC0/PT0
18
17
16
15
12
11
10
9
PA7/AD15 64
SCK2/PW7/KWP7/PP7
SS2/PW6/KWP6/PP6 PA6/AD14/TMOD2 63
PA5/AD13 62
MOSI2/PW5/KWP5/PP5
MISO2/PW4/KWP4/PP4 PA4/AD12/TMOD1 61
PA3/AD11 60
SS1/PW3/KWP3/PP3
PA2/AD10 59
SCK1/PW2/KWP2/PP2
PA1/AD9 58
MOSI1/PW1/KWP1/PP1
PA0/AD8 57
MISO1/PW0/KWP0/PP0
109
110
111
112
1
2
3
4
Y1
CRYSTAL-16.0MHz
C13
C12
C11
33pF
C10
33pF
47 XTAL
83
10uH
L1
48
2
4
6
1
3
5
VDDA
PAD15/AN15
PAD14/AN14
PAD13/AN13
PAD12/AN12
PAD11/AN11
PAD10/AN10
PAD09/AN09
PAD08/AN08
TEST
81
79
77
75
73
71
69
67
96
95
94
93
92
91
90
89
SS_CAN
SCLK
MOSI
MISO
TXD0
RXD0
SS_CAN
SCLK
MOSI
MISO
TXD0
RXD0
Freescale Semiconductor, Inc...
INT
PE7/XCLKSn/NOACC PM0/RXB/RXCAN0 105
PE6/MODB/IPIPE1 PM1/TXB/TXCAN0 104
PM2/RXCAN1 103
PE5/MODA/IPIPE0
PM3/TXCAN1 102
PE4/ECLK
PM4/RXCAN2 101
PE3/LSTRBN/TAGLOn
PM5/TXCAN2 100
PE2/RWn
88
PE1/IRQn
PM6/RXCAN3
87
PE0/XIRQn
PM7/TXCAN3
EXTAL 46
EXTAL
R14
10K
VDDX
XTAL
VDDA
100nF
10nF
84 VRH
85 VRL
R15
10K
97
VREGEN
42 RESETn
RESET
82
80
78
76
74
72
70
68
+
C14
22uF/6.3V
SS_CAN
SCLK
MOSI
MISO
TxD0
RxD0
RxCAN0
TxCAN0
RxCAN0
TxCAN0
99
PJ6/KWJ6/SDA/RXCAN4
98
PJ7/KWJ7/SCL/TXCAN4
KWH0/PH0
KWH1/PH1
KWH2/PH2
KWH3/PH3
KWH4/PH4
KWH5/PH5
KWH6/PH6
KWH7/PH7
PK0/PIX0
PK1/PIX1
PK2/PIX2
PK3/PIX3
PK4/PIX4
PK5/PIX5
PK7/ECSn
52
51
50
49
35
34
33
32
8
7
6
5
20
19
108
22
KWJ0/PJ0
21
KWJ1/PJ1
VDD1
13
VDD1
65
VDD2
107
VDDX
41
VDDR
23 MODC/TAGHIn/BKGD
VDPLL 43
VDDPLL
J3
CON6A
XFC
44
VSS1
VSS2
VSSX
VSSR
VSSA
VSSPLL
VDD2
VDDX
VDDR
C21
10nF
14
66
106
40
86
45
VDDR
C18
10nF
VDDX
C19
100nF
C16
10nF
C17
100nF C20
10nF
C15
100nF
C22
100nF
DGND
MC9S12DP256
C24
3.3 nF
C23
33nF
XFC
VDD
L2
VDDR
10uH
+
100nF
10nF
C26
C25
R16
2.7K
C27
22uF/6.3V
L3
VDDX
10uH
C28
22uF/6.3V
+
Bill of Materials and Schematics
PC_CAN Interface Schematics
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Bill of Materials and Schematics
Designer Reference Manual
80
DRM034 — Rev 0
Bill of Materials and Schematics
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Designer Reference Manual — PC_CAN
Appendix B. Source Code Files
Freescale Semiconductor, Inc...
B.1 Contents
B.2
CAN_master.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
B.3
CAN_master.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.4
rti.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
B.5
rti.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
B.6
spi.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
B.7
spi.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
B.8
s12_regs.c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
B.9
s12_regs.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
B.10 MC9S12DP256_RAM.prm . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
B.11 MC9S12DP256_FLAT.prm. . . . . . . . . . . . . . . . . . . . . . . . . . .119
DRM034 — Rev 0
MOTOROLA
Designer Reference Manual
Source Code Files
For More Information On This Product,
Go to: www.freescale.com
81
Freescale Semiconductor, Inc.
Source Code Files
Freescale Semiconductor, Inc...
B.2 CAN_master.c
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: CAN_master.c
*
* Description: Code for the “CAN / SCI Gateway module” for the “CAN I/O
*
Industrial module” project
*
* Modules Included:
*
IRQ_ISR()
*
init()
*
rxCANProcess()
*
nodeIDProcess()
*
analogConfigProcess()
*
blackBoxProcess()
*
main()
*
*******************************************************************************/
#include “s12_regs.h”
/* register definition */
#include “CAN_master.h”
#include “spi.h”
#include “rti.h”
/* project main header file */
#include “msCANstd.h”
#include “msCANdrv.h”
/* msCAN module */
#include “pcmaster.h”
/* PC master header file */
Designer Reference Manual
82
DRM034 — Rev 0
Source Code Files
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Source Code Files
CAN_master.c
Freescale Semiconductor, Inc...
/******************************************************************************/
/*
P R O T O T Y P E S
*/
/******************************************************************************/
void IRQ_ISR();
void init(void);
void rxCANProcess(void);
void nodeIDProcess(void);
void analogConfigProcess(void);
void blackBoxProcess(void);
/******************************************************************************/
/*
G L O B A L
V A R I A B L E S
*/
/******************************************************************************/
volatile sNode node;
/* complete Node information from CAN network */
volatile tU08 IDChanged = 0;
volatile tU16 tmp;
/* status of ID: unchanged / changed */
/* temporary variable */
extern tU32 M_Identifier_CAN0[]; /* array of CAN identifiers of msCAN driver */
extern UINT8 CANBTR0_Def;
/* bitrate 0 CAN register value */
/* these two entities were originally constants of msCAN driver, but there were
changed to be variables placed in RAM memory */
/* variables dedicated for Black Box application */
volatile tU16 delayCounter[2]; /* counters for delay period after capacitor
uncharging */
/******************************************************************************/
/* G L O B A L
V A R I A B L E S
S H A R E D
F O R
P C
M a s t e r */
/******************************************************************************/
/* variables dedicated for sharing with PC via PC Master */
volatile tU08 pcState;
/* node status */
/* STATE_KO 0x0
state of node is “data are not ready” */
/* STATE_OK 0xFF state of node is “communicating” */
volatile tU08 pcGTWState;
/* gateway status */
/* GTW_CAN_KO
0x1
state of the gateway: CAN failure */
/* GTW_TEMP_WARN 0x2
state of the gateway: Vdd temperature warn */
/* GTW_OK
0xFF state of the gateway: no issues */
volatile tU08 pcNodeID;
/* node identification */
volatile uDigital pcDigitIn;
/* digital input values */
volatile uDigital pcDigitOut;
/* digital output values */
volatile uAnalog pcAnalog[8];
/* array of structure of analog values */
volatile sAnalogConf pcAnalogConf[8]; /* analog configuration structure */
/* variables dedicated for sharing with PC via PC Master for Black Box applic */
volatile sPcDemoStatus pcDemoStatus;
/* status of the demo */
volatile tU16 pcAnalogLimit_1;
/* analog limit value for process #1 */
volatile tU16 pcAnalogLimit_2;
/* analog limit value for process #2 */
/* Note that value equal to 1 makes delay 25ms long */
DRM034 — Rev 0
MOTOROLA
Designer Reference Manual
Source Code Files
For More Information On This Product,
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83
Freescale Semiconductor, Inc.
Source Code Files
Freescale Semiconductor, Inc...
volatile tU16 pcDelayTime_1;
volatile tU16 pcDelayTime_2;
volatile tU16 pcAccuracyRange;
/* VALUE_FOR_8BIT
/* VALUE_FOR_10BIT
/* delay time value for process #1 */
/* delay time value for process #2 */
/* value for PC Master linear transformation */
128
value for PC Master transformation */
512
according to desired ADC accuracy */
/*******************************************************************************
*
* Module: void IRQ_ISR()
*
* Description: This is the interrupt service routine of the IRQ connected to
*
INTB pin of SBC.
*
The routine read the status of device when INTB signal of SBC is active.
*
It can indicate the CAN failure and VDDTEMP pre-warning of the device.
*
* Returns: None
*
* Global Data: pcGTWState is a variable shared with PC Master, it indicates the
*
status of GTW: GTW_CAN_KO
0x1 - CAN failure
*
GTW_TEMP_WARN 0x2 - Vdd temperature warning
*
GTW_OK
0xFF - no issues
*
* Arguments: None
*
* Range Issues: IRQ interrupt is enabled only when SBC MC33989 is used.
*
* Special Issues: None
*
*******************************************************************************/
void IRQ_ISR()
{
tU08 tmp;
tmp = spi0TxByte(INTR, READ, 0x3);
/* read interrupt source status,
do not mask CAN failure and VDDTEMP pre-warning */
if (tmp == 0x1)
/* set the state of the gateway to */
pcGTWState = GTW_CAN_KO;
/* CAN failure */
else if (tmp == 0x2)
pcGTWState = GTW_TEMP_WARN; /* Vdd temperature warning */
else
pcGTWState = GTW_OK;
/* no issues */
}
/*******************************************************************************
*
* Module: void init(void)
*
* Description: This routine initializes all used periphery modules: PIM, SPI,
*
IRQ, RTI, SCI, msCAN plus routines for PC Master initialization.
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*
Note that msCAN driver is used for msCAN periphery module.
*
It also configures the CAN message objects (MO) for 6 used message
*
buffers + configure CAN identifiers for those 6 msg buffers.
*
And finally set default values for:
*
GTW related variable
*
node related variables
*
PC Master related variables
*
* Returns: None
*
* Global Data:
*
FAST_CAN_ENABLE is a symbolic constant, if defined the SBC MC33989 (fast
*
CAN physical layer driver) is used, otherwise MC33388D is used as
*
a slow CAN physical layer driver
*
OSC_16MHZ is a symbolic constant, when defined, 16MHz crystal is
*
connected to board
*
OSC_4MHZ is a symbolic constant, when defined 4MHz crystal is
*
connected to board
*
pcGTWState
*
pcNodeID
*
pcDigitIn
*
pcDigitOut
*
pcAnalog
*
pcState
*
node.nodeID
*
node.state
*
M_Identifier_CAN0[]
*
pcDelayTime_1
*
pcDelayTime_2
*
pcAnalogLimit_1
*
pcAnalogLimit_2
*
pcAccuracyRange
*
* Arguments: None
*
* Range Issues: None
*
if defined FAST_CAN_ENABLED (Power Oak connected)
*
Crystal on 4MHz - CAN baudrate is fixed at 125kbps
*
Crystal on 16MHz - CAN baudrate is variable (125, 250 and 500kbps)
*
if not defined FAST_CAN_ENABLED (MC33388D device connected)
*
Crystal on 4MHz - CAN baudrate is fixed at 125kbps
*
Crystal on 16MHz - CAN baudrate is fixed at 125kbps
*
* Special Issues: None
*
*******************************************************************************/
void init(void)
{
tU16 shiftedNodeID;
/* temp shifted variable for Msg Group 2 */
tU08 i;
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#ifdef FAST_CAN_ENABLE
/* PORT S configuration */
pim.pts.bit.pts7 = 1;
/* set bit - default value of CSB of MC33989 */
pim.ddrs.bit.ddrs7 = 1; /* set PE7 bit as output */
/* SPI0 configuration - being used for MC33989 communication */
spi0Init();
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/* IRQ setting */
reg.intcr.bit.irqe = 1;
/* falling edge active IRQ */
#else
/* PORT S configuration */
pim.pts.bit.pts7 = 1;
/* set bit - SS_CAN (STB) signal for MC33388 */
pim.ddrs.bit.ddrs7 = 1; /* set PE7 bit as output */
/* IRQ setting */
reg.intcr.bit.irqen = 0;
/* disable external IRQ */
#endif
/* RTI - real time interrupt module */
rtiInit();
/* SCI0 configuration */
#ifdef OSC_16MHZ
/* Module Clock with EVB = 16 / 2 MHz */
sci0.scibd.word = 0x1A;
/* baudrate is set to 19.200 */
/* 0x0034: BR = 9.600Bd, 0x001A: BR = 19.200Bd, 0x000D: BR = 38.400Bd */
#endif
#ifdef OSC_4MHZ
/* Module Clock on module = 4 / 2 MHz */
sci0.scibd.word = 0x0D;
/* baudrate is set to 9.600 */
/* 0x0034: BR = 2.400Bd, 0x001A: BR = 4.800Bd, 0x000D: BR = 9.600Bd */
#endif
sci0.scicr2.byte = TE | RE; /* set TE, RE */
tmp = sci0.scisr1.byte;
/* clear Status Register */
/* PC Master initialization */
tmp = pcmasterInit();
/* CAN init & configuration */
tmp = CAN_Init(FAST, 0);
/* used CAN
Rx [letter
0 [A1] ...
1 [A2] ...
2 [B] ...
3 [C] ...
MO numbers plus letter names:
identifier used in notation]:
first analog status msg - Msg Group 1 with msg group ID = 1000
scnd analog status msg - Msg Group 1 with msg group ID = 1001
digital status msg - Msg Group 1 with msg group ID = 0100
dig input change-of-state msg - Group 1 with msg group ID = 0001
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Tx [letter identifier used in notation]:
3 [D] ... configure digital output msg - Msg Group 2 with msg group ID =010
4 [E] ... analog configure msg - Msg Group 2 with msg group ID = 101 */
tmp = CAN_ConfigMB(0, RXDF, 0,
/* analog status msg, part
tmp = CAN_ConfigMB(1, RXDF, 1,
/* analog status msg, part
tmp = CAN_ConfigMB(2, RXDF, 2,
/* digital status msg */
tmp = CAN_ConfigMB(3, RXDF, 3,
/* digital input change of
tmp = CAN_ConfigMB(4, TXDF, 4,
/* configure (set) digital
tmp = CAN_ConfigMB(5, TXDF, 5,
/* configure analog inputs
archEnableInt();
0); /* configure MO 0 to receive, ID = 0 */
1 */
0); /* configure MO 1 to receive, ID = 1 */
2 */
0); /* configure MO 2 to receive, ID = 2 */
0); /* configure MO 3 to receive, ID = 3 */
state msg */
0); /* configure MO 4 to transmit, ID = 4 */
outputs msg */
0); /* configure MO 5 to transmit, ID = 5 */
msg */
/* enable interrupts */
/* CAN / SCI gateway preset of values */
pcGTWState = GTW_OK;
/* set state of the gateway: no issues */
/* preset of values - PC Master values */
pcNodeID = 10;
pcDigitIn.word = pcDigitOut.word = 0;
for (i = 0; i < 8; i++) pcAnalog[i].word = 0;
pcState = STATE_KO; /* set state of node to “data are not ready” */
/* preset of values - local values which differs from PC Master ones */
node.nodeID = 0;
node.state = STATE_KO; /* set state of node to “data are not ready” */
/* Set CAN identificators according to: - key message identificators
- desired node ID address */
/* Note this functionality is slightly modified from original msCAN Drv */
shiftedNodeID = pcNodeID << 3;
M_Identifier_CAN0[0] = ((tU32)(CAN_KEYID_MSG_A1 | pcNodeID) << 21);
M_Identifier_CAN0[1] = ((tU32)(CAN_KEYID_MSG_A2 | pcNodeID) << 21);
M_Identifier_CAN0[2] = ((tU32)(CAN_KEYID_MSG_B | pcNodeID) << 21);
M_Identifier_CAN0[3] = ((tU32)(CAN_KEYID_MSG_C | pcNodeID) << 21);
M_Identifier_CAN0[4] = ((tU32)(CAN_KEYID_MSG_D | shiftedNodeID) << 21);
M_Identifier_CAN0[5] = ((tU32)(CAN_KEYID_MSG_E | shiftedNodeID) << 21);
/* initial values for Black Box */
pcDelayTime_1 = pcDelayTime_2 = 4;
/* default delay time values */
pcAnalogLimit_1 = pcAnalogLimit_2 = 250;
/* default analog limit value */
/* Following values are default after start */
for (i = 0; i < 8; i++)
{
/* default accuracy of ADC is 10 bit */
pcAnalogConf[i].accuracy = node.analogConf[i].accuracy = 1;
/* default voltage range: 0-10V */
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pcAnalogConf[i].range = node.analogConf[i].range = 1;
}
pcAccuracyRange = VALUE_FOR_10BIT; /* 10bit accuracy set for PC Scope */
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}
/*******************************************************************************
*
* Module: void rxCANProcess(void)
*
* Description: This is the CAN reception routine, done in pooling style.
*
Message buffers 0 to 3 are configured as reception buffers.
*
*
buffer number [letter identifier used in notation]:
*
0 [A1] ... first analog status msg - Msg Group 1 with msg group ID = 1000
*
1 [A2] ... scnd analog status msg - Msg Group 1 with msg group ID = 1001
*
2 [B] ... digital status msg - Msg Group 1 with msg group ID = 0100
*
3 [C] ... dig input change-of-state msg - Group 1 with msg group ID = 0001
*
* Returns: None
*
* Global Data:
*
node.analog[8]
*
pcAnalog[8]
*
node.state
*
pcState
*
IDChanged
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
// #pragma INLINE
void rxCANProcess(void)
{
tU08 i;
tU08 bufSts[2];
/* buffer status of CAN reception */
tU08 bufData[9];
/* buffer of received CAN message */
tmp = CAN_CheckStatusMB(0, bufSts, 0); /* MB 0 - analog status - part 1 */
if(bufSts[0] == NEWDATA)
/* new data in MB 0? */
{
tmp = CAN_ReadDataMB(0, bufData, 0);
for (i = 0; i < 4; i++)
{
/* write analog value + mode */
node.analog[i].byte.lsb = pcAnalog[i].byte.lsb = bufData[2 * i + 1];
node.analog[i].byte.msb = pcAnalog[i].byte.msb = bufData[2 * i + 2];
}
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node.state = pcState = STATE_OK; /* state of node is “communicating” */
}
tmp = CAN_CheckStatusMB(1, bufSts, 0); /* MB 1 - analog status - part 2 */
if(bufSts[0] == NEWDATA)
/* new data in MB 1? */
{
tmp = CAN_ReadDataMB(1, bufData, 0);
for (i = 0; i < 4; i++)
{
/* write analog value + mode */
node.analog[i+4].byte.lsb = pcAnalog[i+4].byte.lsb = bufData[2*i+1];
node.analog[i+4].byte.msb = pcAnalog[i+4].byte.msb = bufData[2*i+2];
}
node.state = pcState = STATE_OK; /* state of node is “communicating” */
}
tmp = CAN_CheckStatusMB(2, bufSts, 0); /* MB 2 - digital status */
if(bufSts[0] == NEWDATA)
/* new data in MB 2? */
{
tmp = CAN_ReadDataMB(2, bufData, 0); /* load digital inputs & outputs*/
node.digitIn.byte.lsb = pcDigitIn.byte.lsb = bufData[1];
node.digitIn.byte.msb = pcDigitIn.byte.msb = bufData[2];
if (IDChanged == 1)
/* if node ID has changed */
{
IDChanged = 0; /* clear status */
node.digitOut.byte.lsb = pcDigitOut.byte.lsb = bufData[3];
node.digitOut.byte.msb = pcDigitOut.byte.msb = bufData[4];
}
node.state = pcState = STATE_OK; /* state of node is “communicating” */
}
tmp = CAN_CheckStatusMB(3, bufSts, 0); /* MB 3 - digital input
change of state */
if(bufSts[0] == NEWDATA)
/* new data in MB 3? */
{
tmp = CAN_ReadDataMB(3, bufData, 0);
/* load digital inputs values */
node.digitIn.byte.lsb = pcDigitIn.byte.lsb = bufData[1];
node.digitIn.byte.msb = pcDigitIn.byte.msb = bufData[2];
node.state = pcState = STATE_OK; /* state of node is “communicating” */
}
}
/*******************************************************************************
*
* Module: void nodeIDProcess(void)
*
* Description: In this routine a reaction to “user’s change of the node ID”
*
through the PC Master environment is done, in pooling style.
*
When “black box” demo application is enabled, it switch off the demo
*
process before switching to another ID.
*
Then set CAN identifiers according to the new node ID.
*
And finally preset the default values of variables + transmission of
*
the CAN analog configuration message.
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*
* Returns: None
*
* Global Data:
*
BLACK_BOX is a symbolic constant, if defined the “black box” demo
*
application is enabled
*
pcNodeID
*
node.nodeID
*
status_1
*
status_2
*
inDelay_1
*
inDelay_2
*
M_Identifier_CAN0[]
*
pcState
*
node.state
*
pcDigitIn
*
pcAnalog
*
pcAnalogConf[].accuracy
*
pcAnalogConf[].range
*
node.analogConf[].accuracy
*
node.analogConf[].range
*
pcAccuracyRange
*
IDChanged
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
// #pragma INLINE
void nodeIDProcess(void)
{
tU08 i;
tU16 shiftedNodeID;
/* temp shifted variable for Msg Group 2 */
tU08 sendData[9];
/* pass data to CAN Tx routine */
if (pcNodeID != node.nodeID) /* if desired node address has changed */
{
#ifdef BLACK_BOX
/* when switching between nodes, stop processes first on previous node */
stopProcess1();
/* LED and output ctrl */
stopProcess2();
/* LED and output ctrl */
status_1 = STOPPED;
/* set status */
status_2 = STOPPED;
/* set status */
inDelay_1 = NO;
inDelay_2 = NO;
digitOutProcess();
#endif
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node.nodeID = pcNodeID;
/* write new value */
shiftedNodeID = pcNodeID << 3;
/* Set CAN identificators according to: - key message identificators
- desired node ID address */
/* Note this functionality is slightly modified from original msCAN Drv */
M_Identifier_CAN0[0] = ((tU32)(CAN_KEYID_MSG_A1 | pcNodeID) << 21);
M_Identifier_CAN0[1] = ((tU32)(CAN_KEYID_MSG_A2 | pcNodeID) << 21);
M_Identifier_CAN0[2] = ((tU32)(CAN_KEYID_MSG_B | pcNodeID) << 21);
M_Identifier_CAN0[3] = ((tU32)(CAN_KEYID_MSG_C | pcNodeID) << 21);
M_Identifier_CAN0[4] = ((tU32)(CAN_KEYID_MSG_D |shiftedNodeID)<<21);
M_Identifier_CAN0[5] = ((tU32)(CAN_KEYID_MSG_E |shiftedNodeID)<<21);
pcState = node.state = STATE_KO;
/* set state of node to “data are not ready” */
/* Set initial values after ID change (default values has to be defined) */
/* Following default values will be updated according to the real values */
pcDigitIn.word = 0;
/* will be read afterward */
for (i = 0; i < 8; i++) pcAnalog[i].word = 0; /* will be read */
/* Following values are default after each Node ID change */
for (i = 0; i < 8; i++)
{
/* default accuracy of ADC is 10 bit */
pcAnalogConf[i].accuracy = node.analogConf[i].accuracy = 1;
/* default voltage range: 0-10V */
pcAnalogConf[i].range = node.analogConf[i].range = 1;
}
pcAccuracyRange = VALUE_FOR_10BIT; /* 10bit accuracy set for PC Scope */
IDChanged = 1;
/* node ID has changed, for dig. outputs reading */
/* Send CAN analog configuration message according to default values */
sendData[0] = 8;
/* store desired data to sendData */
for (i = 0; i < 8; i++)
{
sendData[i + 1] = (tU08) node.analogConf[i].range;/* store range*/
if (pcAnalogConf[0].accuracy == 1)
sendData[i + 1] |= 0x80;
/* store accuracy bit value */
}
tmp = CAN_LoadMB(5, sendData, 0);
/* load buf */
tmp = CAN_TransmitMB(5, 0);
/* send buf */
}
}
/*******************************************************************************
*
* Module: void analogConfigProcess(void)
*
* Description: In this routine a reaction to “user’s change of the analog
*
configuration” through the PC Master environment is done, in pooling
*
style. The ADC accuracy of ADC range of operation can be changed.
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*
When “black box” demo application is enabled, it switch off the demo
*
process before changing any parameters.
*
Then it load new parameters from PC Master shared variables and
*
finally it sends the CAN analog configuration message.
*
* Returns: None
*
* Global Data:
*
BLACK_BOX is a symbolic constant, if defined the “black box” demo
*
application is enabled
*
node.analogConf[].range
*
node.analogConf[].accuracy
*
pcAnalogConf[].range
*
pcAnalogConf[].accuracy
*
status_1
*
status_2
*
inDelay_1
*
inDelay_2
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
// #pragma INLINE
void analogConfigProcess(void)
{
tU08 sendData[9];
/* pass data to CAN Tx routine */
tU08 i;
if ((node.analogConf[0].range != pcAnalogConf[0].range) ||
(node.analogConf[1].range != pcAnalogConf[1].range) ||
(node.analogConf[2].range != pcAnalogConf[2].range) ||
(node.analogConf[3].range != pcAnalogConf[3].range) ||
(node.analogConf[4].range != pcAnalogConf[4].range) ||
(node.analogConf[5].range != pcAnalogConf[5].range) ||
(node.analogConf[6].range != pcAnalogConf[6].range) ||
(node.analogConf[7].range != pcAnalogConf[7].range) ||
(node.analogConf[0].accuracy != pcAnalogConf[0].accuracy))
/* note only pcAnalogConf[0].accuracy value can be changed by user */
/* pcAnalogConf[1..7].accuracy value is a copy of pcAnalogConf[0] one */
{
/* write new values */
/* when modifying either range or accuracy, stop both processes first */
#ifdef BLACK_BOX
stopProcess1();
/* LED and output ctrl */
stopProcess2();
/* LED and output ctrl */
status_1 = STOPPED;
/* set status */
status_2 = STOPPED;
/* set status */
inDelay_1 = NO;
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inDelay_2 = NO;
digitOutProcess();
#endif
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sendData[0] = 8;
for (i = 0; i < 8; i++)
{
/* store desired data to sendData */
/* new accuracy */
pcAnalogConf[i].accuracy = pcAnalogConf[0].accuracy;
node.analogConf[i].accuracy = pcAnalogConf[i].accuracy;
node.analogConf[i].range = pcAnalogConf[i].range; /* new range*/
sendData[i + 1] = (tU08) node.analogConf[i].range;/* store range*/
if (pcAnalogConf[0].accuracy == 1)
sendData[i + 1] |= 0x80;
/* store accuracy bit value */
}
if (pcAnalogConf[0].accuracy == 1)
pcAccuracyRange = VALUE_FOR_10BIT;
else
pcAccuracyRange = VALUE_FOR_8BIT;
/* 10 bit accuracy set */
tmp = CAN_LoadMB(5, sendData, 0);
tmp = CAN_TransmitMB(5, 0);
/* load buf */
/* send buf */
/* 8 bit accuracy set */
}
}
/*******************************************************************************
*
* Module: void digitOutProcess(void)
*
* Description: This routine sends the digital output message (message buffer
*
number 5) via CAN network.
*
* Returns: None
*
* Global Data:
*
pcDigitOut.word
*
node.digitOut
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
// #pragma INLINE
void digitOutProcess(void)
{
tU08 sendData[9];
/* pass data to CAN Tx routine */
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if (pcDigitOut.word != node.digitOut.word)/* if digit. output changed */
{
node.digitOut.word = pcDigitOut.word;
/* write new value */
sendData[0] = 2;
/* store desired data to sendData */
sendData[1] = node.digitOut.byte.lsb;
sendData[2] = node.digitOut.byte.msb;
tmp = CAN_LoadMB(4, sendData, 0);
/* load buf */
tmp = CAN_TransmitMB(4, 0);
/* send buf */
}
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}
/*******************************************************************************
*
* Module: void blackBoxProcess(void)
*
* Description: This routine is the “black box” demo application controller.
*
It consists of two independent analog controllers; “analog level” and
*
“desired delay” before capacitor charging can be set both independently.
*
*
* Returns: None
*
* Global Data:
*
node.digitIn
*
status_1
*
status_2
*
inDelay_1
*
inDelay_2
*
pcDigitOut
*
node.analog
*
pcAnalogLimit_1
*
pcAnalogLimit_2
*
delayCounter[0] and delayCounter[1]
*
pcDelayTime_1
*
pcDelayTime_2
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
// #pragma INLINE
void blackBoxProcess(void)
{
/* START / STOP buttons control for process #1 */
if ((node.digitIn.byte.lsb & 0x2) && !(node.digitIn.byte.lsb & 0x1) &&
(status_1 != STARTED))
/* if START1 button and not started yet */
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{
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startProcess1();
digitOutProcess();
status_1 = STARTED;
inDelay_1 = NO;
/* LED and output ctrl */
/* set status */
}
if ((node.digitIn.byte.lsb & 0x1) && !(node.digitIn.byte.lsb & 0x2) &&
(status_1 != STOPPED))
/* if STOP1 button and not stopped yet */
{
stopProcess1();
/* LED and output ctrl */
digitOutProcess();
status_1 = STOPPED;
/* set status */
inDelay_1 = NO;
}
/* START / STOP buttons control for process #2 */
if ((node.digitIn.byte.lsb & 0x8) && !(node.digitIn.byte.lsb & 0x4) &&
(status_2 != STARTED))
/* if START2 button and not started yet */
{
startProcess2();
/* LED and output ctrl */
digitOutProcess();
status_2 = STARTED;
/* set status */
inDelay_2 = NO;
}
if ((node.digitIn.byte.lsb & 0x4) && !(node.digitIn.byte.lsb & 0x8) &&
(status_2 != STOPPED))
/* if STOP2 button and not stopped yet */
{
stopProcess2();
/* LED and output ctrl */
digitOutProcess();
status_2 = STOPPED;
/* set status */
inDelay_2 = NO;
}
/* Analog value control - analog process #1 */
if ((inDelay_1 == NO) && (status_1 == STARTED))
/* if not in delay period after de-charging AND if started */
{
if (node.analog[0].struc.value <= pcAnalogLimit_1) /* compare value */
{
periphBitClear(0x1, &pcDigitOut.byte.lsb); /* switch off output */
digitOutProcess();
delayCounter[0] = pcDelayTime_1;
inDelay_1 = YES;
/* set desired delay */
/* set on delay */
}
}
/* Analog value control - analog process #2 */
if ((inDelay_2 == NO) && (status_2 == STARTED))
/* if not in delay period after de-charging AND if started */
{
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if (node.analog[1].struc.value <= pcAnalogLimit_2) /* compare value */
{
periphBitClear(0x2, &pcDigitOut.byte.lsb); /* switch off output */
digitOutProcess();
delayCounter[1] = pcDelayTime_2;
inDelay_2 = YES;
/* set desired delay */
/* set on delay */
}
}
Freescale Semiconductor, Inc...
}
/*******************************************************************************
*
* Module: void main(void)
*
* Description: This is the main routine of the “CAN / SCI Gateway” for the
*
“CAN I/O Industrial module” project.
*
First, it calls the init() funtion
*
Than it polls the following:
*
- PC Master Rx / Tx routine
*
- complete CAN reception routine
*
- node ID change routine
*
- Digital output change routine
*
- Analog configuration routine
*
- finally “Black Box” demo application implementation (if enabled)
*
* Returns: None
*
* Global Data:
*
BLACK_BOX is a symbolic constant, if defined the “black box” demo
*
application is enabled
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
void main(void)
{
init();
/* Initialization of periphery modules & variables */
while(1)
{
pcmasterRxTxPoll();
rxCANProcess();
nodeIDProcess();
digitOutProcess();
analogConfigProcess();
/*
/*
/*
/*
/*
PC Master routine */
CAN reception */
Node ID testing condition */
Digital output testing condition */
Analog configuration testing condition */
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CAN_master.h
#ifdef BLACK_BOX
blackBoxProcess();
#endif
}
}
/* Black Box Application */
Freescale Semiconductor, Inc...
B.3 CAN_master.h
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: CAN_master.h
*
* Description: Header file for the main file of the project CAN_master
*
* Modules Included: None
*
*******************************************************************************/
#ifndef _CAN_master_H_
#define _CAN_master_H_
#include “s12_common.h”
/******************************************************************************/
/*
P R O T O T Y P E S
*/
/******************************************************************************/
void digitOutProcess(void);
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/******************************************************************************/
/*
A P P L I C A T I O N
D E F I N E S
*/
/******************************************************************************/
/* public defines for user’s reconfiguration */
#define OSC_16MHZ
/* running on 16Mhz crystal */
//#define OSC_4MHZ
/* running on 4MHz crystal */
Freescale Semiconductor, Inc...
#define CAN_SPEED
BAUDRATE_500
/* this defines the CAN baudrate, valid values are 125, 250 and 500 kbps */
/* note that this settings is valid only when OSC_16MHZ is defined
and SBC MC33989 is connected (FAST_CAN_ENABLE has to be defined) */
#define BLACK_BOX
/* if defined, the Black Box demo application is ON */
#define FAST_CAN_ENABLE /* if defined, MC33989 SBC is used instead of MC33388D*/
/******************************************************************************/
/*
A P P L I C A T I O N
D E F I N E S
*/
/******************************************************************************/
/* private ones */
/* CAN baudrates valid only for 16MHz crystal */
#define BAUDRATE_125
8
/* value for 125kbps CAN baudrate */
#define BAUDRATE_250
4
/* value for 250kbps CAN baudrate */
#define BAUDRATE_500
2
/* value for 500kbps CAN baudrate */
/* state of the node */
#define STATE_KO
0
#define STATE_OK
0xFF
/* state of the CAN /
#define GTW_CAN_KO
#define GTW_TEMP_WARN
#define GTW_OK
/* state of node is “data are not ready” */
/* state of node is “communicating” */
SPI gateway */
0x1
/* state of the gateway: CAN failure */
0x2
/* state of the gateway: Vdd temperature warn */
0xFF
/* state of the gateway: no issues */
/* state of the “black box” demo */
#define STOPPED
0
/* state of demo is “stopped” */
#define STARTED
1
/* state of demo is “running” */
#define NO
#define YES
0
1
/* ADC accuracy */
#define VALUE_FOR_8BIT
#define VALUE_FOR_10BIT
/* demo is not in delay stage */
/* demo is in delay stage */
128
512
/* value for PC Master transformation */
/* according to desired ADC accuracy */
/******************************************************************************/
/*
S T R U C T U R E S
*/
/******************************************************************************/
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CAN_master.h
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typedef struct
{
tU16 value : 10;
tU16 dumb : 5;
tU16 mode : 1;
/* mode = 0 ...
/* mode = 1 ...
} sAnalog;
/* structure of pcAnalog variable word */
/* analog value of ADC */
/* reserved for future */
/* mode configuration of ADC module */
normal voltage measurement according to “range” value */
current loop measurement */
typedef struct
/* structure of pcAnalogConf byte variable */
{
tU08 range : 2;
/* range configuration of ADC module */
tU08 dumb : 5;
/* reserved for future */
tU08 accuracy : 1; /* ADC module accuracy */
/* accuracy = 0 ... 8 bit accuracy */
/* accuracy = 1 ... 10 bit accuracy */
} sAnalogConf;
typedef union
{
tU16
word;
struct
{
tU08
msb;
tU08
lsb;
} byte;
sAnalog
struc;
} uAnalog;
typedef union
{
tU16
word;
struct
{
tU08
msb;
tU08
lsb;
} byte;
} uDigital;
/* union for Analog variable word */
/* access whole word */
/* access byte at a time */
/* access as declared in sAnalog structure */
/* union for Digital variable word */
/* access whole word */
/* access byte at a time */
typedef struct
{
tU08 state;
/* state = STATE_KO (0)
/* state = STATE_OK (1)
tU08
nodeID;
uDigital
digitIn;
uDigital
digitOut;
uAnalog
analog[8];
sAnalogConf analogConf[8];
} sNode;
/* structure of the node information */
/* node status */
... node is not connected or not ready */
... node is connected */
/* node identification */
/* digital input values */
/* digital output values */
/* union of analog value */
/* analog configuration structure */
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typedef struct
{
tU08 state_1 : 1;
tU08 delay_1 : 1;
Freescale Semiconductor, Inc...
tU08 dumb
: 2;
tU08 state_2 : 1;
tU08 delay_2 : 1;
tU08 dumb2
: 2;
} sPcDemoStatus;
/* structure of pcDemoStatus byte variable */
/* status of first demo LED */
/* 0 - process is stopped
1 - process is started */
/* first demo LED is in delay (while running) */
/* 0 - not delayed, charging
1 - delayed after de-charging */
/* reserved for future */
/* status of second demo LED */
/* 0 - process is stopped
1 - process is started */
/* second demo LED is in delay (while running) */
/* 0 - not delayed, charging
1 - delayed after de-charging */
/* reserved for future */
/******************************************************************************/
/*
S H O R T
C U T S
*/
/******************************************************************************/
#define status_1
pcDemoStatus.state_1
#define status_2
pcDemoStatus.state_2
#define inDelay_1
pcDemoStatus.delay_1
#define inDelay_2
pcDemoStatus.delay_2
/******************************************************************************/
/*
M C 9 S 1 2 D P 2 5 6
D e p e n d e n t
S t u f f
*/
/******************************************************************************/
/* INTERRUPTS ENABLE / DISABLE function style macros */
#define archEnableInt()
{__asm CLI;}
#define archDisableInt()
{__asm SEI;}
/******************************************************************************/
/*
A P P L I C A T I O N
F U N C T I O N
S T Y L E
M A C R O S
*/
/******************************************************************************/
#define startProcess1()
periphBitClear(0x8, &pcDigitOut.byte.lsb); \
periphBitSet(0x4, &pcDigitOut.byte.lsb);
\
periphBitSet(0x1, &pcDigitOut.byte.lsb)
/* switch on green LED, switch off red LED and finally switch on the output 1 */
#define stopProcess1()
periphBitSet(0x8, &pcDigitOut.byte.lsb);
\
periphBitClear(0x4, &pcDigitOut.byte.lsb); \
periphBitClear(0x1, &pcDigitOut.byte.lsb)
/* switch off green LED, switch on red LED and finally switch off the output 1 */
#define startProcess2()
periphBitClear(0x20, &pcDigitOut.byte.lsb);
periphBitSet(0x10, &pcDigitOut.byte.lsb);
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\
\
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CAN_master.h
periphBitSet(0x2, &pcDigitOut.byte.lsb)
/* switch on green LED, switch off red LED and finally switch on the output 2 */
periphBitSet(0x20, &pcDigitOut.byte.lsb);
\
periphBitClear(0x10, &pcDigitOut.byte.lsb); \
periphBitClear(0x2, &pcDigitOut.byte.lsb)
/* switch off green LED, switch on red LED and finally switch off the output 2 */
Freescale Semiconductor, Inc...
#define stopProcess2()
/******************************************************************************/
/*
G E N E R I C
F U N C T I O N
S T Y L E
M A C R O S
*/
/******************************************************************************/
/* Bit operation function style macros */
#define periphBitSet(Mask, Addr)
*(Addr) |= Mask
#define periphBitClear(Mask, Addr)
*(Addr) &= ~(Mask)
/* void periphBitChange(UWord16 Mask, volatile UWord16 * Addr); */
#define periphBitChange(Mask, Addr)
*(Addr) ^= Mask
/* bool periphBitTest(UWord16 Mask, volatile UWord16 * Addr); */
#define periphBitTest(Mask, Addr)
( *(Addr) & (Mask) )
/******************************************************************************/
/*
A P P L I C A T I O N
C A N
D E F I N E S
*/
/******************************************************************************/
/* defines of the “key” CAN 11-bit long standard identifiers */
/* these key identifiers are then enhanced by the Node ID information */
/* note that this is a slight modification of msCAN driver functionality where
identifiers were originally stored in ROM area */
#define CAN_KEYID_MSG_A1
0x0200
#define CAN_KEYID_MSG_A2
0x0240
#define CAN_KEYID_MSG_B
0x0100
#define CAN_KEYID_MSG_C
0x0040
#define CAN_KEYID_MSG_D
0x0402
#define CAN_KEYID_MSG_E
0x0405
/******************************************************************************/
/*
m s C A N
D R I V E R
D E F I N E S
*/
/******************************************************************************/
/* these two defines are necessary for proper msCAN driver operations */
#define HICROSS
#define MSCAN12
#endif
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B.4 rti.c
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: rti.c
*
* Description: Routines of the RTI module of the MC9S12DP256.
*
* Modules Included:
*
rtiInit()
*
rti_ISR()
*
*******************************************************************************/
#include “s12_regs.h”
/* register definition */
#include “CAN_master.h”
#include “rti.h”
#include “spi.h”
/* project main header file */
#include “msCANstd.h”
#include “msCANdrv.h”
/* msCAN module */
/******************************************************************************/
/*
G L O B A L
V A R I A B L E S
*/
/******************************************************************************/
extern volatile sPcDemoStatus pcDemoStatus;
/* status of the demo */
extern volatile sNode node;
/* complete Node information from CAN network */
extern volatile uDigital pcDigitOut;
/* digital output values */
extern volatile tU16 delayCounter[2];
/* counters for delay period after uncharging */
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Source Code Files
rti.c
/*******************************************************************************
*
* Module: void rtiInit(void)
*
* Description: In this routine the initialization of RTI is done.
*
When running with 4MHz crystal, it interrupts 15.25 times per second
*
When running with 16MHz crystal, it interrupts 40.7 times per second,
*
with one clock tick circa 25ms
*
* Returns: None
*
* Global Data:
*
OSC_16MHZ is a symbolic constant, when defined, 16MHz crystal is
*
connected to board
*
OSC_4MHZ is a symbolic constant, when defined 4MHz crystal is
*
connected to board
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues:
*
*******************************************************************************/
void rtiInit(void)
{
#ifdef OSC_4MHZ
crg.rtictl = 0x73;
/* real time interrupt 15.25 times per second */
#endif
#ifdef OSC_16MHZ
//
crg.rtictl.byte = 0x7F;
/* real time interrupt 15.25 times per second */
//
crg.rtictl.byte = 0x7B;
/* real time interrupt 20.35 times per second */
crg.rtictl.byte = 0x75;
/* real time interrupt 40.7 times per second */
/* one tick is circa 25ms */
#endif
crg.crgint.bit.rtie = 1;
/* real time interrupt enable */
}
/*******************************************************************************
*
* Module: void rti_ISR(void)
*
* Description: This routine is the interrupt service routine of the RTI module.
*
When SBC MC33989 is connected, it is used for watch-dog feeding.
*
When “black box” application is enabled, it is used for generation of
*
delay pulses for both analog variables.
*
When running with 4MHz crystal, it interrupt 15.25 times per second
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*
When running with 16MHz crystal, it interrupt 40.7 times per second,
*
with one clock tick circa 25ms
*
* Returns: None
*
* Global Data:
*
FAST_CAN_ENABLE is a symbolic constant, if defined the SBC MC33989 (fast
*
CAN physical layer driver) is used, otherwise MC33388D is used as
*
a slow CAN physical layer driver
*
BLACK_BOX is a symbolic constant, if defined the “black box” demo
*
application is enabled
*
status_1
*
status_2
*
inDelay_1
*
inDelay_2
*
delayCounter[0] and delayCounter[1]
*
pcDigitOut
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues:
*
*******************************************************************************/
#pragma TRAP_PROC
void rti_ISR(void)
/* interrupt each 25 ms (with 16MHz crystal) */
{
static count = 0;
/* routine counter */
tU08 tmp;
crg.crgflg.bit.rtif = 1;
count++;
/* clear flag of real time interrupt */
#ifdef FAST_CAN_ENABLE
/* SBC watch dog serving */
if (count >= 4)
/* each 100ms */
{
tmp = spi0TxByte(TIM, WRITE, 0x3);
/* set watchdog to 400ms */
/* this command is necessary to serve the SBC watchdog */
count = 0;
}
#endif
#ifdef BLACK_BOX
/* Demo process #1 */
if (status_1 == STARTED)
{
if (delayCounter[0] == 0)
{
inDelay_1 = NO;
/* if counter is over => */
/* set process to NO delayed period */
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rti.h
periphBitSet(0x1, &pcDigitOut.byte.lsb); /* switch on output */
digitOutProcess();
}
if (inDelay_1 == YES) delayCounter[0]--;
/* decrement counter */
Freescale Semiconductor, Inc...
}
/* Demo process #2 */
if (status_2 == STARTED)
{
if (delayCounter[1] == 0)
/* if counter is over => */
{
inDelay_2 = NO;
/* set process to NO delayed period */
periphBitSet(0x2, &pcDigitOut.byte.lsb); /* switch on output */
digitOutProcess();
}
if (inDelay_2 == YES) delayCounter[1]--; /* decrement counter */
}
#endif
}
B.5 rti.h
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: s12_rti.h
*
* Description: Header file for the RTI module of the MC9S12DP256
*
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* Modules Included: None
*
*******************************************************************************/
#ifndef _rti_H_
#define _rti_H_
Freescale Semiconductor, Inc...
/******************************************************************************/
/*
P R O T O T Y P E S
*/
/******************************************************************************/
void rtiInit(void);
void rti_ISR(void);
/******************************************************************************/
/*
RTI Function style macros
*/
/******************************************************************************/
#endif
B.6 spi.c
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: spi.c
*
* Description: Routines of the SPI module of the MC9S12DP256.
*
SPI format of communication is used for the configuration with the
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spi.c
*
following devices:
*
SBC MC33989 - System Basis Chip with High speed CAN physical line driver
*
* Modules Included:
*
spi0Init()
*
tU08 spi0TxByte (tU08 byte, tU08 chipSelect)
*
*******************************************************************************/
#include “s12_regs.h”
/* register definition */
Freescale Semiconductor, Inc...
#include “CAN_master.h”
#include “spi.h”
/* project main header file */
/*******************************************************************************
*
* Module: void spi0Init(void)
*
* Description: The SPI channel is used for communication with MC33989 SBC.
*
This device is used when FAST_CAN_ENABLE symbolic constant is defined,
*
otherwise the MC33388D device is used instead of SBC.
*
This routine configures the SPI communication parameters.
*
And finally it configures the SBC device into normal mode of operation.
*
Note that there has to be delays at least 20ms long between any SBC
*
communication.
*
* Returns: None
*
* Global Data: None
*
* Arguments: None
*
* Range Issues: None
*
* Special Issues: GPIO initialization has to be done before.
*
Note that SBC device has the watch dog running, the watch dog feeding is
*
done in rti.c
*
*******************************************************************************/
void spi0Init(void)
{
tU08 tmp;
tU16 delay;
spi0.spicr1.bit.lsbf
= 0;
spi0.spicr1.bit.ssoe
= 0;
spi0.spicr1.bit.cpha
= 1;
/*
/*
/*
/*
/*
/*
lsb first enable bit */
msb bit is transferred first */
slave select output enable */
slave select output is not enabled */
SPI clock phase bit */
first SCLK edge issued at the beginning
of the 8-cycle transfer operation */
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spi0.spicr1.bit.cpol
= 0;
spi0.spicr1.bit.mstr
= 1;
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spi0.spicr1.bit.sptie = 0;
spi0.spicr1.bit.spe
= 1;
spi0.spicr1.bit.spie
= 0;
spi0.spicr2.bit.spc0
= 0;
spi0.spicr2.bit.spiswai = 0;
spi0.spicr2.bit.bidiroe = 0;
spi0.spicr2.bit.modfen
//
//
= 0;
/* clock polarity bit */
/* serial clock (SCK) active in high, SCK
idles low */
/* master/slave mode select bit */
/* Master mode selected */
/* transmit interrupt enable bit */
/* transmit interrupt disabled, SPI
communication done in pooling style */
/* spi enable bit */
/* enable SPI, SPI port pins are dedicated
to SPI module */
/* spi interrupt enable bit */
/* SPI interrupt disabled */
/* serial pin control 0 bit */
/* no bidirectional pin configuration of
the SPI */
/* SPI stop in wait mode bit */
/* SCLK operates normally in wait mode */
/* bi-directional mode output enable bit */
/* output buffer disable in bidirectional
mode */
/* mode fault enable bit */
/* disable the MODF error */
/* divider is set to 8, so SCLK is 1MHz for 8MHz Module Clk */
spi0.spibr.bit.spr = 2;
/* baud rate selection */
spi0.spibr.bit.sppr = 0;
/* baud rate pre-selection */
/* in order to run the SCLK on 4MHz while 16MHz crystal is connected
(thus 8 MHz Module CLK), SPI module clock divisor has to be 2 */
/* divider is set to 2, so SCLK is 4MHz for 8 MHzModule Clk */
spi0.spibr.bit.spr = 0;
/* baud rate selection */
spi0.spibr.bit.sspr = 0;
/* baud rate pre-selection */
#if 1
/* configuration of the MC33989 chip for the first time */
tmp = spi0TxByte(TIM, WRITE, 0x3);
/* set no window watchdog with
400ms timing */
/* this watchdog configuration command is necessary, it has to be
called during first 350ms after entering the “Normal request” mode */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(MCR, WRITE, 0x1);
/* set SBC mode to “Normal” */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(RCR, WRITE, 0x0);
/* set Reset mode to “first mode” */
/* SAFE bit = 0 */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(CAN, WRITE, 0x0);
/* set CAN mode to “normal”,
slew rate 0 */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(INTR, WRITE, 0x3);
/* do not mask CAN failure and
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spi.c
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for (delay = 0; delay < 10000; delay ++)
VDDTEMP pre-warning */
{ asm NOP; }
#else
/* “Normal debug” mode of operation, watchdog is disabled */
/* Watchdog time out do not push reset pin to low level */
/* configuration of the MC33989 chip for the first time */
tmp = spi0TxByte(TIM, WRITE, 0x3);
/* set no window watchdog with
400ms timing */
/* this watchdog configuration command is necessary, it has to be
called during first 350ms after entering the “Normal request” mode */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(MCR, WRITE, 0x0);
/* set SBC mode to “Debug” */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(MCR, WRITE, 0x5);
/* set SBC mode to “Normal debug” */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(RCR, WRITE, 0x2);
/* set Reset mode to “safe mode” */
/* SAFE bit = 1 */
/* note that in this mode watchdog time out do not control the reset */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(CAN, WRITE, 0x0);
/* set CAN mode to “normal”,
slew rate 0 */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
tmp = spi0TxByte(INTR, WRITE, 0x3);
/* do not mask CAN failure and
VDDTEMP pre-warning */
for (delay = 0; delay < 10000; delay ++) { asm NOP; }
#endif
}
/*******************************************************************************
*
* Module: tU08 spi0TxByte (tU08 address, tU08 readWrite, tU08 value)
*
* Description: This is the SPI communication function. It transmit one byte via
*
SPI (address | readWrite | value) and pass the received one as an
*
argument.
*
* Returns: outByte as the SPI received byte
*
* Global Data: None
*
* Arguments: composite of (address | readWrite | value) which is 1B long value
*
* Range Issues: None
*
* Special Issues: None
*
*******************************************************************************/
tU08 spi0TxByte (tU08 address, tU08 readWrite, tU08 value)
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{
tU08 outByte;
while (spi0.spisr.bit.sptef == 0);
clearCSB();
spi0Write(address | readWrite | value);
while (spi0.spisr.bit.spif == 0);
outByte = spi0Read();
while (spi0.spisr.bit.sptef == 0);
setCSB();
return (outByte);
/*
/*
/*
/*
/*
/*
/*
while Tx reg not empty
set “chip select” */
write value to be send
while Rx reg not empty
store status byte */
while Tx reg not empty
unset “chip select” */
*/
*/
*/
*/
Freescale Semiconductor, Inc...
}
B.7 spi.h
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: s12_spi.h
*
* Description: Header file for the SPI module of the MC9S12DP256
*
* Modules Included: None
*
*******************************************************************************/
#ifndef _spi_H_
#define _spi_H_
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s12_regs.c
/******************************************************************************/
/*
P R O T O T Y P E S
*/
/******************************************************************************/
void spi0Init(void);
tU08 spi0TxByte (tU08 address, tU08 readWrite, tU08 value);
Freescale Semiconductor, Inc...
/******************************************************************************/
/*
S P I
D E F I N E S
*/
/******************************************************************************/
/* chip select pin for SPI communication with MC33989 */
#define CSB
PTS7
/* MC33989 addresses used for SPI communication */
#define MCR
0x00
/* Mode control register */
#define RCR
0x20
/* Reset control register */
#define CAN
0x40
/* CAN control register */
#define IOR
0x60
/* I/O control register */
#define WUR
0x80
/* Wake-up input register */
#define TIM
0xA0
/* Timing register */
#define LPC
0xC0
/* Low power mode control register */
#define INTR
0xE0
/* Interrupt register */
/* MC33989 read / write command used for SPI communication */
#define READ
0x00
/* read operation with MC33989 */
#define WRITE
0x10
/* write operation with MC33989 */
/******************************************************************************/
/*
SPI Function style macros
*/
/******************************************************************************/
#define spi0Read()
spi0.spidr.byte
#define spi0Write(x)
{ spi0.spidr.byte = x; }
/* chip select signal control for MC33989 */
#define setCSB()
periphBitSet(CSB, &pim.pts.byte)
#define clearCSB()
periphBitClear(CSB, &pim.pts.byte)
#endif
B.8 s12_regs.c
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
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*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
*
* File Name: s12_regs.c
*
* Description: Periphery module allocation
*
* Modules Included: None
*
*******************************************************************************/
#include “s12_common.h”
#include “s12_atd.h”
#include “s12_bdlc.h”
#include “s12_crg.h”
#include “s12_eeprom.h”
#include “s12_flash.h”
#include “s12_iic.h”
#include “s12_mscan.h”
#include “s12_page.h”
#include “s12_pim.h”
#include “s12_pwm.h”
#include “s12_register.h”
#include “s12_sci.h”
#include “s12_spi.h”
#include “s12_template.h”
#include “s12_timer.h”
#pragma DATA_SEG SHORT REG_REG
tREGISTER reg;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT PAGE_REG
tPAGE page;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT CRG_REG
tCRG crg;
#pragma DATA_SEG DEFAULT
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s12_regs.c
#pragma DATA_SEG PIM_REG
tPIM pim;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT TIM_REG
tTIMER tim;
#pragma DATA_SEG DEFAULT
Freescale Semiconductor, Inc...
#pragma DATA_SEG SHORT ATD0_REG
tATD atd0;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT PWM_REG
tPWM pwm;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT SCI0Regs
tSCI sci0;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT SCI1Regs
tSCI sci1;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT SPI0Regs
tSPI spi0;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT SPI1Regs
tSPI spi1;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT SPI2Regs
tSPI spi2;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT IIC_REG
tIIC iic;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG SHORT BDLC_REG
tBDLC bdlc;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG FLSH_REG
tFLASH flash;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG EPRM_REG
tEEPROM eeprom;
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#pragma DATA_SEG DEFAULT
#pragma DATA_SEG ATD1_REG
tATD atd1;
#pragma DATA_SEG DEFAULT
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#pragma DATA_SEG CAN0_REG
tMSCAN can0;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG CAN1_REG
tMSCAN can1;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG CAN2_REG
tMSCAN can2;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG CAN3_REG
tMSCAN can3;
#pragma DATA_SEG DEFAULT
#pragma DATA_SEG CAN4_REG
tMSCAN can4;
#pragma DATA_SEG DEFAULT
B.9 s12_regs.h
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* THIS SOFTWARE IS PROVIDED BY MOTOROLA “AS IS” AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL MOTOROLA OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
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Source Code Files
s12_regs.h
********************************************************************************
*
* File Name: s12_regs.h
*
* Description: Periphery module allocation
*
* Modules Included: None
*
*******************************************************************************/
#include “s12_common.h”
#include “s12_atd.h”
#include “s12_bdlc.h”
#include “s12_crg.h”
#include “s12_eeprom.h”
#include “s12_flash.h”
#include “s12_iic.h”
#include “s12_mscan.h”
#include “s12_page.h”
#include “s12_pim.h”
#include “s12_pwm.h”
#include “s12_register.h”
#include “s12_sci.h”
#include “s12_spi.h”
#include “s12_template.h”
#include “s12_timer.h”
extern tREGISTER reg;
extern tPAGE page;
extern tCRG crg;
extern tPIM pim;
extern tTIMER tim;
extern tATD atd0;
extern tPWM pwm;
extern tSCI sci0;
extern tSCI sci1;
extern tSPI spi0;
extern tSPI spi1;
extern tSPI spi2;
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extern tIIC iic;
extern tBDLC bdlc;
extern tFLASH flash;
extern tEEPROM eeprom;
extern tATD atd1;
Freescale Semiconductor, Inc...
extern tMSCAN can0;
extern tMSCAN can1;
extern tMSCAN can2;
extern tMSCAN can3;
extern tMSCAN can4;
B.10 MC9S12DP256_RAM.prm
NAMES
msCANs12drv.o
END
SECTIONS
REG_RG0 =
PAGE_RG0=
CRG_RG0 =
TIM_RG0 =
ATD_RG0 =
PWM_RG0 =
SCI_RG0 =
SCI_RG1 =
SPI_RG0 =
IIC_RG0 =
BDL_RG0 =
SPI_RG1 =
SPI_RG2 =
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
0x0000
0x0030
0x0034
0x0040
0x0080
0x00A0
0x00C8
0x00D0
0x00D8
0x00E0
0x00E8
0x00F0
0x00F8
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
0x002F;
0x0033;
0x003F;
0x007F;
0x009F;
0x00C7;
0x00CF;
0x00D7;
0x00DF;
0x00E7;
0x00EF;
0x00F7;
0x00FF;
// from here on can not be short definitions
FSH_RG0 = NO_INIT 0x0100 TO 0x010F;
EE2_RG0 = NO_INIT 0x0110 TO 0x011B;
ATD_RG1 = NO_INIT 0x0120 TO 0x013F;
CAN_RG0 = NO_INIT 0x0140 TO 0x017F;
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Source Code Files
MC9S12DP256_RAM.prm
CAN_RG1
CAN_RG2
CAN_RG3
PIM_RG0
CAN_RG4
=
=
=
=
=
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
0x0180
0x01C0
0x0200
0x0240
0x0280
TO
TO
TO
TO
TO
0x01BF;
0x01FF;
0x023F;
0x026F;
0x02BF;
MY_RAM
= READ_WRITE 0x1010 TO 0x1FFF;
MY_PSEUDO_ROM = READ_ONLY 0x2000 TO 0x3FFF;
MSCAN0_START = NO_INIT
0x0140 TO 0x0140;
Freescale Semiconductor, Inc...
END
PLACEMENT
_PRESTART, STARTUP,
ROM_VAR, STRINGS,
NON_BANKED,DEFAULT_ROM,
COPY
INTO
DEFAULT_RAM
INTO
MY_PSEUDO_ROM;
MY_RAM;
CAN0_REG
CAN1_REG
CAN2_REG
CAN3_REG
CAN4_REG
FLSH_REG
EPRM_REG
BDLC_REG
IIC_REG
TIM_REG
PAGE_REG
SCI0Regs
SCI1Regs
SPI0Regs
SPI1Regs
SPI2Regs
PWM_REG
REG_REG
CRG_REG
ATD0_REG
ATD1_REG
PIM_REG
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
CAN_RG0;
CAN_RG1;
CAN_RG2;
CAN_RG3;
CAN_RG4;
FSH_RG0;
EE2_RG0;
BDL_RG0;
IIC_RG0;
TIM_RG0;
PAGE_RG0;
SCI_RG0;
SCI_RG1;
SPI_RG0;
SPI_RG1;
SPI_RG2;
PWM_RG0;
REG_RG0;
CRG_RG0;
ATD_RG0;
ATD_RG1;
PIM_RG0;
MSCAN0
INTO
MSCAN0_START;
END
STACKSIZE 0x100
VECTOR 0 _Startup
VECTOR ADDRESS 0xFFB0
VECTOR ADDRESS 0xFFB2
CAN0_TransmitISR
CAN0_ReceiveISR
/* CAN0 Tx */
/* CAN0 Rx */
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VECTOR ADDRESS 0xFFB6
VECTOR ADDRESS 0xFFF2
VECTOR ADDRESS 0xFFF0
Freescale Semiconductor, Inc...
/*
/*
Interrupt
0xFF8C:8D
0xFF8E:8F
0xFF90:91
0xFF92:93
0xFF94:95
0xFF96:97
0xFF98:99
0xFF9A:9B
0xFF9C:9D
0xFF9E:9F
0xFFA0:A1
0xFFA2:A3
0xFFA4:A5
0xFFA6:A7
0xFFA8:A9
0xFFAA:AB
0xFFAC:AD
0xFFAE:AF
0xFFB0:B1
0xFFB2:B3
0xFFB4:B5
0xFFB6:B7
0xFFB8:B9
0xFFBA:BB
0xFFBC:BD
0xFFBE:BF
0xFFC0:C1
0xFFC2:C3
0xFFC4:C5
0xFFC6:C7
0xFFC8:C9
0xFFCA:CB
0xFFCC:CD
0xFFCE:CF
0xFFD0:D1
0xFFD2:D3
0xFFD4:D5
0xFFD6:D7
0xFFD8:D9
0xFFDA:DB
0xFFDC:DD
0xFFDE:DF
0xFFE0:E1
0xFFE2:E3
0xFFE4:E5
CAN0_WakeupISR
/* CAN0 Wake-up */
IRQ_ISR
/* CAN0 Error */
rti_ISR
/* real time interrupt service routine */
Vector Table */
PWM Emergency Shutdown
Port P Interrupt
MSCAN 4 transmit
MSCAN 4 receive
MSCAN 4 errors
MSCAN 4 wake- up
MSCAN 3 transmit
MSCAN 3 receive
MSCAN 3 errors
MSCAN 3 wake- up
MSCAN 2 transmit
MSCAN 2 receive
MSCAN 2 errors
MSCAN 2 wake-up
MSCAN 1 transmit
MSCAN 1 receive
MSCAN 1 errors
MSCAN 1 wake-up
MSCAN 0 transmit
MSCAN 0 receive
MSCAN 0 errors
MSCAN 0 wake-up
FLASH
EEPROM
SPI2
SPI1
IIC Bus
DLC
SCME
CRG lock
Pulse Accumulator B Overflow
Modulus Down Counter underflow
Port H
Port J
ATD1
ATD0
SCI1
SCI0
SPI0
Pulse accumulator input edge
Pulse accumulator A overflow
Timer overflow
Timer channel 7
Timer channel 6
Timer channel 5
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MC9S12DP256_FLAT.prm
0xFFE6:E7
0xFFE8:E9
0xFFEA:EB
0xFFEC:ED
0xFFEE:EF
0xFFF2:F3
0xFFF4:F5
0xFFF6:F7
0xFFF8:F9
0xFFFA:FB
0xFFFC:FD
Timer channel 4
Timer channel 3
Timer channel 2
Timer channel 1
Timer channel 0
IRQ
XIRQ
SWI
Unimplemented instruction trap
COP failure reset
Clock Monitor fail reset
Freescale Semiconductor, Inc...
*/
B.11 MC9S12DP256_FLAT.prm
NAMES
msCANs12drv.o
END
SECTIONS
REG_RG0 =
PAGE_RG0=
CRG_RG0 =
TIM_RG0 =
ATD_RG0 =
PWM_RG0 =
SCI_RG0 =
SCI_RG1 =
SPI_RG0 =
IIC_RG0 =
BDL_RG0 =
SPI_RG1 =
SPI_RG2 =
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
NO_INIT
0x0000
0x0030
0x0034
0x0040
0x0080
0x00A0
0x00C8
0x00D0
0x00D8
0x00E0
0x00E8
0x00F0
0x00F8
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
TO
0x002F;
0x0033;
0x003F;
0x007F;
0x009F;
0x00C7;
0x00CF;
0x00D7;
0x00DF;
0x00E7;
0x00EF;
0x00F7;
0x00FF;
// from here on can not be short definitions
FSH_RG0 = NO_INIT 0x0100 TO 0x010F;
EE2_RG0 = NO_INIT 0x0110 TO 0x011B;
ATD_RG1 = NO_INIT 0x0120 TO 0x013F;
CAN_RG0 = NO_INIT 0x0140 TO 0x017F;
CAN_RG1 = NO_INIT 0x0180 TO 0x01BF;
CAN_RG2 = NO_INIT 0x01C0 TO 0x01FF;
CAN_RG3 = NO_INIT 0x0200 TO 0x023F;
PIM_RG0 = NO_INIT 0x0240 TO 0x026F;
CAN_RG4 = NO_INIT 0x0280 TO 0x02BF;
RAM = READ_WRITE 0x1010 TO 0x3FFF;
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/* unbanked FLASH ROM */
ROM_4000 = READ_ONLY 0x4000 TO 0x7FFF;
ROM_C000 = READ_ONLY 0xC000 TO 0xFEFF;
EEPROM = READ_WRITE 0x0400 TO 0x0FFF;
MSCAN0_START = NO_INIT
0x0140 TO 0x0140;
Freescale Semiconductor, Inc...
END
PLACEMENT
_PRESTART, STARTUP,
ROM_VAR, STRINGS,
NON_BANKED, DEFAULT_ROM,
COPY
INTO
DEFAULT_RAM
INTO
ROM_C000, ROM_4000;
RAM;
CAN0_REG
CAN1_REG
CAN2_REG
CAN3_REG
CAN4_REG
FLSH_REG
EPRM_REG
BDLC_REG
IIC_REG
TIM_REG
PAGE_REG
SCI0Regs
SCI1Regs
SPI0Regs
SPI1Regs
SPI2Regs
PWM_REG
REG_REG
CRG_REG
ATD0_REG
ATD1_REG
PIM_REG
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
INTO
CAN_RG0;
CAN_RG1;
CAN_RG2;
CAN_RG3;
CAN_RG4;
FSH_RG0;
EE2_RG0;
BDL_RG0;
IIC_RG0;
TIM_RG0;
PAGE_RG0;
SCI_RG0;
SCI_RG1;
SPI_RG0;
SPI_RG1;
SPI_RG2;
PWM_RG0;
REG_RG0;
CRG_RG0;
ATD_RG0;
ATD_RG1;
PIM_RG0;
MSCAN0
INTO
MSCAN0_START;
END
STACKSIZE 0x100
VECTOR
VECTOR
VECTOR
VECTOR
VECTOR
VECTOR
0 _Startup
ADDRESS 0xFFB0
ADDRESS 0xFFB2
ADDRESS 0xFFB6
ADDRESS 0xFFF2
ADDRESS 0xFFF0
CAN0_TransmitISR
/* CAN0 Tx */
CAN0_ReceiveISR
/* CAN0 Rx */
CAN0_WakeupISR
/* CAN0 Wake-up */
IRQ_ISR
/* CAN0 Error */
rti_ISR
/* real time interrupt service routine */
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Source Code Files
MC9S12DP256_FLAT.prm
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/*
/*
Interrupt
0xFF8C:8D
0xFF8E:8F
0xFF90:91
0xFF92:93
0xFF94:95
0xFF96:97
0xFF98:99
0xFF9A:9B
0xFF9C:9D
0xFF9E:9F
0xFFA0:A1
0xFFA2:A3
0xFFA4:A5
0xFFA6:A7
0xFFA8:A9
0xFFAA:AB
0xFFAC:AD
0xFFAE:AF
0xFFB0:B1
0xFFB2:B3
0xFFB4:B5
0xFFB6:B7
0xFFB8:B9
0xFFBA:BB
0xFFBC:BD
0xFFBE:BF
0xFFC0:C1
0xFFC2:C3
0xFFC4:C5
0xFFC6:C7
0xFFC8:C9
0xFFCA:CB
0xFFCC:CD
0xFFCE:CF
0xFFD0:D1
0xFFD2:D3
0xFFD4:D5
0xFFD6:D7
0xFFD8:D9
0xFFDA:DB
0xFFDC:DD
0xFFDE:DF
0xFFE0:E1
0xFFE2:E3
0xFFE4:E5
0xFFE6:E7
0xFFE8:E9
0xFFEA:EB
0xFFEC:ED
Vector Table */
PWM Emergency Shutdown
Port P Interrupt
MSCAN 4 transmit
MSCAN 4 receive
MSCAN 4 errors
MSCAN 4 wake- up
MSCAN 3 transmit
MSCAN 3 receive
MSCAN 3 errors
MSCAN 3 wake- up
MSCAN 2 transmit
MSCAN 2 receive
MSCAN 2 errors
MSCAN 2 wake-up
MSCAN 1 transmit
MSCAN 1 receive
MSCAN 1 errors
MSCAN 1 wake-up
MSCAN 0 transmit
MSCAN 0 receive
MSCAN 0 errors
MSCAN 0 wake-up
FLASH
EEPROM
SPI2
SPI1
IIC Bus
DLC
SCME
CRG lock
Pulse Accumulator B Overflow
Modulus Down Counter underflow
Port H
Port J
ATD1
ATD0
SCI1
SCI0
SPI0
Pulse accumulator input edge
Pulse accumulator A overflow
Timer overflow
Timer channel 7
Timer channel 6
Timer channel 5
Timer channel 4
Timer channel 3
Timer channel 2
Timer channel 1
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Source Code Files
0xFFEE:EF
0xFFF2:F3
0xFFF4:F5
0xFFF6:F7
0xFFF8:F9
0xFFFA:FB
0xFFFC:FD
Timer channel 0
IRQ
XIRQ
SWI
Unimplemented instruction trap
COP failure reset
Clock Monitor fail reset
Freescale Semiconductor, Inc...
*/
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Designer Reference Manual — PC_CAN
Appendix C. Glossary
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A — See “accumulators (A and B or D).”
accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers
in the CPU. The CPU uses the accumulators to hold operands and results of arithmetic
and logic operations.
acquisition mode — A mode of PLL operation with large loop bandwidth. Also see ’tracking
mode’.
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC12 CPU has 15 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
analogue-to-digital converter (ATD) — The ATD module is an 8-channel, multiplexed-input
successive-approximation analog-to-digital converter.
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
ATD — See “analogue-to-digital converter”.
B — See “accumulators (A and B or D).”
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
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Glossary
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
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234 (decimal) = 0010 0011 0100 (BCD)
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — The break module allows software to halt program execution at a
programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — See "CPU clock".
byte — A set of eight bits.
CAN — See "Motorola scalable CAN."
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CGM — See “clock generator module (CGM).”
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — The CGM module generates a base clock signal from which
the system clocks are derived. The CGM may include a crystal oscillator circuit and/or
phase-locked loop (PLL) circuit.
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Glossary
comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module that resets the MCU if
allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU that contains the interrupt mask
bit and five bits that indicate the results of the instruction just executed.
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control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
CPU — See “central processor unit (CPU).”
CPU12 — The CPU of the MC68HC12 Family.
CPU clock — Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL)
determine which clock drives SYSCLK for the main system, including the CPU and buses.
When EXTALi drives the SYSCLK, the CPU or bus clock frequency (fo) is equal to the
EXTALi frequency divided by 2.
CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing
a crystal oscillator source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in CPU clock cycles.
CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC12 are:
•
A (8-bit accumulator)
•
B (8-bit accumulator)
– D (16-bit accumulator formed by concatenation of
accumulators A and B)
•
IX (16-bit index register)
•
IY (16-bit index register)
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Glossary
•
SP (16-bit stack pointer)
•
PC (16-bit program counter)
• CCR (8-bit condition code register)
cycle time — The period of the operating frequency: tCYC = 1/fOP.
D — See “accumulators (A and B or D).”
Freescale Semiconductor, Inc...
decimal number system — Base 10 numbering system that uses the digits zero through nine.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
ECT — See “enhanced capture timer.”
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically erased and reprogrammed.
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
enhanced capture timer (ECT) — The HC12 Enhanced Capture Timer module has the features
of the HC12 Standard Timer module enhanced by additional features in order to enlarge
the field of applications.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
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Glossary
index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing
modes, the CPU uses the contents of IX or IY to determine the effective address of the
operand. IX and IY can also serve as a temporary data storage locations.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
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instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
inter-IC bus (I2C) — A two-wire, bidirectional serial bus that provides a simple, efficient method
of data exchange between devices.
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
M68HC12 — A Motorola family of 16-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
MCU — Microcontroller unit. See “microcontroller.”
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Glossary
memory location — Each M68HC12 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
Freescale Semiconductor, Inc...
MI-Bus — See "Motorola interconnect bus".
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
most significant bit (MSB) — The leftmost digit of a binary number.
Motorola interconnect bus (MI-Bus) — The Motorola Interconnect Bus (MI Bus) is a serial
communications protocol which supports distributed real-time control efficiently and with
a high degree of noise immunity.
Motorola scalable CAN (msCAN) — The Motorola scalable controller area network is a serial
communications protocol that efficiently supports distributed real-time control with a very
high level of data integrity.
msCAN — See "Motorola scalable CAN".
MSI — See "multiple serial interface".
multiple serial interface — A module consisting of multiple independent serial I/O sub-systems,
e.g. two SCI and one SPI.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
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operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
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overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A clock generator circuit in which a voltage controlled oscillator
produces an oscillation which is synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
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program counter (PC) — A 16-bit register in the CPU. The PC register holds the address of the
next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
Freescale Semiconductor, Inc...
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
reset — To force a device to a known condition.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
serial communications interface module (SCI) — A module that supports asynchronous
communication.
serial peripheral interface module (SPI) — A module that supports synchronous
communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
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Glossary
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
Freescale Semiconductor, Inc...
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — A mode of PLL operation with narrow loop bandwidth. Also see ‘acquisition
mode.’
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two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
Freescale Semiconductor, Inc...
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
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