ETC HD6473847X

Hitachi Single-Chip Microcomputer
H8/3887 Series
H8/3887
HD6473887, HD6433887
H8/3886
HD6433886
H8/3885
HD6433885
H8/3884
HD6433884
H8/3883
HD6433883
H3/3882
HD6433882
H8/3847 Series
H8/3847
HD6473847, HD6433847
H8/3846
HD6433846
H8/3845
HD6433845
H8/3844
HD6433844
H8/3843
HD6433843
H8/3842
HD6433842
Hardware Manual
ADE-602-151A
Rev. 2.0
4/8/99
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
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semiconductor products.
List of Items Revised or Added for This Version
Page
Item
General modification
Description
Addition of H8/3847 Series
2
Table 1-1 Features / CPU
Change in specification of operation speed
2
Table 1-1 Features / Clock pulse
generators
Modification
3
Table 1-1 Features / Memory supply
Addition
4
Table 1-1 Features / LCD drive power
supply
Addition
5 and 6
Table 1-1 Features / Product lineup
Addition
7
1.2 Internal Block Diagram
Addition of description and modification of
figure 1-1
8 and 9
Figure 1-2 and figure 1-3
Modification
10
Table 1-2 Pin Functions / Power source Modification
pins
14
Table 1-2 Pin Functions / LCD
controller/driver
Addition
15
2.1.1 Features
Change in high-speed operation
49 to 54
Figure 2-16 (1) to figure 2-16 (6) /
Memory Map
Modification
56
Figure 2-17 Data Size and Number of
States for Access to and from On-Chip
Peripheral Modules
Modification
89
Figure 4-2 Typical Connection to Crystal Modification
Oscillator
Table 4-1 Crystal Oscillator Parameters Modification
90
Figure 4-4 Typical Connection to
Ceramic Oscillator
Modification
93
Figure 4-9 Pin Connection when not
Using Subclock
Modification
96
Table 5-1 Operating Modes
Addition of subsleep mode/watch mode
descriptions
97
Figure 5-1 Mode Transition Diagram
Modification of mode transition condition (2)
98
Table 5-2 Internal State in Each
Operating Mode
Modification
100
Bits 6 to 4
Addition of Note
101
Bit 4
Modification of description
Page
Item
Description
104
5.2 Sleep Mode
Addition of description
106
5.3.3 Oscillator Settling Timer after
Standby Mode is Cleared
Modification of description
109
5.5 Subsleep Mode
Addition of description
111
5.7.1 Transition to Active (MediumSpeed) Mode
Addition of description
119
Table 6-2 Socket Adapter
Modification
131
Table 8-1 Port Functions
Modification of port 9 to port C
151
Table 8-10 Port 3 Pin States
Modification
167
Figure 8-9 Port 9 Pin Configuration
Modification
169
8.10.3 Pin Functions
Modification of description and table 8-27
170
8.10.4 Pin States
Modification of description and table 8-28
175
Figure 8-12 Port C Pin Configuration
Modification
1. Port data register C (PDRC)
Addition of description
198
Figure 9-3 Block Diagram of Timer F
Modification
202
Bits 6 to 4
Modification of table
203
Bits 2 to 0
Modification of table
227
Table 9-13 Timer G Operation Modes
Addition and modification of description in
note
239
Table 9-18 Watchdog Timer Operation
States
Modification
250
9.7.5 Application Notes
Addition and modification of descriptions and
table
260
Bit 7
Addition of description in note
265
10.2.6 Application Note
Addition of description
268
Figure 10-6 SCI3 Block Diagram
Modification
275
Bits 1 and 0
Addition of description in notes
284
Table 10-7 Relation between n and
Clock
Modification
284
Table 10-8 Maximum Bit Rate for Each
Frequency (Asynchronous Mode)
Addition of description in notes
286
Table 10-10 Relation between n and
Clock
Modification
287
Bit 6 and bit 5
Addition of description in notes
319, 322 10.3.5 Application Notes / 8 to 10
and 323
Addition of description
Page
Item
Description
331
12.1.1 Features
Change in input channels
332
Figure 12-1 Block Diagram of the A/D
Converter
Modification
333
Table 12-1 Pin Configuration
Addition
336
Bits 3 to 0
Addition of table
343
13.1.1 Features
Modification of display capacity and LCD
RAM capacity
344
Figure 13-1 Block Diagram of LCD
Controller/Driver
Modification
345
Table 13-1 Pin Configuration
Addition
346
13.2.1 LCD Port Control Register
(LPCR)
Modification
347
Bit 4 and Bits 3 to 0
Modification
354
13.3.1 Settings up to LCD Display / f
Addition of description
356
13.3.2 Relationship between LCD RAM Addition of description
and Display
359 to
362
Figure 13-9 to figure 13-12
Addition
364
13.3.4 Step-Up Constant-Voltage (5 V)
Power Supply
Addition of description
372
14.2 When Using the Internal Power
Supply Step-Down Circuit
Modification of description
375 to
377
15.2.1 Power Supply Voltage and
Operating Range / 1 to 3
Modification of figures
378 to
383
Table 15-2 DC Characteristics
Addition and modification
384 to
386
Table 15-3 Control Signal Timing
Modification
389
Table 15-6 A/D Converter
Characteristics
Modification
390 and
391
Table 15-7 and table 15-8
Modification
393
Figure 15-5 SCI1 Input/Output Timing
Modification
394
Figure 15-7 SCI3 Synchronous Mode
Input/Output Timing
Addition
395
Figure 15-8 Segment Expansion Signal Addition
Timing
Page
Item
Description
397
15.5 Resonator Equivalent Circuit
Addition
446
LPCR — LCD port control register H'C0
Modification
449
AMR — A/D mode register H'C6
Modification
498
Figure C-12 Port C Block Diagram
Modification
500
Table E.1 Product Code Lineup
Modification
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is
compatible with the H8/300 CPU.
The H8/3887 Series and H8/3847 Series have an on-chip architecture that includes such peripheral
functions as an LCD controller/driver, six types of timers, a 14-bit PWM, a three-channel serial
communication interface, and an A/D converter. This allows H8/3887 Series and H8/3847 Series
devices to be used as embedded microcomputers in systems requiring LCD display.
The H8/3887 Series incorporates an LCD drive power supply and step-up constant power supply
(5 V), enabling a fixed 5 V voltage to be obtained independently of VCC.
This manual describes the hardware of H8/3887 and H8/3847 Series. For details on H8/3887
Series and H8/3847 Series instruction set, refer to the H8/300L Series Programming Manual.
The H8/3887 Series incorporates an LCD drive powe supply and set-up constant power supply (5
V), enabling a fixed 5 V voltage to be obtained independently of VCC.
Contents
Section 1
1.1
1.2
1.3
Overview............................................................................................................ 1
Overview............................................................................................................................ 1
Internal Block Diagram...................................................................................................... 7
Pin Arrangement and Functions......................................................................................... 8
1.3.1 Pin Arrangement ................................................................................................... 8
1.3.2 Pin Functions ........................................................................................................ 10
Section 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
CPU .....................................................................................................................
Overview............................................................................................................................
2.1.1 Features .................................................................................................................
2.1.2 Address Space.......................................................................................................
2.1.3 Register Configuration..........................................................................................
Register Descriptions .........................................................................................................
2.2.1 General Registers..................................................................................................
2.2.2 Control Registers ..................................................................................................
2.2.3 Initial Register Values ..........................................................................................
Data Formats......................................................................................................................
2.3.1 Data Formats in General Registers .......................................................................
2.3.2 Memory Data Formats..........................................................................................
Addressing Modes..............................................................................................................
2.4.1 Addressing Modes ................................................................................................
2.4.2 Effective Address Calculation ..............................................................................
Instruction Set ....................................................................................................................
2.5.1 Data Transfer Instructions ....................................................................................
2.5.2 Arithmetic Operations ..........................................................................................
2.5.3 Logic Operations ..................................................................................................
2.5.4 Shift Operations ....................................................................................................
2.5.5 Bit Manipulations..................................................................................................
2.5.6 Branching Instructions..........................................................................................
2.5.7 System Control Instructions..................................................................................
2.5.8 Block Data Transfer Instruction............................................................................
Basic Operational Timing ..................................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM) .........................................................
2.6.2 Access to On-Chip Peripheral Modules................................................................
CPU States .........................................................................................................................
2.7.1 Overview...............................................................................................................
2.7.2 Program Execution State .....................................................................................
2.7.3 Program Halt State................................................................................................
2.7.4 Exception-Handling State .....................................................................................
15
15
15
16
16
17
17
17
18
19
20
21
22
22
24
28
30
32
33
33
35
39
41
42
44
44
45
47
47
48
48
48
i
2.8
2.9
Memory Map......................................................................................................................
Application Notes ..............................................................................................................
2.9.1 Notes on Data Access ...........................................................................................
2.9.2 Notes on Bit Manipulation....................................................................................
2.9.3 Notes on Use of the EEPMOV Instruction ...........................................................
Section 3
3.1
3.2
3.3
3.4
Exception Handling ........................................................................................
Overview............................................................................................................................
Reset...................................................................................................................................
3.2.1 Overview...............................................................................................................
3.2.2 Reset Sequence .....................................................................................................
3.2.3 Interrupt Immediately after Reset .........................................................................
Interrupts ............................................................................................................................
3.3.1 Overview...............................................................................................................
3.3.2 Interrupt Control Registers ...................................................................................
3.3.3 External Interrupts ................................................................................................
3.3.4 Internal Interrupts..................................................................................................
3.3.5 Interrupt Operations..............................................................................................
3.3.6 Interrupt Response Time.......................................................................................
Application Notes ..............................................................................................................
3.4.1 Notes on Stack Area Use ......................................................................................
3.4.2 Notes on Rewriting Port Mode Registers .............................................................
Section 4
4.1
4.2
4.3
4.4
4.5
Clock Pulse Generators .................................................................................
Overview............................................................................................................................
4.1.1 Block Diagram......................................................................................................
4.1.2 System Clock and Subclock..................................................................................
System Clock Generator ....................................................................................................
Subclock Generator............................................................................................................
Prescalers ...........................................................................................................................
Note on Oscillators ............................................................................................................
Section 5
5.1
5.2
5.3
ii
49
55
55
57
63
64
64
64
64
64
65
66
66
68
78
78
79
84
85
85
86
88
88
88
88
89
92
94
95
Power-Down Modes ...................................................................................... 96
Overview............................................................................................................................
5.1.1 System Control Registers......................................................................................
Sleep Mode ........................................................................................................................
5.2.1 Transition to Sleep Mode......................................................................................
5.2.2 Clearing Sleep Mode ............................................................................................
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode ..............................................
Standby Mode ....................................................................................................................
5.3.1 Transition to Standby Mode..................................................................................
5.3.2 Clearing Standby Mode ........................................................................................
5.3.3 Oscillator Settling Time after Standby Mode is Cleared......................................
96
99
104
104
104
105
106
106
106
106
5.4
5.5
5.6
5.7
5.8
5.9
5.3.4 Standby Mode Transition and Pin States..............................................................
Watch Mode .......................................................................................................................
5.4.1 Transition to Watch Mode ....................................................................................
5.4.2 Clearing Watch Mode ...........................................................................................
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................
Subsleep Mode ...................................................................................................................
5.5.1 Transition to Subsleep Mode ................................................................................
5.5.2 Clearing Subsleep Mode .......................................................................................
Subactive Mode..................................................................................................................
5.6.1 Transition to Subactive Mode...............................................................................
5.6.2 Clearing Subactive Mode......................................................................................
5.6.3 Operating Frequency in Subactive Mode .............................................................
Active (Medium-Speed) Mode ..........................................................................................
5.7.1 Transition to Active (Medium-Speed) Mode........................................................
5.7.2 Clearing Active (Medium-Speed) Mode ..............................................................
5.7.3 Operating Frequency in Active (Medium-Speed) Mode ......................................
Direct Transfer ...................................................................................................................
5.8.1 Overview of Direct Transfer.................................................................................
5.8.2 Direct Transition Times........................................................................................
Module Standby Mode.......................................................................................................
5.9.1 Setting Module Standby Mode .............................................................................
5.9.2 Clearing Module Standby Mode...........................................................................
Section 6
6.1
6.2
6.3
6.4
ROM....................................................................................................................
Overview............................................................................................................................
6.1.1 Block Diagram......................................................................................................
PROM Mode (H8/3887, H8/3847) ....................................................................................
6.2.1 Setting to PROM Mode .......................................................................................
6.2.2 Socket Adapter Pin Arrangement and Memory Map ...........................................
Programming (H8/3887, H8/3847)....................................................................................
6.3.1 Writing and Verifying...........................................................................................
6.3.2 Programming Precautions.....................................................................................
Reliability of Programmed Data ........................................................................................
107
108
108
108
108
109
109
109
110
110
110
110
111
111
111
111
112
112
113
116
116
116
118
118
118
119
119
119
122
122
127
128
Section 7
7.1
RAM.................................................................................................................... 129
Overview............................................................................................................................ 129
7.1.1 Block Diagram...................................................................................................... 129
Section 8
8.1
8.2
I/O Ports .............................................................................................................
Overview............................................................................................................................
Port 1..................................................................................................................................
8.2.1 Overview...............................................................................................................
8.2.2 Register Configuration and Description ...............................................................
130
130
132
132
132
iii
8.2.3 Pin Functions ........................................................................................................
8.2.4 Pin States ..............................................................................................................
8.2.5 MOS Input Pull-Up...............................................................................................
8.3 Port 2..................................................................................................................................
8.3.1 Overview...............................................................................................................
8.3.2 Register Configuration and Description ...............................................................
8.3.3 Pin Functions ........................................................................................................
8.3.4 Pin States ..............................................................................................................
8.4 Port 3..................................................................................................................................
8.4.1 Overview...............................................................................................................
8.4.2 Register Configuration and Description ...............................................................
8.4.3 Pin Functions ........................................................................................................
8.4.4 Pin States ..............................................................................................................
8.4.5 MOS Input Pull-Up...............................................................................................
8.5 Port 4..................................................................................................................................
8.5.1 Overview...............................................................................................................
8.5.2 Register Configuration and Description ...............................................................
8.5.3 Pin Functions ........................................................................................................
8.5.4 Pin States ..............................................................................................................
8.6 Port 5..................................................................................................................................
8.6.1 Overview...............................................................................................................
8.6.2 Register Configuration and Description ...............................................................
8.6.3 Pin Functions ........................................................................................................
8.6.4 Pin States ..............................................................................................................
8.6.5 MOS Input Pull-Up...............................................................................................
8.7 Port 6..................................................................................................................................
8.7.1 Overview...............................................................................................................
8.7.2 Register Configuration and Description ...............................................................
8.7.3 Pin Functions ........................................................................................................
8.7.4 Pin States ..............................................................................................................
8.7.5 MOS Input Pull-Up...............................................................................................
8.8 Port 7..................................................................................................................................
8.8.1 Overview...............................................................................................................
8.8.2 Register Configuration and Description ...............................................................
8.8.3 Pin Functions ........................................................................................................
8.8.4 Pin States ..............................................................................................................
8.9 Port 8..................................................................................................................................
8.9.1 Overview...............................................................................................................
8.9.2 Register Configuration and Description ...............................................................
8.9.3 Pin Functions ........................................................................................................
8.9.4 Pin States ..............................................................................................................
8.10 Port 9..................................................................................................................................
8.10.1 Overview...............................................................................................................
iv
137
139
139
140
140
140
144
144
145
145
145
149
151
151
152
152
152
153
154
155
155
155
157
158
158
159
159
159
161
161
161
162
162
162
164
164
165
165
165
166
166
167
167
8.11
8.12
8.13
8.14
8.10.2 Register Configuration and Description ...............................................................
8.10.3 Pin Functions ........................................................................................................
8.10.4 Pin States ..............................................................................................................
Port A .................................................................................................................................
8.11.1 Overview...............................................................................................................
8.11.2 Register Configuration and Description ...............................................................
8.11.3 Pin Functions ........................................................................................................
8.11.4 Pin States ..............................................................................................................
Port B .................................................................................................................................
8.12.1 Overview...............................................................................................................
8.12.2 Register Configuration and Description ...............................................................
Port C .................................................................................................................................
8.13.1 Overview...............................................................................................................
8.13.2 Register Configuration and Description ...............................................................
Input/Output Data Inversion Function ...............................................................................
8.14.1 Overview...............................................................................................................
8.14.2 Register Configuration and Descriptions..............................................................
8.14.3 Note on Modification of Serial Port Control Register..........................................
Section 9
9.1
9.2
9.3
9.4
9.5
Timers .................................................................................................................
Overview............................................................................................................................
Timer A..............................................................................................................................
9.2.1 Overview...............................................................................................................
9.2.2 Register Descriptions............................................................................................
9.2.3 Timer Operation....................................................................................................
9.2.4 Timer A Operation States .....................................................................................
Timer C ..............................................................................................................................
9.3.1 Overview...............................................................................................................
9.3.2 Register Descriptions............................................................................................
9.3.3 Timer Operation....................................................................................................
9.3.4 Timer C Operation States......................................................................................
Timer F...............................................................................................................................
9.4.1 Overview...............................................................................................................
9.4.2 Register Descriptions............................................................................................
9.4.3 CPU Interface........................................................................................................
9.4.4 Operation ..............................................................................................................
9.4.5 Application Notes .................................................................................................
Timer G..............................................................................................................................
9.5.1 Overview...............................................................................................................
9.5.2 Register Descriptions............................................................................................
9.5.3 Noise Canceler......................................................................................................
9.5.4 Operation ..............................................................................................................
9.5.5 Application Notes .................................................................................................
167
169
170
171
171
171
173
173
174
174
174
175
175
175
176
176
176
178
179
179
181
181
183
187
188
189
189
191
194
196
197
197
200
207
210
213
215
215
217
221
223
227
v
9.6
9.7
9.5.6 Timer G Application Example..............................................................................
Watchdog Timer ................................................................................................................
9.6.1 Overview...............................................................................................................
9.6.2 Register Descriptions............................................................................................
9.6.3 Timer Operation....................................................................................................
9.6.4 Watchdog Timer Operation States........................................................................
Asynchronous Event Counter (AEC).................................................................................
9.7.1 Overview...............................................................................................................
9.7.2 Register Descriptions............................................................................................
9.7.3 Operation ..............................................................................................................
9.7.4 Asynchronous Event Counter Operation Modes ..................................................
9.7.5 Application Notes .................................................................................................
232
233
233
234
238
239
240
240
242
247
249
250
Section 10 Serial Communication Interface ................................................................. 251
10.1 Overview............................................................................................................................ 251
10.2 SCI1 ................................................................................................................................... 252
10.2.1 Overview............................................................................................................... 252
10.2.2 Register Descriptions............................................................................................ 254
10.2.3 Operation .............................................................................................................. 260
10.2.4 Operation in SSB Mode........................................................................................ 263
10.2.5 Interrupt Source .................................................................................................... 265
10.2.6 Application Note................................................................................................... 265
10.3 SCI3 ................................................................................................................................... 266
10.3.1 Overview............................................................................................................... 266
10.3.2 Register Descriptions............................................................................................ 270
10.3.3 Operation .............................................................................................................. 290
10.3.4 Interrupts ............................................................................................................... 318
10.3.5 Application Notes ................................................................................................. 319
Section 11 14-Bit PWM...................................................................................................... 324
11.1 Overview............................................................................................................................
11.1.1 Features .................................................................................................................
11.1.2 Block Diagram......................................................................................................
11.1.3 Pin Configuration..................................................................................................
11.1.4 Register Configuration..........................................................................................
11.2 Register Descriptions .........................................................................................................
11.2.1 PWM Control Register (PWCR) ..........................................................................
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) ............................................
11.2.3 Clock Stop Register 2 (CKSTPR2) ......................................................................
11.3 Operation............................................................................................................................
11.3.1 Operation ..............................................................................................................
11.3.2 PWM Operation Modes........................................................................................
vi
324
324
324
325
325
326
326
327
328
329
329
330
Section 12 A/D Converter.................................................................................................. 331
12.1 Overview............................................................................................................................
12.1.1 Features .................................................................................................................
12.1.2 Block Diagram......................................................................................................
12.1.3 Pin Configuration..................................................................................................
12.1.4 Register Configuration..........................................................................................
12.2 Register Descriptions .........................................................................................................
12.2.1 A/D Result Registers (ADRRH, ADRRL) ...........................................................
12.2.2 A/D Mode Register (AMR) ..................................................................................
12.2.3 A/D Start Register (ADSR) ..................................................................................
12.2.4 Clock Stop Register 1 (CKSTPR1) ......................................................................
12.3 Operation............................................................................................................................
12.3.1 A/D Conversion Operation ...................................................................................
12.3.2 Start of A/D Conversion by External Trigger Input .............................................
12.3.3 A/D Converter Operation Modes..........................................................................
12.4 Interrupts ............................................................................................................................
12.5 Typical Use ........................................................................................................................
12.6 Application Notes ..............................................................................................................
331
331
332
333
333
334
334
334
336
337
338
338
338
339
339
339
342
Section 13 LCD Controller/Driver .................................................................................. 343
13.1 Overview............................................................................................................................
13.1.1 Features .................................................................................................................
13.1.2 Block Diagram......................................................................................................
13.1.3 Pin Configuration..................................................................................................
13.1.4 Register Configuration..........................................................................................
13.2 Register Descriptions .........................................................................................................
13.2.1 LCD Port Control Register (LPCR)......................................................................
13.2.2 LCD Control Register (LCR)................................................................................
13.2.3 LCD Control Register 2 (LCR2) ..........................................................................
13.2.4 Clock Stop Register 2 (CKSTPR2) ......................................................................
13.3 Operation............................................................................................................................
13.3.1 Settings up to LCD Display..................................................................................
13.3.2 Relationship between LCD RAM and Display ....................................................
13.3.3 Luminance Adjustment Function (V0 Pin)...........................................................
13.3.4 Step-Up Constant-Voltage (5 V) Power Supply...................................................
13.3.5 Low-Power-Consumption LCD Drive System.....................................................
13.3.6 Operation in Power-Down Modes ........................................................................
13.3.7 Boosting the LCD Drive Power Supply................................................................
13.3.8 Connection to HD66100 .......................................................................................
343
343
344
345
345
346
346
348
350
352
353
353
356
363
364
364
368
369
369
Section 14 Power Supply Circuit ..................................................................................... 372
14.1 Overview............................................................................................................................ 372
14.2 When Using the Internal Power Supply Step-Down Circuit ............................................. 372
vii
14.3 When Not Using the Internal Power Supply Step-Down Circuit ...................................... 373
Section 15 Electrical Characteristics .............................................................................. 374
15.1 Absolute Maximum Ratings ..............................................................................................
15.2 Electrical Characteristics....................................................................................................
15.2.1 Power Supply Voltage and Operating Range .......................................................
15.2.2 DC Characteristics ................................................................................................
15.2.3 AC Characteristics ................................................................................................
15.2.4 A/D Converter Characteristics..............................................................................
15.2.5 LCD Characteristics..............................................................................................
15.3 Operation Timing ...............................................................................................................
15.4 Output Load Circuit ...........................................................................................................
15.5 Resonator Equivalent Circuit .............................................................................................
374
375
375
378
384
389
390
392
396
397
Appendix A
398
398
406
408
A.1
A.2
A.3
CPU Instruction Set ...................................................................................
Instructions ........................................................................................................................
Operation Code Map..........................................................................................................
Number of Execution States ..............................................................................................
Appendix B
B.1
B.2
Internal I/O Registers ................................................................................ 414
Addresses ........................................................................................................................... 414
Functions............................................................................................................................ 417
Appendix C
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
C.12
I/O Port Block Diagrams ..........................................................................
Block Diagrams of Port 1 ..................................................................................................
Block Diagrams of Port 2 ..................................................................................................
Block Diagrams of Port 3 ..................................................................................................
Block Diagrams of Port 4 ..................................................................................................
Block Diagram of Port 5 ....................................................................................................
Block Diagram of Port 6 ....................................................................................................
Block Diagram of Port 7 ....................................................................................................
Block Diagrams of Port 8 ..................................................................................................
Block Diagram of Port 9 ....................................................................................................
Block Diagram of Port A ...................................................................................................
Block Diagram of Port B ...................................................................................................
Block Diagram of Port C ...................................................................................................
473
473
476
480
487
491
492
493
494
495
496
497
498
Appendix D
Port States in the Different Processing States .................................... 499
Appendix E
List of Product Codes ................................................................................ 500
Appendix F
Package Dimensions .................................................................................. 502
viii
Section 1 Overview
1.1
Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3887 and H8/3847 Series comprise single-chip
microcomputers equipped with a controller/driver. Other on-chip peripheral functions include six
types of timers, a 14-bit pulse width modulator (PWM), three serial communication interface
channels, and an A/D converter. Together, these functions make the H8/3887 and H8/3847 Series
ideally suited for embedded applications in systems requiring low power consumption and LCD
display. Models in the H8/3887 and H8/3847 Series are the H8/3882 and H8/3842, with on-chip
16-kbyte ROM and 1-kbyte RAM, the H8/3883 and H8/3843, with on-chip 24-kbyte ROM and 1kbyte RAM, the H8/3884 and H8/3844, with on-chip 32-kbyte ROM and 2-kbyte RAM, the
H8/3885 and H8/3845, with 40-kbyte ROM and 2-kbyte RAM, the H8/3886 and H8/3846, with
48-kbyte ROM and 2-kbyte RAM, and the H8/3887 and H8/3847, with 60-kbyte ROM and 2kbyte RAM.
The H8/3887 and H8/3847 Series are also available in a ZTAT™* version with on-chip PROM
which can be programmed as required by the user.
Table 1-1 summarizes the features of the H8/3887 and H8/3847 Series.
Note: *ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd.
1
Table 1-1
Features
Item
Description
CPU
High-speed H8/300L CPU
•
General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
•
Operating speed
 Max. operating speed: 3 Mhz
 Add/subtract: 0.67 µs (operating at 3 Mhz)
 Multiply/divide: 4.67 µs (operating at 3 Mhz)
 Can run on 32.768 kHz or 38.4 kHz subclock
•
Instruction set compatible with H8/300 CPU
 Instruction length of 2 bytes or 4 bytes
 Basic arithmetic operations between registers
 MOV instruction for data transfer between memory and registers
•
Typical instructions
 Multiply (8 bits × 8 bits)
 Divide (16 bits ÷ 8 bits)
 Bit accumulator
 Register-indirect designation of bit position
Interrupts
Clock pulse
generators
Power-down
modes
2
37 interrupt sources
•
13 external interrupt sources (IRQ4 to IRQ0, WKP7 to WKP0)
•
24 internal interrupt sources
Two on-chip clock pulse generators
•
System clock pulse generator: 0.4 to 6 Mhz
•
Subclock pulse generator: 32.768 kHz, 38.4 kHz
Seven power-down modes
•
Sleep (high-speed) mode
•
Sleep (medium-speed) mode
•
Standby mode
•
Watch mode
•
Subsleep mode
•
Subactive mode
•
Active (medium-speed) mode
Table 1-1
Features (cont)
Item
Description
Memory
Large on-chip memory
I/O ports
Timers
•
H8/3882 and H8/3842: 16-kbyte ROM, 1-kbyte RAM
•
H8/3883 and H8/3843: 24-kbyte ROM, 1-kbyte RAM
•
H8/3884 and H8/3844: 32-kbyte ROM, 2-kbyte RAM
•
H8/3885 and H8/3845: 40-kbyte ROM, 2-kbyte RAM
•
H8/3886 and H8/3846: 48-kbyte ROM, 2-kbyte RAM
•
H8/3887 and H8/3847: 60-kbyte ROM, 2-kbyte RAM
84 pins
•
71 I/O pins
•
13 input pins
Six on-chip timers
•
Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from the
system clock (ø)* and four clock signals divided from the watch clock (øw)*
•
Asynchronous event counter: 16-bit timer
 Count-up timer able to count asynchronous external events independently
of the MCU's internal clocks
•
Timer C: 8-bit timer
 Count-up/down timer with selection of seven internal clock signals or event
input from external pin
 Auto-reloading
•
Timer F: 16-bit timer
 Can be used as two independent 8-bit timers
 Count-up timer with selection of four internal clock signals or event input
from external pin
 Provision for toggle output by means of compare-match function
•
Timer G: 8-bit timer
 Count-up timer with selection of four internal clock signals
 Incorporates input capture function (built-in noise canceler)
•
Watchdog timer
 Reset signal generated by overflow of 8-bit counter
Note:
*
See section 4, Clock Pulse Generator, for the definition of ø and øw.
3
Table 1-1
Features (cont)
Item
Description
Serial
communication
interface
Three serial communication interface channels on chip
14-bit PWM
•
SCI1: Synchronous serial interface
Choice of 8-bit or 16-bit transfer data
•
SCI3-1: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
•
SCI3-2: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
Pulse-division PWM output for reduced ripple
•
A/D converter
LCD
controller/driver
Can be used as a 14-bit D/A converter by connecting to an external low-pass
filter.
Successive approximations using a resistance ladder
•
12-channel analog input pins
•
Conversion time: 31/ø or 62/ø per channel
LCD controller/driver equipped with a maximum of 40 segment pins and four
common pins
•
Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
•
Segment pins can be switched to general-purpose port function in 8-bit units
LCD drive power Step-up constant-voltage power supply allows LCD display.(H8/3887 Series only)
supply
4
Table 1-1
Features (cont)
Item
Specification
Product lineup
Product Code
Mask ROM
Version
ZTAT
Version
Package
ROM/RAM
Size (Byte)
HD6433882H,
HD6433842H
—
100-pin QFP (FP-100B)
16 k/1 k
HD6433882F,
HD6433842F
—
100-pin QFP (FP-100A)
HD6433882X,
HD6433842X
—
100-pin TQFP (TFP-100B)
HD6433882W,
HD6433842W
—
100-pin TQFP (TFP-100G)
HD6433883H,
HD6433843H
—
100-pin QFP (FP-100B)
HD6433883F,
HD6433843F
—
100-pin QFP (FP-100A)
HD6433883X,
HD6433843X
—
100-pin TQFP (TFP-100B)
HD6433883W,
HD6433843W
—
100-pin TQFP (TFP-100G)
HD6433884H,
HD6433844H
—
100-pin QFP (FP-100B)
HD6433884F,
HD6433844F
—
100-pin QFP (FP-100A)
HD6433884X,
HD6433844X
—
100-pin TQFP (TFP-100B)
HD6433884W,
HD6433844W
—
100-pin TQFP (TFP-100G)
HD6433885H,
HD6433845H
—
100-pin QFP (FP-100B)
HD6433885F,
HD6433845F
—
100-pin QFP (FP-100A)
HD6433885X,
HD6433845X
—
100-pin TQFP (TFP-100B)
HD6433885W,
HD6433845W
—
100-pin TQFP (TFP-100G)
24 k/1 k
32 k/2 k
40 k/2 k
5
Table 1-1
Features (cont)
Item
Specification
Product lineup
Product Code
6
Mask ROM
Version
ZTAT
Version
Package
ROM/RAM
Size (Byte)
HD6433886H,
HD6433846H
—
100-pin QFP (FP-100B)
48 k/2 k
HD6433886F,
HD6433846F
—
100-pin QFP (FP-100A)
HD6433886X,
HD6433846X
—
100-pin TQFP (TFP-100B)
HD6433886W,
HD6433846W
—
100-pin TQFP (TFP-100G)
HD6433887H,
HD6433847H
HD6473887H,
HD6473847H
100-pin QFP (FP-100B)
HD6433887F,
HD6433847F
HD6473887F,
HD6473847F
100-pin QFP (FP-100A)
HD6433887X,
HD6433847X
HD6473887X,
HD6473847X
100-pin TQFP (TFP-100B)
HD6433887W,
HD6433847W
HD6473887W,
HD6473847W
100-pin TQFP (TFP-100G)
60 k/2 k
1.2
Internal Block Diagram
LCD power
supply
RES
TEST
VSS
VSS
VCC
CVCC
X1
X2
Sub clock
OSC
Port A
Port 9
Port 8
Port 7
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Port 6
System clock
OSC
Port 2
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
14-bit PWM
Timer-G
LCD
controller/driver
WDT
Asynchronous
counter
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Port B
Port C
PC0/AN8
PC1/AN9
PC2/AN10
PC3/AN11
A/D (10-bit)
AVSS
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Serial
communication
interface 3-2
Timer-F
AVCC
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
P97/SEG40/CL1
P96/SEG39/CL2
P95/SEG38/DO
P94/SEG37/M
P93/SEG36
P92/SEG35
P91/SEG34
P90/SEG33
Serial
communication
interface 3-1
Timer-C
Port 3
P30/PWM
P31/UD
P32/RESO
P33/SCK31
P34/RXD31
P35/TXD31
P36/AEVH
P37/AEVL
Serial
communication
interface 1
Timer-A
V0
V1
V2
V3
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
RAM
(2 k and 1 k)
Port 4
P20/SCK1
P21/SI1
P22/SO1
P23
P24
P25
P26
P27
H8/300L
CPU
ROM
(60 k, 48 k, 40 k, 32 k,
24 k, and 16 k)
Port 5
P10/TMOW
P11/TMOFL
P12/TMOFH
P13/TMIG
P14/IRQ4/ADTRG
P15/IRQ1/TMIC
P16/IRQ2
P17/IRQ3/TMIF
Port 1
OSC1
OSC2
Figure 1-1 shows a block diagram of the H8/3887 and H8/3847 Series.
Figure 1-1 Block Diagram
7
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
P90/SEG33
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
The H8/3887 and H8/3847 Series pin arrangement is shown in figures 1-2 and 1-3.
P91/SEG34
76
50
P57/WKP7/SEG8
P92/SEG35
77
49
P56/WKP6/SEG7
P93/SEG36
78
48
P55/WKP5/SEG6
P94/SEG37/M
79
47
P54/WKP4/SEG5
P95/SEG38/DO
80
46
P53/WKP3/SEG4
P96/SEG39/CL2
81
45
P52/WKP2/SEG3
P97/SEG40/CL1
82
44
P51/WKP1/SEG2
P40/SCK32
83
43
P50/WKP0/SEG1
P41/RXD32
84
42
PA0/COM1
P42/TXD32
85
41
PA1/COM2
P43/IRQ0
86
40
PA2/COM3
AVCC
87
39
PA3/COM4
PB0/AN0
88
38
VCC
PB1/AN1
89
37
V0
PB2/AN2
90
36
V1
PB3/AN3
91
35
V2
PB4/AN4
92
34
V3
PB5/AN5
93
33
VSS
PB6/AN6
94
32
CVCC
PB7/AN7
95
31
P37/AEVL
PC0/AN8
96
30
P36/AEVH
21
22
23
24
25
P25
P26
P27
P30/PWM
P31/UD
15
RES
20
14
TEST
P24
13
OSC1
19
12
OSC2
P23
11
VSS
18
10
X2
P22/SO1
9
X1
17
8
P17/IRQ3/TMIF
P21/SI1
7
P16/IRQ2
16
6
P15/IRQ1/TMIC
P20/SCK1
5
P32/RESO
P14/IRQ4/ADTRG
26
4
P33/SCK31
100
AVSS
P13/TMIG
27
3
99
P12/TMOFH
P34/RXD31
PC3/AN11
2
P35/TXD31
28
1
29
98
P10/TMOW
97
P11/TMOFL
PC1/AN9
PC2/AN10
Figure 1-2 Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View)
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
OSC2
OSC1
TEST
RES
P20/SCK1
P21/SI1
P22/SO1
P23
P24
P25
P26
P27
P30/PWM
P31/UD
P32/RESO
P33/SCK31
9
P15/IRQ1/TMIC
13
8
P14/IRQ4/ADTRG
X2
7
P13/TMIG
12
6
P12/TMOFH
X1
5
P11/TMOFL
11
4
P17/IRQ3/TMIF
3
AVSS
P10/TMOW
10
2
PC3/AN11
P16/IRQ2
1
PC2/AN10
P93/SEG36
81
50
P54/WKP4/SEG5
P94/SEG37/M
82
49
P53/WKP3/SEG4
P95/SEG38/DO
83
48
P52/WKP2/SEG3
P96/SEG39/CL2
84
47
P51/WKP1/SEG2
P97/SEG40/CL1
85
46
P50/WKP0/SEG1
P40/SCK32
86
45
PA0/COM1
P41/RXD32
87
44
PA1/COM2
P42/TXD32
88
43
PA2/COM3
P43/IRQ0
89
42
PA3/COM4
AVCC
90
41
VCC
PB0/AN0
91
40
V0
PB1/AN1
92
39
V1
PB2/AN2
93
38
V2
PB3/AN3
94
37
V3
PB4/AN4
95
36
VSS
PB5/AN5
96
35
CVCC
PB6/AN6
97
34
P37/AEVL
PB7/AN7
98
33
P36/AEVH
PC0/AN8
99
32
P35/TXD31
PC1/AN9
100
31
P34/RXD31
Figure 1-3 Pin Arrangement (FP-100A: Top View)
9
P92/SEG35
P91/SEG34
P90/SEG33
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1.3.2
Pin Functions
Table 1-2 outlines the pin functions of the H8/3887 Series.
Table 1-2
Pin Functions
Pin No.
Type
Symbol
FP-100B
TFP-100B
TFP-100G
Power
source
pins
VCC
CV CC
38
32
41
35
Input
Power supply: All VCC connected to
the system power supply.pins should
be See section 14, Power Supply
Circuit.
VSS
11
33
14
36
Input
Ground: All VSS pins should be
connected to the system power supply
(0 V).
AVCC
87
90
Input
Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.
AVSS
100
3
Input
Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0V).
V0
37
40
Output
LCD power supply: These are the
V1
V2
V3
36
35
34
39
38
37
Input
power supply pins for the LCD
controller/driver. They incorporate a
power supply split-resistance, and are
normally used with V0 and V1 shorted.
Clock pins OSC 1
13
16
Input
These pins connect to a crystal or
OSC 2
12
15
Output
ceramic oscillator, or can be used to
input an external clock. See section 4,
Clock Pulse Generators, for a typical
connection diagram.
X1
9
12
Input
These pins connect to a 32.768-kHz or
X2
10
13
10
FP-100A
I/O
Name and Functions
38.4-kHz crystal oscillator. Output See
section 4, Clock Pulse Genera–tors, for
a typical connection diagram.
Table 1-2
Pin Functions (cont)
Pin No.
Type
Symbol
FP-100B
TFP-100B
TFP-100G
System
control
RES
15
18
Input
Reset: When this pin is driven low, the
chip is reset
RESO
26
29
Output
Reset output: Outputs the CPU
internal reset signal.
TEST
14
17
Output
Test pin: This pin is reserved and
cannot be used. It should be
connected to VSS .
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
86
6
7
8
5
89
9
10
11
8
Input
IRQ interrupt request 0 to 4: These
are input pins for edge-sensitive
external interrupts, with a selection of
rising or falling edge.
WKP 7 to
WKP 0
50 to 43
53 to 46
Input
Wakeup interrupt request 0 to 7:
These are input pins for rising or
falling- edge-sensitive external
interrupts.
2
4
Output
Clock output: This is an output pin for
waveforms generated by the timer A
output circuit.
AEVL
AEVH
31
30
34
33
Input
Asynchronous event counter event
input: This is an event input pin for
input to the asynchronous event
counter.
TMIC
6
9
Input
Timer C event input: This is an event
input pin for input to the timer C
counter.
UD
25
28
Input
Timer C up/down select: This pin
selects up- or down-counting for the
timer C counter. The counter operates
as an up-counter when this pin is high,
and as a down-counter when low.
TMIF
8
11
Input
Timer F event input: This is an event
input pin for input to the timer F
counter.
TMOFL
2
5
Output
Timer FL output: This is an output pin
for waveforms generated by the timer
FL output compare function.
Interrupt
pins
Timer pins TMOW
FP-100A
I/O
Name and Functions
11
Table 1-2
Pin Functions (cont)
Pin No.
FP-100B
TFP-100B
TFP-100G
FP-100A
I/O
Name and Functions
3
6
Output
Timer FH output: This is an output pin
for waveforms generated by the timer
FH output compare function.
TMIG
4
7
Input
Timer G capture input: This is an
input pin for timer G input capture.
14-bit
PWM pin
PWM
24
27
Output
14-bit PWM output: This is an output
pin for waveforms generated by the 14bit PWM
I/O ports
PB7 to PB 0 95 to 88
98 to 91
Input
Port B: This is an 8-bit input port.
PC 3 to PC0 99 to 96
2, 1,
100, 99
Input
Port C: This is a 4-bit input port.
P43
86
89
Input
Port 4 (bit 3): This is a 1-bit input port.
P42 to P4 0
85 to 83
88 to 86
I/O
Port 4 (bits 2 to 0): This is a 3-bit I/O
port. Input or output can be
designated for each bit by means of
port control register 4 (PCR4).
PA3 to PA 0 39 to 42
42 to 45
I/O
Port A: This is a 4-bit I/O port. Input or
output can be designated for each bit
by means of port control register A
(PCRA).
P17 to P1 0
8 to 1
11 to 4
I/O
Port 1: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 1
(PCR1).
P27 to P2 0
23 to 16
26 to 19
I/O
Port 2: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 2
(PCR2).
P37 to P3 0
31 to 24
34 to 27
I/O
Port 3: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 3
(PCR3).
P57 to P5 0
50 to 43
53 to 46
I/O
Port 5: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 5
(PCR5).
Type
Symbol
Timer pins TMOFH
12
Table 1-2
Pin Functions (cont)
Pin No.
Type
Symbol
FP-100B
TFP-100B
TFP-100G
I/O ports
P67 to P6 0
58 to 51
61 to 54
I/O
Port 6: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 6
(PCR6).
P77 to P7 0
66 to 59
69 to 62
I/O
Port 7: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 7
(PCR7).
P87 to P8 0
74 to 67
77 to 70
I/O
Port 8: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 8
(PCR8).
P97 to P9 0
82 to 75
85 to 78
I/O
Port 9: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 9
(PCR9).
Serial
SI 1
communi-
17
20
Input
SCI1 receive data input: This is the
SCI1 data input pin.
cation
interface
SO1
18
21
Output
SCI1 transmit data output: This is the
SCI1 data output pin.
(SCI)
SCK 1
16
19
I/O
SCI1 clock I/O: This is the SCI1 clock
I/O pin.
RXD31
28
31
Input
SCI3-1 receive data input: This is the
SCI31 data input pin.
TXD31
29
32
Output
SCI3-1 transmit data output: This is
the SCI31 data output pin.
SCK 31
27
30
I/O
SCI3-1 clock I/O: This is the SCI31
clock I/O pin.
RXD32
84
87
Input
SCI3-2 receive data input: This is the
SCI32 data input pin.
TXD32
85
88
Output
SCI3-2 transmit data output: This is
the SCI32 data output pin.
SCK 32
83
86
I/O
SCI3-2 clock I/O: This is the SCI32
clock I/O pin.
FP-100A
I/O
Name and Functions
13
Table 1-2
Pin Functions (cont)
Pin No.
Type
Symbol
FP-100B
TFP-100B
TFP-100G
FP-100A
I/O
Name and Functions
2 to 1 100
to 91
Input
Analog input channels 11 to 0:
These are analog data input channels
to the A/D converter
5
8
Input
A/D converter trigger input: This is
the external trigger input pin to the A/D
converter
LCD
COM4 to
controller/ COM1
39 to 42
42 to 45
Output
LCD common output: These are the
LCD common output pins.
driver
SEG40 to
SEG1
82 to 43
85 to 46
Output
LCD segment output: These are the
LCD segment output pins.
CL 1
82
85
Output
LCD latch clock: This is the display
data latch clock output pin for external
expansion of the segment.
CL 2
81
84
Output
LCD shift clock: This is the display
data shift clock output pin for external
expansion of the segment.
DO
80
83
Output
LCD serial data output: This is the
serial display data output pin for
external expansion of the segment.
M
79
82
Output
LCD alternating signal: This is the
LCD alternating signal output pin for
external expansion of the segment.
A/D
AN 11 to An 0 99 to 88
convert–er
ADTRG
14
Section 2 CPU
2.1
Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1
Features
Features of the H8/300L CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct
 Register indirect
 Register indirect with displacement
 Register indirect with post-increment or pre-decrement
 Absolute address
 Immediate
 Program-counter relative
 Memory indirect
• 64-kbyte address space
• High-speed operation
 All frequently used instructions are executed in two to four states
 High-speed arithmetic and logic operations
 8- or 16-bit register-register add or subtract:
0.67 µs*
 8 × 8-bit multiply:
4.67 µs*
 16 ÷ 8-bit divide:
4.67 µs*
• Low-power operation modes
SLEEP instruction for transfer to low-power operation
Note: * These values are at ø = 3 MHz.
15
2.1.2
Address Space
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and
data.
See 2.8, Memory Map, for details of the memory map.
2.1.3
Register Configuration
Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
0
R0H
R0L
R1H
R1L
R2H
R2L
R3H
R3L
R4H
R4L
R5H
R5L
R6H
R6L
R7H
(SP)
SP: Stack pointer
R7L
Control registers (CR)
15
0
PC
CCR
7 6 5 4 3 2 1 0
I UHUNZ VC
PC: Program counter
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
Figure 2-1 CPU Registers
16
2.2
Register Descriptions
2.2.1
General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2-2 Stack Pointer
2.2.2
Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of
the PC is ignored (always regarded as 0).
Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC,
ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for
conditional branching (Bcc) instructions.
17
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see section 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.
2.2.3
Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer
should be initialized by software, by the first instruction executed after a reset.
18
2.3
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
19
2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2-3.
Data Type
Register No.
Data Format
7
1-bit data
RnH
1-bit data
RnL
7
0
6
5
4
3
2
1
0
don’t care
7
Byte data
RnH
Byte data
RnL
Word data
Rn
don’t care
7
0
MSB
LSB
don’t care
RnH
4-bit BCD data
RnL
6
5
3
2
1
0
don’t care
7
0
MSB
LSB
15
0
LSB
4
3
Upper digit
0
Lower digit
don’t care
7
don’t care
4
Upper digit
Notation:
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2-3 Register Data Formats
20
4
MSB
7
4-bit BCD data
0
7
0
3
Lower digit
2.3.2
Memory Data Formats
Figure 2-4 indicates the data formats in memory. The H8/300L CPU can access word data stored
in memory (MOV.W instruction), but the word data must always begin at an even address. If word
data starting at an odd address is accessed, the least significant bit of the address is regarded as 0,
and the word data starting at the preceding address is accessed. The same applies to instruction
codes.
Data Type
Address
Data Format
7
1-bit data
Address n
7
Byte data
Address n
MSB
Even address
MSB
Word data
Odd address
Byte data (CCR) on stack
Word data on stack
0
6
5
4
3
2
1
0
LSB
Upper 8 bits
Lower 8 bits
LSB
Even address
MSB
CCR
LSB
Odd address
MSB
CCR*
LSB
Even address
MSB
Odd address
LSB
CCR: Condition code register
Note: * Ignored on return
Figure 2-4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.
21
2.4
Addressing Modes
2.4.1
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a
subset of these addressing modes.
Table 2-1
Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
@Rn+
Register indirect with pre-decrement
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
22
The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented
value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original
contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second
byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can
contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits
and added to the program counter contents to generate a branch destination address. The
possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
The displacement should be an even number.
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at this
address contains the branch destination address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area.
23
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
2.4.2
Effective Address Calculation
Table 2-2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position
in the operand.
24
25
4
3
2
rm
op
7 6
rm
4 3
4 3
rn
0
0
op
disp
7 6
rm
op
7 6
rm
4 3
4 3
0
0
15
op
7 6
rm
4 3
0
Register indirect with pre-decrement,
@–Rn
15
Register indirect with
post-increment, @Rn+
15
Register indirect with displacement,
@(d:16, Rn)
15
Register indirect, @Rn
op
8 7
Register direct, Rn
1
15
Addressing Mode and
Instruction Format
No.
Table 2-2 Effective Address Calculation
0
0
0
Contents (16 bits) of register
indicated by rm
0
1 or 2
Contents (16 bits) of register
indicated by rm
disp
Contents (16 bits) of register
indicated by rm
Contents (16 bits) of register
indicated by rm
3
rm
0
3
rn
Effective Address (EA)
0
15
15
15
15
0
0
0
0
Operand is contents of registers indicated by rm/rn
Incremented or decremented
by 1 if operand is byte size,
1 or 2
and by 2 if word size
15
15
15
15
Effective Address Calculation Method
26
7
6
5
No.
op
op
IMM
op
8 7
abs
op
8 7
IMM
abs
15
op
8 7
disp
Program-counter relative
@(d:8, PC)
15
#xx:16
15
Immediate
#xx:8
15
@aa:16
15
Absolute address
@aa:8
Addressing Mode and
Instruction Format
0
0
0
0
0
Table 2-2 Effective Address Calculation (cont)
PC contents
Sign extension
15
disp
0
Effective Address Calculation Method
H'FF
8 7
0
0
15
0
Operand is 1- or 2-byte immediate data
15
15
Effective Address (EA)
27
Notation:
rm, rn: Register field
Operation field
op:
disp: Displacement
IMM: Immediate data
abs: Absolute address
op
8 7
abs
Memory indirect, @@aa:8
8
15
Addressing Mode and
Instruction Format
No.
0
Table 2-2 Effective Address Calculation (cont)
15
8 7
abs
Memory contents (16 bits)
H'00
0
Effective Address Calculation Method
15
Effective Address (EA)
0
2.5
Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3.
Table 2-3
Instruction Set
Function
Instructions
Number
1
1
Data transfer
MOV, PUSH* , POP*
1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS,
DAA, DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, 14
BXOR, BIXOR, BLD, BILD, BST, BIST
Branch
Bcc* 2, JMP, BSR, JSR, RTS
5
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
EEPMOV
1
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine
language.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
28
Notation
Rd
General register (destination)
Rs
General register (source)
Rn
General register
(EAd), <EAd>
Destination operand
(EAs), <EAs>
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
~
Logical negation (logical complement)
:3
3-bit length
:8
8-bit length
:16
16-bit length
( ), < >
Contents of operand indicated by effective address
29
2.5.1
Data Transfer Instructions
Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats.
Table 2-4
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (Ead)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not
specify byte size for these two modes.
POP
W
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
PUSH
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to
MOV.W Rn, @–SP.
Notes: * Size: Operand size
B: Byte
W: Word
Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details.
30
15
8
7
0
op
rm
15
8
rn
0
rm
8
Rm→Rn
7
op
15
MOV
rn
@Rm←→Rn
7
0
op
rm
rn
rm
rn
@(d:16, Rm)←→Rn
disp
15
8
7
0
op
15
8
op
7
0
rn
15
@Rm+→Rn, or
Rn →@–Rm
abs
8
@aa:8←→Rn
7
0
op
rn
@aa:16←→Rn
abs
15
8
op
7
0
rn
15
IMM
8
#xx:8→Rn
7
0
op
rn
#xx:16→Rn
IMM
15
8
op
7
0
1
1
1
rn
PUSH, POP
@SP+ → Rn, or
Rn → @–SP
Notation:
op:
Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2-5 Data Transfer Instruction Codes
31
2.5.2
Arithmetic Operations
Table 2-5 describes the arithmetic instructions.
Table 2-5
Arithmetic Instructions
Instruction
Size*
Function
ADD
SUB
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
ADDX
SUBX
B
INC
DEC
B
ADDS
SUBS
W
DAA
DAS
B
MULXU
B
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general register.
Word data can be added or subtracted only when both words are in
general registers.
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data
and data in a general register.
Rd ± 1 → Rd
Increments or decrements a general register by 1.
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction
result in a general register by referring to the CCR
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
CMP
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the CCR.
Word data can be compared only between two general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Notes: * Size: Operand size
B: Byte
W: Word
32
2.5.3
Logic Operations
Table 2-6 describes the four instructions that perform logic operations.
Table 2-6
Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data
NOT
B
~ Rd → Rd
Obtains the one’s complement (logical complement) of general
register contents
Notes: * Size: Operand size
B: Byte
2.5.4
Shift Operations
Table 2-7 describes the eight shift instructions.
Table 2-7
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd shift → Rd
SHLL
SHLR
B
ROTL
ROTR
B
ROTXL
ROTXR
B
Performs an arithmetic shift operation on general register contents
Rd shift → Rd
Performs a logical shift operation on general register contents
Rd rotate → Rd
Rotates general register contents
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit
Notes: * Size: Operand size
B: Byte
33
Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
8
7
op
0
rm
15
8
7
0
op
15
8
7
0
rm
8
op
8
0
8
0
AND, OR, XOR (Rm)
0
IMM
8
op
rn
7
rn
15
ADD, ADDX, SUBX,
CMP (#XX:8)
7
rm
15
MULXU, DIVXU
IMM
op
op
rn
7
rn
15
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
rn
op
15
ADD, SUB, CMP,
ADDX, SUBX (Rm)
rn
AND, OR, XOR (#xx:8)
7
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
Notation:
Operation field
op:
rm, rn: Register field
IMM: Immediate data
Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes
34
2.5.5
Bit Manipulations
Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats.
Table 2-8
Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <Ead>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.
BCLR
B
0 → (<bit-No.> of <Ead>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
~ (<bit-No.> of <EAd>) → (<bit-No.> of <Ead>)
Inverts a specified bit in a general register or memory. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.
BTST
B
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIAND
B
C ∧ [~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIOR
B
C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size
B: Byte
35
Table 2-8
Bit-Manipulation Instructions (cont)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIXOR
B
C ⊕ [~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
BILD
B
~ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or memory
to the C flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
BIST
B
~ C → (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size
B: Byte
Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for
details.
36
BSET, BCLR, BNOT, BTST
15
8
7
op
0
IMM
15
8
7
op
0
rm
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
rn
7
op
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
op
rn
0
0
0
0 Operand: register indirect (@Rn)
op
rm
0
0
0
0 Bit No.:
op
15
8
15
8
7
0
7
abs
IMM
15
8
0
Operand: absolute (@aa:8)
0
0
7
0 Bit No.:
immediate (#xx:3)
0
op
abs
op
register direct (Rm)
0
op
op
immediate (#xx:3)
rm
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Notation:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2-7 Bit Manipulation Instruction Codes
37
BIAND, BIOR, BIXOR, BILD, BIST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Notation:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2-7 Bit Manipulation Instruction Codes (cont)
38
2.5.6
Branching Instructions
Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats.
Table 2-9
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The
branching conditions are given below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ⁄ (N ⊕ V) = 0
BLE
Less or equal
Z ⁄ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
39
15
8
op
7
0
cc
15
disp
8
7
op
0
rm
15
Bcc
8
0
0
0
7
0
JMP (@Rm)
0
op
JMP (@aa:16)
abs
15
8
7
0
op
abs
15
8
JMP (@@aa:8)
7
0
op
disp
15
8
7
op
0
rm
15
BSR
8
0
0
0
7
0
JSR (@Rm)
0
op
JSR (@aa:16)
abs
15
8
7
op
0
abs
15
8
7
op
Notation:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2-8 Branching Instruction Codes
40
JSR (@@aa:8)
0
RTS
2.5.7
System Control Instructions
Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats.
Table 2-10 System Control Instructions
Instruction
Size*
Function
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition from active mode to a power-down mode. See
section 5, Power-Down Modes, for details.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition
code register
STC
B
CCR → Rd
Copies the condition code register to a specified general register
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data
NOP
—
PC + 2 → PC
Only increments the program counter
Notes: * Size: Operand size
B: Byte
41
15
8
7
0
op
15
8
RTE, SLEEP, NOP
7
0
op
15
rn
8
7
LDC, STC (Rn)
0
op
IMM
ANDC, ORC,
XORC, LDC (#xx:8)
Notation:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2-9 System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format.
Table 2-11 Block Data Transfer Instruction
Instruction
Size
Function
EEPMOV
—
If R4L ≠ 0 then
repeat
until
@R5+ → @R6+
R4L – 1 → R4L
R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the
EEPMOV Instruction, for details.
42
15
8
7
0
op
op
Notation:
op: Operation field
Figure 2-10 Block Data Transfer Instruction Code
43
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock (ø) or a subclock (øSUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or øSUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2-11 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
ø or ø SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-11 On-Chip Memory Access Cycle
44
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle.
Two-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
ø or ø SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access)
45
Three-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
T3 state
ø or ø SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access)
46
2.7
CPU States
2.7.1
Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2-14. Figure 2-15 shows the state transitions.
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Low-power
modes
Sleep (high-speed)
mode
Sleep (medium-speed)
mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2-14 CPU Operation States
47
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
occurs
Program halt state
Interrupt
source
occurs
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2-15 State Transitions
2.7.2
Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3
Program Halt State
In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.
2.7.4
Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3.3, Interrupts.
48
2.8
Memory Map
The memory map of the H8/3882 and H8/3842 is shown in figure 2-16 (1), that of the H8/3883
and H8/3843 in figure 2-16 (2), that of the H8/3884 and H8/3844 in figure 2-16 (3), that of the
H8/3885 and H8/3845 in figure 2-16 (4), that of the H8/3886 and H8/3846 in figure 2-16 (5), and
that of the H8/3887 and H8/3847 in figure 2-16 (6).
H'0000
Interrupt vector area
H'0029
H'002A
16 kbytes
On-chip ROM
(16384 bytes)
H'3FFF
Not used
H'F740
LCD RAM
(32 bytes)
H'F75F
Not used
H'F780
On-chip RAM
1024 bytes
H'FB7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2-16 (1) H8/3882 and H8/3842 Memory Map
49
H'0000
H'0029
Interrupt
vector area
H'002A
24 kbytes
On-chip ROM
(24576 bytes)
H'5FFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
1024 bytes
H'FB7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2-16 (2) H8/3883 and H8/3843 Memory Map
50
H'0000
Interrupt vector area
H'0029
H'002A
32 kbytes
On-chip ROM
(32768 bytes)
H'7FFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2-16 (3) H8/3884 and H8/3844 Memory Map
51
H'0000
Interrupt vector area
H'0029
H'002A
40 kbytes
On-chip ROM
(40960 bytes)
H'9FFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2-16 (4) H8/3885 and H8/3845 Memory Map
52
H'0000
Interrupt vector area
H'0029
H'002A
48 kbytes
(49152 bytes)
On-chip ROM
H'BFFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2-16 (5) H8/3886 and H8/3846 Memory Map
53
H'0000
Interrupt vector area
H'0029
H'002A
60 kbytes
On-chip ROM
(60928 bytes)
H'EDFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2-16 (6) H8/3887 and H8/3847 Memory Map
54
2.9
Application Notes
2.9.1
Notes on Data Access
1. Access to Empty Areas:
The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Data transfer from empty area to CPU:
Unpredictable data is transferred.
2. Access to Internal I/O Registers:
Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of
states in which on-chip peripheral modules can be accessed.
55
Access
States
Word
Byte
H'0000
H'0029
Interrupt vector area
(42 bytes)
H'002A
2
32kbytes*1
On-chip ROM
*1
H'7FFF
—
Not used
—
—
H'F740
LCD RAM
(20 bytes)
2
H'F753
—
Not used
—
—
H'F780
*2
H'FF7F
On-chip RAM
2048 bytes*2
Not used
—
H'FF90
Internal I/O registers
(112 bytes)
2
H'FF98 to H'FF9F
H'FFA8 to H'FFAF
H'FFFF
—
—
×
2
×
3
×
2
×
3
×
2
Notes: The H8/3884 and H8/3844 are shown as an example.
1. The address is H'3FFF in the H8/3882 and H8/3842 (16-kbyte on-chip ROM), H'5FFF in
the H8/3883 and H8/3843 (24-kbyte on-chip ROM), H'9FFF in the H8/3885 and H8/3845
(40-kbyte on-chip ROM), H'BFFF in the H8/3886 and H8/3846 (48-kbyte on-chip ROM),
and H'EDFF in the H8/3887 and H8/3847 (60-kbyte on-chip ROM).
2. The address is H'FB7F in the H8/3882, H8/3842, H8/3883 and H8/3843 (1024-byte onchip ROM).
Figure 2-17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
56
2.9.2
Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation
Operation
1
Read
Read byte data at the designated address
2
Modify
Modify a designated bit in the read data
3
Write
Write the altered byte data to the designated address
1. Bit manipulation in two registers assigned to the same address
Example 1: timer load register and timer counter
Figure 2-18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation
Operation
1
Read
Timer counter data is read (one byte)
2
Modify
The CPU modifies (sets or resets) the bit designated in the instruction
3
Write
The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal bus
Figure 2-18 Timer Configuration Example
57
Example 2: BSET instruction executed designating port 3
P3 7 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P3 6. The remaining pins, P35 to P30, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P30 to high-level output.
[A: Prior to executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET
#0
,
@PDR3
The BSET instruction is executed designating port 3.
[C: After executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
0
0
1
1
1
1
1
1
PDR3
0
1
0
0
0
0
0
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P3 5 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P3 0 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
58
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B #80
MOV. B R0L
MOV. B R0L
,
,
,
R0L
@RAM0
@PDR3
The PDR3 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET
#0
,
@RAM0
The BSET instruction is executed designating the PDR3
work area (RAM0).
[C: After executing BSET]
MOV. B @RAM0,
MOV. B R0L,
R0L
@PDR3
The work area (RAM0) value is written to PDR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
59
2. Bit manipulation in a register containing a write-only bit
Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a
high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
[B: BCLR instruction executed]
BSET
#0
,
@PCR3
The BCLR instruction is executed designating PCR3.
[C: After executing BCLR]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
1
1
1
1
1
1
1
0
PDR3
1
0
0
0
0
0
0
0
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR3 becomes 0, making P3 0 an input port. However, bits 7
and 6 in PCR3 change to 1, so that P3 7 and P36 change from input pins to output pins.
60
To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.
[A: Prior to executing BCLR]
MOV. B #3F
MOV. B R0L
MOV. B R0L
,
,
,
R0L
@RAM0
@PCR3
The PCR3 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
[B: BCLR instruction executed]
BSET
#0
,
@RAM0
The BCLR instruction is executed designating the PCR3
work area (RAM0).
[C: After executing BCLR]
MOV. B @RAM0,
MOV. B R0L,
R0L
@PCR3
The work area (RAM0) value is written to PCR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
0
0
1
1
1
1
1
0
PDR3
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
61
Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers
that contain write-only bits.
Table 2-12 Registers with Shared Addresses
Register Name
Abbreviation
Address
Timer counter and timer load register C
TCC/TLC
H'FFB5
Port data register 1*
PDR1
H'FFD4
Port data register 2*
PDR2
H'FFD5
Port data register 3*
PDR3
H'FFD6
Port data register 4*
PDR4
H'FFD7
Port data register 5*
PDR5
H'FFD8
Port data register 6*
PDR6
H'FFD9
Port data register 7*
PDR7
H'FFDA
Port data register 8*
PDR8
H'FFDB
Port data register 9*
PDR9
H'FFDC
Port data register A*
PDRA
H'FFDD
Note:
*
Port data registers have the same addresses as input pins.
Table 2-13 Registers with Write-Only Bits
Register Name
Abbreviation
Address
Port control register 1
PCR1
H'FFE4
Port control register 2
PCR2
H'FFE5
Port control register 3
PCR3
H'FFE6
Port control register 4
PCR4
H'FFE7
Port control register 5
PCR5
H'FFE8
Port control register 6
PCR6
H'FFE9
Port control register 7
PCR7
H'FFEA
Port control register 8
PCR8
H'FFEB
Port control register 9
PCR9
H'FFEC
Port control register A
PCRA
H'FFED
Timer control register F
TCRF
H'FFB6
PWM control register
PWCR
H'FFD0
PWM data register U
PWDRU
H'FFD1
PWM data register L
PWDRL
H'FFD2
62
2.9.3
Notes on Use of the EEPMOV Instruction
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5 →
← R6
R5 + R4L →
← R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
R5 + R4L →
← R6
H'FFFF
Not allowed
← R6 + R4L
63
Section 3 Exception Handling
3.1
Overview
Exception handling is performed in the H8/3887 Series when a reset or interrupt occurs. Table 3-1
shows the priorities of these two types of exception handling.
Table 3-1
Exception Handling Types and Priorities
Priority
Exception Source
Time of Start of Exception Handling
High
Reset
Exception handling starts as soon as the reset state is cleared
Interrupt
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Low
3.2
Reset
3.2.1
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized.
3.2.2
Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
64
When system power is turned on or off, the RES pin should be held low.
Figure 3-1 shows the reset sequence starting from RES input.
Reset cleared
Program initial
instruction prefetch
Vector fetch Internal
processing
RES
ø
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3-1 Reset Sequence
3.2.3
Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
65
3.3
Interrupts
3.3.1
Overview
The interrupt sources include 13 external interrupts (IRQ4 to IRQ0, WKP7 to WKP0) and 24
internal interrupts from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their
priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with
the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQ4 to IRQ0 and WKP 7 to WKP0 can be set to either rising edge sensing or falling edge
sensing.
66
Table 3-2
Interrupt Sources and Their Priorities
Interrupt Source
RES
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
WKP 0
WKP 1
WKP 2
WKP 3
WKP 4
WKP 5
WKP 6
WKP 7
SCI1
Timer A
Asynchronous
counter
Timer C
Interrupt
Vector Number
Vector Address Priority
Reset
0
H'0000 to H'0001 High
IRQ0
4
H'0008 to H'0009
IRQ1
5
H'000A to H'000B
IRQ2
6
H'000C to H'000D
IRQ3
7
H'000E to H'000F
IRQ4
8
H'0010 to H'0011
WKP 0
9
H'0012 to H'0013
WKP 1
WKP 2
WKP 3
WKP 4
WKP 5
WKP 6
WKP 7
SCI1 transfer complete
10
H'0014 to H'0015
Timer A overflow
11
H'0016 to H'0017
Asynchronous counter
12
H'0018 to H'0019
overflow
Timer C overflow or
13
H'001A to H'001B
underflow
Timer FL
Timer FL compare match
14
H'001C to H'001D
Timer FL overflow
Timer FH
Timer FH compare match
15
H'001E to H'001F
Timer FH overflow
Timer G
Timer G input capture
16
H'0020 to H'0021
Timer G overflow
17
H'0022 to H'0023
SCI3-1
SCI3-1 transmit end
SCI3-1 transmit data empty
SCI3-1 receive data full
SCI3-1 overrrun error
SCI3-1 framing error
SCI3-1 parity error
18
H'0024 to H'0025
SCI3-2
SCI3-2 transmit end
SCI3-2 transmit data empty
SCI3-2 receive data full
SCI3-2 overrun error
SCI3-2 framing error
SCI3-2 parity error
A/D
A/D conversion end
19
H'0026 to H'0027
(SLEEP instruction Direct transfer
20
H'0028 to H'0029 Low
executed)
Note: Vector addresses H'0002 to H'0007 and H'0014 to H'0015 are reserved and cannot be
used.
67
3.3.2
Interrupt Control Registers
Table 3-3 lists the registers that control interrupts.
Table 3-3
Interrupt Control Registers
Name
Abbreviation
R/W
Initial Value
Address
IRQ edge select register
IEGR
R/W
H'E0
H'FFF2
Interrupt enable register 1
IENR1
R/W
H'00
H'FFF3
Interrupt enable register 2
IENR2
R/W
H'00
H'FFF4
Interrupt request register 1
IRR1
R/W*
H'20
H'FFF6
Interrupt request register 2
IRR2
R/W*
H'00
H'FFF7
Wakeup interrupt request register
IWPR
R/W*
H'00
H'FFF9
Wakeup edge select register
WEGR
R/W
H'00
H'FF90
Note:
*
Write is enabled only for writing of 0 to clear a flag.
1. IRQ edge select register (IEGR)
Bit
7
6
5
4
3
2
1
0
—
—
—
IEG4
IEG3
IEG2
IEG1
IEG0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ4 to IRQ0 are set to rising
edge sensing or falling edge sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Bit 4: IRQ4 edge select (IEG4)
Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin.
Bit 4
IEG4
Description
0
Falling edge of IRQ4 and ADTRG pin input is detected
1
Rising edge of IRQ4 and ADTRG pin input is detected
68
(initial value)
Bit 3: IRQ3 edge select (IEG3)
Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin.
Bit 3
IEG3
Description
0
Falling edge of IRQ3 and TMIF pin input is detected
1
Rising edge of IRQ3 and TMIF pin input is detected
(initial value)
Bit 2: IRQ2 edge select (IEG2)
Bit 2 selects the input sensing of pin IRQ2.
Bit 2
IEG2
Description
0
Falling edge of IRQ2 pin input is detected
1
Rising edge of IRQ2 pin input is detected
(initial value)
Bit 1: IRQ1 edge select (IEG1)
Bit 3 selects the input sensing of the IRQ1 pin and TMIC pin.
Bit 1
IEG1
Description
0
Falling edge of IRQ1 and TMIC pin input is detected
1
Rising edge of IRQ1 and TMIC pin input is detected
(initial value)
Bit 0: IRQ0 edge select (IEG0)
Bit 0 selects the input sensing of pin IRQ0.
Bit 0
IEG0
Description
0
Falling edge of IRQ0 pin input is detected
1
Rising edge of IRQ0 pin input is detected
(initial value)
69
2. Interrupt enable register 1 (IENR1)
Bit
7
6
5
4
3
2
1
0
IENTA
IENS1
IENWP
IEN4
IEN3
IEN2
IEN1
IEN0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
Disables timer A interrupt requests
1
Enables timer A interrupt requests
(initial value)
Bit 6: SCI1 interrupt enable (IENS1)
Bit 6 enables or disables SCI1 transfer complete interrupt requests.
Bit 6
IENS1
Description
0
Disables SCI1 interrupt requests
1
Enables SCI1 interrupt requests
(initial value)
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5
IENWP
Description
0
Disables WKP 7 to WKP 0 interrupt requests
1
Enables WKP 7 to WKP 0 interrupt requests
70
(initial value)
Bits 4 to 0: IRQ4 to IRQ0 interrupt enable (IEN4 to IEN0)
Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 4 to 0)
3. Interrupt enable register 2 (IENR2)
Bit
7
6
5
4
IENDT
IENAD
—
IENTG
Initial value
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
3
1
0
IENTC
IENEC
0
0
0
R/W
R/W
R/W
2
IENTFH IENTFL
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
Disables direct transfer interrupt requests
1
Enables direct transfer interrupt requests
(initial value)
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
Disables A/D converter interrupt requests
1
Enables A/D converter interrupt requests
(initial value)
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
71
Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0
Disables timer G interrupt requests
1
Enables timer G interrupt requests
(initial value)
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
Disables timer FH interrupt requests
1
Enables timer FH interrupt requests
(initial value)
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
Disables timer FL interrupt requests
1
Enables timer FL interrupt requests
(initial value)
Bit 1: Timer C interrupt enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0
Disables timer C interrupt requests
1
Enables timer C interrupt requests
72
(initial value)
Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
Disables asynchronous event counter interrupt requests
1
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in
section 10.4.2.
4. Interrupt request register 1 (IRR1)
Bit
7
6
5
4
3
2
1
0
IRRTA
IRRS1
—
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ 4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
(initial value)
Bit 6: SCI1 interrupt request flag (IRRS1)
Bit 6
IRRS1
Description
0
Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
1
Setting conditions:
When SCI1 completes transfer
(initial value)
73
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 to 0: IRQ4 to IRQ0 interrupt request flags (IRRI4 to IRRI0)
Bit n
IRRIn
Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin IRQn is designated for interrupt input and the designated
signal edge is input
(n = 4 to 0)
5. Interrupt request register 2 (IRR2)
Bit
7
6
5
4
IRRDT
IRRAD
—
IRRTG
Initial value
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
3
1
0
IRRTC
IRREC
0
0
0
R/(W)*
R/(W)*
R/(W)*
2
IRRTFH IRRTFL
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The
flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear
each flag.
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction
while DTON = 1 in SYSCR2
74
(initial value)
Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
1
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
(initial value)
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4: Timer G interrupt request flag (IRRTG)
Bit 4
IRRTG
Description
0
Clearing conditions:
When IRRTG = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3: Timer FH interrupt request flag (IRRTFH)
Bit 3
IRRTFH
Description
0
Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Bit 2: Timer FL interrupt request flag (IRRTFL)
Bit 2
IRRTFL
Description
0
Clearing conditions:
When IRRTFL= 1, it is cleared by writing 0
1
Setting conditions:
When TCFL and OCRFL match in 8-bit timer mode
(initial value)
75
Bit 1: Timer C interrupt request flag (IRRTC)
Bit 1
IRRTC
Description
0
Clearing conditions:
When IRRTC= 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When the timer C counter value overflows (from H'FF to H'00) or underflows
(from H'00 to H'FF)
Bit 0: Asynchronous event counter interrupt request flag (IRREC)
Bit 0
IRREC
Description
0
Clearing conditions:
When IRREC = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
6. Wakeup Interrupt Request Register (IWPR)
Bit
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note:
*
All bits can only be written with 0, for flag clearing.
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
76
Bits 7 to 0: Wakeup interrupt request flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0
Clearing conditions:
When IWPFn= 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin WKP n is designated for wakeup input and a rising or falling edge is input at
that pin
(n = 7 to 0)
7. Wakeup Edge Select Register (WEGR)
Bit
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n: WKPn edge select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
Description
0
WKPn pin falling edge detected
1
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
77
3.3.3
External Interrupts
There are 13 external interrupts: IRQ 4 to IRQ0 and WKP 7 to WKP0.
1. Interrupts WKP 7 to WKP0
Interrupts WKP 7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to
WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP 7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
2. Interrupts IRQ4 to IRQ0
Interrupts IRQ4 to IRQ 0 are requested by input signals to pins IRQ4 to IRQ0. These interrupts are
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG 4 to IEG0 in IEGR.
When these pins are designated as pins IRQ4 to IRQ0 in port mode register 3 and 1 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN0
to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ 4 to IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 8 to 4 are assigned to interrupts IRQ4 to IRQ0. The order of priority is from IRQ0 (high)
to IRQ4 (low). Table 3-2 gives details.
3.3.4
Internal Interrupts
There are 24 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 10
are assigned to these interrupts. Table 3-2 shows the order of priority of interrupts from on-chip
peripheral modules.
78
3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the
interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance.
Priority decision logic
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3-2 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to table 3-2
for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
79
• If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes:
1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits
in an interrupt request register, always do so while interrupts are masked (I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises between
the clear instruction and an interrupt request, exception processing for the interrupt will be
executed after the clear instruction has been executed.
80
Program execution state
IRRI0 = 1
No
Yes
IEN0 = 1
No
Yes
IRRI1 = 1
No
Yes
IEN1 = 1
Yes
No
IRRI2 = 1
No
Yes
IEN2 = 1
No
Yes
IRRDT = 1
No
Yes
IENDT = 1
No
Yes
No
I=0
Yes
PC contents saved
CCR contents saved
I←1
Branch to interrupt
handling routine
Notation:
PC: Program counter
CCR: Condition code register
I:
I bit of CCR
Figure 3-3 Flow up to Interrupt Acceptance
81
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR *
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP + 4
SP (R7)
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
Notation:
PCH: Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
PCL:
CCR: Condition code register
Stack pointer
SP:
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return.
Figure 3-4 Stack State after Completion of Interrupt Exception Handling
Figure 3-5 shows a typical interrupt sequence.
82
Figure 3-5 Interrupt Sequence
83
Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
ø
Interrupt
request signal
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(2)
(1)
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
3.3.6
Interrupt Response Time
Table 3-4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3-4
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 13
15 to 27
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
84
*
Not including EEPMOV instruction.
3.4
Application Notes
3.4.1
Notes on Stack Area Use
When word data is accessed in the H8/3887 Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-6.
SP →
SP →
PCH
PC L
R1L
PC L
SP →
H'FEFC
H'FEFD
H'FEFF
BSR instruction
SP set to H'FEFF
MOV. B R1L, @–R7
Stack accessed beyond SP
Contents of PCH are lost
Notation:
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3-6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
85
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ4 to IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at the time
the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the
interrupt request flag to 0 after switching pin functions. Table 3-5 shows the conditions under
which interrupt request flags are set to 1 in this way.
Table 3-5
Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1
IWPR
86
Conditions
IRRI4
When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR
bit IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR
bit IEG4 = 1.
IRRI3
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR
bit IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR
bit IEG3 = 1.
IRRI2
When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR
bit IEG2 = 0.
When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR
bit IEG2 = 1.
IRRI1
When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR
bit IEG1 = 0.
When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR
bit IEG1 = 1.
IRRI0
When PMR3 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR
bit IEG0 = 0.
When PMR3 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR
bit IEG0 = 1.
IWPF7
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP 7 is low.
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP 6 is low.
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP 5 is low.
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP 4 is low.
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP 3 is low.
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP 2 is low.
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP 1 is low.
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP 0 is low.
Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit
Execute NOP instruction
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3-7 Port Mode Register Setting and Interrupt Request Flag
Clearing Procedure
87
Section 4 Clock Pulse Generators
4.1
Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1
Block Diagram
Figure 4-1 shows a block diagram of the clock pulse generators.
OSC 1
OSC 2
System clock
oscillator
øOSC
(f OSC)
øOSC/2
System clock
divider (1/2)
System
clock
divider
øOSC/128
øOSC/64
øOSC/32
øOSC/16
ø
Prescaler S
(13 bits)
System clock pulse generator
X1
X2
Subclock
oscillator
øW
(f W )
Subclock
divider
(1/2, 1/4, 1/8)
Subclock pulse generator
øW /2
øW /4
øW /8
ø/2
to
ø/8192
øW
øSUB
Prescaler W
(5 bits)
øW /2
øW /4
øW /8
to
øW /128
Figure 4-1 Block Diagram of Clock Pulse Generators
4.1.2
System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and øSUB. Four of
the clock signals have names: ø is the system clock, ø SUB is the subclock, øOSC is the oscillator
clock, and ø W is the watch clock.
The clock signals available for use by peripheral modules are ø/2, ø/4, ø/8, ø/16, ø/32, ø/64, ø/128,
ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, ø W , øW /2, øW /4, øW /8, øW /16, øW /32, øW /64, and
øW /128. The clock requirements differ from one module to another.
88
4.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
1. Connecting a crystal oscillator
Figure 4-2 shows a typical method of connecting a crystal oscillator.
C1
R f = 1 MΩ ±20%
OSC 1
Oscillation
frequency Manufacturer
Rf
OSC 2
C2
Recommended value
for C1 and C2
1.0 MHz
Nihon Denpa Kogyo 27 pF ±10%
4.19 MHz
Nihon Denpa Kogyo 12 pF ±20%
Figure 4-2 Typical Connection to Crystal Oscillator
Figure 4-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4-1 should be used.
CS
LS
RS
OSC 1
OSC 2
C0
Figure 4-3 Equivalent Circuit of Crystal Oscillator
Table 4-1
Crystal Oscillator Parameters
Frequency
1 MHz
4.193 MHz
RS (max)
40 Ω
100 Ω
C0 (max)
3.5 pF
16 pF
89
2. Connecting a ceramic oscillator
Figure 4-4 shows a typical method of connecting a ceramic oscillator.
C1
OSC 1
Rf
OSC 2
C2
R f = 1 MΩ ±20%
Oscillation
frequency Manufacturer
Recommended value
for C1 and C2
1.0 MHz
Murata Seisakusho
150 pF ±10%
4.0 MHz
Murata Seisakusho
30 pF ±10%
Figure 4-4 Typical Connection to Ceramic Oscillator
3. Notes on board design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4-5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
To be avoided
Signal A Signal B
C1
OSC 1
OSC 2
C2
Figure 4-5 Board Design of Oscillator Circuit
90
4. External clock input method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4-6 shows a
typical connection.
OSC 1
OSC 2
External clock input
Open
Figure 4-6 External Clock Input (Example)
Frequency
Oscillator Clock (øOSC)
Duty cycle
45% to 55%
91
4.3
Subclock Generator
1. Connecting a 32.768-kHz/38.4 kHz crystal oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz/38.4 kHz crystal
oscillator, as shown in figure 4-7. Follow the same precautions as noted under 3. notes on board
design for the system clock in 4.2.
C1
X1
X2
C1 = C 2 = 15 pF (typ.)
C2
Figure 4-7 Typical Connection to 32.768-kHz/38.4 kHz Crystal Oscillator (Subclock)
Figure 4-8 shows the equivalent circuit of the 32.768-kHz/38.4 kHz crystal oscillator.
CS
LS
RS
X1
X2
C0
C0 = 1.5 pF typ
RS = 14 k Ω typ
f W = 32.768 kHz/38.4kHz
Figure 4-8 Equivalent Circuit of 32.768-kHz/38.4 kHz Crystal Oscillator
92
2. Pin connection when not using subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure
4-9.
X1
GND
X2
Open
Figure 4-9 Pin Connection when not Using Subclock
3. External clock input
Connect the external clock to the X 1 pin and leave the X2 pin open, as shown in figure 4-10.
X1
X2
External clock input
Open
Figure 4-10 Pin Connection when Inputting External Clock
Frequency
Subclock (øw)
Duty
45% to 55%
93
4.4
Prescalers
The H8/3887 Series is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768-kHz or 38.4 kHz signal divided by 4 (øW/4) as its
input clock. Its prescaled outputs are used by timer A as a time base for timekeeping.
1. Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI1, SCI3-1, SC3-2,
the A/D converter, the LCD controller, the watchdog timer, and the 14-bit PWM. The divider
ratio can be set separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is øosc/16, øosc/32, øosc/64, or
øosc/128.
2. Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (øW /4) as its input
clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
94
4.5
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user in mask ROM and ZTAT™ versions, referring to the examples shown in this section.
Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its
interconnecting circuit, and other factors. Suitable constants should be determined in consultation
with the oscillator element manufacturer. Design the circuit so that the oscillator element never
receives voltages exceeding its maximum rating.
95
Section 5 Power-Down Modes
5.1
Overview
The H8/3887 Series has nine modes of operation after a reset. These include eight power-down
modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the
eight operating modes.
Table 5-1
Operating Modes
Operating Mode
Description
Active (high-speed) mode
The CPU and all on-chip peripheral functions are operable on the
system clock in high-speed operation
Active (medium-speed) mode
The CPU and all on-chip peripheral functions are operable on the
system clock in low-speed operation
Subactive mode
The CPU is operable on the subclock in low-speed operation
Sleep (high-speed) mode
The CPU halts. On-chip peripheral functions are operable on the
system clock
Sleep (medium-speed) mode
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency
Subsleep mode
The CPU halts. The time-base function of timer A, timer C, timer
G, timer F, WDT, SCI1, SCI3-1, SCI3-2, AEC and LCD
controller/driver are operable on the subclock.
Watch mode
The CPU halts. The time-base function of timer A, timer F, timer
G, AEC and LCD controller/driver are operable on the subclock.
Standby mode
The CPU and all on-chip peripheral functions halt
Module standby mode
Individual on-chip peripheral functions specified by software enter
standby mode and halt
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal
states in each mode.
96
Program
execution state
Reset state
SLEEP
instruction*a
Active
(high-speed)
mode
P *d
EE n
SL uctio
tr
ins
Program
halt state
Program
halt state
*a
SLEEP
instruction*f
SLEEP
instruction*g
*4
SL
instr EEP
uctio *d
n
*4
*1
*1
SLEEP
instruction*e
Watch
mode
*1
SLEEP
instruction*i
P *e
EE tion
L
S ruc
st
in
SLEEP
instruction*h
ins SLEE
tru
ctio P
n *e
Active
(medium-speed)
mode
Subactive
mode
P
EE tion
SL ruc
st
inin SL
st E
ru EP
ct
io
n *b
SLEEP
instruction*b
*3
Sleep
(medium-speed)
mode
ins SLEE
tru P
cti
on *j
S
ins LE
tru EP
ctio
n *i
Standby
mode
Sleep
(high-speed)
mode
*3
SLEEP
instruction*c
*2
Subsleep
mode
Power-down modes
Mode Transition Conditions (1)
Mode Transition Conditions (2)
LSON MSON SSBY TMA3 DTON
Interrupt Sources
a
b
0
0
0
1
0
0
✻
✻
0
0
1
c
d
e
1
0
✻
✻
✻
✻
0
1
1
1
0
1
0
0
0
2
Timer A, Timer F, Timer G interrupt, IRQ0 interrupt,
WKP7 to WKP0 interrupt
Timer A, Timer C, Timer F, Timer G, SCI1, SCI3-1,
SCI3-2 interrupt, IRQ4 to IRQ0 interrupts,
WKP7 to WKP0 interrupts, AEC
f
g
h
i
J
0
0
0
1
0
0
1
1
✻
0
0
0
1
1
1
✻
✻
1
1
1
1
1
1
1
1
3
All interrupts
4
IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts
✻ Don’t care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is performed after the interrupt is
accepted.
2. Details on the mode transition conditions are given in the explanations of each mode,
in sections 5-2 through 5-8.
Figure 5-1 Mode Transition Diagram
97
Table 5-2
Internal State in Each Operating Mode
Function
Active Mode
Sleep Mode
HighSpeed
HighSpeed
MediumSpeed
MediumSpeed
Watch
Mode
Subactive Subsleep
Mode
Mode
Standby
Mode
System clock oscillator
Functions
Functions
Functions
Functions
Halted
Halted
Halted
Halted
Subclock oscillator
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Instructions Functions
Functions
Halted
Halted
Halted
Functions
Halted
Halted
Retained
Retained
Retained
Retained
Retained
CPU
operations RAM
Registers
Retained* 1
I/O ports
External
IRQ0
interrupts
IRQ1
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Retained* 6
Retained* 6
IRQ2
IRQ3
IRQ4
WKP0
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions*5 Functions*5 Functions*5 Retained
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Peripheral Timer A
functions
Asynchronous counter
Functions*8 Functions
Timer C
Retained
WDT
Notes:
98
Functions
Functions*8
Functions/ Functions/ Retained
Retained* 2 Retained* 2
Functions/ Retained
Retained* 7
Timer G,
Timer F
Functions/ Functions/ Functions/
Retained* 9 Retained* 9 Retained* 9
SCI1
Retained
Functions/ Functions/ Retained
Retained* 9 Retained* 9
SCI3-1,
SCI3-2
Reset
Functions/ Functions/ Reset
Retained* 3 Retained* 3
PWM
Retained
Retained
Retained
Retained
A/D
converter
Retained
Retained
Retained
Retained
LCD
Functions/ Functions/ Functions/ Retained
Retained* 4 Retained* 4 Retained* 4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Register contents are retained, but output is high-impedance state.
Functions if an external clock or the øW/4 internal clock is selected; otherwise halted and retained.
Functions if øW /2 is selected as the internal clock; otherwise halted and retained.
Functions if øW or øW /2 or øW /4 is selected as the operating clock; otherwise halted and retained.
Functions if the timekeeping time-base function is selected.
External interrupt requests are ignored. Interrupt request register contents are not altered.
Functions if øW /32 is selected as the internal clock; otherwise halted and retained.
Incrementing is possible, but interrupt generation is not.
Functions if øW /4 is selected as the external or internal clock; otherwise halted and retained.
5.1.1
System Control Registers
The operation mode is selected using the system control registers described in table 5-3.
Table 5-3
System Control Registers
Name
Abbreviation
R/W
Initial Value
Address
System control register 1
SYSCR1
R/W
H'07
H'FFF0
System control register 2
SYSCR2
R/W
H'F0
H'FFF1
1. System control register 1 (SYSCR1)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7: Software standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0
•
When a SLEEP instruction is executed in active mode, a transition (initial value)
is made to sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode
•
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode
1
99
Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation settling time.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 32,768 states
0
1
1
Wait time = 65,536 states
1
0
0
Wait time = 131,072 states
1
0
1
Wait time = 2 states
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
(initial value)
(External clock input mode)
Note: When inputting the external clock, set the standby timer select to the external clock input
mode. Also, when not using the external clock, do not set the standby timer select to the
external clock input mode.
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (ø) or subclock (øSUB ) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
The CPU operates on the system clock (ø)
1
The CPU operates on the subclock (ø SUB)
Bits 2: Reserved bits
Bit 2 is reserved: it is always read as 1 and cannot be modified.
100
(initial value)
Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose øOSC /128, øOSC /64, øOSC /32, or ø OSC /16 as the operating clock in active
(medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in
active (high-speed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0
Description
0
0
øOSC/16
0
1
øOSC/32
1
0
øOSC/64
1
1
øOSC/128
(initial value)
2. System control register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (øW) generated by the subclock pulse
generator is sampled, in relation to the oscillator clock (øOSC) generated by the system clock pulse
generator. When ø OSC = 2 to 6 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0
Sampling rate is ø OSC/16
1
Sampling rate is ø OSC/4
(initial value)
101
Bit 3: Direct transfer on flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of this
and other control bits.
Bit 3
DTON
Description
0
•
When a SLEEP instruction is executed in active mode, a transition (initial value)
is made to standby mode, watch mode, or sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode
•
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON
= 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 1
1
Bit 2: Medium speed on flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Bit 2
MSON
Description
0
Operation in active (high-speed) mode
1
Operation in active (medium-speed) mode
102
(initial value)
Bits 1 and 0: Subactive mode clock select (SA1 and SA0)
These bits select the CPU clock rate (øW/2, øW /4, or ø W /8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0
Description
0
0
øW/8
0
1
øW/4
*
øW/2
1
Note:
*
(initial value)
Don’t care
103
5.2
Sleep Mode
5.2.1
Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON
bits in SYSCR2 are also cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
The CPU may operate at a 1/2 state faster timing at transition to sleep (medium-speed) mode.
5.2.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter,
IRQ4 to IRQ0, WKP7 to WKP0, SCI1, SCI3-1, SCI3-2, or A/D converter), or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A
transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the
condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
To synchronize the interrupt request signal with the system clock, up to 2/ø (s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
104
5.2.3
Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
105
5.3
Standby Mode
5.3.1
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2
Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP 7 to WKP0 or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in bits
STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip,
standby mode is cleared, and interrupt exception handling starts. Operation resumes in active
(high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1.
Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since
system clock signals are supplied to the entire chip as soon as the system clock pulse generator
starts functioning, the RES pin should be kept at the low level until the pulse generator output
stabilizes.
5.3.3
Oscillator Settling Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When a crystal oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time at least as long as the oscillation settling time.
106
Table 5-4
Clock Frequency and Settling Time (times are in ms)
STS2
STS1
STS0
Waiting Time
2 MHz
1 MHz
0.5 MHz
0
0
0
8,192 states
4.1
8.2
16.4
0
0
1
16,384 states
8.2
16.4
32.8
0
1
0
32,768 states
16.4
32.8
65.5
0
1
1
65,536 states
32.8
65.5
131.1
1
0
0
131,072 states
65.5
131.1
262.1
1
0
1
2 states (not available)
0.001
0.002
0.004
1
1
0
8 states
0.004
0.008
0.016
1
1
1
16 states
0.008
0.016
0.032
• When an external clock is used
STS2 = 1, STS1 = 0 and STS0 = 1 are recommended. Other values can be set, but with other
settings, operation may start before the standby time is over.
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5-2 shows
the timing in this case.
ø
Internal data bus
SLEEP instruction fetch
Fetch of next instruction
SLEEP instruction execution
Pins
Internal processing
Port output
Active (high-speed) mode or active (medium-speed) mode
High-impedance
Standby mode
Figure 5-2 Standby Mode Transition and Pin States
107
5.4
Watch Mode
5.4.1
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted.
As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip
RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same
states as before the transition.
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ 0, or WKP7 to WKP0) or by
input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on the
settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0,
transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active
(medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to
active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is
supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch
mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
5.4.3
Oscillator Settling Time after Watch Mode is Cleared
The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
108
5.5
Subsleep Mode
5.5.1
Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter, PWM and WDT is halted. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous
counter, SCI1, SCI3-2, SCI3-1, IRQ 4 to IRQ0, WKP7 to WKP0) or by a low input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
To synchronize the interrupt request signal with the subclock, up to 2/øSUB (s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
109
5.6
Subactive Mode
5.6.1
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to
WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous counter, SCI1,
SCI3-1, SCI3-2, IRQ4 to IRQ0, or WKP7 to WKP0 interrupt is requested. A transition to subactive
mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
5.6.2
Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is
executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is
entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are øW /2, øW /4, and øW /8.
110
5.7
Active (Medium-Speed) Mode
5.7.1
Transition to Active (Medium-Speed) Mode
If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2
is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed)
mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby mode, timer A, timer F,
timer G, IRQ0 or WKP 7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode. A
transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
The CPU may operate at a 1/2 state faster timing at transition to active (medium-speed) mode.
5.7.2
Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit
in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is
cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3
in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See 5.8, Direct Transfer, below for details.
• Clearing by RES pin
When the RES pin is driven low, a transition is made to the reset state and active (medium-speed)
mode is cleared.
5.7.3
Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
111
5.8
Direct Transfer
5.8.1
Overview of Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead
to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is
set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting
mode by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in
SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set
to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to
1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON
bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to
active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0
has elapsed.
112
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits
in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to
1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to
1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in
SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active
(medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0
has elapsed.
5.8.2
Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when ø/8 is selected as
the CPU operating clock)
Notation:
tosc: OSC clock cycle time
tcyc: System clock (ø) cycle time
113
2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (2)
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when ø/8 is selected as
the CPU operating clock)
Notation:
tosc: OSC clock cycle time
tcyc: System clock (ø) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
øw/8 is selected as the CPU operating clock, and wait time = 8192 states)
Notation:
tosc:
tw:
tcyc:
tsubcyc:
114
OSC clock cycle time
Watch clock cycle time
System clock (ø) cycle time
Subclock (øSUB) cycle time
4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
(when øw/8 or ø8 is selected as the CPU operating clock, and wait time = 8192 states)
Notation:
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (ø) cycle time
Subclock (øSUB) cycle time
115
5.9
Module Standby Mode
5.9.1
Setting Module Standby Mode
Module standby mode is set for individual peripheral functions. All the on-chip peripheral
modules can be placed in module standby mode. When a module enters module standby mode,
the system clock supply to the module is stopped and operation of the module halts. This state is
identical to standby mode.
Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock
stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5-5.)
5.9.2
Clearing Module Standby Mode
Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in
clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5-5.)
Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both
initialized to H'FF.
Table 5-5
Register Name
Bit Name
CKSTPR1
TACKSTP
TCCKSTP
TFCKSTP
TGCKSTP
ADCKSTP
S1CKSTP
S32CKSTP
S31CKSTP
116
Operation
1
Timer A module standby mode is cleared
0
Timer A is set to module standby mode
1
Timer C module standby mode is cleared
0
Timer C is set to module standby mode
1
Timer F module standby mode is cleared
0
Timer F is set to module standby mode
1
Timer G module standby mode is cleared
0
Timer G is set to module standby mode
1
A/D converter module standby mode is cleared
0
A/D converter is set to module standby mode
1
SCI1 module standby mode is cleared
0
SCI1 is set to module standby mode
1
SCI3-2 module standby mode is cleared
0
SCI3-2 is set to module standby mode
1
SCI3-1 module standby mode is cleared
0
SCI3-1 is set to module standby mode
Table 5-5 (cont)
Register Name
Bit Name
CKSTPR2
LDCKSTP
PWCKSTP
WDCKSTP
AECKSTP
Operation
1
LCD module standby mode is cleared
0
LCD is set to module standby mode
1
PWM module standby mode is cleared
0
PWM is set to module standby mode
1
Watchdog timer module standby mode is cleared
0
Watchdog timer is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
0
Asynchronous event counter is set to module standby mode
Note: For details of module operation, see the sections on the individual modules.
117
Section 6 ROM
6.1
Overview
The H8/3882 and H8/3842 have 16 kbytes of mask ROM, the H8/3883 and H8/3843 have 24
kbytes of mask ROM, the H8/3884 and H8/3844 have 32 kbytes of mask ROM, the H8/3885 and
H8/3845 have 40 kbytes of mask ROM, the H8/3886 and H8/3846 have 48 kbytes of mask ROM,
and the H8/3887 and H8/3847 have 60 kbytes of mask ROM on-chip. The ROM is connected to
the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word
data. The H8/3887 and H8/3847 have a ZTAT™ version with 60-kbyte PROM.
6.1.1
Block Diagram
Figure 6-1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0000
H'0001
H'0002
H'0002
H'0003
On-chip ROM
H'7FFE
H'7FFE
H'7FFF
Even-numbered
address
Odd-numbered
address
Figure 6-1 ROM Block Diagram (H8/3884 and H8/3844)
118
6.2
PROM Mode (H8/3887, H8/3847)
6.2.1
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C101 EPROM. However, page programming is not supported. Table 6-1 shows how to set
the chip to PROM mode.
Table 6-1
Setting to PROM Mode
Pin Name
Setting
TEST
High level
PB4/AN4
Low level
PB5/AN5
PB6/AN6
6.2.2
High level
Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 32 pins, as listed in table 6-2.
Figure 6-2 shows the pin-to-pin wiring of the socket adapter. Figure 6-3 shows a memory map.
Table 6-2
Socket Adapter
Package
Socket Adapter Model (Manufacturer)
100-pin (FP-100B)
ME3887ESHS1H (MINATO)
H7388BQ100D3201 (DATA-I/O)
100-pin (FP-100A)
ME3887ESFS1H (MINATO)
H7388AQ100D3201 (DATA-I/O)
100-pin (TFP-100B)
ME3887ESNS1H (MINATO)
H7388BT100D3201 (DATA-I/O)
100-pin (TFP-100G)
Underdevelopement
119
H8/3887, H8/3847
EPROM socket
HN27C101
(32-pin)
FP-100B,
TFP-100B
FP-100A
Pin
Pin
15
18
RES
VPP
1
51
54
P60
EO0
13
52
55
P61
EO1
14
53
56
P62
EO2
15
54
57
P63
EO3
17
55
58
P64
EO4
18
56
59
P65
EO5
19
57
60
P66
EO6
20
58
61
P67
EO7
21
74
77
P87
EA0
12
73
76
P86
EA1
11
72
75
P85
EA2
10
71
74
P84
EA3
9
70
73
P83
EA4
8
69
72
P82
EA5
7
68
71
P81
EA6
6
67
70
P80
EA7
5
59
62
P70
EA8
27
86
89
P43
EA9
26
61
64
P72
EA10
23
62
65
P73
EA11
25
63
66
P74
EA12
4
64
67
P75
EA13
28
65
68
P76
EA14
29
5
8
P14
EA15
3
6
9
P15
EA16
66
69
P77
CE
22
60
63
P71
OE
24
4
7
P13
PGM
31
38, 32
41, 35
VCC, CVCC
VCC
32
87
90
AVCC
14
17
TEST
9
12
X1
94
97
PB6
2
5
P11
3
6
P12
7
10
P16
11, 33
14, 36
VSS
VSS
16
100
3
AVSS
92
95
PB4
93
96
PB5
Note: Pins not indicated in the figure should be left open.
Figure 6-2 Socket Adapter Pin Correspondence (with HN27C101)
120
2
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'EDFF
H'EDFF
Uninstalled area*
H'1FFFF
Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore,
when programming with a PROM programmer, be sure to specify addresses from H'0000
to H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be
possible to continue PROM programming and verification.
When programming, H'FF should be set as the data in this address area (H'EE00 to
H'1FFFF).
Figure 6-3 H8/3887, H8/3847 Memory Map in PROM Mode
121
6.3
Programming (H8/3887, H8/3847)
The write, verify, and other modes are selected as shown in table 6-3 in PROM mode. (H8/3887,
H8/3847)
Table 6-3
Mode Selection in PROM Mode (H8/3887, H8/3847)
Pins
Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA 16 to EA0
Write
L
H
L
VPP
VCC
Data input
Address input
Verify
L
L
H
VPP
VCC
Data output
Address input
Programming
L
L
L
VPP
VCC
High impedanc e
Address input
disabled
L
H
H
H
L
L
H
H
H
Notation:
L:
Low level
H:
High level
VPP level
VPP :
VCC:
VCC level
The specifications for writing and reading are identical to those for the standard HN27C101
EPROM. However, page programming is not supported, and so page programming mode must not
be set. A PROM programmer that only supports page programming mode cannot be used. When
selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte
programming. Also, be sure to specify addresses from H'0000 to H'EDFF.
6.3.1
Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. The basic flow of this high-speed, high-reliability programming
method is shown in figure 6-4.
122
Start
Set write/verify mode
VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n=0
n+1 →n
No
Yes
n < 25
Write time t PW = 0.2 ms ± 5%
No Go
Address + 1 → address
Verify
Go
Write time t OPW = 3n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V ± 0.25 V, V PP = VCC
No Go
Error
Read all
addresses?
Go
End
Figure 6-4 High-Speed, High-Reliability Programming Flow Chart
123
Table 6-4 and table 6-5 give the electrical characteristics in programming mode.
Table 6-4
DC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Min
Typ
Max
Input highEO7 to EO 0, EA16 to EA 0 VIH
level voltage OE, CE, PGM
2.4
—
VCC + 0.3 V
Input lowEO7 to EO 0, EA16 to EA 0 VIL
level voltage OE, CE, PGM
–0.3
—
0.8
V
Output high- EO7 to EO 0
level voltage
VOH
2.4
—
—
V
I OH = –200 µA
Output low
EO7 to EO 0
level voltage
VOL
—
—
0.45
V
I OL = 0.8 mA
Input leakage EO7 to EO 0, EA16 to EA 0 |ILI|
current
OE, CE, PGM
—
—
2
µA
Vin = 5.25 V/0.5 V
VCC current
I CC
—
—
40
mA
VPP current
I PP
—
—
40
mA
124
Symbol
Unit
Test Condi ti on
Table 6-5
AC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Unit Test Condition
Address setup time
t AS
2
—
—
µs
OE setup time
t OES
2
—
—
µs
Data setup time
t DS
2
—
—
µs
Address hold time
t AH
0
—
—
µs
Data hold time
t DH
2
—
—
µs
—
—
130
µs
2
—
—
µs
0.19
0.20
0.21
ms
0.19
—
5.25
ms
Data output disable time
t DF *
VPP setup time
t VPS
Programming pulse width
t PW
2
PGM pulse width for overwrite programming
t OPW*
CE setup time
t CES
2
—
—
µs
VCC setup time
t VCS
2
—
—
µs
Data output delay time
t OE
0
—
200
ns
3
Figure 6-5* 1
Notes: 1. Input pulse level: 0.45 V to 2.2 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 0.8 V, 2.0 V
Output: 0.8 V, 2.0 V
2. t DF is defined at the point at which the output is floating and the output level cannot be
read.
3. t OPW is defined by the value given in figure 6-4, High-Speed, High-Reliability
Programming Flow Chart.
125
Figure 6-5 shows a PROM write/verify timing diagram.
Write
Verify
Address
tAS
Data
tAH
Input data
tDS
VPP
tDH
tDF
VPP
VCC
VCC
Output data
tVPS
VCC+1
VCC
tVCS
CE
tCES
PGM
tPW
tOES
tOE
OE
tOPW*
Note: * topw is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6-5 PROM Write/Verify Timing
126
6.3.2
Programming Precautions
• Use the specified programming voltage and timing.
• The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in
correct VPP of 12.5 V.
• Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
• Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
• Take care when setting the programming mode, as page programming is not supported.
• When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be
possible to continue PROM programming and verification. When programming, H'FF should
be set as the data in address area H'EE00 to H'1FFFF.
127
6.4
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 6-6 Shows the recommended screening procedure.
Program chip and verify
programmed data
Bake chip for 24 to 48 hours at
125°C to 150°C with power off
Read and check program
Install
Figure 6-6 Recommended Screening Procedure
If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects. Please inform
Hitachi of any abnormal conditions noted during or after programming or in screening of program
data after high-temperature baking.
128
Section 7 RAM
7.1
Overview
The H8/3882, H8/3883, H8/3842 and H8/3843 have 1 kbytes of high-speed static RAM, and
H8/3884, H8/3885, H8/3886, H8/3887, H8/3844, H8/3845, H8/3846 and H8/3847 have 2 kbytes
of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus,
allowing high-speed 2-state access for both byte data and word data.
7.1.1 Block Diagram
Figure 7-1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'F780
H'F780
H'F781
H'F782
H'F782
H'F783
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even-numbered
address
Odd-numbered
address
Figure 7-1 RAM Block Diagram (H8/3884, H8/3844)
129
Section 8 I/O Ports
8.1
Overview
The H8/3887 Series is provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port,
one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. Table 8-1
indicates the functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions
to write data in PCR or PDR.
Ports 5, 6, 7, 8, 9, and A are also used as liquid crystal display segment and common pins,
selectable in 8-bit units.
Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams
Table 8-1
Port
Port Functions
Description
Port 1 •
•
Port 2 •
•
•
Pins
8-bit I/O port
P17 to P1 5/IRQ3 to External interrupts 3 to 1
MOS input pull-up option IRQ1/TMIF, TMIC Timer event interrupts
TMIF, TMIC
PMR1
TCRF,
TMC
P14/IRQ4/ADTRG External interrupt 4 and A/D
converter external trigger
PMR1,
AMR
P13/TMIG
Timer G input capture input
PMR1
P12, P11/
TMOFH, TMOFL
Timer F output compare output PMR1
P10/TMOW
Timer A clock output
PMR1
SCI1 data output (SO1), data
input (SI 1), clock input/output
(SCK1)
PMR2
P20/SCK1
8-bit I/O port
Open-drain output option P21/SI1
P22/SO 1
Large-current port
P27 to P2 3
130
Other Functions
Function
Switching
Registers
None
Table 8-1
Port
Port Functions (cont)
Description
Port 3 •
•
•
Port 4 •
•
Pins
Other Functions
Function
Switching
Registers
P37/AEVL
8-bit I/O port
MOS input pull-up option P36/AEVH
P35/TXD31
Large-current port
P34/RXD31
P33/SCK31
SCI3-1 data output (TXD31 ),
data input (RXD31 ), clock
input/output (SCK31 ), and
asynchronous counter event
inputs AEVL, AEVH
PMR3
SCR31
SMR31
P32/RESO
P31/UD
P30/PWM
Reset output, timer C countup/down select input, and
14-bit PWM output
PMR3
1-bit input port
P43/IRQ0
External interrupt 0
PMR3
3-bit I/O port
P42/TXD32
P41/RXD32
P40/SCK32
SCI3-2 data output (TXD32 ),
data input (RXD32 ), clock
input/output (SCK32 )
SCR32
SMR32
Port 5 •
•
8-bit I/O port
P57 to P5 0/
MOS input pull-up option WKP 7 to WKP 0/
SEG8 to SEG 1
Wakeup input (WKP 7 to
PMR5
WKP 0), segment output (SEG 8 LPCR
to SEG1)
Port 6 •
•
8-bit I/O port
P67 to P6 0/
MOS input pull-up option SEG16 to SEG 9
Segment output (SEG16 to
SEG9)
LPCR
Port 7 •
8-bit I/O port
P77 to P7 0/
SEG24 to SEG 17
Segment output (SEG24 to
SEG17 )
LPCR
Port 8 •
8-bit I/O port
P87 to P8 0/
SEG32 to SEG 25
Segment output (SEG32 to
SEG25 )
LPCR
Port 9 •
8-bit I/O port
P97/SEG 40 /CL1
P96/SEG 39 /CL2
P95/SEG 38 /DO
P94/SEG 37 /M
P93 to P9 0/
SEG36 to SEG 33
•
Port A •
4-bit I/O port
PA3 to PA 0/
COM4 to COM1
Port B •
8-bit input port
PB7 to PB 0/
AN 7 to AN0
A/D converter analog input
AMR
Port C •
4-bit input port
PC 3 to PC0/
AN 11 to AN8
A/D converter analog input
AMR
Segment output (SEG40 to LPCR
SEG37 )
• Latch clock (CL1), shift
clock (CL2), display data
(DO) and alternating signal
(M) for external expansion
of segment
• Segment output (SEG36 to
SEG33 )
Common output (COM4 to
LPCR
COM1)
131
8.2
Port 1
8.2.1
Overview
Port 1 is an 8-bit I/O port. Figure 8-1 shows its pin configuration.
P1 7 /IRQ 3 /TMIF
P1 6 /IRQ 2
P1 5 /IRQ 1 /TMIC
P1 4 /IRQ 4 /ADTRG
Port 1
P1 3 /TMIG
P1 2 /TMOFH
P1 1 /TMOFL
P1 0 /TMOW
Figure 8-1 Port 1 Pin Configuration
8.2.2
Register Configuration and Description
Table 8-2 shows the port 1 register configuration.
Table 8-2
Port 1 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 1
PDR1
R/W
H'00
H'FFD4
Port control register 1
PCR1
W
H'00
H'FFE4
Port pull-up control register 1
PUCR1
R/W
H'00
H'FFE0
Port mode register 1
PMR1
R/W
H'00
H'FFC8
132
1. Port data register 1 (PDR1)
Bit
7
6
5
4
3
2
1
0
P1 7
P1 6
P1 5
P1 4
P1 3
P1 2
P1 1
P1 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR1 is an 8-bit register that stores data for port 1 pins P17 to P10. If port 1 is read while PCR1
bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is
read while PCR1 bits are cleared to 0, the pin states are read.
Upon reset, PDR1 is initialized to H'00.
2. Port control register 1 (PCR1)
Bit
7
6
5
4
3
2
1
0
PCR17
PCR16
PCR15
PCR14
PCR13
PCR12
PCR11
PCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 to P10 functions as an
input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only
when the corresponding pin is designated in PMR1 as a general I/O pin.
Upon reset, PCR1 is initialized to H'00.
PCR1 is a write-only register, which is always read as all 1s.
3. Port pull-up control register 1 (PUCR1)
Bit
7
6
5
4
3
2
1
0
PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 to P10 is on or off. When
a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR1 is initialized to H'00.
133
4. Port mode register 1 (PMR1)
Bit
7
6
5
4
3
2
1
0
IRQ3
IRQ2
IRQ1
IRQ4
TMIG
TMOFH
TMOFL
TMOW
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Upon reset, PMR1 is initialized to H'00.
Bit 7: P17/IRQ3/TMIF pin function switch (IRQ3)
This bit selects whether pin P17/IRQ3/TMIF is used as P1 7 or as IRQ3/TMIF.
Bit 7
IRQ3
Description
0
Functions as P1 7 I/O pin
1
Functions as IRQ3/TMIF input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ3/TMIF. For details on TMIF
settings, see 3. Timer Control Register F (TCRF) in 9.4.2.
Bit 6: P16/IRQ2 pin function switch (IRQ2)
This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2.
Bit 6
IRQ2
Description
0
Functions as P1 6 I/O pin
1
Functions as IRQ2 input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ2.
Bit 5: P15/IRQ1/TMIC pin function switch (IRQ1)
This bit selects whether pin P15/IRQ1/TMIC is used as P15 or as IRQ1/TMIC.
Bit 5
IRQ1
Description
0
Functions as P1 5 I/O pin
1
Functions as IRQ1/TMIC input pin
Note: Rising or falling edge sensing can be designated for IRQ1/TMIC.
For details of TMIC pin setting, see 1. Timer mode register C (TMC) in 9.3.2.
134
(initial value)
Bit 4: P14/IRQ4/ADTRG pin function switch (IRQ4)
This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG.
Bit 4
IRQ4
Description
0
Functions as P1 4 I/O pin
1
Functions as IRQ4/ADTRG input pin
(initial value)
Note: For details of ADTRG pin setting, see 12.3.2, Start of A/D Conversion by External Trigger.
Bit 3: P13/TMIG pin function switch (TMIG)
This bit selects whether pin P13/TMIG is used as P13 or as TMIG.
Bit 3
TMIG
Description
0
Functions as P1 3 I/O pin
1
Functions as TMIG input pin
(initial value)
Bit 2: P12/TMOFH pin function switch (TMOFH)
This bit selects whether pin P12/TMOFH is used as P12 or as TMOFH.
Bit 2
TMOFH
Description
0
Functions as P1 2 I/O pin
1
Functions as TMOFH output pin
(initial value)
Bit 1: P11/TMOFL pin function switch (TMOFL)
This bit selects whether pin P11/TMOFL is used as P1 1 or as TMOFL.
Bit 1
TMOFL
Description
0
Functions as P1 1 I/O pin
1
Functions as TMOFL output pin
(initial value)
135
Bit 0: P10/TMOW pin function switch (TMOW)
This bit selects whether pin P10/TMOW is used as P10 or as TMOW.
Bit 0
TMOW
Description
0
Functions as P1 0 I/O pin
1
Functions as TMOW output pin
136
(initial value)
8.2.3
Pin Functions
Table 8-3 shows the port 1 pin functions.
Table 8-3
Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/IRQ3/TMIF
The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF,
and bit PCR1 7 in PCR1.
IRQ3
PCR17
CKSL2 to CKSL0
Pin function
0
0
1
*
P17 input pin
1
*
Not 0**
P17 output pin IRQ3 input pin
0**
IRQ3/TMIF
input pin
Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1
to disable the IRQ3 interrupt.
P16/IRQ2
The pin function depends on bits IRQ2 in PMR1 and bit PCR1 6 in PCR1.
IRQ2
PCR16
Pin function
P15/IRQ1
TMIC
0
0
P16 input pin
1
P16 output pin
1
*
IRQ2 input pin
The pin function depends on bit IRQ1 in PMR1, bits TMC2 to TMC0 in TMC, and
bit PCR15 in PCR1.
IRQ1
PCR15
TMC2 to TMC0
Pin function
0
0
1
*
P15 input pin
1
*
Not 111
P15 output pin IRQ1 input pin
111
IRQ1/TMIC
input pin
Note: When this pin is used as the TMIC input pin, clear bit IEN1 to 0 in IENR1
to disable the IRQ1 interrupt.
P14/IRQ4
ADTRG
The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR1 4
in PCR1.
IRQ4
PCR14
TRGE
Pin function
0
0
1
*
P14 input pin
1
*
0
P14 output pin IRQ4 input pin
1
I RQ4/ ADTRG
input pin
Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in
IENR1 to disable the IRQ4 interrupt.
137
Table 8-3
Port 1 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P13/TMIG
The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1.
TMIG
PCR13
Pin function
P12/TMOFH
1
*
TMIG input pin
0
0
P12 input pin
1
P12 output pin
1
*
TMOFH output pin
The pin function depends on bit TMOFL in PMR1 and bit PCR1 1 in PCR1.
TMOFL
PCR11
Pin function
P10/TMOW
1
P13 output pin
The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1.
TMOFH
PCR12
Pin function
P11/TMOFL
0
0
P13 input pin
0
0
P11 input pin
1
P11 output pin
1
*
TMOFL output pin
The pin function depends on bit TMOW in PMR1 and bit PCR1 0 in PCR1.
TMOW
PCR10
Pin function
0
0
P10 input pin
1
P10 output pin
1
*
TMOW output pin
*: Don’t care
138
8.2.4
Pin States
Table 8-4 shows the port 1 pin states in each operating mode.
Table 8-4
Port 1 Pin States
Pins
Reset
P17/IRQ3/TMIF
P16/IRQ2
P15/IRQ1/TMIC
P14/IRQ4/ADTRG
P13/TMIG
P12/TMOFH
P11/TMOFL
P10/TMOW
HighRetains
impedance previous
state
Note:
*
8.2.5
Sleep
Subsleep
Standby
Watch
Retains
previous
state
HighRetains
impedance* previous
state
Subactive
Active
Functional
Functional
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up
for that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n
0
0
1
PUCR1n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
139
8.3
Port 2
8.3.1
Overview
Port 2 is an 8-bit I/O port. Figure 8-2 shows its pin configuration.
P27
P26
P25
P24
Port 2
P23
P22/SO1
P21/SI1
P20/SCK1
Figure 8-2 Port 2 Pin Configuration
8.3.2
Register Configuration and Description
Table 8-5 shows the port 2 register configuration.
Table 8-5
Port 2 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 2
PDR2
R/W
H'00
H'FFD5
Port control register 2
PCR2
W
H'00
H'FFE5
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Port mode register 4
PMR4
R/W
H'00
H'FFCB
140
1. Port data register 2 (PDR2)
Bit
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR2 is an 8-bit register that stores data for port 2 pins P27 to P20. If port 2 is read while PCR2
bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is
read while PCR2 bits are cleared to 0, the pin states are read.
Upon reset, PDR2 is initialized to H'00.
2. Port control register 2 (PCR2)
Bit
7
6
5
4
3
2
1
0
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR2 is an 8-bit register for controlling whether each of the port 2 pins P27 to P20 functions as an
input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and PDR2 are valid only
when the corresponding pin is designated in PMR1 as a general I/O pin.
Upon reset, PCR2 is initialized to H'00.
PCR2 is a write-only register, which is always read as all 1s.
3. Port mode register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
SO1
SI1
SCK1
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register that controls the selection of pin functions for port 2 pins P20,
P2 1, and P23, and the PMOS on/off state for the P22/SO 1 pin.
Upon reset, PMR2 is initialized to H'D8.
141
Bits 7, 6, 4, and 3: Reserved bits
Bits 7, 6, 4, and 3 are reserved; they are always read as 1 and cannot be modified.
Bit 5: P22/SO 1 pin PMOS control (POF1)
This bit controls the on/off state of the P2 2/SO 1 pin output buffer PMOS.
Bit 5
POF1
Description
0
CMOS output
1
NMOS open-drain output
(initial value)
Bit 2: P22/SO 1 pin function switch (SO1)
This bit selects whether pin P22/SO 1 is used as P22 or as SO1.
Bit 2
SO1
Description
0
Functions as P2 2 I/O pin
1
Functions as SO 1 output pin
(initial value)
Bit 1: P21/SI1 pin function switch (SI1)
This bit selects whether pin P21/SI1 is used as P21 or as SI1.
Bit 1
SI1
Description
0
Functions as P2 1 I/O pin
1
Functions as SI1 input pin
(initial value)
Bit 0: P20/SCK1 pin function switch (SCK1)
This bit selects whether pin P20/SCK1 is used as P20 or as SCK 1.
Bit 0
SCK1
Description
0
Functions as P2 0 I/O pin
1
Functions as SCK1 I/O pin
142
(initial value)
4. Port mode register 4 (PMR4)
Bit
7
6
5
4
3
2
1
0
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR4 is an 8-bit read/write register that controls whether individual port 2 pins are CMOS
outputs or NMOS open-drain outputs when 1 is set in PCR2.
Upon reset, PMR4 is initialized to H'00.
Bit n: NMOS open-drain output select (NMODn)
These bits select NMOS open-drain output when pin P2n is used as an output pin.
Bit n
NMODn
Description
0
CMOS output
1
NMOS open-drain output
(initial value)
(n = 7 to 0)
143
8.3.3
Pin Function
Table 8-6 shows the port 2 pin functions.
Table 8-6
Port 2 Pin Functions
Pin
Pin Functions and Selection Method
P27 to P2 3
The pin function depends on the corresponding bit in PCR2.
(n = 7 to 3)
0
P2n input pin
PCR2n
Pin function
P22/SO 1
1
P2n output pin
The pin function depends on bit SO1 in PMR2 and bit PCR22 in PCR2.
SO1
PCR22
Pin function
P21/SI1
0
0
P22 input pin
1
P22 output pin
1
*
SO1 output pin
The pin function depends on bit SI1 in PMR2 and bit PCR2 1 in PCR2.
SI1
PCR21
Pin function
P20/SCK1
0
0
P21 input pin
1
P21 output pin
1
*
SI 1 input pin
The pin function depends on bit SCK1 in PMR2 and bit PCR2 0 in PCR2.
SCK1
PCR20
Pin function
0
0
P20 input pin
1
P20 output pin
1
*
SCK 1 I/O pin
*: Don’t care
8.3.4
Pin States
Table 8-7 shows the port 2 pin states in each operating mode.
Table 8-7
Port 2 Pin States
Pins
Reset
P27 to P23
P22/SO1
P21/SI1
P20/SCK 1
HighRetains
impedance previous
state
144
Sleep
Subsleep
Standby
Watch
Subactive
Active
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
8.4
Port 3
8.4.1
Overview
Port 3 is an 8-bit I/O port, configured as shown in figure 8-3.
P3 7 /AEVL
P3 6 /AEVH
P3 5 /TXD31
P3 4 /RXD31
Port 3
P3 3 /SCK 31
P3 2 /RESO
P3 1 /UD
P3 0 /PWM
Figure 8-3 Port 3 Pin Configuration
8.4.2
Register Configuration and Description
Table 8-8 shows the port 3 register configuration.
Table 8-8
Port 3 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 3
PDR3
R/W
H'00
H'FFD6
Port control register 3
PCR3
W
H'00
H'FFE6
Port pull-up control register 3
PUCR3
R/W
H'00
H'FFE1
Port mode register 3
PMR3
R/W
H'04
H'FFCA
145
1. Port data register 3 (PDR3)
Bit
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P3 3
P32
P31
P3 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
2. Port control register 3 (PCR3)
Bit
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR34
PCR3 3
PCR3 2
PCR31
PCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register, which is always read as all 1s.
3. Port pull-up control register 3 (PUCR3)
Bit
7
6
5
4
3
2
1
0
PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31 PUCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.
146
4. Port mode register 3 (PMR3)
Bit
7
6
5
4
3
2
1
0
AEVL
AEVH
WDCKS
NCS
IRQ0
RESO
UD
PWM
Initial value
0
0
0
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Upon reset, PMR3 is initialized to H'04.
Bit 7: P37/AEVL pin function switch (AEVL)
This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Bit 7
AEVL
Description
0
Functions as P3 7 I/O pin
1
Functions as AEVL input pin
(initial value)
Bit 6: P36/AEVH pin function switch (AEVH)
This bit selects whether pin P36/AEVH is used as P36 or as AEVH.
Bit 6
AEVH
Description
0
Functions as P3 6 I/O pin
1
Functions as AEVH input pin
(initial value)
Bit 5: Watchdog timer source clock select (WDCKS)
This bit selects the watchdog timer source clock.
Bit 5
WDCKS
Description
0
ø/8192 selected
1
øw/32 selected
(initial value)
147
Bit 4: TMIG noise canceler select (NCS)
This bit controls the noise canceler for the input capture input signal (TMIG).
Bit 4
NCS
Description
0
Noise cancellation function not used
1
Noise cancellation function used
(initial value)
Bit 3: P43/IRQ0 pin function switch (IRQ0)
This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Bit 3
IRQ0
Description
0
Functions as P4 3 input pin
1
Functions as IRQ0 input pin
(initial value)
Bit 2: P32/RESO pin function switch (RESO)
This bit selects whether pin P32/RESO is used as P32 or as RESO.
Bit 2
RESO
Description
0
Functions as P3 2 I/O pin
1
Functions as RESO output pin
(initial value)
Bit 1: P31/UD pin function switch (UD)
This bit selects whether pin P31/UD is used as P31 or as UD.
Bit 1
UD
Description
0
Functions as P3 1 I/O pin
1
Functions as UD input pin
148
(initial value)
Bit 0: P30/PWM pin function switch (PWM)
This bit selects whether pin P30/PWM is used as P3 0 or as PWM.
Bit 0
PWM
Description
0
Functions as P3 0 I/O pin
1
Functions as PWM output pin
8.4.3
(initial value)
Pin Functions
Table 8-9 shows the port 3 pin functions.
Table 8-9
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P37/AEVL
The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3.
AEVL
PCR37
Pin function
P36/AEVH
0
0
P37 input pin
1
P37 output pin
1
*
AEVL input pin
The pin function depends on bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH
PCR36
Pin function
0
0
P36 input pin
1
P36 output pin
1
*
AEVH input pin
*: Don’t care
149
Table 8-9
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P35/TXD31
The pin function depends on bit TE in SCR3-1, bit SPC31 in SPCR, and bit
PCR35 in PCR3.
SPC31
TE
PCR35
Pin function
P34/RXD31
1
*
RXD31 input pin
1
P34 output pin
0
0
0
1
0
1
P33 input pin P33 output pin
1
*
*
*
SCK 31
input pin
1
*
*
SCK 31
output pin
0
0
P32 input pin
1
P32 output pin
1
*
RESO output pin
The pin function depends on bit UD in PMR3 and bit PCR31 in PCR3.
UD
PCR31
Pin function
P30/PWM
0
0
P34 input pin
The pin function depends on bit RESO in PMR3 and bit PCR3 2 in PCR3.
RESO
PCR32
Pin function
P31/UD
1
P35output pin
The pin function depends on bits CKE1, CKE0, and SMR31 in SCR3-1 and bit
PCR33 in PCR3.
CKE1
CKE0
COM31
PCR33
Pin function
P32/RESO
0
P35 input pin
1
1
*
TXD31 output pin
The pin function depends on bit RE in SCR3-1 and bit PCR3 4 in PCR3.
RE
PCR34
Pin function
P33/SCK31
0
0
0
0
P31 input pin
1
P31 output pin
1
*
UD input pin
The pin function depends on bit PWM in PMR3 and bit PCR30 in PCR3.
PWM
PCR30
Pin function
0
0
P30 input pin
1
P30 output pin
1
*
PWM output pin
*: Don’t care
150
8.4.4
Pin States
Table 8-10 shows the port 3 pin states in each operating mode.
Table 8-10 Port 3 Pin States
Pins
Reset
Sleep
Subsleep
Standby
P37/AEVL
P36/AEVH
P35/TXD31
P34/RXD31
P33/SCK 31
Highimpedance
Retains
previous
state
Retains
previous
state
HighRetains
impedance* previous
state
P32/RESO
Reset output
P31/UD
P30/PWM
Highimpedance
Note:
*
8.4.5
Watch
Subactive
Active
Functional
Functional
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR3n
0
0
1
PUCR3n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
151
8.5
Port 4
8.5.1
Overview
Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8-4.
P4 3 /IRQ0
P4 2 /TXD32
Port 4
P4 1 /RXD32
P4 0 /SCK32
Figure 8-4 Port 4 Pin Configuration
8.5.2
Register Configuration and Description
Table 8-11 shows the port 4 register configuration.
Table 8-11 Port 4 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 4
PDR4
R/W
H'F8
H'FFD7
Port control register 4
PCR4
W
H'F8
H'FFE7
1. Port data register 4 (PDR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P43
P4 2
P4 1
P4
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
0
PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
152
2. Port control register 4 (PCR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
PCR42
PCR4 1
PCR4 0
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an
input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the
corresponding pins are designated for general-purpose input/output by SCR3-2.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register, which always reads all 1s.
8.5.3
Pin Functions
Table 8-12 shows the port 4 pin functions.
Table 8-12 Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P43/IRQ0
The pin function depends on bit IRQ0 in PMR3.
IRQ0
Pin function
P42/TXD32
1
IRQ0 input pin
The pin function depends on bit TE in SCR3-2, bit SPC32 in SPCR, and bit
PCR42 in PCR4.
SPC32
TE
PCR42
Pin function
P41/RXD32
0
P43 input pin
0
0
1
P42 output pin
0
P42 input pin
1
1
*
TXD32 output pin
The pin function depends on bit RE in SCR3-2 and bit PCR41 in PCR4.
RE
PCR41
Pin function
0
0
P41 input pin
1
P41 output pin
1
*
RXD32 input pin
*: Don’t care
153
Table 8-12 Port 4 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P40/SCK32
The pin function depends on bits CKE1 and CKE0 in SCR3-2, bit COM32 in
SMR32, and bit PCR4 0 in PCR4.
CKE1
CKE0
COM32
PCR40
Pin function
8.5.4
0
0
0
0
P40 input pin
1
1
P40 output pin
1
*
*
SCK 32
output pin
1
*
*
*
SCK 32
input pin
Pin States
Table 8-13 shows the port 4 pin states in each operating mode.
Table 8-13 Port 4 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P43/IRQ0
P42/TXD32
P41/RXD32
P40/SCK 32
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
154
8.6
Port 5
8.6.1
Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8-5.
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
Port 5
P54/WKP4/SEG5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
Figure 8-5 Port 5 Pin Configuration
8.6.2
Register Configuration and Description
Table 8-14 shows the port 5 register configuration.
Table 8-14 Port 5 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 5
PDR5
R/W
H'00
H'FFD8
Port control register 5
PCR5
W
H'00
H'FFE8
Port pull-up control register 5
PUCR5
R/W
H'00
H'FFE2
Port mode register 5
PMR5
R/W
H'00
H'FFCC
155
1. Port data register 5 (PDR5)
Bit
7
6
5
4
3
2
1
0
P5 7
P5 6
P55
P5 4
P53
P52
P51
P5 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
2. Port control register 5 (PCR5)
Bit
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the
corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to
SGS0 in LPCR.
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
3. Port pull-up control register 5 (PUCR5)
Bit
7
6
5
4
3
2
1
0
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5 controls whether the MOS pull-up of each of port 5 pins P5 7 to P50 is on or off. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.
156
4. Port mode register 5 (PMR5)
Bit
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n: P5n/WKPn/SEGn+1 pin function switch (WKPn)
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as P5n
or WKPn.
Bit n
WKPn
Description
0
Functions as P5 n I/O pin
1
Functions as WKP n input pin
(initial value)
(n = 7 to 0)
Note: For use as SEGn+1, see 13.2.1, LCD Port Control Register (LPCR).
8.6.3
Pin Functions
Table 8-15 shows the port 5 pin functions.
Table 8-15 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/WKP 7/
SEG8 to
The pin function depends on bit WKP n in PMR5, bit PCR5n in PCR5, and bits
SEG8 to SGS3 to SGS0 in LPCR.
P50/WKP 0/
SEG1
SGS3 to SGS0
WKP n
PCR5n
Pin function
0***
0
0
P5n input pin
1
P5n output pin
1
*
WKP n
input pin
1***
*
*
SEGn+1
output pin
*: Don’t care
157
8.6.4
Pin States
Table 8-16 shows the port 5 pin states in each operating mode.
Table 8-16 Port 5 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P57/WKP7/
SEG8 to P50/
WKP0/SEG1
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance*
Retains
previous
state
Functional
Functional
Note:
*
8.6.5
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR5n
0
0
1
PUCR5n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
158
8.7
Port 6
8.7.1
Overview
Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8-6.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
Port 6
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Figure 8-6 Port 6 Pin Configuration
8.7.2
Register Configuration and Description
Table 8-17 shows the port 6 register configuration.
Table 8-17 Port 6 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 6
PDR6
R/W
H'00
H'FFD9
Port control register 6
PCR6
W
H'00
H'FFE9
Port pull-up control register 6
PUCR6
R/W
H'00
H'FFE3
159
1. Port data register 6 (PDR6)
Bit
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P6 3
P62
P61
P6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.
If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the
actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
2. Port control register 6 (PCR6)
Bit
7
6
5
4
3
2
1
0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
Setting a PCR6 bit to 1 makes the corresponding pin (P6 7 to P60) an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which always reads all 1s.
3. Port pull-up control register 6 (PUCR6)
Bit
7
6
5
4
3
2
1
0
PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When
a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
160
8.7.3
Pin Functions
Table 8-18 shows the port 6 pin functions.
Table 8-18 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/SEG 16
to P60/SEG 9
The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 0)
SGS3 to SGS0
PCR6n
Pin function
00**, 010*
0
1
P6n input pin
P6n output pin
011**, 1***
*
SEGn+9 output pin
*: Don’t care
8.7.4
Pin States
Table 8-19 shows the port 6 pin states in each operating mode.
Table 8-19 Port 6 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P67/SEG16 to
P60/SEG9
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance*
Retains
previous
state
Functional
Functional
Note:
*
8.7.5
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The
MOS pull-up function is in the off state after a reset.
PCR6n
0
0
1
PUCR6n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
161
8.8
Port 7
8.8.1
Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8-7.
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
Port 7
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Figure 8-7 Port 7 Pin Configuration
8.8.2
Register Configuration and Description
Table 8-20 shows the port 7 register configuration.
Table 8-20 Port 7 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 7
PDR7
R/W
H'00
H'FFDA
Port control register 7
PCR7
W
H'00
H'FFEA
162
1. Port data register 7 (PDR7)
Bit
7
6
5
4
3
2
1
0
P7 7
P7 6
P75
P7 4
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
2. Port control register 7 (PCR7)
Bit
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which always reads as all 1s.
163
8.8.3
Pin Functions
Table 8-21 shows the port 7 pin functions.
Table 8-21 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/SEG 24
to P70/SEG 17
The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 0)
SGS3 to SGS0
PCR7n
Pin function
00**
0
P7n input pin
1
P7n output pin
01**, 1***
*
SEGn+17 output pin
*: Don’t care
8.8.4
Pin States
Table 8-22 shows the port 7 pin states in each operating mode.
Table 8-22 Port 7 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P77/SEG24
to
P70/SEG17
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
164
8.9
Port 8
8.9.1
Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8-8.
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
Port 8
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Figure 8-8 Port 8 Pin Configuration
8.9.2
Register Configuration and Description
Table 8-23 shows the port 8 register configuration.
Table 8-23 Port 8 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 8
PDR8
R/W
H'00
H'FFDB
Port control register 8
PCR8
W
H'00
H'FFEB
1. Port data register 8 (PDR8)
Bit
7
6
5
4
3
2
1
0
P8 7
P8 6
P85
P8 4
P83
P82
P81
P8 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
165
2. Port control register 8 (PCR8)
Bit
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an
input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR8 and PDR8 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register, which is always read as all 1s.
8.9.3
Pin Functions
Table 8-24 shows the port 8 pin functions.
Table 8-24 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P87/SEG 32
to P80/SEG 25
The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 0)
SGS3 to SGS0
PCR8n
Pin function
000*
0
P8n input pin
1
P8n output pin
001*, 01**,1***
*
SEGn+25 output pin
*: Don’t care
8.9.4
Pin States
Table 8-25 shows the port 8 pin states in each operating mode.
Table 8-25 Port 8 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P87/SEG32 to
P80/SEG25
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
166
8.10
Port 9
8.10.1
Overview
Port 9 is an 8-bit I/O port. Figure 8-9 shows its pin configuration.
P97/SEG40/CL1
P96/SEG39/CL2
P95/SEG38/DO
P94/SEG37/M
Port 9
P93/SEG36
P92/SEG35
P91/SEG34
P90/SEG33
Figure 8-9 Port 9 Pin Configuration
8.10.2
Register Configuration and Description
Table 8-26 shows the port 9 register configuration.
Table 8-26 Port 9 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 9
PDR9
R/W
H'00
H'FFDC
Port control register 9
PCR9
R
H'00
H'FFEC
167
1. Port data register 9 (PDR9)
Bit
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P97 to P90. If port 9 is read while PCR9
bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is
read while PCR9 bits are cleared to 0, the pin states are read.
Upon reset, PDR9 is initialized to H'00.
2. Port control register 9 (PCR9)
Bit
7
6
5
4
3
2
1
0
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR9 is an 8-bit register for controlling whether each of the port 9 pins P97 to P90 functions as an
input pin or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and PDR9 are valid only
when the corresponding pin is designated by bits SGS3 to SGS0 in LPCR as a general I/O pin.
Upon reset, PCR9 is initialized to H'00.
PCR9 is a write-only register, which is always read as all 1s.
168
8.10.3
Pin Functions
Table 8-27 shows the port 9 pin functions.
Table 8-27 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P97/SEG 40 /CL1
The pin function depends on bit PCR97 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR97
Pin function
P96/SEG 39 /CL2
1
P97 output pin
*
1
*
CL 1
output pin
0000
0
0
P96 input pin
1
P96 output pin
Not 0000
0
*
SEG39
output pin
*
1
*
CL 2
output pin
The pin function depends on bit PCR95 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR95
Pin function
P94/SEG 37 /M
0
P97 input pin
Not 0000
0
*
SEG40
output pin
The pin function depends on bit PCR96 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR96
Pin function
P95/SEG 38 /DO
0000
0
0000
0
0
P95 input pin
1
P95 output pin
Not 0000
0
*
SEG38
output pin
*
1
*
DO
output pin
The pin function depends on bit PCR94 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR94
Pin function
0000
0
0
P94 input pin
1
P94 output pin
Not 0000
0
*
SEG37
output pin
*
1
*
M output pin
*: Don’t care
169
Table 8-27 Port 9 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P93/SEG 36 to
P90/SEG 33
The pin function depends on bit PCR9n in PCR9 and bits SGS3 to SGS0 in
LPCR.
(n = 3 to 0)
SGS3 to SGS0
PCR9n
Pin function
000*
0
P9n input pin
1
P9n output pin
Not 0000
*
SEGn+33 output pin
*: Don’t care
8.10.4
Pin States
Table 8-28 shows the port 9 pin states in each operating mode.
Table 8-28 Port 9 Pin States
Pins
Reset
P97/SEG40 /CL1 HighP96/SEG39 /CL2 impedance
P95/SEG38 /DO
P94/SEG37 /M
P93/SEG36 to
P90/SEG33
170
Sleep
Subsleep
Standby
Watch
Subactive
Active
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
8.11
Port A
8.11.1
Overview
Port A is a 4-bit I/O port, configured as shown in figure 8-10.
PA3/COM4
PA2/COM3
Port A
PA1/COM2
PA0/COM1
Figure 8-10 Port A Pin Configuration
8.11.2
Register Configuration and Description
Table 8-29 shows the port A register configuration.
Table 8-29 Port A Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register A
PDRA
R/W
H'F0
H'FFDD
Port control register A
PCRA
W
H'F0
H'FFED
1. Port data register A (PDRA)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PA 3
PA 2
PA 1
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
PA 0
PDRA is an 8-bit register that stores data for port A pins PA3 to PA 0. If port A is read while
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
171
2. Port control register A (PCRA)
Bit
7
6
5
4
3
2
1
—
—
—
—
PCRA 3
PCRA 2
PCRA 1
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
0
PCRA 0
PCRA controls whether each of port A pins PA3 to PA 0 functions as an input pin or output pin.
Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are
designated for general-purpose input/output by LPCR.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register, which always reads all 1s.
172
8.11.3
Pin Functions
Table 8-30 shows the port A pin functions.
Table 8-30 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/COM4
The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA3
Pin function
PA2/COM3
Not 0000
*
COM4 output pin
0000
1
PA2 output pin
0
PA2 input pin
Not 0000
*
COM3 output pin
The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA1
Pin function
PA0/COM1
1
PA3 output pin
The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA2
Pin function
PA1/COM2
0000
0
PA3 input pin
0000
1
PA1 output pin
0
PA1 input pin
Not 0000
*
COM2 output pin
The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA0
Pin function
0000
0
PA0 input pin
1
PA0 output pin
Not 0000
*
COM1 output pin
*: Don’t care
8.11.4
Pin States
Table 8-31 shows the port A pin states in each operating mode.
Table 8-31 Port A Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
PA 3/COM4
PA 2/COM3
PA 1/COM2
PA 0/COM1
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
173
8.12
Port B
8.12.1
Overview
Port B is an 8-bit input-only port, configured as shown in figure 8-11.
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
Port B
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 8-11 Port B Pin Configuration
8.12.2
Register Configuration and Description
Table 8-32 shows the port B register configuration.
Table 8-32 Port B Register
Name
Abbrev.
R/W
Address
Port data register B
PDRB
R
H'FFDE
Port Data Register B (PDRB)
Bit
Read/Write
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB 0
R
R
R
R
R
R
R
R
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
174
8.13
Port C
8.13.1
Overview
Port C is a 4-bit input-only port, configured as shown in figure 8-12.
PC3/AN11
PC2/AN10
Port C
PC1/AN9
PC0/AN8
Figure 8-12 Port C Pin Configuration
8.13.2
Register Configuration and Description
Table 8-33 shows the port C register configuration.
Table 8-33 Port C Register
Name
Abbrev.
R/W
Address
Port data register C
PDRC
R
H'FFDF
1. Port data register C (PDRC)
Bit
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
PC3
PC2
PC1
PC0
—
—
—
—
R
R
R
R
Reading PDRC always gives the pin states.
Reading the pin for which an analog input channel is selected by the AMR CH3 to CH0 of the
A/D converter, "0" is read regardless of the input voltage.
175
8.14
Input/Output Data Inversion Function
8.14.1
Overview
With input pins RXD31, and RXD32, and output pins TXD31 and TXD32, the data can be handled in
inverted form.
SCINV0
SCINV2
RXD31
RXD32
P34/RXD31
P41/RXD32
SCINV1
SCINV3
P35/TXD31
P42/TXD32
TXD31
TXD32
Figure 8.13 Input/Output Data Inversion Function
8.14.2
Register Configuration and Descriptions
Table 8.34 shows the registers used by the input/output data inversion function.
Table 8.34 Register Configuration
Name
Abbreviation
R/W
Address
Serial port control register
SPCR
R/W
H'FF91
Serial Port Control Register (SPCR)
Bit
7
6
5
—
—
SPC32
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
SPC31 SCINV3 SCINV2 SCINV1 SCINV0
SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin
input/output data inversion switching. SPCR is initialized to H'C0 by a reset.
176
Bit 0: RXD 31 pin input data inversion switch
Bit 0 specifies whether or not RXD 31 pin input data is to be inverted.
Bit 0
SCINV0
Description
0
RXD31 input data is not inverted
1
RXD31 input data is inverted
(initial value)
Bit 1: TXD31 pin output data inversion switch
Bit 1 specifies whether or not TXD31 pin output data is to be inverted.
Bit 1
SCINV1
Description
0
TXD31 output data is not inverted
1
TXD31 output data is inverted
(initial value)
Bit 2: RXD 32 pin input data inversion switch
Bit 2 specifies whether or not RXD 32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bit 3: TXD32 pin output data inversion switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
177
Bit 4: P35/TXD 31 pin function switch (SPC31)
This bit selects whether pin P35/TXD31 is used as P35 or as TXD31.
Bit 4
SPC31
Description
0
Functions as P3 5 I/O pin
1
Functions as TXD 31 output pin*
Note:
*
(initial value)
Set the TE bit in SCR3 after setting this bit to 1.
Bit 5: P42/TXD32 pin function switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P4 2 I/O pin
1
Note:
(initial value)
Functions as TXD 32 output pin*
*
Set the TE bit in SCR3 after setting this bit to 1.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
8.14.3
Note on Modification of Serial Port Control Register
When a serial port control register is modified, the data being input or output up to that point is
inverted immediately after the modification, and an invalid data change is input or output. When
modifying a serial port control register, do so in a state in which data changes are invalidated
178
Section 9 Timers
9.1
Overview
The H8/3887 Series provides six timers: timers A, C, F, G, and a watchdog timer, and an
asynchronous event counter. The functions of these timers are outlined in table 9-1.
Table 9-1
Timer Functions
Name
Functions
Internal Clock
Event
Waveform
Input Pin Output Pin Remarks
Timer A
• 8-bit interval timer
ø/8 to ø/8192
—
• Interval function
(8 choices)
• Time base
øW/128 (choice of
4 overflow periods)
• Clock output
ø/4 to ø/32 ø W , øW/4 —
to ø W /32 (9 choices)
—
TMOW
Timer C
ø/4 to ø/8192, øW/4 TMIC
• 8-bit timer
(7 choices)
• Interval function
• Event counting function
• Up-count/down-count
selectable
—
Timer F
ø/4 to ø/32, øW/4
• 16-bit timer
• Event counting function (4 choices)
• Also usable as two
independent 8-bit timers
• Output compare output
function
TMIF
TMOFL
TMOFH
Timer G
• 8-bit timer
• Input capture function
• Interval function
TMIG
—
Watchdog
timer
ø/2 to ø/64, øW/4
(4 choices)
• Reset signal generated ø/8192
when 8-bit counter
øw/32
overflows
Up- count/
down-count
controllable by
software or
hardware
Counter
clearing option
Built-in capture
input signal
noise canceler
—
—
179
Table 9-1
Name
Timer Functions (cont)
Functions
Asynchro- • 16-bit counter
nous event • Also usable as two
counter
independent 8-bit
counters
• Counts events
asynchronous to ø and
øW
180
Internal Clock
—
Event
Waveform
Input Pin Output Pin Remarks
AEVL
AEVH
—
9.2
Timer A
9.2.1
Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal
divided from 32.768 kHz, from 38.4 kHz (if a 38.4 kHz crystal oscillator is connected), or from
the system clock, can be output at the TMOW pin.
1. Features
Features of timer A are given below.
• Choice of eight internal clock sources (ø/8192, ø/4096, ø/2048, ø/512, ø/256, ø/128, ø/32, ø/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal oscillator).
• An interrupt is requested when the counter overflows.
• Any of nine clock signals can be output at the TMOW pin: 32.768 kHz divided by 32, 16, 8, or
4 (1 kHz, 2 kHz, 4 kHz, 8 kHz) or 38.4 kHz divided by 32, 16, 8, or 4 (1.2 kHz, 2.4 kHz, 4.8
kHz, 9.6 kHz), and the system clock divided by 32, 16, 8, or 4.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
181
2. Block diagram
Figure 9-1 shows a block diagram of timer A.
CWORS
PSW
TMA
øW/4
øW/32
øW/16
øW/8
øW/4
Internal data bus
1/4
øW /128
ø
÷64*
ø/8192, ø/4096, ø/2048,
ø/512, ø/256, ø/128,
ø/32, ø/8
÷8*
ø/32
ø/16
ø/8
ø/4
÷128*
TCA
TMOW
÷256*
øW
PSS
IRRTA
Notation:
TMA:
TCA:
IRRTA:
PSW:
PSS:
CWOSR:
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
Subclock output select register
Note: * Can be selected only when the prescaler W output (øW/128) is used as the TCA input clock.
Figure 9-1 Block Diagram of Timer A
3. Pin configuration
Table 9-2 shows the timer A pin configuration.
Table 9-2
Pin Configuration
Name
Abbrev.
I/O
Function
Clock output
TMOW
Output
Output of waveform generated by timer A output circuit
182
4. Register configuration
Table 9-3 shows the register configuration of timer A.
Table 9-3
Timer A Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer mode register A
TMA
R/W
H'10
H'FFB0
Timer counter A
TCA
R
H'00
H'FFB1
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Subclock output select register
CWOSR
R/W
H'FE
H'FF92
9.2.2
Register Descriptions
1. Timer mode register A (TMA)
Bit
7
6
5
4
3
2
1
0
TMA7
TMA6
TMA5
—
TMA3
TMA2
TMA1
TMA0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock.
Upon reset, TMA is initialized to H'10.
183
Bits 7 to 5: Clock output select (TMA7 to TMA5)
Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock
divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz or 38.4
kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive
mode. øw is output in all modes except the reset state.
CWOSR
TMA
CWOS
Bit 7
TMA7
Bit 6
TMA6
Bit 5
TMA5
Clock Output
0
0
0
0
ø/32
1
ø/16
0
ø/8
1
ø/4
0
øW/32
1
øW/16
0
øW/8
1
øW/4
*
øW
1
1
0
1
1
*
*
(initial value)
*: Don’t care
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 1, and cannot be modified.
184
Bits 3 to 0: Internal clock select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
TMA3
Bit 2
TMA2
Bit 1
TMA1
Bit 0
TMA0
Prescaler and Divider Ratio
or Overflow Period
0
0
0
0
PSS, ø/8192
1
PSS, ø/4096
0
PSS, ø/2048
1
PSS, ø/512
0
PSS, ø/256
1
PSS, ø/128
0
PSS, ø/32
1
PSS, ø/8
0
PSW, 1 s
Clock time base
1
PSW, 0.5 s
(when using
0
PSW, 0.25 s
32.768 kHz)
1
PSW, 0.03125 s
0
PSW and TCA are reset
1
1
0
1
1
0
0
1
1
0
Function
(initial value) Interval timer
1
1
0
1
185
2. Timer counter A (TCA)
Bit
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
3. Clock stop register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0: Timer A module standby mode control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP
Description
0
Timer A is set to module standby mode
1
Timer A module standby mode is cleared
186
(initial value)
4. Subclock Output Select Register (CWOSR)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CWOS
Initial value:
1
1
1
1
1
1
1
0
Read/Write:
R
R
R
R
R
R
R
R/W
Bit:
CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin.
CWOSR is initialized to H'FE by a reset.
Bits 7 to 1: Reserved bits
Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified.
Bit 0: TMOW pin clock select (CWOS)
Bit 0 selects the clock to be output from the TMOW pin.
Bit 0
CWOS
Description
0
Clock output from timer A is output (see TMA)
1
øW is output
9.2.3
(initial value)
Timer Operation
1. Interval timer operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see 3.3, Interrupts.
187
2. Real-time clock time base operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and
TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting
bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.
3. Clock output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Nine different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA and bit CWOS in CWOSR. The system clock divided by 32, 16, 8, or 4 can be output in
active mode and sleep mode. A 32.768 kHz or 38.4 kHz signal divided by 32, 16, 8, or 4 can be
output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. The 32.768
kHz or 38.4 kHz clock is output in all modes except the reset state.
9.2.4
Timer A Operation States
Table 9-4 summarizes the timer A operation states.
Table 9-4
Timer A Operation States
Operation Mode
Reset Active
Watch
Subactive
Subsleep
Standby
Module
Standby
TCA
Reset Functions Functions Halted
Halted
Halted
Halted
Halted
Clock time base Reset Functions Functions Functions Functions Functions Halted
Halted
TMA
Interval
Sleep
Reset Functions Retained Retained Functions Retained Retained Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ø (s) in
the count cycle.
188
9.3
Timer C
9.3.1
Overview
Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operation modes, interval and auto reload.
1. Features
Features of timer C are given below.
• Choice of seven internal clock sources (ø/8192, ø/2048, ø/512, ø/64, ø/16, ø/4, ø W /4) or an
external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode and subsleep mode operation is possible when øW/4 is selected as the internal
clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
189
2. Block diagram
Figure 9-2 shows a block diagram of timer C.
UD
TCC
ø
PSS
Internal data bus
TMC
TMIC
TLC
øW/4
IRRTC
Notation:
TMC
: Timer mode register C
TCC
: Timer counter C
TLC
: Timer load register C
IRRTC : Timer C overflow interrupt request flag
PSS
: Prescaler S
Figure 9-2 Block Diagram of Timer C
3. Pin configuration
Table 9-5 shows the timer C pin configuration.
Table 9-5
Pin Configuration
Name
Abbrev.
I/O
Function
Timer C event input
TMIC
Input
Input pin for event input to TCC
Timer C up/down-count selection
UD
Input
Timer C up/down select
190
4. Register configuration
Table 9-6 shows the register configuration of timer C.
Table 9-6
Timer C Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer mode register C
TMC
R/W
H'18
H'FFB4
Timer counter C
TCC
R
H'00
H'FFB5
Timer load register C
TLC
W
H'00
H'FFB5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.3.2
Register Descriptions
1. Timer mode register C (TMC)
Bit
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and
performing up/down-counter control.
Upon reset, TMC is initialized to H'18.
Bit 7: Auto-reload function select (TMC7)
Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7
TMC7
Description
0
Interval timer function selected
1
Auto-reload function selected
(initial value)
191
Bits 6 and 5: Counter up/down control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
TMC6
Bit 5
TMC5
Description
0
0
TCC is an up-counter
0
1
TCC is a down-counter
1
*
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
(initial value)
*: Don't care
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0: Clock select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2
Bit 1
TMC1
Bit 0
TMC0
Description
0
0
0
Internal clock: ø/8192
0
0
1
Internal clock: ø/2048
0
1
0
Internal clock: ø/512
0
1
1
Internal clock: ø/64
1
0
0
Internal clock: ø/16
1
0
1
Internal clock: ø/4
1
1
0
Internal clock: ø W /4
1
1
1
External event (TMIC): rising or falling edge*
Note:
192
*
(initial value)
The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See 1. IRQ edge select register (IEGR) in 3.3.2 for details. IRQ2 must
be set to 1 in port mode register 1 (PMR1) before setting 111 in bits TMC2 to TMC0.
2. Timer counter C (TCC)
Bit
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode
register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
3. Timer load register C (TLC)
Bit
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).
When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC
starts counting up from that value. When TCC overflows or underflows during operation in autoreload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow periods can be
set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
4. Clock stop register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer C is described here. For details of the other bits, see the
sections on the relevant modules.
193
Bit 1: Timer C module standby mode control (TCCKSTP)
Bit 1 controls setting and clearing of module standby mode for timer C.
TCCKSTP
Description
0
Timer C is set to module standby mode
1
Timer C module standby mode is cleared
9.3.3
(initial value)
Timer Operation
1. Interval timer operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an
interval up-counter without halting immediately after a reset. The timer C operating clock is
selected from seven internal clock signals output by prescalers S and W, or an external clock input
at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
TCC up/down-count control can be performed either by software or hardware. The selection is
made by bits TMC6 and TMC5 in TMC.
After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow
(underflow), setting bit IRRTC to 1 in IRR2. If IENTC = 1 in interrupt enable register 2 (IENR2),
a CPU interrupt is requested.
At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: * For details on interrupts, see 3.3, Interrupts.
194
2. Auto-reload timer operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
3. Event counter operation
Timer C can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in
timer mode register C to all 1s (111).
When timer C is used to count external event input, , bit IRQ2 in PMR1 should be set to 1 and bit
IEN2 in IENR1 cleared to 0 to disable interrupt IRQ2 requests.
4. TCC up/down control by hardware
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 is set to
1 in TMC, TCC functions as an up-counter when UD pin input is high, and as a down-counter
when low.
When using UD pin input, set bit UD to 1 in PMR3.
195
9.3.4
Timer C Operation States
Table 9-7 summarizes the timer C operation states.
Table 9-7
Timer C Operation States
TCC
Interval
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Auto reload
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Reset
Functions Retained Retained
Functions Retained Retained
Retained
196
*
Standby
Module
Standby
Active
Note:
Watch
Subsleep
Reset
TMC
Sleep
Subactive
Operation Mode
When øw/4 is selected as the TCC internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø (s). When the counter is operated in subactive mode or subsleep mode, either
select øw/4 as the internal clock or select an external clock. The counter will not
operate on any other internal clock. If øw/4 is selected as the internal clock for the
counter when øw/8 has been selected as subclock øSUB, the lower 2 bits of the counter
operate on the same cycle, and the operation of the least significant bit is unrelated to
the operation of the counter.
9.4
Timer F
9.4.1
Overview
Timer F is a 16-bit timer with a built-in output compare function. As well as counting external
events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc.,
using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH
and timer FL).
1. Features
Features of timer F are given below.
• Choice of four internal clock sources (ø/32, ø/16, ø/4, øw/4) or an external clock (can be used
as an external event counter)
• TMOFH pin toggle output provided using a single compare match signal (toggle output initial
value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FH 8-Bit Timer*
Timer FL 8-Bit Timer/Event Counter
Internal clock
Choice of 4 (ø/32, ø/16, ø/4, øw/4)
Event input
—
TMIF pin
Toggle output
One compare match signal,
output to TMOFH pin
(initial value settable)
One compare match signal,
output to TMOFL pin
(initial value settable)
Counter reset
Counter can be reset by compare match signal
Interrupt sources
One compare match
One overflow
Note:
*
When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
• Operation in watch mode, subactive mode, and subsleep mode
When øw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
197
2. Block diagram
Figure 9-3 shows a block diagram of timer F.
UD
TCC
ø
PSS
Internal data bus
TMC
TMIC
TLC
øW/4
IRRTC
Notation:
TMC
TMC: Timer mode register C
TCC
TCC: timer counter C
TLC
TLC: Timer load register C
IRRTC IRRTC: Timer C overflow interrupt request flag
PSS
PSS: Prescaler S
Figure 9-3 Block Diagram of Timer F
198
3. Pin configuration
Table 9-8 shows the timer F pin configuration.
Table 9-8
Pin Configuration
Name
Abbrev.
I/O
Function
Timer F event input
TMIF
Input
Event input pin for input to TCFL
Timer FH output
TMOFH
Output
Timer FH toggle output pin
Timer FL output
TMOFL
Output
Timer FL toggle output pin
4. Register configuration
Table 9-9 shows the register configuration of timer F.
Table 9-9
Timer F Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer control register F
TCRF
W
H'00
H'FFB6
Timer control/status register F
TCSRF
R/W
H'00
H'FFB7
8-bit timer counter FH
TCFH
R/W
H'00
H'FFB8
8-bit timer counter FL
TCFL
R/W
H'00
H'FFB9
Output compare register FH
OCRFH
R/W
H'FF
H'FFBA
Output compare register FL
OCRFL
R/W
H'FF
H'FFBB
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
199
9.4.2
Register Descriptions
1. 16-bit timer counter (TCF)
8-bit timer counter (TCFH)
8-bit timer counter (TCFL)
TCF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCFH
TCFL
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see 9.4.3, CPU Interface.
TCFH and TCFL are each initialized to H'00 upon reset.
a. 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input
clock is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
b. 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH
(CCLRL) in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF.
If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and
if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
200
2. 16-bit output compare register (OCRF)
8-bit output compare register (OCRFH)
8-bit output compare register (OCRFL)
OCRF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRFH
OCRFL
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see 9.4.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF
contents are constantly compared with TCF, and when both values match, CMFH is set to
1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at
this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and
the output level can be set (high or low) by means of TOLH in TCRF.
b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with
TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is
set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH
(IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in
TCRF.
201
3. Timer control register F (TCRF)
Bit:
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
W
W
W
W
W
W
W
W
TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the
input clock from among four internal clock sources or external event input, and sets the output
level of the TMOFH and TMOFL pins.
TCRF is initialized to H'00 upon reset.
Bit 7: Toggle output level H (TOLH)
Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is
written.
Bit 7
TOLH
Description
0
Low level
1
High level
(initial value)
Bits 6 to 4: Clock select H (CKSH2 to CKSH0)
Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL
overflow.
Bit 6
CKSH2
Bit 5
CKSH1
Bit 4
CKSH0
Description
0
0
0
16-bit mode, counting on TCFL overflow signal
0
0
1
0
1
0
0
1
1
Not available
1
0
0
Internal clock: counting on ø/32
1
0
1
Internal clock: counting on ø/16
1
1
0
Internal clock: counting on ø/4
1
1
1
Internal clock: counting on øw/4
(initial value)
*: Don't care
202
Bit 3: Toggle output level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL
Description
0
Low level
1
High level
(initial value)
Bits 2 to 0: Clock select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event
input.
Bit 2
CKSL2
Bit 1
CKSL1
Bit 0
CKSL0
Description
0
0
0
Counting on external event (TMIF) rising/falling
0
0
1
0
1
0
0
1
1
Not available
1
0
0
Internal clock: counting on ø/32
1
0
1
Internal clock: counting on ø/16
1
1
0
Internal clock: counting on ø/4
1
1
1
Internal clock: counting on øw/4
Note:
edge*
(initial value)
1
*: Don't care
1. External event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
For details, see 1. IRQ edge select register (IEGR) in section 3.3.2.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register
1 (PMR1) is changed from 0 to 1 while the TMIF pin is low in order to change the TMIF
pin function.
203
4. Timer control/status register F (TCSRF)
Bit:
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
R/W
R/W
R/W
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H'FF to H'00
(initial value)
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
204
(initial value)
Bit 5: Timer overflow interrupt enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
Description
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
(initial value)
Bit 4: Counter clear H (CCLRH)
In 8-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
0
1
Description
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
(initial value)
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Bit 3: Timer overflow flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when TCFL overflows from H'FF to H'00
(initial value)
205
Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting conditions:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
(initial value)
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
(initial value)
5. Clock stop register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
206
Bit 2: Timer F module standby mode control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
Timer F is set to module standby mode
1
Timer F module standby mode is cleared
9.4.3
(initial value)
CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
In 16-bit mode, TCF read/write access and OCRF write access must be performed 16 bits at a time
(using two consecutive byte-size MOV instructions), and the upper byte must be accessed before
the lower byte. Data will not be transferred correctly if only the upper byte or only the lower byte
is accessed.
In 8-bit mode, there are no restrictions on the order of access.
207
1. Write access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next,
write access to the lower byte results in transfer of the data in TEMP to the upper register byte,
and direct transfer of the lower-byte write data to the lower register byte.
Figure 9-4 shows an example in which H'AA55 is written to TCF.
Write to upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(
)
TCFL
(
)
Write to lower byte
CPU
(H'55)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Figure 9-4 Write Access to TCR (CPU Æ TCF)
208
2. Read access
In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the
CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the
lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9-5 shows an example in which TCF is read when it contains H'AAFF.
Read upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Read lower byte
CPU
(H'FF)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(AB)*
TCFL
(00)*
Note: * H'AB00 if counter has been updated once.
Figure 9-5 Read Access to TCF (TCF Æ CPU)
209
9.4.4
Operation
Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can
also function as two independent 8-bit timers.
1. Timer F operation
Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each
of these modes is described below.
a. Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16bit timer.
Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F
(OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F
(TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The
external event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
The timer F operating clock can be selected from four internal clocks output by prescaler S
or an external clock by means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is
set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the
CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF
is cleared. TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
b. Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH
and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to
CKSL0 in TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at
the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF
is 1, TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by
TOLH/TOLL in TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request
is sent to the CPU.
210
2. TCF increment timing
TCF is incremented by clock input (internal clock or external event input).
a. Internal clock operation
Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock
sources (ø/32, ø/16, ø/4, or øw/4) created by dividing the system clock (ø or øw).
b. External event operation
External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on
either the rising or falling edge of external event input. External event edge selection is set
by IEG3 in the interrupt controller's IEGR register. An external event pulse width of at
least 2 system clocks (ø) is necessary. Shorter pulses will not be counted correctly.
3. TMOFH/TMOFL output timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match. Figure 9-6 shows the output timing.
ø
TMIF
(when IEG3 = 1)
Count input
clock
TCF
OCRF
N
N+1
N
N
N+1
N
Compare match
signal
TMOFH TMOFL
Figure 9-6 TMOFH/TMOFL Output Timing
211
4. TCF clear timing
TCF can be cleared by a compare match with OCRF.
5. Timer overflow flag (OVF) set timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
6. Compare match flag set timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
7. Timer F operation modes
Timer F operation modes are shown in table 9-10.
Table 9-10 Timer F Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
TCF
Reset
Functions
Functions
Functions/ Functions/ Functions/ Halted
Halted*
Halted*
Halted*
Halted
OCRF
Reset
Functions
Held
Held
Functions
Held
Held
Held
TCRF
Reset
Functions
Held
Held
Functions
Held
Held
Held
TCSRF
Reset
Functions
Held
Held
Functions
Held
Held
Held
Note:
212
*
Subactive Subsleep Standby
Module
Standby
When ø w /4 is selected as the TCF internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, øw /4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
9.4.5
Application Notes
The following types of contention and operation can occur when timer F is used.
1. 16-bit timer mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
2. 8-bit timer mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur
simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the
compare match signal is invalid. However, if the written data and the counter value match,
a compare match signal will be generated at that point. The compare match signal is output
in synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is
not output.
213
b. TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur
simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the
compare match signal is invalid. However, if the written data and the counter value match,
a compare match signal will be generated at that point. As the compare match signal is
output in synchronization with the TCFL clock, a compare match will not result in compare
match signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is
not output.
214
9.5
Timer G
9.5.1
Overview
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of
pulses input from the input capture input pin (input capture input signal). High-frequency
component noise in the input capture input signal can be eliminated by a noise canceler, enabling
accurate measurement of the input capture input signal duty cycle. If input capture input is not set,
timer G functions as an 8-bit interval timer.
1. Features
Features of timer G are given below.
• Choice of four internal clock sources (ø/64, ø/32, ø/2, øw/2)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow
It is possible to detect whether overflow occurred when the input capture input signal was high
or when it was low.
• Selection of whether or not the counter value is to be cleared at the input capture input signal
rising edge, falling edge, or both edges
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising
or falling edge can be selected as the interrupt source.
• A built-in noise canceler eliminates high-frequency component noise in the input capture input
signal.
• Watch mode, subactive mode and subsleep mode operation is possible when øw/2 is selected
as the internal clock.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
215
2. Block diagram
Figure 9-7 shows a block diagram of timer G.
ø
PSS
Level
detector
øw/4
ICRGF
TMIG
Noise
canceler
Edge
detector
NCS
Internal data bus
TMG
TCG
ICRGR
IRRTG
Notation:
TMG
: Timer mode register G
TCG
: Timer counter G
ICRGF : Input capture register GF
ICRGR : Input capture register GR
IRRTG : Timer G interrupt request flag
NCS
: Noise canceler select
PSS
: Prescaler S
Figure 9-7 Block Diagram of Timer G
216
3. Pin configuration
Table 9-11 shows the timer G pin configuration.
Table 9-11 Pin Configuration
Name
Abbrev.
I/O
Function
Input capture input
TMIG
Input
Input capture input pin
4. Register configuration
Table 9-12 shows the register configuration of timer G.
Table 9-12 Timer G Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer control register G
TMG
R/W
H'00
H'FFBC
Timer counter G
TCG
—
H'00
—
Input capture register GF
ICRGF
R
H'00
H'FFBD
Input capture register GR
ICRGR
R
H'00
H'FFBE
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.5.2
Register Descriptions
1. Timer counter (TCG)
Bit:
7
6
5
4
3
2
1
0
TCG7
TCG6
TCG5
TCG4
TCG3
TCG2
TCG1
TCG0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
—
—
—
—
—
—
—
—
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
217
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
2. Input capture register GF (ICRGF)
Bit:
7
6
5
4
3
2
1
0
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2øSUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
3. Input capture register GR (ICRGR)
7
6
5
4
3
2
1
0
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
Bit:
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2øSUB (when the noise canceler is not used).
ICRGR is initialized to H'00 upon reset.
218
4. Timer mode register G (TMG)
7
6
5
4
3
2
1
0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
Description
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCG overflows from H'FF to H'00
(initial value)
Bit 6: Timer overflow flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software.
It cannot be set by software.
Bit 6
OVFL
Description
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when TCG overflows from H'FF to H'00
(initial value)
219
Bit 5: Timer overflow interrupt enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
Description
0
TCG overflow interrupt request is disabled
1
TCG overflow interrupt request is enabled
(initial value)
Bit 4: Input capture interrupt edge select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
Description
0
Interrupt generated on rising edge of input capture input signal
1
Interrupt generated on falling edge of input capture input signal
(initial value)
Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
Bit 2
CCLR0
Description
0
0
TCG clearing is disabled
0
1
TCG cleared by falling edge of input capture input signal
1
0
TCG cleared by rising edge of input capture input signal
1
1
TCG cleared by both edges of input capture input signal
(initial value)
Bits 1 and 0: Clock select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
Internal clock: counting on ø/64
0
1
Internal clock: counting on ø/32
1
0
Internal clock: counting on ø/2
1
1
Internal clock: counting on øw/4
220
(initial value)
5. Clock stop register 1 (CKSTPR1)
7
Bit:
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 3: Timer G module standby mode control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP
Description
0
Timer G is set to module standby mode
1
Timer G module standby mode is cleared
9.5.3
(initial value)
Noise Canceler
The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR3.
Figure 9-8 shows a block diagram of the noise canceler.
Sampling
clock
C
Input capture
input signal
C
D
Q
D
Latch
Q
Latch
C
D
C
Q
Latch
D
C
Q
Latch
D
Q
Latch
Match
detector
Noise
canceler
output
∆t
Sampling clock
∆t: Set by CKS1 and CKS0
Figure 9-8 Noise Canceler Block Diagram
221
The noise canceler consists of five latch circuits connected in series and a match detector circuit.
When the noise cancellation function is not used (NCS = 0), the system clock is selected as the
sampling clock When the noise cancellation function is used (NCS = 1), the sampling clock is the
internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the
rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If
all the outputs do not match, the previous value is retained. After a reset, the noise canceler output
is initialized when the falling edge of the input capture input signal has been sampled five times.
Therefore, after making a setting for use of the noise cancellation function, a pulse with at least
five times the width of the sampling clock is a dependable input capture signal. Even if noise
cancellation is not used, an input capture input signal pulse width of at least 2ø or 2ø SUB is
necessary to ensure that input capture operations are performed properly
Note: * An input capture signal may be generated when the NCS bit is modified.
Figure 9-9 shows an example of noise canceler timing.
In this example, high-level input of less than five times the width of the sampling clock at the
input capture input pin is eliminated as noise.
Input capture
input signal
Sampling clock
Noise canceler
output
Eliminated as noise
Figure 9-9 Noise Canceler Timing (Example)
222
9.5.4
Operation
Timer G is an 8-bit timer with built-in input capture and interval functions.
1. Timer G functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
a. Input capture timer operation
When the TMIG bit is set to 1 in port mode register 1 (PMR1), timer G functions as an
input capture timer*.
In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts incrementing on the ø/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0
in TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG
pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected
by IIEGS in TMG is input, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1
at this time, an interrupt request is sent to the CPU. For details of the interrupt, see 3.3.,
Interrupts.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the
input capture signal is high, the OVFH bit is set in TMG; if TCG overflows when the input
capture signal is low, the OVFL bit is set in TMG. If the OVIE bit in TMG is 1 when these
bits are set, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1, timer G sends
an interrupt request to the CPU. For details of the interrupt, see 3.3., Interrupts.
Timer G has a built-in noise canceler that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see 9.5.3, Noise Canceler.
Note: * An input capture signal may be generated when TMIG is modified.
b. Interval timer operation
When the TMIG bit is cleared to 0 in PMR1, timer G functions as an interval timer.
Following a reset, TCG starts incrementing on the ø/64 internal clock. The input clock can
be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG
increments on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit
is set to 1 in TMG. If the OVIE bit in TMG is 1 at this time, IRRTG is set to 1 in IRR2,
and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For
details of the interrupt, see 3.3., Interrupts.
223
2. Increment timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (ø/64, ø/32, ø/2, or øw/4) created by dividing the system clock (ø) or watch
clock (øw).
3. Input capture input timing
a. Without noise cancellation function
For input capture input, dedicated input capture functions are provided for rising and
falling edges.
Figure 9-10 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
Figure 9-10 Input Capture Input Timing (without Noise Cancellation Function)
b. With noise cancellation function
When noise cancellation is performed on the input capture input, the passage of the input
capture signal through the noise canceler results in a delay of five sampling clock cycles
from the input capture input signal edge.
224
Figure 9-11 shows the timing in this case.
Input capture
input signal
Sampling clock
Noise canceler
output
Input capture
signal R
Figure 9-11 Input Capture Input Timing (with Noise Cancellation Function)
4. Timing of input capture by input capture input
Figure 9-12 shows the timing of input capture by input capture input
Input capture
signal
TCG
N-1
N
N+1
Input capture
register
H'XX
N
Figure 9-12 Timing of Input Capture by Input Capture Input
225
5. TGC clear timing
TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input
signal.
Figure 9-13 shows the timing for clearing by both edges.
Input capture
input signal
Input capture
signal F
Input capture
signal R
TCG
N
H'00
Figure 9-13 TCG Clear Timing
226
N
H'00
6. Timer G operation modes
Timer G operation modes are shown in table 9-13.
Table 9-13 Timer G Operation Modes
Reset Active
TCG
Input capture
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
Interval
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
ICRGF
Reset Functions* Functions* Functions/ Functions/ Functions/ Held
halted*
halted*
halted*
Held
ICRGR
Reset Functions* Functions* Functions/ Functions/ Functions/ Held
halted*
halted*
halted*
Held
TMG
Reset Functions
Held
Note:
9.5.5
*
Sleep
Held
Watch
Module
Subactive Subsleep Standby Standby
Operation Mode
Held
Functions Held
Held
When øw/4 is selected as the TCG internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/ø(s). When øw/4 is selected as the TCG internal clock in watch mode, TCG and the
noise canceler operate on the øw/4 internal clock without regard to the ø subclock
(øw/8, øw/4, øw/2). Note that when another internal clock is selected, TCG and the
noise canceler do not operate, and input of the input capture input signal does not result
in input capture.
To operate the timer G in subactive mode or subsleep mode, select øw/4 as the TCG
internal clock and øw/2 as the subclock ø SUB. Note that when other internal clock is
selected, or when øw/8 or øw/4 is selected as the subclock ø SUB, TCG and the noise
canceler do not operate.
Application Notes
1. Internal clock switching and TCG operation
Depending on the timing, TCG may be incremented by a switch between difference internal clock
sources. Table 9-14 shows the relation between internal clock switchover timing (by write to bits
CKS1 and CKS0) and TCG operation.
When TCG is internally clocked, an increment pulse is generated on detection of the falling edge
of an internal clock signal, which is divided from the system clock (ø) or subclock (øw). For this
reason, in a case like No. 3 in table 9-14 where the switch is from a high clock signal to a low
clock signal, the switchover is seen as a falling edge, causing TCG to increment.
227
Table 9-14 Internal Clock Switching and TCG Operation
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
1
Goes from low level to low level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
Write to CKS1 and CKS0
2
Goes from low level to high level
Clock before
switching
Clock before
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
3
Goes from high level to low level
Clock before
switching
Clock before
switching
*
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
228
Table 9-14 Internal Clock Switching and TCG Operation (cont)
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
4
Goes from high level to high level
Clock before
switching
Clock before
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Note:
*
The switchover is seen as a falling edge, and TCG is incremented.
2. Notes on port mode register modification
The following points should be noted when a port mode register is modified to switch the input
capture function or the input capture input noise canceler function.
• Switching input capture input pin function
Note that when the pin function is switched by modifying TMIG in port mode register 1 (PMR1),
which performs input capture input pin control, an edge will be regarded as having been input at
the pin even though no valid edge has actually been input. Input capture input signal input edges,
and the conditions for their occurrence, are summarized in table 9-15.
229
Table 9-15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When TMIG is modified from 0 to 1 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
Generation of falling edge
When TMIG is modified from 1 to 0 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is low, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 1 to 0 after the signal is sampled five times by
the noise canceler
Note: When the P13 pin is not set as an input capture input pin, the timer G input capture input
signal is low.
• Switching input capture input noise canceler function
When performing noise canceler function switching by modifying NCS in port mode register 3
(PMR3), which controls the input capture input noise canceler, TMIG should first be cleared to 0.
Note that if NCS is modified without first clearing TMIG, an edge will be regarded as having been
input at the pin even though no valid edge has actually been input. Input capture input signal input
edges, and the conditions for their occurrence, are summarized in table 9-16.
Table 9-16 Input Capture Input Signal Input Edges Due to Noise Canceler Function
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When the TMIG pin level is switched from low to high while TMIG is
set to 1, then NCS is modified from 0 to 1 before the signal is sampled
five times by the noise canceler
Generation of falling edge
When the TMIG pin level is switched from high to low while TMIG is
set to 1, then NCS is modified from 1 to 0 before the signal is sampled
five times by the noise canceler
230
When the pin function is switched and an edge is generated in the input capture input signal, if this
edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt
request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use.
Figure 9-14 shows the procedure for port mode register manipulation and interrupt request flag
clearing. When switching the pin function, set the interrupt-disabled state before manipulating the
port mode register, then, after the port mode register operation has been performed, wait for the
time required to confirm the input capture input signal as an input capture signal (at least two
system clocks when the noise canceler is not used; at least five sampling clocks when the noise
canceler is used), before clearing the interrupt enable flag to 0. There are two ways of preventing
interrupt request flag setting when the pin function is switched: by controlling the pin level so that
the conditions shown in tables 9-15 and 9-16 are not satisfied, or by setting the opposite of the
generated edge in the IIEGS bit in TMG.
Set I bit to 1 in CCR
Manipulate port mode register
TMIG confirmation time
Clear interrupt request flag to 0
Clear I bit to 0 in CCR
Disable interrupts. (Interrupts can also be disabled by
manipulating the interrupt enable bit in interrupt enable
register 2.)
After manipulating he port mode register, wait for the
TMIG confirmation time (at least two system clocks when
the noise canceler is not used; at least five sampling
clocks when the noise canceler is used), then clear the
interrupt enable flag to 0.
Enable interrupts
Figure 9-14 Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure
231
9.5.6
Timer G Application Example
Using timer G, it is possible to measure the high and low widths of the input capture input signal
as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG.
Figure 9-15 shows an example of the operation in this case.
Input capture
input signal
H'FF
Input capture
register GF
Input capture
register GR
H'00
TCG
Counter cleared
Figure 9-15 Timer G Application Example
232
9.6
Watchdog Timer
9.6.1
Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
1. Features
Features of the watchdog timer are given below.
• Incremented by internal clock source (ø/8192 or øw/32).
• A reset signal is generated when the counter overflows. The overflow period can be set from
from 1 to 256 times 8192/ø or 32/øw (from approximately 4 ms to 1000 ms when ø = 2.00
MHz).
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
2. Block diagram
Figure 9-16 shows a block diagram of the watchdog timer.
ø
PSS
ø/8192
TCW
Internal data bus
TCSRW
øw/32
Notation:
TCSRW: Timer control/status register W
Timer counter W
TCW:
Prescaler S
PSS:
Reset signal
Figure 9-16 Block Diagram of Watchdog Timer
233
3. Register configuration
Table 9-17 shows the register configuration of the watchdog timer.
Table 9-17 Watchdog Timer Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer control/status register W
TCSRW
R/W
H'AA
H'FFB2
Timer counter W
TCW
R/W
H'00
H'FFB3
Clock stop register 2
CKSTP2
R/W
H'FF
H'FFFB
Port mode register 3
PMR3
R/W
H'00
H'FFCA
9.6.2
Register Descriptions
1. Timer control/status register W (TCSRW)
Bit
7
6
5
4
3
2
1
0
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
Initial value
1
0
1
0
1
0
1
0
Read/Write
R
R/W *
R
R/W *
R
R/W*
R
R/W *
Note: * Write is permitted only under certain conditions, which are given in the descriptions of
the individual bits.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7: Bit 6 write inhibit (B6WI)
Bit 7 controls the writing of data to bit 6 in TCSRW.
Bit 7
B6WI
Description
0
Bit 6 is write-enabled
1
Bit 6 is write-protected
This bit is always read as 1. Data written to this bit is not stored.
234
(initial value)
Bit 6: Timer counter W write enable (TCWE)
Bit 6 controls the writing of data to TCW.
Bit 6
TCWE
Description
0
Data cannot be written to TCW
1
Data can be written to TCW
(initial value)
Bit 5: Bit 4 write inhibit (B4WI)
Bit 5 controls the writing of data to bit 4 in TCSRW.
Bit 5
B4WI
Description
0
Bit 4 is write-enabled
1
Bit 4 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 4: Timer control/status register W write enable (TCSRWE)
Bit 4 controls the writing of data to TCSRW bits 2 and 0.
Bit 4
TCSRWE
Description
0
Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
(initial value)
Bit 3: Bit 2 write inhibit (B2WI)
Bit 3 controls the writing of data to bit 2 in TCSRW.
Bit 3
B2WI
Description
0
Bit 2 is write-enabled
1
Bit 2 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
235
Bit 2: Watchdog timer on (WDON)
Bit 2 enables watchdog timer operation.
Bit 2
WDON
Description
0
Watchdog timer operation is disabled
Clearing conditions:
Reset, or when TCSRWE = 1 and 0 is written in both B2WI and
WDON
1
Watchdog timer operation is enabled
Setting conditions:
When TCSRWE = 1 and 0 is written in B2WI and 1 is written in
WDON
(initial value)
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1: Bit 0 write inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI
Description
0
Bit 0 is write-enabled
1
Bit 0 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 0: Watchdog timer reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES pin, or when software writes 0.
Bit 0
WRST
Description
0
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST
1
Setting conditions:
When TCW overflows and an internal reset signal is generated
236
2. Timer counter W (TCW)
Bit
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input
clock is ø/8192 or øw/32. The TCW value can always be written or read by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
3. Clock stop register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
AECKSTP WDCKSTP PWCKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other
bits, see the sections on the relevant modules.
Bit 2: Watchdog timer module standby mode control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP
Description
0
Watchdog timer is set to module standby mode
1
Watchdog timer module standby mode is cleared
(initial value)
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
237
4. Port mode register 3 (PMR3)
PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3
pins. Only the bit relating to the watchdog timer is described here. For details of the other bits,
see section 8, I/O Ports.
Bit 5: Watchdog timer source clock select (WDCKS)
WDCKS
Description
0
ø/8192 selected
1
øw/32 selected
9.6.3
(initial value)
Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (ø/8192 or
øw/32). The input clock is selected by bit WDCKS in port mode register 3 (PMR3): ø/8192 is
selected when WDCKS is cleared to 0, and øw/32 when set to 1. When TCSRWE = 1 in TCSRW,
if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When
the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow,
and an internal reset signal is generated one base clock (ø or øSUB) cycle later. The internal reset
signal is output for 512 clock cycles of the øOSC clock. It is possible to write to TCW, causing
TCW to count up from the written value. The overflow period can be set in the range from 1 to
256 input clocks, depending on the value written in TCW.
238
Figure 9-17 shows an example of watchdog timer operations.
Example: ø = 2 MHz and the desired overflow period is 30 ms.
2 × 106
× 30 × 10–3 = 7.3
8192
The value set in TCW should therefore be 256 – 8 = 248 (H'F8).
TCW overflow
H'FF
H'F8
TCW count
value
H'00
Start
H'F8 written
in TCW
H'F8 written in TCW
Reset
Internal reset
signal
512 øOSC clock cycles
Figure 9-17 Typical Watchdog Timer Operations (Example)
9.6.4
Watchdog Timer Operation States
Table 9-18 summarizes the watchdog timer operation states.
Table 9-18 Watchdog Timer Operation States
Operation
Mode
Reset
Active
Sleep
TCW
Reset
Functions
Functions Halted
Functions/ Halted
Halted*
Halted
Halted
TCSRW
Reset
Functions
Functions Retained
Functions/ Retained
Halted*
Retained
Retained
Note:
*
Watch
Subactive Subsleep Standby
Module
Standby
Functions when øw/32 is selected as the input clock.
239
9.7
Asynchronous Event Counter (AEC)
9.7.1
Overview
The asynchronous event counter is incremented by external event clock input.
1. Features
Features of the asynchronous event counter are given below.
• Can count asynchronous events
• Can count external events input asynchronously without regard to the operation of base clocks
ø and øSUB.
• The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
240
2. Block diagram
Figure 9-18 shows a block diagram of the asynchronous event counter.
IRREC
OVH
ECH
CK
ECL
CK
AEVH
Internal data bus
ECCSR
OVL
AEVL
Notation:
ECCSR : Event counter control/status register
: Event counter H
ECH
: Event counter L
ECL
AEVH : Asynchronous event input H
: Asynchronous event input L
AEVL
IRREC : Event counter overflow interrupt request flag
Figure 9-18 Block Diagram of Asynchronous Event Counter
3. Pin configuration
Table 9-19 shows the asynchronous event counter pin configuration.
Table 9-19 Pin Configuration
Name
Abbrev. I/O
Function
Asynchronous event input H
AEVH
Input
Event input pin for input to event counter H
Asynchronous event input L
AEVL
Input
Event input pin for input to event counter L
241
4. Register configuration
Table 9-20 shows the register configuration of the asynchronous event counter.
Table 9-20 Asynchronous Event Counter Registers
Name
Abbrev.
R/W
Initial Value
Address
Event counter control/status register
ECCSR
R/W
H'00
H'FF95
Event counter H
ECH
R
H'00
H'FF96
Event counter L
ECL
R
H'00
H'FF97
Clock stop register 2
CKSTP2
R/W
H'FF
H'FFFB
9.7.2
Register Descriptions
1. Event counter control/status register (ECCSR)
Bit
7
6
5
4
3
2
1
0
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
242
Bit 7: Counter overflow flag H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0
ECH has not overflowed
Clearing conditions:
After reading OVH = 1, cleared by writing 0 to OVH
1
ECH has overflowed
Setting conditions:
Set when ECH overflows from H'FF to H'00
(initial value)
Bit 6: Counter overflow flag L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Bit 6
OVL
Description
0
ECL has not overflowed
Clearing conditions:
After reading OVL = 1, cleared by writing 0 to OVL
1
ECL has overflowed
Setting conditions:
Set when ECL overflows from H'FF to H'00 while CH2 is set to 1
(initial value)
Bit 5: Reserved bit
Bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset.
243
Bit 4: Channel select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin as
asynchronous event input. In this case, the overflow signal from ECL is selected as the ECH input
clock. When CH2 is set to 1, ECH and ECL function as independent 8-bit event counters which
are incremented each time an event clock is input to the AEVH or AEVL pin, respectively, as
asynchronous event input.
Bit 4
CH2
Description
0
ECH and ECL are used together as a single-channel 16-bit event counter
(initial value)
1
ECH and ECL are used as two independent 8-bit event counter channels
Bit 3: Count-up enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
Description
0
ECH event clock input is disabled
ECH value is held
1
ECH event clock input is enabled
(initial value)
Bit 2: Count-up enable L (CUEL)
Bit 3 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
Description
0
ECL event clock input is disabled
ECL value is held
1
ECL event clock input is enabled
244
(initial value)
Bit 1: Counter reset control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0
ECH is reset
1
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0: Counter reset control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
Description
0
ECL is reset
1
ECL reset is cleared and count-up function is enabled
(initial value)
2. Event counter H (ECH)
Bit
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source by bit CH2. ECH can be cleared to H'00 by
software, and is also initialized to H'00 upon reset.
245
3. Event counter L (ECL)
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin is used as the input clock source.
ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Bit
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
2
1
0
4. Clock stop register 2 (CKSTPR2)
Bit
7
6
5
4
3
—
—
—
—
Initial value
1
1
1
1
AECKSTP WDCKSTP PWCKSTP LDCKSTP
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3: Asynchronous event counter module standby mode control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
246
(initial value)
9.7.3
Operation
1. 16-bit event counter operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Figure
9-19 shows an example of the software processing when ECH and ECL are used as a 16-bit event
counter.
Start
Clear CH2 to 0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9-19 Example of Software Processing when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset.
They can also be used as a 16-bit event counter by carrying out the software processing shown in
the example in figure 9-19. The operating clock source is asynchronous event input from the
AEVL pin. When the next clock is input after the count value reaches H'FF in both ECH and
ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the
ECH and ECL count values each return to H'00, and counting up is restarted. When overflow
occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt
request is sent to the CPU.
247
2. 8-bit event counter operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
Figure 9-20 shows an example of the software processing when ECH and ECL are used as 8-bit
event counters.
Start
Set CH2 to 1
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9-20 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9-20. The 8-bit event counter operating clock source is asynchronous
event input from the AEVH pin for ECH, and asynchronous event input from the AEVL pin for
ECL. When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the
OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted.
Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows,
the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is
restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is
1 at this time, an interrupt request is sent to the CPU.
248
9.7.4.
Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9-21.
Table 9-21 Asynchronous Event Counter Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
ECCSR
Functions
Functions
Held*1
Functions
Functions
Held*1
ECH
ECL
Note:
Reset
Reset
Reset
Functions
Functions
Module
Standby
Held
1
1
Functions
Functions* Halted
1
1
Functions
Functions*1 Halted
Functions* Functions* Functions
Functions* Functions* Functions
1
1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
249
9.7.5
Application Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR to
prevent asynchronous event input to the counter. The correct value will not be returned if the
event counter increments while being read. Note that ECH and ECL counter may be
incremented by 1 when clearing CUEH and CUEL to 0 in ECCSR.
2. The maximum clock frequencies to be input to AEVH and AEVL pins with the internal power
supply step-down circuir not used are: 6 MHz when VCC = 4.5 to 5.5 V, 4 MHz when VCC = 3.0
to 5.5V, and 3.2 MHz when VCC = 2.6 to 5.5 V. The maximum clock frequency with the
internal power supply step-down circuit used is 2 MHz when VCC = 2.2 to 5.5 V. Otherwise,
ensure that the maximum frequency is 1 MHz. In addition, ensure that the high and low widths
of the clock are at least 83 ns. The duty cycle is immaterial.
Mode
Maximum AEVH/AEVL Pin
Input Clock Frequency
16-bit mode
When not using the internal
8-bit mode Active (high-speed), sleep (high-speed)
step-down circuit
VCC = 4.5 to 5.5 V/6 MHz
VCC = 3.0 to 5.5 V/4 MHz
VCC = 2.6 to 5.5 V/3.2 MHz
VCC = 2.2 to 5.5 V/2 MHz
Others/1 MHz
When using the internal
step-down circuit
VCC = 2.2 to 5.5 V/2 MHz
Others/1 MHz
8-bit mode Active (medium-speed), sleep (medium-speed) (ø/16)
f OSC = 400 kHz to 4 MHz
8-bit mode Watch, subactive, subsleep, standby
øw = 32.768 kHz or 38.4 kHz
2 · fOSC
(ø/32)
f OSC
(ø/64)
1/2 · f OSC
(ø/128) 1/4 · f OSC
(øw/2)
1000 kHz
(øw/4)
500 kHz
(øw/8)
250 kHz
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur.
250
Section 10 Serial Communication Interface
10.1
Overview
The H8/3887 Series is provided with three serial communication interface (SCI) channels. The
functions of the three SCI channels are summarized in table 10-1.
Table 10-1 Overview of SCI Functions
SCI Name Functions
Features
SCI1
Synchronous serial transfer functions
• Choice of transfer data length (8 or 16
bits)
• Continuous clock output function
SCI31,
SCI32
Synchronous serial transfer functions
• 8-bit transfer data length
• Transmission/reception/simultaneous
transmission and reception
• Choice of 8 internal clocks (ø/1024 to
ø/4, øW/4) or external clock
• Open-drain output option
• Interrupt generated on completion of
transfer
• On-chip baud rate generator
• Receive error detection
• Break detection
• Interrupt generated on completion of
transfer or in case of error
Asynchronous serial transfer functions
• Multiprocessor communication function
• Choice of transfer data length (7 or 8
bits)
• Choice of stop bit length (1 or 2 bits)
• Parity addition function
251
10.2
SCI1
10.2.1
Overview
Serial communication interface 1 (SCI1) can carry out 8-bit or 16-bit serial data transfer in
synchronous mode. It is also provided with a communication function called a Synchronized
Serial Bus (SSB) that enables a number of ICs to be controlled.
1. Features
Features of SCI1 are listed below.
• Choice of 8-bit or 16-bit transfer data length
• Choice of 8 internal clocks (ø/1024, ø/256, ø/64, ø/32, ø/16, ø/8, ø/4, or øW /4) or external clock
as clock source
• Interrupt request generated on completion of transfer
• Choice of hold mode or latch mode in SSB mode
252
2. Block Diagram
Figure 10-1 shows a block diagram of SCI1.
ø
PSS
SCK1
SCR1
Transmit/receive
control circuit
SCSR1
Transfer bit counter
SI1
Transfer bit counter
øW/4
SDRU
SDRL
SO1
IRRS1
Notation:
SCR1:
SCSR1:
SDRU:
SDRL:
IRRS1:
PSS:
Serial control register 1
Serial control status register 1
Serial data register U
Serial data register L
Serial 1 interrupt request flag
Prescaler S
Figure 10-1 SCI1 Block Diagram
253
3. Pin configuration
Table 10-2 shows the SCI1 pin configuration.
Table 10-2 SCI1 Pin Configuration
Name
Abbrev.
I/O
Function
SCI1 clock
SCK 1
I/O
SCI1 clock input/output
SCI1 data input
SI 1
Input
SCI1 receive data input
SCI1 data output
SO1
Output
SCI1 transmit data output
4. Register configuration
Table 10-3 shows the SCI1 register configuration.
Table 10-3 Registers
Name
Abbrev.
R/W
Initial Value
Address
Serial control register 1
SCR1
R/W
H'00
H'FFA0
Serial control status register 1
SCSR1
R/W
H'9C
H'FFA1
Serial data register U
SDRU
R/W
Undefined
H'FFA2
Serial data register L
SDRL
R/W
Undefined
H'FFA3
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
10.2.2
Register Descriptions
1. Serial control register 1 (SCR1)
Bit
7
6
5
4
3
2
1
0
SNC1
SNC0
MRKON
LTCH
CKS3
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR1 is an 8-bit read/write register that controls the operating mode, serial clock source, and
prescaler division ratio.
Upon reset, SCR1 is initialized to H'00. If this register is written to during transfer, transfer will be
halted.
254
Bits 7 and 6: Operating mode select 1 and 0 (SNC1, SNC0)
Bits 7 and 6 select the operating mode.
Bit 7
SNC1
Bit 6
SNC0
Description
0
0
8-bit synchronous mode
0
1
16-bit synchronous mode
1
0
Continuous clock output mode* 1
1
1
Reserved* 2
(initial value)
Notes: 1. Use pins SI1 and SO1 as ports.
2. Do not set bits SNC1 and SNC0 to 11.
Bit 5: Tail mark control (MRKON)
Bit 5 controls tail mark output after transfer of 8-bit or 16-bit data.
Bit 5
MRKON
Description
0
Tail mark is not output (synchronous mode)
1
Tail mark is output (SSB mode)
(initial value)
Bit 4: LATCH TAIL select (LTCH)
Bit 4 selects whether LATCH TAIL or HOLD TAIL is output as the tail mark when MRKON = 1
(i.e. in SSB mode).
Bit 4
LTCH
Description
0
HOLD TAIL is output
1
LATCH TAIL is output
(initial value)
Bit 3: Clock source select 3 (CKS3)
Bit 3 selects the clock source to be supplied and sets the SCK1 pin to input or output mode.
Bit 3
CKS3
Description
0
Clock source is prescaler S, SCK 1 is output pin
1
Clock source is external clock, SCK1 is input pin
(initial value)
255
Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0)
When CKS3 is cleared to 0, bits 2 to 0 selects the prescaler division ratio and the serial clock
cycle.
Serial Clock Cycle
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Prescaler Division Ratio
ø = 2.5 MHz
0
0
0
ø/1024 (initial value)
409.6 µs
0
0
1
ø/256
102.4 µs
0
1
0
ø/64
25.6 µs
0
1
1
ø/32
12.8 µs
1
0
0
ø/16
6.4 µs
1
0
1
ø/8
3.2 µs
1
1
0
ø/4
1.6 µs
1
1
1
øW/4
122 µs
2. Serial control status register 1 (SCSR1)
Bit
7
6
5
4
3
2
1
0
—
SOL
ORER
—
—
—
MTRF
STF
Initial value
1
0
0
1
1
1
0
0
Read/Write
—
R/W
R/(W)*
—
—
—
R
R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR1 is an 8-bit register that indicates the operational and error status of SCI1.
Upon reset, SCSR1 is initialized to H'9C.
Bit 7: Reserved bit
Bits 7 is reserved; it is always read as 1 and cannot be modified.
256
Bit 6: Extension data bit (SOL)
The SOL bit changes the output level of the SO1 pin. When read, SOL returns the output level of
the SO1 pin. After transfer is completed, SO1 pin output retains the value of the last bit of the
transmit data, and therefore the SO1 pin output level can be changed by manipulating this bit
before or after transmission. However, the SOL bit setting becomes invalid when the next
transmission starts*. Therefore, when changing the SO1 pin output level after transmission, a write
operation must be performed on the SOL bit each time transmission is completed. Writing to this
register during data transfer will cause incorrect operation, so this register should not be
manipulated during transmission.
Note: * The SOL bit setting is also invalid in SSB mode.
Bit 6
SOL
Description
0
Read
SO1 pin output level is low
Write
Changes SO 1 pin output to low level
Read
SO1 pin output level is high
Write
Changes SO 1 pin output to high level
1
(initial value)
Bit 5: Overrun error flag (ORER)
Bit 5 indicates that an overrun error has occurred when using an external clock. If extra pulses are
superimposed on the regular serial clock due to extraneous noise, etc., the transfer data cannot be
guaranteed. If the clock is input after transfer is completed, this will be interpreted as an overrun
state and this bit will be set to 1.
Bit 5
ORER
Description
0
Clearing conditions:
After reading ORER = 1, cleared by writing 0 to ORER
(initial value)
1
Setting conditions:
When an external clock is used and the clock is input after transfer is completed
Bits 4 to 2: Reserved bits
Bits 4 to 2 are reserved; they are always read as 0 and cannot be modified.
257
Bit 1: Tail mark transmission flag (MTRF)
When MRKON = 1, bit 1 indicates that a tail mark is being transmitted. MTRF is a read-only bit,
and cannot be modified.
Bit 1
MTRF
Description
0
Idle state, or 8-bit/16-bit data transfer in progress
1
Tail mark transmission in progress
(initial value)
Bit 0: Start flag (STF)
The STF bit controls the start of transfer operations. SCI1 transfer operation is started when this
bit is set to 1.
STF remains set to 1 during transfer and while SCI1 is waiting for a start bit, and is cleared to 0
when transfer ends. It can therefore be used as a busy flag.
Bit 0
STF
Description
0
Read
Transfer operation stopped
Write
Invalid
Read
Transfer operation in progress
Write
Starts transfer operation
1
(initial value)
3. Serial data register U (SDRU)
Bit
7
SDRU7
Initial value
Read/Write
6
5
SDRU6 SDRU5
4
3
SDRU4 SDRU3
2
SDRU2
1
0
SDRU1 SDRU0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRU is an 8-bit read/write register used as the data register for the upper 8 bits in 16-bit transfer
(while SDRL is used for the lower 8 bits).
The data written into SDRU is output to SDRL in LSB-first order. In the replacement process, data
is input LSB-first from the SI1 pin, and the data is shifted in the MSB → LSB direction.
SDRU read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRU is undefined upon reset.
258
4. Serial data register L (SDRL)
Bit
Initial value
7
6
5
4
3
2
1
0
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
In 8-bit transfer, the data written into SDRL is output from the SO1 pin in LSB-first order. In the
replacement process, data is input LSB-first from the SI 1 pin, and the data is shifted in the MSB →
LSB direction.
The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken
from SDRU.
SDRL read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRL is undefined upon reset.
5. Clock stop register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the
sections on the relevant modules.
259
Bit 7: SCI1 module standby mode control (S1CKSTP)
Bit 7 controls setting and clearing of module standby mode for SCI1.
Bit 7
S1CKSTP
Description
0
SCI1 is set to module standby mode* 1
1
SCI1 module standby mode is cleared
Note:
*
10.2.3
(initial value)
Setting to module standby mode resets SCR1, SCSR1, SDRU and SDRL.
Operation
Either 8-bit or 16-bit transfer data can be selected as the transfer format. An internal clock or
external clock can be selected as the clock source. When an external clock is used, overrun errors
can be detected.
1. Clock
The serial clock can be selected from 8 internal clocks or an external clock. When an internal
clock is selected, the SCK1 pin functions as the clock output pin. When continuous clock output
mode is set (SNC1, SNC0 = 10 in SCR1), the clock selected by bits CKS2 to CKS0 (ø/1024 to
øW /4) is output continuously from the SCK1 pin. When an external clock is selected, the SCK1 pin
functions as the clock input pin.
2. Data transfer format
The SCI1 transfer format is shown in figure 10-2. LSB-first transfer is used (i.e. transmission and
reception are performed starting with the least significant bit of the transfer data). Transfer data is
output from one falling edge of the serial clock until the next falling edge. Receive data is latched
at the rising edge of the serial clock.
SCK1
SO1/SI1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Figure 10-2 Transfer Format
260
Bit 6
Bit 7
3. Data transfer operations
Transmitting: The procedure for transmitting data is as follows.
(1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 pin functions. If
necessary, also designate the SO1 pin as an NMOS open-drain output with bit POF1 in PMR2.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) Write the transfer data to SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1
pin.
(5) After transmission is completed, IRRS1 is set to 1 in IRR1.
When an internal clock is used, the serial clock is output from the SCK1 pin simultaneously with
transmit data output. When transmission ends, the serial clock is not output until the start flag is
next set to 1. During this interval, the SO1 pin continuously outputs the last bit of the previous
data.
When an external clock is used, data is transmitted in synchronization with the clock input from
the SCK1 pin. If the serial clock continues to be input after the end of transmission, this is regarded
as an overrun state, and the ORER flag is set to 1 in SCSR1 (consequently, transmission is not
performed).
While transmission is halted, the output value of the SO1 pin can be changed by means of the SOL
bit in SCSR1.
Receiving: The procedure for receiving data is as follows.
(1) Set both SI1 and SCK1 to 1 in PMR2 to designate the SI1 and SCK1 pin functions.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) When STF is set to 1 in SCSR1, SCI1 starts operating and receive data is taken in from the SI1
pin.
261
(4) After reception is completed, IRRS1 is set to 1 in IRR1.
(5) Read the transfer data from SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL
(6) If the serial clock continues to be input after the end of reception, this is regarded as an overrun
state, and the ORER flag is set to 1 in SCSR1 (consequently, reception is not performed).
Simultaneous transmitting and receiving: The procedure for simultaneously transmitting and
receiving data is as follows.
(1) Set SO1, SI1, and SCK1 all to 1 in PMR2 to designate the SO1, SI1, and SCK1 pin functions.
If necessary, also designate the SO1 pin as an NMOS open-drain output with bit POF1 in
PMR2.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) Write the transfer data to SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1
pin, or receive data is input from the SI1 pin.
(5) After transmission/reception is completed, IRRS1 is set to 1 in IRR1.
(6) Read the transfer data from SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL
When an internal clock is used, the serial clock is output from the SCK1 pin simultaneously with
transmit data output. When transmission ends, the serial clock is not output until the start flag is
next set to 1. During this interval, the SO1 pin continuously outputs the last bit of the previous
data.
When an external clock is used, data is transmitted and received in synchronization with the clock
input from the SCK1 pin. If the serial clock continues to be input after the end of
transmission/reception, this is regarded as an overrun state, and the ORER flag is set to 1 in
SCSR1 (consequently, transmission/reception is not performed).
262
While transmission is halted, the output value of the SO1 pin can be changed by means of the SOL
bit in SCSR1.
10.2.4
Operation in SSB Mode
SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables a
number of ICs to be controlled when connected as shown in figure 10-3.
In SSB mode, a tail mark is attached and transmitted following an 8-bit or 16-bit data transfer.
Either HOLD TAIL or LATCH TAIL can be selected as the tail mark.
SCL
H8/3887 SCK1
Series chip SO1
IC-A
IC-B
SDA
SCL
SDA
SCL
SDA
SCL
SDA
IC-C
Figure 10-3 Example of SSB Connections
1. Clock
The serial clock can be selected from 8 internal clocks or an external clock, but since the H8/3887
Series chip provides the clock output, an external clock should not be selected. The transfer rate
can be selected with bits CKS2 to CKS0 in SCR1; since this is also the tail mark transfer rate, the
setting should provide for a serial clock cycle of at least 2 µs.
2. Data transfer format
The SCI1 transfer format is shown in figure 10-4. LSB-first transfer is used (i.e. transmission is
performed starting with the least significant bit of the transfer data). A tail mark is added after an
8-bit or 16-bit transfer.
263
SCK1
SO1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 14
Bit 15
Tail mark
1 frame
Figure 10-4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1)
3. Tail mark
There are two tail marks: HOLD TAIL and LATCH TAIL. The output waveforms of HOLD TAIL
and LATCH TAIL are shown in figure 10-5. Time t in figure 10-5 is determined by the serial
clock cycle set by bits CKS2 to CKS0 in SCR1.
HOLD TAIL
SCK1
t
SO1
t
Bit 14
t
2t
t
t
t
Bit 15
Bit 0
LATCH TAIL
SCK1
t
SO1
Bit 14
t
t
2t
t
t
Bit 15
Figure 10-5 HOLD TAIL and LATCH TAIL Output Waveforms
4. Transmitting
The procedure for transmitting data is as follows.
(1) Set SOL to 1 in SCSR1.
(2) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 pin functions. Set POF1
to 1 in PMR2 to designate the SO1 pin as an NMOS open-drain output.
264
(3) Clear SNC1 in SCR1 to 0, and clear or set SNC0 to 0 or 1, to select 8-bit mode or 16-bit mode.
Set MRKON to 1 in SCR1 to select SSB mode.
(4) Write the transfer data to SDRL/SDRU. Set the tail mark with LTCH in SCR1.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(5) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1
pin.
(6) After 8-bit or 16-bit data has been transmitted, STF is reset to 0 in SCSR1 and at the same time
IRRS1 is set to 1 in IRR2. Following data transmission, the selected tail mark is output. MTRF
is set to 1 in SCSR1 during tail mark output.
Data can be transmitted continuously by repeating steps (4) to (6). Ensure that SCI1 is in the idle
state before modifying the MRKON bit in SCR1.
10.2.5
Interrupt Source
SCI1 has one interrupt source: transfer completion.
When SCI1 completes transfer, IRRS1 is set to 1 in IRR1. The SCI1 interrupt source can be
enabled or disabled by the IENS1 bit in IENR1.
For details, see 3.3, Interrupts.
10.2.6
Application Note
(1) When SCK1 is designated as an input pin and an external clock is selected as the clock source,
the external clock must not be input before transfer operation is started by setting STF to 1 in
SCSR1.
(2) In subactive or subsleep mode, SCI1 can be used only when the CPU operation clock is øW/2.
265
10.3
SCI3
10.3.1
Overview
In addition to SCI1, the H8/3887 Series has two serial communication interfaces, SCI3-1 and
SCI3-2, with identical functions. In this manual, the generic term SCI3 is used to refer to both of
these SCIs.
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode. It is also provided with a multiprocessor communication
function that enables serial data to be transferred among processors.
1. Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
 Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A multiprocessor communication function is also provided, enabling serial data
communication among processors.
There is a choice of 16 data transfer formats.
Data length
7, 8, 5 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Multiprocessor bit
“1” or “0”
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD 3X pin level directly when a framing
error occurs
266
 Synchronous mode
Serial data communication is synchronized with a clock. In his mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length
8 bits
Receive error detection
Overrun errors
• Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error
267
2. Block diagram
Figure 10-6 shows a block diagram of SCI3.
SCK 3x
External
clock
Internal clock (ø/64, ø/16, øw/2, ø)
Baud rate generator
BRC
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD
TSR
TDR
RSR
RDR
Internal data bus
Clock
SPCR
RXD
Interrupt request
(TEI, TXI, RXI, ERI)
Notation:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
SPCR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Serial port control register
Figure 10-6 SCI3 Block Diagram
268
3. Pin configuration
Table 10-4 shows the SCI3 pin configuration.
Table 10-4 Pin Configuration
Name
Abbrev.
I/O
Function
SCI3 clock
SCK 3X
I/O
SCI3 clock input/output
SCI3 receive data input
RXD3X
Input
SCI3 receive data input
SCI3 transmit data output
TXD3X
Output
SCI3 transmit data output
4. Register configuration
Table 10-5 shows the SCI3 register configuration.
Table 10-5 Registers
Name
Abbrev.
R/W
Initial Value
Address
Serial mode register
SMR
R/W
H'00
H'FFA8/FF98
Bit rate register
BRR
R/W
H'FF
H'FFA9/FF99
Serial control register 3
SCR3
R/W
H'00
H'FFAA/FF9A
Transmit data register
TDR
R/W
H'FF
H'FFAB/FF9B
Serial data register
SSR
R/W
H'84
H'FFAC/FF9C
Receive data register
RDR
R
H'00
H'FFAD/FF9D
Transmit shift register
TSR
Protected
—
—
Receive shift register
RSR
Protected
—
—
Bit rate counter
BRC
Protected
—
—
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Serial port control register
SPCR
R/W
H'C0
H'FF91
269
10.3.2
Register Descriptions
1. Receive shift register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
RSR is a register used to receive serial data. Serial data input to RSR from the RXD3X pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
2. Receive data register (RDR)
Bit
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is an 8-bit register that stores received serial data.
When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then able to receive data. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, watch or module standby mode.
270
3. Transmit shift register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD 3X pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is
not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status
register (SSR)).
TSR cannot be read or written directly by the CPU.
4. Transmit data register (TDR)
Bit
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, watch or module standby mode.
271
5. Serial mode register (SMR)
Bit
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, watch or module standby mode.
Bit 7: Communication mode (COM)
Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7
COM
Description
0
Asynchronous mode
1
Synchronous mode
(initial value)
Bit 6: Character length (CHR)
Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous
mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6
CHR
Description
0
8-bit data/5-bit data* 2
1
7-bit data*1/5-bit data*
(initial value)
2
Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits
(bits 7, 6, and 5) of TDR are not transmitted.
272
Bit 5: Parity enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
Description
0
Parity bit addition and checking disabled* 2
1
(initial value)
1/ 2
Parity bit addition and checking enabled* *
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
2. For the case where 5-bit data is selected, see table 10-11.
Bit 4: Parity mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
Description
0
Even parity* 1
1
Odd parity*
(initial value)
2
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
273
Bit 3: Stop bit length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is
only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is
invalid since stop bits are not added.
Bit 3
STOP
Description
0
1 stop bit* 1
1
2 stop bits*
(initial value)
2
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2: Multiprocessor mode (MP)
Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor
communication function is disabled, the parity settings in the PE and PM bits are invalid. The MP
bit setting is only valid in asynchronous mode. When synchronous mode is selected the MP bit
should be set to 0. For details on the multiprocessor communication function, see 10.1.6,
Multiprocessor Communication Function.
Bit 2
MP
Description
0
Multiprocessor communication function disabled*
1
Note:
274
Multiprocessor communication function enabled*
*
For the case where 5-bit data is selected, see table 10-11.
(initial value)
Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose ø/64, ø/16, ø/2, or ø as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate
register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
ø clock
(initial value)
1
0
1
øW/2 clock* /øW clock*
1
0
ø/16 clock
1
1
ø/64 clock
2
Notes: 1. øW/2 clock is selected in active (medium- and high-speed) or sleep (medium- and highspeed) mode.
2. øW clock is selected in subactive or subsleep mode. SCI3 can be used only when the
øW/2 is selected as the CPU clock in subactive or subsleep mode.
6. Serial control register 3 (SCR3)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, watch or module standby mode.
275
Bit 7: Transmit interrupt enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
Description
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
(initial value)
Bit 6: Receive interrupt enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing
bit RIE to 0.
Bit 6
RIE
Description
0
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial value)
Bit 5: Transmit enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
Description
0
Transmit operation disabled* 1 (TXD pin is I/O port)
1
(initial value)
2
Transmit operation enabled* (TXD pin is transmit data pin)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
276
Bit 4: Receive enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
Description
0
Receive operation disabled* 1 (RXD pin is I/O port)
(initial value)
2
1
Receive operation enabled* (RXD pin is receive data pin)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3: Multiprocessor interrupt enable (MPIE)
Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is
only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR
set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupt request disabled (normal receive operation)
Clearing conditions:
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled*
Note:
*
(initial value)
Receive data transfer from RSR to RDR, receive error detection, and setting of the
RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of
the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor
bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is
received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI
and ERI requests (when bits TIE and RIE in serial control register 3 (SCR3) are set to
1) and setting of the RDRF, FER, and OER flags are enabled.
277
Bit 2: Transmit end interrupt enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
1
Note:
(initial value)
Transmit end interrupt request (TEI) enabled*
*
TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK3X pin.
The combination of CKE1 and CKE0 determines whether the SCK 3X pin functions as an I/O port,
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10-4 in 10.1.3, Operation.
Bit 1
Bit 0
Description
CKE1
CKE0
Communication Mode
Clock Source
SCK3X Pin Function
0
0
Asynchronous
Internal clock
I/O port* 1
Synchronous
Internal clock
Serial clock output* 1
Asynchronous
Internal clock
Clock output* 2
Synchronous
Reserved
Asynchronous
External clock
Clock input* 3
Synchronous
External clock
Serial clock input
Asynchronous
Reserved
Synchronous
Reserved
0
1
1
1
0
1
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
278
7. Serial status register (SSR)
Bit
Initial value
Read/Write
Note: *
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
1
0
0
0
0
1
0
0
R/(W)*
R/(W) *
R/(W)*
R/(W) *
R
R
R/W
R/(W) *
Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7: Transmit data register empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
(initial value)
279
Bit 6: Receive data register full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
(initial value)
0
There is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
1
There is receive data in RDR
Setting conditions:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.
Bit 5: Overrun error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER
Description
0
Reception in progress or completed* 1
Clearing conditions:
After reading OER = 1, cleared by writing 0 to OER
1
An overrun error has occurred during reception* 2
Setting conditions:
When reception is completed with RDRF set to 1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
280
Bit 4: Framing error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER
Description
0
Reception in progress or completed* 1
Clearing conditions:
After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
Setting conditions:
When the stop bit at the end of the receive data is checked for a value
of 1 at the end of reception, and the stop bit is 0* 2
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit
FER set to 1. In synchronous mode, neither transmission nor reception is possible
when bit FER is set to 1.
Bit 3: Parity error (PER)
Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous
mode.
Bit 3
PER
Description
0
Reception in progress or completed* 1
Clearing conditions:
After reading PER = 1, cleared by writing 0 to PER
1
A parity error has occurred during reception* 2
Setting conditions:
When the number of 1 bits in the receive data plus parity bit does not
match the parity designated by bit PM in the serial mode register
(SMR)
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit FER is set to 1.
281
Bit 2: Transmit end (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
Description
0
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmission ended
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is
sent
(initial value)
Bit 1: Multiprocessor bit receive (MPBR)
Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in
asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1
MPBR
Description
0
Data in which the multiprocessor bit is 0 has been received*
1
Data in which the multiprocessor bit is 1 has been received
Note:
*
(initial value)
When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.
Bit 0: Multiprocessor bit transfer (MPBT)
Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous
mode. The bit MPBT setting is invalid when synchronous mode is selected, when the
multiprocessor communication function is disabled, and when not transmitting.
Bit 0
MPBT
Description
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
282
(initial value)
8. Bit rate register (BRR)
Bit
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10-6 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
OSC
32.8 kHz
Bit Rate
(bit/s)
n
N
38.4 kHz
Error
(%) n
2 MHz
2.4576 MHz
4 MHz
N
Error
(%) n
N
Error
(%)
n
N
Error
(%) n
N
Error
(%)
110
Cannot be used,
—
—
—
—
—
—
2
21
–0.83 —
—
—
150
as error exceeds
0
3
0
2
12
0.16
3
3
0
2
25
0.16
200
3%
0
2
0
0
155
0.16
3
2
0
—
—
—
250
—
—
—
0
124
0
0
153
–0.26 0
249
0
300
0
1
0
0
103
0.16
3
1
0
2
12
0.16
600
0
0
0
0
51
0.16
3
0
0
0
103
0.16
1200
—
—
—
0
25
0.16
2
1
0
0
51
0.16
2400
—
—
—
0
12
0.16
2
0
0
0
25
0.16
4800
—
—
—
—
—
—
0
7
0
0
12
0.16
9600
—
—
—
—
—
—
0
3
0
—
—
—
19200
—
—
—
—
—
—
0
1
0
—
—
—
31250
—
—
—
—
—
—
—
—
—
0
1
0
38400
—
—
—
—
—
—
0
0
0
—
—
—
283
Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
OSC
N=
—1
(64 × 2 2n × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of ø OSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10-7.)
Table 10-7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
1
2
0
øW/2* /øW *
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. øW/2 clock is selected in active (medium- and high-speed) or sleep
(medium- and high-speed) mode.
2. øW clock is selected in subactive or subsleep mode. SCI3 can be used only
when the ø W /2 is selected as the CPU clock in subactive or subsleep mode.
3. The error in table 10-6 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
B (rate obtained from n, N, OSC) — R (bit rate in left-hand column in table 10-6.)
R (bit rate in left-hand column in table 10-6.)
Table 10-8 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10-8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
Maximum Bit Rate (bit/s)
n
N
0.0384*
600
0
0
2
31250
0
0
2.4576
38400
0
0
4
62500
0
0
Note:
284
*
When SMR is set up to CKS1 = “0”, CKS0 = “1”.
× 100
Table 10-9 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
Table 10-9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode)
OSC
38.4 kHz
2 MHz
4 MHz
Bit Rate (bit/s) n
N
Error
n
N
Error
n
N
Error
200
0
23
0
—
—
—
—
—
—
250
—
—
—
—
—
—
2
124
0
300
2
0
0
—
—
—
—
—
—
500
—
—
—
—
—
—
1k
0
249
0
—
—
—
2.5k
0
99
0
0
199
0
5k
0
49
0
0
99
0
10k
0
24
0
0
49
0
25k
0
9
0
0
19
0
50k
0
4
0
0
9
0
100k
—
—
—
0
4
0
250k
0
0
0
0
1
0
0
0
0
500k
1M
Blank: Cannot be set.
— : A setting can be made, but an error will result.
* : Continuous transmission/reception is not possible.
285
Notes: The value set in BRR is given by the following equation:
OSC
N=
—1
(8 × 2 2n × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of ø OSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10-10.)
Table 10-10 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
0
øW/2* 1/øW * 2
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. øW/2 clock is selected in active (medium- and high-speed) or sleep (mediumand high-speed) mode.
2. øW clock is selected in subactive or subsleep mode. SCI3 can be used only
when the ø W /2 is selected as the CPU operation clock in subactive or subsleep
mode.
286
9. Clock stop register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 6: SCI3-1 module standby mode control (S31CKSTP)
Bit 6 controls setting and clearing of module standby mode for SCI31.
S31CKSTP
Description
0
SCI3-1 is set to module standby mode* 1
1
SCI3-1 module standby mode is cleared
Note:
(initial value)
1. Setting to module standby mode resets all the registers in SCI31.
Bit 5: SCI3-2 module standby mode control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI32.
S32CKSTP
Description
0
SCI3-2 is set to module standby mode* 1
1
SCI3-2 module standby mode is cleared
Note:
(initial value)
1. Setting to module standby mode resets all the registers in SCI32.
287
10. Serial Port Control Register (SPCR)
Bit
7
6
5
—
—
SPC32
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
SPC31 SCINV3 SCINV2 SCINV1 SCINV0
SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin
input/output data inversion switching. SPCR is initialized to H'C0 by a reset.
Bit 0: RXD 31 pin input data inversion switch
Bit 0 specifies whether or not RXD 31 pin input data is to be inverted.
Bit 0
SCINV0
Description
0
RXD31 input data is not inverted
1
RXD31 input data is inverted
(initial value)
Bit 1: TXD31 pin output data inversion switch
Bit 1 specifies whether or not TXD31 pin output data is to be inverted.
Bit 1
SCINV1
Description
0
TXD31 output data is not inverted
1
TXD31 output data is inverted
(initial value)
Bit 2: RXD 32 pin input data inversion switch
Bit 2 specifies whether or not RXD 32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
288
(initial value)
Bit 3: TXD32 pin output data inversion switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
Bit 4: P35/TXD31 pin function switch (SPC31)
This bit selects whether pin P35/TXD31 is used as P35 or as TXD31.
Bit 4
SPC31
Description
0
Functions as P3 5 I/O pin
1
Functions as TXD 31 output pin*
Note:
*
(initial value)
Set the TE bit in SCR3 after setting this bit to 1.
Bit 5: P42/TXD32 pin function switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P4 2 I/O pin
1
Note:
(initial value)
Functions as TXD 32 output pin*
*
Set the TE bit in SCR3 after setting this bit to 1.
Bits 7 to 6: Reserved bits
Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified.
289
10.3.3
Operation
1. Overview
SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10-11.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10-12.
a. Asynchronous mode
• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The
combination of these parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
b. Synchronous mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.
290
Table 10-11 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
bit 7
COM
bit 6
CHR
bit 2
MP
bit 5
PE
bit 3
STOP Mode
Data
Length
Multiprocessor Parity
Bit
Bit
0
0
0
0
0
Asynchronous 8-bit data No
0
0
0
0
1
mode
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
*
0
*
*
No
Stop Bit
Length
1 bit
2 bits
Yes
1 bit
2 bits
7-bit data
No
1 bit
2 bits
Yes
1 bit
2 bits
8-bit data Yes
No
1 bit
2 bits
5-bit data No
1 bit
2 bits
7-bit data Yes
1 bit
2 bits
5-bit data No
Yes
1 bit
2 bits
Synchronous
mode
8-bit data No
No
No
*: Don’t care
291
Table 10-12 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
bit 7
bit 1
COM
CKE1 CKE0 Mode
0
0
0
0
0
1
0
1
0
1
0
0
1
1
0
Synchronous
mode
0
1
1
Reserved (Do not specify these combinations)
1
0
1
1
1
1
292
bit 0
Transmit/Receive Clock
Clock Source SCK3X Pin Function
Asynchronous Internal
mode
I/O port (SCK3X pin not used)
Outputs clock with same frequency as bit rate
External
Outputs clock with frequency 16 times bit rate
Internal
Outputs serial clock
External
Inputs serial clock
c. Interrupts and continuous transmission/reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10-13.
Table 10-13 Transmit/Receive Interrupts
Interrupt Flags
Interrupt Request Conditions
Notes
RXI
RDRF
RIE
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10-7 (a).)
The RXI interrupt routine reads the
receive data transferred to RDR
and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.
TXI
TDRE
TIE
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10-7 (b).)
The TXI interrupt routine writes the
next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations
until the data transferred to TSR
has been transmitted.
TEI
TEND
TEIE
When the last bit of the character in TSR
is transmitted, if bit TDRE is set to 1, bit
TEND is set to 1. If bit TEIE is set to 1 at
this time, TEI is enabled and an interrupt
is requested. (See figure 10-7 (c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
293
RDR
RDR
RSR (reception in progress)
RXD3x pin
RSR↑ (reception completed, transfer)
RXD3x pin
RDRF ← 1
(RXI request when RIE = 1)
RDRF = 0
Figure 10-7 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR (transmission in progress)
TXD3x pin
TSR↓ (transmission completed, transfer)
TXD3x pin
TDRE ← 1
(TXI request when TIE = 1)
TDRE = 0
Figure 10-7 (b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TXD3x pin
TSR (reception completed)
TXD3x pin
TEND = 0
TEND ← 1
(TEI request when TEIE = 1)
Figure 10-7 (c) TEND Setting and TEI Interrupt
294
2. Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided
character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
a. Data transfer format
The general data transfer format in asynchronous communication is shown in figure 10-8.
(LSB)
Serial
data
(MSB)
1
Start
bit
Transmit/receive data
Parity
bit
1 bit
5, 7 or 8 bits
1 bit
or none
Stop
bit(s)
Mark
state
1 or 2 bits
One transfer data unit (character or frame)
Figure 10-8 Data Format in Asynchronous Communication
In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit
period, so that the transfer data is latched at the center of each bit.
Table 10-14 shows the 12 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
295
Table 10-14 Data Transfer Formats (Asynchronous Mode)
SMR
CHR PE
Serial Data Transfer Format and Frame Length
MP
STOP
1
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
0
1
0
S
8-bit data
MPB STOP
S
8-bit data
MPB STOP STOP
S
8-bit data
P
STOP
S
8-bit data
P
STOP STOP
S
5-bit data
STOP
S
5-bit data
STOP STOP
S
7-bit data
STOP
S
7-bit data
STOP STOP
S
7-bit data
MPB STOP
S
7-bit data
MPB STOP STOP
S
7-bit data
P
STOP
P
STOP STOP
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
S
7-bit data
1
1
1
0
S
5-bit data
P
STOP
1
1
1
1
S
5-bit data
P
STOP STOP
Notation:
Start bit
S:
STOP: Stop bit
Parity bit
P:
MPB: Multiprocessor bit
296
2
*: Don’t care
b. Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK3X pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10-12 for details on clock source
selection.
When an external clock is input at the SCK3X pin, the clock frequency should be 16 times the bit
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK 3X pin. In this case
the frequency of the output clock is the same as the bit rate, and the phase is such that the clock
rises at the center of each bit of transmit/receive data, as shown in figure 10-9.
Clock
Serial
data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (1 frame)
Figure 10-9 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-bit data, parity, 2 stop bits)
c. Data transfer operations
• SCI3 initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
297
Figure 10-10 shows an example of a flowchart for initializing SCI3.
Start
Clear bits TE and
RE to 0 in SCR3
1
Set bits CKE1
and CKE0
2
Set data transfer
format in SMR
3
Set value in BRR
1. Set clock selection in SCR3. Be sure to
clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
2. Set the data transfer format in the serial
mode register (SMR).
Wait
Has 1-bit period
elapsed?
Yes
Set bits SPC31 and
SPC32 to 1 in SPCR
4
Set bits TIE, RIE,
MPIE, and TEIE in
SCR3, and set bits
RE and TE to 1
in PMR7
No
3. Write the value corresponding to the
transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
4. Wait for at least one bit period, then set
bits TIE, RIE, MPIE, and TEIE in SCR3,
and set bits RE and TE to 1 in PMR7.
Setting bits TE and RE enables the TXD3x
and RXD3x pins to be used. In asynchronous
mode the mark state is established when
transmitting, and the idle state waiting for
a start bit when receiving.
End
Figure 10-10 Example of SCI3 Initialization Flowchart
298
• Transmitting
Figure 10-11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
Read bit TDRE
in SSR
No
TDRE = 1?
Yes
Write transmit
data to TDR
2
Continue data
transmission?
Yes
2. When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
No
Read bit TEND
in SSR
TEND = 1?
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
No
Yes
3
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to 0
in SCR3
End
Figure 10-11 Example of Data Transmission Flowchart (Asynchronous Mode)
299
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD3x pin using the relevant data transfer format in table 1014. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers
data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame.
If bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted,
is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10-12 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10-12 Example of Operation when Transmitting in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
300
Mark
state
1
• Receiving
Figure 10-13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
1
Read bits OER,
PER, FER in SSR
OER + PER
+ FER = 1?
1. Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
Yes
2. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
No
2
Read bit RDRF
in SSR
RDRF = 1?
3.
No
When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
Yes
Read receive
data in RDR
4
3
Continue data
reception?
Receive error
processing
Yes
No
(A)
Clear bit RE to
0 in SCR3
End
Figure 10-13 Example of Data Reception Flowchart (Asynchronous Mode)
301
Start receive
error processing
4
Overrun error
processing
OER = 1?
Yes
No
FER = 1?
Break?
Yes
No
No
PER = 1?
Yes
4. If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Yes
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD3x pin.
Framing error
processing
No
Clear bits OER, PER,
FER to 0 in SSR
Parity error
processing
(A)
End of receive
error processing
Figure 10-13 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
302
SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10-14. The received data is first placed in RSR in LSB-to-MSB
order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following
checks.
• Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
• Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10-15 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10-15 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbreviation Detection Conditions
Receive Data Processing
Overrun error
OER
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR to RDR
Parity error
PER
When the parity (odd or even) set Receive data is transferred
in SMR is different from that of the from RSR to RDR
received data
303
Figure 10-14 shows an example of the operation when receiving in asynchronous mode.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
LSI
operation
RXI request
User
processing
RDRF
cleared to 0
RDR data read
0 start bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10-14 Example of Operation when Receiving in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
3. Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This
mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.
304
a. Data transfer format
The general data transfer format in synchronous communication is shown in figure 10-15.
*
*
Serial
clock
LSB
Serial
data
Bit 0
Don't
care
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
8 bits
Don't
care
One transfer data unit (character or frame)
Note: High level except in continuous transmission/reception
Figure 10-15 Data Format in Synchronous Communication
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the
MSB, the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity and multiprocessor bits cannot be added.
b. Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK3x pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM
in SMR and bits CKE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK3x pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
305
c. Data transfer operations
• SCI3 initialization
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in “SCI
initialization” under 10.3.3, 2. c. Data transfer operations, and shown in figure 10-10.
• Transmitting
Figure 10-16 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
Read bit TDRE
in SSR
No
TDRE = 1?
Yes
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Write transmit
data to TDR
2
Continue data
transmission?
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
Clear bit TE to 0
in SCR3
End
Figure 10-16 Example of Data Transmission Flowchart (Synchronous Mode)
306
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock
is selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD3x pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags are all cleared to 0 before a
transmit operation.
Figure 10-17 shows an example of the operation when transmitting in synchronous mode.
Serial
clock
Serial
data
Bit 0
Bit 1
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
TXI request
LSI
operation
TDRE cleared
to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10-17 Example of Operation when Transmitting in Synchronous Mode
307
• Receiving
Figure 10-18 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
1
Read bit OER
in SSR
1. Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Yes
OER = 1?
2. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
No
2
Read bit RDRF
in SSR
RDRF = 1?
3. When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
4. If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
Yes
Read receive
data in RDR
4
3
Continue data
reception?
Overrun error
processing
Yes
No
Clear bit RE to
0 in SCR3
End
4
Start overrun
error processing
Overrun error
processing
Clear bit OER to
0 in SSR
End of overrun
error processing
Figure 10-18 Example of Data Reception Flowchart (Synchronous Mode)
308
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check
identifies an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10-15 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10-19 shows an example of the operation when receiving in synchronous mode.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI request
RDRE cleared
to 0
RDR data read
RXI request
ERI request in
response to
overrun error
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 10-19 Example of Operation when Receiving in Synchronous Mode
309
• Simultaneous transmit/receive
Figure 10-20 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read bit TDRE
in SSR
No
TDRE = 1?
2. Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
Yes
Write transmit
data to TDR
3. When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
Read bit OER
in SSR
Yes
OER = 1?
No
2
4. If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit
OER is set to 1.
See figure 10-18 for details on overrun error
processing.
Read bit RDRF
in SSR
No
RDRF = 1?
Yes
Read receive data
in RDR
4
3
Continue data
transmission/reception?
No
Clear bits TE and
RE to 0 in SCR3
End
Overrun error
processing
Yes
Notes: 1. When switching from transmission to simultaneous
transmission/reception, check that SCI3 has finished transmitting and
that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set
bits TE and RE to 1.
2. When switching from reception to simultaneous transmission/reception,
check that SCI3 has finished receiving, clear bit RE to 0, then check
that bit RDRF and the error flags (OER, FER, and PER) are cleared to
0, and finally set bits TE and RE to 1.
Figure 10-20 Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode)
310
4. Multiprocessor Communication Function
The multiprocessor communication function enables data to be exchanged among a number of
processors on a shared communication line. Serial data communication is performed in
asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the
transfer data).
In multiprocessor communication, each receiver is assigned its own ID code. The serial
communication cycle consists of two cycles, an ID transmission cycle in which the receiver is
specified, and a data transmission cycle in which the transfer data is sent to the specified receiver.
These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID
transmission cycle, and 0, a data transmission cycle.
The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver
it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the
transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it
compares the ID code with its own ID code, and if they are the same, receives the transfer data
sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor
bit set to 1 is sent again.
In this way, a number of processors can exchange data among themselves.
Figure 10-21 shows an example of communication between processors using the multiprocessor
format.
311
Sender
Communication line
Serial
data
Receiver A
Receiver B
Receiver C
Receiver D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
(MPB = 1)
ID transmission cycle
(specifying the receiver)
H'AA
(MPB = 0)
Data transmission cycle
(sending data to the receiver
specified buy the ID)
MPB: Multiprocessor bit
Figure 10-21 Example of Inter-Processor Communication Using Multiprocessor Format
(Sending data H'AA to receiver A)
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10-14 for details.
For details on the clock used in multiprocessor communication, see 10.3.3, 2. Operation in
Asynchronous Mode.
• Multiprocessor transmitting
Figure 10-22 shows an example of a flowchart for multiprocessor data transmission. This
procedure should be followed for multiprocessor data transmission after initializing SCI3.
312
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
Read bit TDRE
in SSR
TDRE = 1?
No
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that a
write can be performed before writing data
to TDR. When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Yes
Set bit MPDT
in SSR
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
Write transmit
data to TDR
2
Continue data
transmission?
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then set bit MPBT in SSR to 0 or 1 and
write transmit data to the transmit data
register (TDR). When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
3
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to
0 in SCR3
End
Figure 10-22 Example of Multiprocessor Data Transmission Flowchart
313
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10-14.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1 bit TEND in SSR bit is set to 1, the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10-23 shows an example of the operation when transmitting using the multiprocessor
format.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
MPB
0/1
Stop Start
bit bit
1
0
Transmit
data
D0
D1
MPB
D7
0/1
Stop
bit
Mark
state
1
1
1 frame
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10-23 Example of Operation when Transmitting using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)
• Multiprocessor receiving
Figure 10-24 shows an example of a flowchart for multiprocessor data reception. This procedure
should be followed for multiprocessor data reception after initializing SCI3.
314
Start
1
2
1. Set bit MPIE to 1 in SCR3.
Set bit MPIE to 1
in SCR3
2. Read bits OER and FER in the serial
status register (SSR) to determine if
there is an error. If a receive error has
occurred, execute receive error processing.
Read bits OER
and FER in SSR
OER + FER = 1?
3. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR and compare it with this receiver's
own ID. If the ID is not this receiver's,
set bit MPIE to 1 again. When the RDR
data is read, bit RDRF is cleared to 0
automatically.
Yes
No
3
Read bit RDRF
in SSR
RDRF = 1?
4. Read SSR and check that bit RDRF is
set to 1, then read the data in RDR.
No
5. If a receive error has occurred, read bits
OER and FER in SSR to identify the error,
and after carrying out the necessary error
processing, ensure that bits OER and FER
are both cleared to 0. Reception cannot be
resumed if either of these bits is set to 1.
In the case of a framing error, a break can
be detected by reading the value of the
RXD3x pin.
Yes
Read receive
data in RDR
Own ID?
No
Yes
Read bits OER
and FER in SSR
OER + FER = 1?
Yes
No
4
Read bit RDRF
in SSR
RDRF = 1?
No
Yes
Read receive
data in RDR4
Continue data
reception?
No
5
Receive error
processing
Yes
(A)
Clear bit RE to
0 in SCR3
End
Figure 10-24 Example of Multiprocessor Data Reception Flowchart
315
Start receive
error processing
Overrun error
processing
OER = 1?
Yes
Yes
No
FER = 1?
No
Break?
Yes
No
Framing error
processing
Clear bits OER and
FER to 0 in SSR
End of receive
error processing
(A)
Figure 10-24 Example of Multiprocessor Data Reception Flowchart (cont)
Figure 10-25 shows an example of the operation when receiving using the multiprocessor format.
316
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
RXI request
MPIE cleared
to 0
RDRF cleared
to 0
User
processing
No RXI request
RDR retains
previous state
RDR data read
When data is not
this receiver's ID,
bit MPIE is set to
1 again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
LSI
operation
User
processing
ID1
ID2
RXI request
MPIE cleared
to 0
RDRF cleared
to 0
RDR data read
Data2
RXI request
When data is
this receiver's
ID, reception
is continued
RDRF cleared
to 0
RDR data read
Bit MPIE set to
1 again
(b) When data matches this receiver's ID
Figure 10-25 Example of Operation when Receiving using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)
317
10.3.4
Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10-16.
Table 10-16 SCI3 Interrupt Requests
Interrupt
Abbreviation
Interrupt Request
Vector Address
RXI
Interrupt request initiated by receive data full flag (RDRF)
H'0022/H'0024
TXI
Interrupt request initiated by transmit data empty flag (TDRE)
TEI
Interrupt request initiated by transmit end flag (TEND)
ERI
Interrupt request initiated by receive error flag (OER, FER, PER)
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI
interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see 3.3, Interrupts.
318
10.3.5
Application Notes
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not
yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR
once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the
states shown in table 10-17. If an overrun error is detected, data transfer from RSR to RDR will
not be performed, and the receive data will be lost.
Table 10-17 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
RDRF* OER
FER
PER
Receive Data Transfer
RSR → RDR
Receive Error Status
1
1
0
0
×
0
0
1
0
0
0
0
1
•
•
1
1
1
0
×
Overrun error + framing error
1
1
0
1
×
Overrun error + parity error
0
0
1
1
•
Framing error + parity error
1
1
1
×
Overrun error + framing error + parity error
1
Overrun error
Framing error
Parity error
•:
×:
Receive data is transferred from RSR to RDR.
Receive data is not transferred from RSR to RDR.
Note:
*
Bit RDRF retains its state prior to data reception. However, note that if RDR is read
after an overrun error has occurred in a frame because reading of the receive data in
the previous frame was delayed, RDRF will be cleared to 0.
319
3. Break detection and processing
When a framing error is detected, a break can be detected by reading the value of the RXD3X pin
directly. In a break, the input from the RXD 3X pin becomes all 0s, with the result that bit FER is
set and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark state and break detection
When bit TE is cleared to 0, the TXD3X pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD3X pin to the mark
state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and
PDR = 1. Since bit TE is cleared to 0 at this time, the TXD3X pin functions as an I/O port and 1 is
output.
To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD 3X pin functions as an I/O port, and 0 is output from the TXD3X pin.
5. Receive error flags and transmit operation (synchronous mode only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if
bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate.
When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start
bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock.
This is illustrated in figure 10-26.
320
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RXD3x)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10-26 Receive Data Sampling Timing in Asynchronous Mode
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
M ={(0.5 – 1 ) – D – 0.5 – (L – 0.5) F} 5 100 [%]
2N
N
where
..... Equation (1)
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 — 1/(2 × 16)} × 100 [%]
= 46.875%
..... Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
321
7. Relation between RDR reads and bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed while
bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to
0, if the read operation coincides with completion of reception of a frame, the next frame of data
may be read. This is illustrated in figure 10-27.
Communication
line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 10-27 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To
be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
8. Transmission and Reception Operation at State Transition
Make sure state transition operation is performed after transmission and reception operations are
completed.
322
9. Cautions on Switching of SCK3X Pin Function
If the function of the SCK3X pin is switched from clock output to I/O port after using the SCI3 in
clock synchronization mode, the “low” level is output in a moment (1/2 of the system clock ø) at
the SCK3X pin function switching.
This momentary “low” level output can be avoided in either of the following two methods:
a. When disabling SCK3X pin clock output
When stopping signal transmission, clear the bits TE and RE in SCR3, and set the CKE1
bit to “1” and the CKE0 bit to “0” simultaneously with a single command.
In this case, use the COM bit in SMR set at “1”. This means it cannot be used as an I/O
port. Also, to avoid intermediate potential from being applied to the SCK3X pin, pull up the
line connected to the SCK3X pin to VCC potential with a resistance, or supply an output from
other devices.
b. When switching the SCK3X pin function from clock output to I/O port
When stopping signal transmission,
(1) Clear the bits TE and RE in SCR3, and set the CKE1 bit to “1” and the CKE0 bit to “0”
simultaneously with a single command.
(2) Then, clear the COM bit in SMR to “0”.
(3) Finally, clear the bits CKE1 and CKE0 in SCR3 to “0”. Avoid intermediate potential
from being applied to the SCK3X pin.
10. Setting in Subactive and Subsleep Modes
In subactive or subsleep mode, SCI3 can be used only when the øW/2 is selected as the CPU clock.
Set the SA1 bit in SYSCR2 to “1”.
323
Section 11 14-Bit PWM
11.1
Overview
The H8/3887 Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can
be used as a D/A converter by connecting a low-pass filter.
11.1.1
Features
Features of the 14-bit PWM are as follows.
• Choice of two conversion periods
Any of the following four conversion periods can be chosen:
131,072/ø, with a minimum modulation width of 8/ø (PWCR1 = 1, PWCR0 = 1)
65,536/ø, with a minimum modulation width of 4/ø (PWCR1 = 1, PWCR0 = 0)
32,768/ø, with a minimum modulation width of 2/ø (PWCR1 = 0, PWCR0 = 1)
16,384/ø, with a minimum modulation width of 1/ø (PWCR1 = 0, PWCR0 = 0)
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
11.1.2
Block Diagram
Figure 11-1 shows a block diagram of the 14-bit PWM.
324
PWDRU
ø/2
ø/4
ø/8
ø/16
PWM
waveform
generator
Internal data bus
PWDRL
PWCR
PWM
Notation:
PWDRL: PWM data register L
PWDRU: PWM data register U
PWCR: PWM control register
Figure 11-1 Block Diagram of the 14 bit PWM
11.1.3
Pin Configuration
Table 11-1 shows the output pin assigned to the 14-bit PWM.
Table 11-1 Pin Configuration
Name
Abbrev.
I/O
Function
PWM output pin
PWM
Output
Pulse-division PWM waveform output
11.1.4
Register Configuration
Table 11-2 shows the register configuration of the 14-bit PWM.
Table 11-2 Register Configuration
Name
Abbrev.
R/W
Initial Value
Address
PWM control register
PWCR
W
H'FC
H'FFD0
PWM data register U
PWDRU
W
H'C0
H'FFD1
PWM data register L
PWDRL
W
H'00
H'FFD2
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
325
11.2
Register Descriptions
11.2.1
PWM Control Register (PWCR)
Bit
7
6
5
4
3
2
—
—
—
—
—
—
1
0
PWCR1 PWCR0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
PWCR is an 8-bit write-only register for input clock selection.
Upon reset, PWCR is initialized to H'FC.
Bits 7 to 2: Reserved bits
Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified.
Bits 1 and 0: Clock select 1 and 0 (PWCR1, PWCR0)
Bits 1 and 0 select the clock supplied to the 14-bit PWM. These bits are write-only bits; they are
always read as 1.
Bit 1
PWCR1
Bit 0
PWCR0
0
0
The input clock is ø/2 (tø* = 2/ø)
(initial value)
The conversion period is 16,384/ø, with a minimum modulation
width of 1/ø
0
1
The input clock is ø/4 (tø* = 4/ø)
The conversion period is 32,768/ø, with a minimum modulation
width of 2/ø
1
0
The input clock is ø/8 (tø* = 8/ø)
The conversion period is 65,536/ø, with a minimum modulation
width of 4/ø
1
1
The input clock is ø/16 (tø* = 16/ø)
The conversion period is 131,072/ø, with a minimum
modulation width of 8/ø
Description
Note: Period of PWM input clock.
326
11.2.2
PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU
Bit
7
6
—
—
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
7
6
5
4
3
2
1
0
5
4
3
2
1
0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWDRL
Bit
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM
waveform generator, updating the PWM waveform generation data. The 14-bit data should
always be written in the following sequence:
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.
327
11.2.3
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
AECKSTP WDCKSTP PWCKSTP LDCKSTP
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1: PWM module standby mode control (PWCKSTP)
Bit 1 controls setting and clearing of module standby mode for the PWM.
PWCKSTP
Description
0
PWM is set to module standby mode
1
PWM module standby mode is cleared
328
(initial value)
11.3
Operation
11.3.1
Operation
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 3 (PMR3) to 1 so that pin P30/PWM is designated for
PWM output.
2. Set bits PWCR1 and PWCR0 in the PWM control register (PWCR) to select a conversion
period of 131,072/ø (PWCR1 = 1, PWCR0 = 1), 65,536/ø (PWCR1 = 1, PWCR0 = 0),
32,768/ø (PWCR1 = 0, PWCR0 = 1), or 16,384/ø (PWCR1 = 0, PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in
the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data
in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11-2. The total of the highlevel pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL.
This relation can be represented as follows.
TH = (data value in PWDRU and PWDRL + 64) × tø/2
where tø is the PWM input clock period: 2/ø (PWCR = H'0), 4/ø (PWCR = H'1), 8/ø (PWCR =
H'2), or 16/ø (PWCR = H'3).
Example: Settings in order to obtain a conversion period of 32,768 µs:
When PWCR1 = 0 and PWCR0 = 0, the conversion period is 16,384/ø, so ø must be 0.5
MHz. In this case, tfn = 512 µs, with 1/ø (resolution) = 2.0 µs.
When PWCR1 = 0 and PWCR0 = 1, the conversion period is 32,768/ø, so ø must be 1
MHz. In this case, tfn = 512 µs, with 2/ø (resolution) = 2.0 µs.
When PWCR1 = 1 and PWCR0 = 0, the conversion period is 65,536/ø , so ø must be 2
MHz. In this case, tfn = 512 µs, with 4/ø (resolution) = 2.0 µs.
Accordingly, for a conversion period of 32,768 µs, the system clock frequency (ø) must
be 0.5 MHz, 1 MHz, or 2 MHz.
329
1 conversion period
t f1
t H1
t f2
t f63
t H2
TH = t H1 + t H2 + t H3 +
t H3
t f64
t H63
t H64
..... t H64
t f1 = t f2 = t f3 ..... = t f84
Figure 11-2 PWM Output Waveform
11.3.2
PWM Operation Modes
PWM operation modes are shown in table 11-3.
Table 11-3 PWM Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
PWCR
Reset
Functions
Functions
Held
Held
Held
Held
Held
PWDRU
Reset
Functions
Functions
Held
Held
Held
Held
Held
PWDRL
Reset
Functions
Functions
Held
Held
Held
Held
Held
330
Section 12 A/D Converter
12.1
Overview
The H8/3887 Series includes on-chip a resistance-ladder-based successive-approximation analogto-digital converter, and can convert up to 12 channels of analog input.
12.1.1
Features
The A/D converter has the following features.
•
•
•
•
•
•
•
10-bit resolution
12 input channels
Conversion time: approx. 15.5 µs per channel (at 2 MHz operation)
Built-in sample-and-hold function
Interrupt requested on completion of A/D conversion
A/D conversion can be started by external trigger input
Use of module standby mode enables this module to be placed in standby mode independently
when not used.
331
12.1.2
Block Diagram
Figure 12-1 shows a block diagram of the A/D converter.
ADTRG
Multiplexer
ADSR
AVCC
+
Comparator
–
AVCC
Reference
voltage
Control logic
Internal data bus
AMR
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
AN 8
AN 9
AN 10
AN 11
AVSS
AVSS
ADRRH
ADRRL
Notation:
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register
IRRAD: A/D conversion end interrupt request flag
Figure 12-1 Block Diagram of the A/D Converter
332
IRRAD
12.1.3
Pin Configuration
Table 12-1 shows the A/D converter pin configuration.
Table 12-1 Pin Configuration
Name
Abbrev.
I/O
Function
Analog power supply
AVCC
Input
Power supply and reference voltage of analog part
Analog ground
AVSS
Input
Ground and reference voltage of analog part
Analog input 0
AN 0
Input
Analog input channel 0
Analog input 1
AN 1
Input
Analog input channel 1
Analog input 2
AN 2
Input
Analog input channel 2
Analog input 3
AN 3
Input
Analog input channel 3
Analog input 4
AN 4
Input
Analog input channel 4
Analog input 5
AN 5
Input
Analog input channel 5
Analog input 6
AN 6
Input
Analog input channel 6
Analog input 7
AN 7
Input
Analog input channel 7
Analog input 8
AN 8
Input
Analog input channel 8
Analog input 9
AN 9
Input
Analog input channel 9
Analog input 10
AN 10
Input
Analog input channel 10
Analog input 11
AN 11
Input
Analog input channel 11
External trigger input
ADTRG
Input
External trigger input for starting A/D conversion
12.1.4
Register Configuration
Table 12-2 shows the A/D converter register configuration.
Table 12-2 Register Configuration
Name
Abbrev.
R/W
Initial Value
Address
A/D mode register
AMR
R/W
H'30
H'FFC6
A/D start register
ADSR
R/W
H'7F
H'FFC7
A/D result register H
ADRRH
R
Not fixed
H'FFC4
A/D result register L
ADRRL
R
Not fixed
H'FFC5
Clock stop register 1
CKSTPRT1
R/W
H'FF
H'FFFA
333
12.2
Register Descriptions
12.2.1
A/D Result Registers (ADRRH, ADRRL)
Bit
5
4
3
2
1
0
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
—
—
—
—
—
—
Not Not
fixed fixed
—
—
—
—
—
—
—
—
—
—
—
—
7
Initial value
Read/Write
R
6
R
5
4
3
2
1
0
7
6
Not Not Not
Not
Not
Not Not Not
fixed fixed fixed fixed fixed fixed fixed fixed
R
R
R
R
R
R
R
R
ADRRL
ADRRH
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2
bits in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
12.2.2
A/D Mode Register (AMR)
Bit
7
6
5
4
3
2
1
0
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
334
Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
Conversion Time
CKS
Conversion Period
ø = 1 MHz
ø = 5 MHz
0
62/ø (initial value)
62 µs
31 µs
31/ø
31 µs
15.5 µs*
1
Note:
*
Operation is not guaranteed if the conversion time is less than 15.5 µs. Set bit 7 for a
value of at least 15.5 µs.
Bit 6: External trigger select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
Disables start of A/D conversion by external trigger
1
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note:
*
(initial value)
The external trigger (ADTRG) edge is selected by bit INTEG4 of IEGR. See 1. IRQ
edge select register (IEGR) in 3.3.2 for details.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
335
Bits 3 to 0: Channel select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Analog Input Channel
0
0
*
*
No channel selected
0
1
0
0
AN 0
0
1
0
1
AN 1
0
1
1
0
AN 2
0
1
1
1
AN 3
1
0
0
0
AN 4
1
0
0
1
AN 5
1
0
1
0
AN 6
1
0
1
1
AN 7
1
1
0
0
AN 8
1
1
0
1
AN 9
1
1
1
0
AN 10
1
1
1
1
AN 11
(initial value)
*: Don’t care
12.2.3
A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.
336
Bit 7: A/D start flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0
Read: Indicates the completion of A/D conversion
(initial value)
Write: Stops A/D conversion
1
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Bits 6 to 0: Reserved bits
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
12.2.4
Clock Stop Register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the A/D converter is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 4: A/D converter module standby mode control (ADCKSTP)
Bit 4 controls setting and clearing of module standby mode for the A/D converter.
ADCKSTP
Description
0
A/D converter is set to module standby mode
1
A/D converter module standby mode is cleared
(initial value)
337
12.3
Operation
12.3.1
A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2
Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE
in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge
select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D
conversion.
Figure 12-2 shows the timing.
ø
Pin ADTRG
(when bit
IEG4 = 0)
ADSF
A/D conversion
Figure 12-2 External Trigger Input Timing
338
12.3.3
A/D Converter Operation Modes
A/D converter operation modes are shown in table 12-3.
Table 12-3 A/D Converter Operation Modes
Operation
Mode
Reset
Active
AMR
Reset
ADSR
Reset
ADRRH
ADRRL
Note:
12.4
Watch
Subactive
Subsleep
Standby
Module
Standby
Functions Functions
Held
Held
Held
Held
Held
Sleep
Functions Functions
Held
Held
Held
Held
Held
Held*
1
Functions Functions
Held
Held
Held
Held
Held
Held*
1
Functions Functions
Held
Held
Held
Held
Held
1. Undefined in a power-on reset.
Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see 3.3, Interrupts.
12.5
Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12-3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored is stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
339
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12-4 and 12-5 show flow charts of procedures for using the A/D converter.
Interrupt
(IRRAD)
Set *
IENAD
ADSF
Channel 1 (AN1)
operation state
A/D conversion starts
Idle
Set *
A/D conversion (1)
Set *
Idle
A/D conversion (2)
Idle
Read conversion result
ADRRH
ADRRL
A/D conversion result (1)
Read conversion result
A/D conversion result (2)
Note: * ( ) indicates instruction execution by software.
Figure 12-3 Typical A/D Converter Operation Timing
340
Start
Set A/D conversion speed
and input channel
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12-4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
341
Start
Set A/D conversion speed
and input channels
Enable A/D conversion
end interrupt
Start A/D conversion
A/D conversion
end interrupt?
No
Yes
Clear bit IRRAD to
0 in IRR2
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12-5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
12.6
Application Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 ø clock
cycles before starting.
342
Section 13 LCD Controller/Driver
13.1
Overview
The H8/3887 Series has an on-chip segment type LCD control circuit, LCD driver, and power
supply circuit, enabling it to directly drive an LCD panel.
13.1.1
Features
1. Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle
Internal Driver
Segment External Expansion Driver
Static
40 seg
256 seg
1/2
40 seg
128 seg
1/3
40 seg
64 seg
1/4
40 seg
64 seg
• LCD RAM capacity
8 bits × 32 bytes (256 bits)
• Word access to LCD RAM
• All eight segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
• Built-in step-up constant-voltage (5 V) power supply allows LCD display even at low voltages
(H8/3887 Series).
343
• A or B waveform selectable by software
13.1.2
Block Diagram
Figure 13-1 shows a block diagram of the LCD controller/driver.
M
ø/2 to ø/256
V0
V1
V2
V3
VSS
CL2
Common
data latch
øw
Internal data bus
LCD drive power supply
(built-in step-up constantvoltage circuit)
Common
driver
COM4
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
SEG36
LPCR
LCR
LCR2
Display timing generator
COM1
40-bit shift
register
CL1
Segment
driver
LCD RAM
(20 bytes)
SEG1
SEGn, DO
Notation:
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 13-1 Block Diagram of LCD Controller/Driver
344
13.1.3
Pin Configuration
Table 13-1 shows the LCD controller/driver pin configuration.
Table 13-1 Pin Configuration
Name
Abbrev.
I/O
Function
Segment output pins
SEG40 to SEG 1
Output
LCD segment drive pins
All pins are multiplexed as port pins
(setting programmable)
Common output pins
COM4 to COM1
Output
LCD common drive pins
Pins can be used in parallel with static
or 1/2 duty
Segment external expansion CL 1
signal pin
Output
Multiplexed as the display data latch
clock, SEG 40
CL 2
Output
Multiplexed as the display data shift
clock, SEG 39
M
Output
Multiplexed as the LCD alternating
signal, SEG 37
DO
Output
Multiplexed as the serial display data,
SEG38
V0, V1, V2, V3
—
Used when a bypass capacitor is
connected externally, and when an
external power supply circuit is used
LCD power supply pins
13.1.4
Register Configuration
Table 13-2 shows the register configuration of the LCD controller/driver.
Table 13-2 LCD Controller/Driver Registers
Name
Abbrev.
R/W
Initial Value
Address
LCD port control register
LPCR
R/W
H'00
H'FFC0
LCD control register
LCR
R/W
H'80
H'FFC1
LCD control register 2
LCR2
R/W
H'60
H'FFC2
LCD RAM
—
R/W
Undefined
H'F740 to H'F753
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
345
13.2
Register Descriptions
13.2.1
LCD Port Control Register (LPCR)
Bit
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
LPCR is initialized to H'00 upon reset.
Bits 7 to 5: Duty cycle select 1 and 0 (DTS1, DTS0), common function select (CMX)
The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether
or not the same waveform is to be output from multiple pins to increase the common drive power
when not all common pins are used because of the duty setting.
Bit 7
DTS1
Bit 6
DTS0
Bit 5
CMX
Duty Cycle
0
0
0
Static
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
346
1/2 duty
1/3 duty
1/4 duty
Common
Drivers
Notes
COM1
(initial value)
Do not use COM4, COM3, and
COM2.
COM4 to COM1
COM4, COM3, and COM 2 output
the same waveform as COM1.
COM2 to COM1
Do not use COM4 and COM3.
COM4 to COM1
COM4 outputs the same waveform
as COM3, and COM 2 outputs the
same waveform as COM1.
COM3 to COM1
Do not use COM4.
COM4 to COM1
Do not use COM4.
COM4 to COM1
—
Bit 4: Expansion Signal Selection (SGX)
Bit 4 (SGX) selects whether the SEG40/CL 1, SEG39/CL 2, SEG38/DO and SEG 37/M pins are used as
segment pins (SEG40 to SEG37) or as segment external expansion signal pins (CL1, CL2, DO and
M).
Bit 4
SGX
Description
0
SEG40 to SEG 37 pins*
1
CL 1, CL 2, DO and M pins
Note:
*
(Initial value)
Functions as ports when SGS3 to SGS0 are set at “0000”.
Bits 3 to 0: Segment driver select 3 to 0 (SGS3 to SGS0)
Bits 3 to 0 select the segment drivers to be used.
Function of Pins SEG40 to SEG1
Bit 4
SGX
SEG40
Bit 3 Bit 2 Bit 1 Bit 0 to
SGS3 SGS2 SGS1 SGS0 SEG33
SEG32
to
SEG25
SEG24
to
SEG17
SEG16
to
SEG9
SEG8
to
SEG1
Notes
0
0
0
0
0
Port
Port
Port
Port
Port
(Initial value)
0
0
0
0
1
SEG
Port
Port
Port
Port
0
0
0
1
*
SEG
SEG
Port
Port
Port
0
0
1
0
*
SEG
SEG
SEG
Port
Port
0
0
1
1
*
SEG
SEG
SEG
SEG
Port
0
1
*
*
*
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
1
1
0
0
0
0
Port(* ) Port
1
0
0
0
1
Do not use
1
0
0
1
*
1
0
1
*
*
1
1
*
*
*
Note:
1. SEG40 to SEG 37 are external expansion pins.
*: Don’t care
347
13.2.2
LCD Control Register (LCR)
Bit
7
6
5
4
3
2
1
0
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and
display data control, and selects the frame frequency.
LCR is initialized to H'80 upon reset.
Bit 7: Reserved bit
Bit 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6: LCD drive power supply on/off control (PSW)
Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a
power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,
or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit.
Bit 6
PSW
Description
0
LCD drive power supply off
1
LCD drive power supply on
(initial value)
Bit 5: Display function activate (ACT)
Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts
operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless
of the setting of the PSW bit. However, register contents are retained.
Bit 5
ACT
Description
0
LCD controller/driver operation halted
1
LCD controller/driver operates
348
(initial value)
Bit 4: Display data control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
Description
0
Blank data is displayed
1
LCD RAM data is display
(initial value)
Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (ø) is halted, and therefore display operations are not
performed if one of the clocks from ø/2 to ø/256 is selected. If LCD display is required in these
modes, øw, øw/2, or øw/4 must be selected as the operating clock.
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Frame Frequency* 2
Operating Clock
ø = 2 MHz
ø = 250 kHz*1
3
0
*
0
0
øw
128 Hz* (initial value)
0
*
0
1
øw/2
64 Hz* 3
0
*
1
*
øw/4
32 Hz* 3
1
0
0
0
ø/2
—
244 Hz
1
0
0
1
ø/4
977 Hz
122 Hz
1
0
1
0
ø/8
488 Hz
61 Hz
1
0
1
1
ø/16
244 Hz
30.5 Hz
1
1
0
0
ø/32
122 Hz
—
1
1
0
1
ø/64
61 Hz
—
1
1
1
0
ø/128
30.5 Hz
—
1
1
1
1
ø/256
—
—
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, øosc/16) mode when ø = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when øw = 32.768 kHz.
349
13.2.3
LCD Control Register 2 (LCR2)
Bit
7
6
5
4
3
2
1
0
LCDAB
—
—
SUPS
CDS3
CDS2
CDS1
CDS0
Initial value
0
1
1
0
0
0
0
0
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
LCR2 is an 8-bit read/write register which controls switching between the A waveform and B
waveform, selects the drive power supply, controls the step-up constant-voltage (5 V) power
supply, and selects the duty cycle of the charge/discharge pulses which control disconnection of
the power supply split-resistance from the power supply circuit.
LCR2 is initialized to H'60 upon reset.
Bit 7: A waveform/B waveform switching control (LCDAB)
Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Bit 7
LCDAB
Description
0
Drive using A waveform
1
Drive using B waveform
(initial value)
Bits 6 and 5: Reserved bits
Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified.
Bit 4: Drive power supply select, step-up constant-voltage (5 V) power supply control (SUPS)
(Applies only to the H8/3887 Series)
When V CC is selected as the drive power supply, the step-up constant-voltage (5 V) power supply
simultaneously stops operating; when 5 V is selected as the drive power supply, the step-up
constant-voltage (5 V) power supply simultaneously operates.
Bit 4
SUPS
Description
0
Drive power supply is VCC, step-up constant-voltage (5 V) power supply halts
(Initial value)
1
Drive power supply is 5 V, step-up constant-voltage (5 V) power supply operates
350
Bits 3 to 0: Charge/discharge pulse duty cycle select (CDS3 to CDS0)
Bit 3
CDS3
Bit 2
CDS2
Bit 1
CDS1
Bit 0
CDS0
Duty Cycle
Notes
0
0
0
0
1
Fixed high
0
0
0
1
1/8
0
0
1
0
2/8
0
0
1
1
3/8
0
1
0
0
4/8
0
1
0
1
5/8
0
1
1
0
6/8
0
1
1
1
0
1
0
*
*
1/16
1
1
*
*
1/32
(initial value)
Fixed low
*: Don’t care
Bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power
supply circuit.
When a 0 duty cycle is selected, the power supply split-resistance is permanently disconnected
from the power supply circuit, so power should be supplied to pins V1, V2, and V3 by an external
circuit.
Figure 13-2 shows the waveform of the charge/discharge pulses. The duty cycle is Tc/Tw.
1 frame
TW
COM1
Tc
Charge/discharge
pulses
Tdc
Tc
: Power supply split-resistance
connected
Tdc : Power supply split-resistance
disconnected
Figure 13-2 Example of A Waveform with 1/2 Duty and 1/2 Bias
351
13.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
AECKSTP WDCKSTP PWCKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0: LCD controller/driver module standby mode control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP
Description
0
LCD controller/driver is set to module standby mode
1
LCD controller/driver module standby mode is cleared
352
(initial value)
13.3
Operation
13.3.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
1. Hardware settings
a. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V 3 as shown in figure 13-3.
VCC
V0
V1
V2
V3
VSS
Figure 13-3 Handling of LCD Drive Power Supply when Using 1/2 Duty
b. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be
suitable for driving a large panel. If the display lacks sharpness when using a large panel,
refer to section 13.3.7, Boosting the LCD Drive Power Supply. When static or 1/2 duty is
selected, the common output drive capability can be increased. Set CMX to 1 when
selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output
the same waveform, and with 1/2 duty the COM 1 waveform is output from pins COM 2 and
COM1, and the COM2 waveform is output from pins COM4 and COM3.
c. Luminance adjustment function (V0 pin)
Connecting a resistance between the V0 and V1 pins enables the luminance to be adjusted.
For details, see 13.3.3, Luminance Adjustment Function (V0 Pin).
353
d. LCD drive power supply setting
With the H8/3887 Series, there are two ways of providing LCD power: by using the onchip power supply circuit, or by using an external circuit. When the on-chip power supply
circuit is used, with the H8/3887 Series, either the power supply voltage (V CC) or a step-up
constant voltage (5 V) can be selected. For details of the step-up constant-voltage power
supply, see 13.3.4, Step-Up Constant-Voltage (5 V) Power Supply.
When the on-chip power supply circuit is used for the LCD drive power supply, the V0 and
V1 pins should be interconnected externally, as shown in figure 13.4 (a).
When an external power supply circuit is used for the LCD drive power supply, connect
the external power supply to the V1 pin, and short the V0 pin to VCC externally, as shown in
figure 13.4 (b).
VCC
VCC
V0
V0
V1
V1
V2
V2
V3
V3
VSS
External power supply
VSS
(a) Using on-chip power supply circuit
(b) Using external power supply circuit
Figure 13-4 Examples of LCD Power Supply Pin Connections
e. Low-power-consumption LCD drive system
Use of a low-power-consumption LCD drive system enables the power consumption
required for LCD drive to be optimized. For details, see 13.3.5, Low-Power-Consumption
LCD Drive System.
f. External expansion of segment
Segment can be expanded by externally connecting the HD66100. For details, see 13.3.8,
Connection with HD66100.
354
2. Software settings
a. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
b. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
c. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see 13.3.6, Operation in
Power-Down Modes.
d. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
e. LCD drive power supply selection
When the on-chip power supply circuit is used, the power supply to be used can be selected
with the SUPS bit. When an external power supply circuit is used, select VCC with the
SUPS bit and turn the LCD drive power supply off with the PSW bit.
355
13.3.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles with the segment not externally expanded are
shown in figures 13-5 to 13-8, and ones with the segments externally expanded are shown in
figures 13-9 to 13-12.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H'F740
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
H'F753
SEG40
SEG40
SEG40
SEG40
SEG39
SEG39
SEG39
SEG39
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 13-5 LCD RAM Map with Segments Not Externally Expanded (1/4 Duty)
356
bit7
bit6
bit5
bit4
H'F740
SEG2
SEG2
H'F753
SEG40
COM3
bit3
bit2
bit1
bit0
SEG2
SEG1
SEG1
SEG1
SEG40
SEG40
SEG39
SEG39
SEG39
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 13-6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty)
357
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
SEG40
SEG40
SEG39
SEG39
SEG38
SEG38
SEG37
SEG37
H'F74A
Space not used for display
H'F753
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13-7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty)
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display
space
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
H'F745
Space not
used for
display
H'F753
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13-8 LCD RAM Map with Segments Not Externally Expanded (Static Mode)
358
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
Expansion
driver
display
space
H'F75F
SEG64
SEG64
SEG64
SEG64
SEG63
SEG63
SEG63
SEG63
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 13-9 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/4 duty)
359
bit7
H'F740
bit6
bit5
bit4
SEG2
SEG2
SEG2
bit3
bit2
bit1
bit0
SEG1
SEG1
SEG1
Expansion
driver
display
space
H'F75F
SEG64
SEG64
SEG64
SEG63
SEG63
SEG63
COM3
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 13-10 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/3 duty)
360
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Expansion
driver
display
space
H'F75F
SEG128
SEG128
SEG127
SEG127
SEG126
SEG126
SEG125
SEG125
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13-11 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/2 duty)
361
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Expansion
driver
display
space
H'F75F
SEG256
SEG255
SEG254
SEG253
SEG252
SEG251
SEG250
SEG249
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13-12 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” static)
362
13.3.3
Luminance Adjustment Function (V0 Pin)
Figure 13-13 shows a detailed block diagram of the LCD drive power supply unit.
The voltage output to the V0 pin is either VCC or the 5 V output from the step-up conversion power
supply circuit. When either of these voltages is used directly as the LCD drive power supply, the
V0 and V1 pins should be shorted. Also, connecting a variable resistance, R, between the V0 and
V1 pins makes it possible to adjust the voltage applied to the V1 pin, and so to provide luminance
adjustment for the LCD panel.
VCC
Step-up constantvoltage power supply
5V
Power supply
selector
V0
R
V1
V2
V3
Note: * Applied only to the
H8/3887 Series.
VSS
Figure 13-13 LCD Drive Power Supply Unit
363
13.3.4
Step-Up Constant-Voltage (5 V) Power Supply
The H8/3887 Series has an on-chip step-up constant-voltage (5 V) power supply which enables a 5
V constant voltage to be obtained independently of VCC. The H8/3847 Series, however, does not
have this type of power supply.
When the SUPS bit is set to 1 in LCD control register 2 (LCR2), the step-up constant-voltage (5
V) power supply operates, and a 5 V constant voltage is output from the V0 pin. Either short the
V0 and V1 pins or connect a resistance to divide the voltage.
Note: The step-up constant-voltage (5 V) power supply must not be used for any purpose other
than the H8/3887 Series’ LCD drive power supply. In addition, when driving a large
panel, the power supply capacity may not be sufficient. In this case, use VCC as the power
supply, or use an external power supply circuit.
13.3.5
Low-Power-Consumption LCD Drive System
The use of the built-in split-resistance is normally the easiest method for implementing the LCD
power supply circuit, but since the built-in resistance is fixed, a certain direct current flows
constantly from the built-in resistance’s V CC to VSS . As this current does not depend on the current
dissipation of the LCD panel, if an LCD panel with a small current dissipation is used, a wasteful
amount of power will be consumed. The H8/3887 Series is equipped with a function to minimize
this waste of power. Use of this function makes it possible to achieve the optimum power supply
circuit for the LCD panel’s current dissipation.
1. Principles
1. Capacitors are connected as external circuits to LCD power supply pins V1, V2, and V3, as
shown in figure 13-14.
2. The capacitors connected to V1, V2, and V3 are repeatedly charged and discharged in the
cycle shown in figure 13-14, maintaining the potentials.
3. At this time, the charged potential is a potential corresponding to the V1, V2, and V3 pins,
respectively. (For example, with 1/3 bias drive, the charge for V2 is 2/3 that of V1, and that
for V3 is 1/3 that of V1.)
4. Power is supplied to the LCD panel by means of the charges accumulated in these
capacitors.
5. The capacitances and charging/discharging periods of these capacitors are therefore
determined by the current dissipation of the LCD panel.
6. The charging and discharging periods can be selected by software.
364
2. Example of operation (with 1/3 bias drive)
1. During charging period Tc in the figure, the potential is divided among pins V1, V2, and
V3 by the built-in split-resistance (the potential of V2 being 2/3 that of V1, and that of V3
being 1/3 that of V1), as shown in figure 13-14, and external capacitors C1, C2, and C3 are
charged. The LCD panel is continues to be driven during this time.
2. In the following discharging period, Tdc, charging is halted and the charge accumulated in
each capacitor is discharged, driving the LCD panel.
3. At this time, a slight voltage drop occurs due to the discharging; optimum values must be
selected for the charging period and the capacitor capacitances to ensure that this does not
affect the driving of the LCD panel.
4. In this way, the capacitors connected to V1, V2, and V3 are repeatedly charged and
discharged in the cycle shown in figure 13-14, maintaining the potentials and continuously
driving the LCD panel.
5. As can be seen from the above description, the capacitances and charging/discharging
periods of the capacitors are determined by the current dissipation of the LCD panel used.
The charging/discharging periods can be selected with bits CDS3 to CDS0.
6. The actual capacitor capacitances and charging/discharging periods must be determined
experimentally in accordance with the current dissipation requirements of the LCD panel.
An optimum current value can be selected, in contrast to the case in which a direct current
flows constantly in the built-in split-resistance.
Charging
period Tc
Discharging
period Tdc
Vd1
V1 potential
V0
V1
V2 potential
C1
V2
V1×2/3
Voltage drop
associated with
discharging due
to LCD panel
driving
Vd2
C2
V3 potential
V3
C3
V1×1/3
Vd3
Power supply voltage fluctuation in 1/3 bias system
Figure 13-14 Example of Low-Power-Consumption LCD Drive Operation
365
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
V1
V2
V3
VSS
COM4
SEGn
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
VSS
V1
VSS
(d) Waveform with static output
(c) Waveform with 1/2 duty
Figure 13-15 Output Waveforms for Each Duty Cycle (A Waveform)
366
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
COM4
V1
V2
V3
VSS
SEGn
1 frame
1 frame
1 frame
1 frame
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
VSS
V1
VSS
(d) Waveform with static output
(c) Waveform with 1/2 duty
Figure 13-16 Output Waveforms for Each Duty Cycle (B Waveform)
367
Table 13-3 Output Levels
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
13.3.6
Operation in Power-Down Modes
In the H8/3887 Series, the LCD controller/driver can be operated even in the power-down modes.
The operating state of the LCD controller/driver in the power-down modes is summarized in table
13-4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless øw, øw/2, or øw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that øw, øw/2, or øw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Table 13-4 Power-Down Modes and Display Operation
Reset Active
Sleep
Watch
Module
Subactive Subsleep Standby Standby
ø
Runs
Runs
Runs
Stops
Stops
Stops
Stops
øw
Runs
Runs
Runs
Runs
Runs
Runs
Stops*1
Mode
Clock
Display ACT = “0”
operation ACT = “1”
Notes:
368
1.
2.
3.
4.
Stops Stops
Stops
Stops Functions Functions
Stops
Stops
Functions Functions
*3
*3
Stops*4
Stops*4
2
Stops
Functions Stops*2
*3
Stops
Stops
Stops*
The subclock oscillator does not stop, but clock supply is halted.
The LCD drive power supply is turned off regardless of the setting of the PSW bit.
Display operation is performed only if øw, øw/2, or øw/4 is selected as the operating clock.
The clock supplied to the LCD stops.
13.3.7
Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case,
the power supply impedance must be reduced. This can be done by connecting bypass capacitors
of around 0.1 to 0.3 µF to pins V 1 to V3, as shown in figure 13-17, or by adding a split-resistance
externally.
VCC
V0
V1
R
H8/3887 Series
R = several kΩ to
several MΩ
V2
R
C= 0.1 to 0.3µF
V3
R
VSS
Figure 13-17 Connection of External Split-Resistance
13.3.8
Connection to HD66100
If the segments are to be expanded externally, an HD66100 should be connected. Connecting one
HD66100 provides 80-segment expansion. When carrying out external expansion, select the
external expansion signal function of pins SEG40 to SEG 37 with the SGX bit in LPCR, and set bits
SGS3 to SGS0 to 0000. Data is output externally from SEG 1 of the LCD RAM. SEG36 to SEG 1
function as ports.
Figure 13-18 shows examples of connection to an HD66100. The output level is determined by a
combination of the data and the M pin output, but these combinations differ from those in the
HD66100. Table 13-3 shows the output levels of the LCD drive power supply, and figures 13-11
and 13-12 show the common and segment waveforms for each duty cycle.
When ACT is cleared to 0, operation stops with CL2 = 0, CL1 = 0, M = 0, and DO at the data value
(1 or 0) being output at that instant. In standby mode, the expansion pins go to the highimpedance (floating) state.
369
When external expansion is implemented, the load in the LCD panel increases and the on-chip
power supply may not provide sufficient current capacity. In this case, measures should be taken
as described in section 13.3.7, Boosting the LCD Drive Power Supply.
370
VCC
VCC
V0
V1
V2
V3
This LSI
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
M
VSS
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
HD66100
(a) 1/3 bias, 1/4 duty or 1/3 duty
VCC
VCC
V0
V1
V2
V3
This LSI
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
M
VSS
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
HD66100
(b) 1/2 duty
VCC
V0
V1
V2
V3
This LSI
VCC
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
M
VSS
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
HD66100
(c) static
Figure 13-18 Connection to HD66100
371
Section 14 Power Supply Circuit
14.1
Overview
The H8/3887 Series incorporates an internal power supply step-down circuit. Use of this circuit
enables the internal power supply to be fixed at a constant level of approximately 1.5 V,
independently of the voltage of the power supply connected to the external VCC pin. As a result,
the current consumed when an external power supply is used at 1.8 V or above can be held down
to virtually the same low level as when used at approximately 1.5 V. It is, of course, also possible
to use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
14.2
When Using the Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between CV CC and V SS , as shown in figure 14-1. The internal step-down circuit is made
effective simply by adding this external circuit.
Notes: 1. In the external circuit interface, the external power supply voltage connected to VCC
and the GND potential connected to VSS are the reference levels. For example, for port
input/output levels, the V CC level is the reference for the high level, and the VSS level is
that for the low level.
2. When the internal power supply step-down circuit is used, operating frequency fosc
when VCC = 2.2 to 5.5 V is 0.4 MHz to 2 MHz. Otherwise, fosc is 0.4 MHz to 1 MHz.
3. The LCD power supply and A/D converter analog power supply are not affected by
internal step-down processing.
VCC
Step-down circuit
Internal
logic
CVCC
Stabilization
capacitance
(approx. 0.1 µF)
Internal
power
supply
VSS
Figure 14-1 Power Supply Connection when Internal Step-Down Circuit Is Used
372
14.3
When Not Using the Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the VCC pin and CVCC pin, as shown in figure 14-2. The external power supply is then input
directly to the internal power supply.
Note: The permissible range for the power supply voltage is 1.8 V to 5.5 V. Operation cannot be
guaranteed if a voltage outside this range (less than 1.8 V or more than 5.5 V) is input.
VCC
Step-down circuit
Internal
logic
CVCC
Internal
power
supply
VSS
Figure 14-2 Power Supply Connection when Internal Step-Down Circuit Is Not Used
373
Section 15 Electrical Characteristics
15.1
Absolute Maximum Ratings (H8/3887 Series, H8/3847 Series)
Table 15-1 lists the absolute maximum ratings.
Table 15-1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
Ports other than Ports B and C
Vin
–0.3 to VCC +0.3
V
Ports B and C
AVin
–0.3 to AVCC +0.3
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics. Exceeding
these values can result in incorrect operation and reduced reliability.
374
15.2
Electrical Characteristics (H8/3887, H8/3847)
15.2.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range of the H8/3887 Series are indicated by the shaded
region in the figures.
38.4
6.0
fW (kHz)
fosc (MHz)
1. Power supply voltage and oscillator frequency range
4.0
3.2
32.768
2.0
1.0
0.4
1.8 2.2 2.6 3.0
4.5
5.5
1.8
5.5
VCC (V)
VCC (V)
• Active (high-speed) mode
3.6
• All operating modes
• Sleep (high-speed) mode
fosc (MHz)
• Internal power supply step-down circuit not used
2.0
1.0
0.4
1.8 2.2
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
• Internal power supply step-down circuit used
375
2. Power supply voltage and operating frequency range
ø (MHz)
3.0
19.2
2.0
1.6
16.384
1.0
0.5
0.2
4.5
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
øSUB (kHz)
9.6
1.8 2.2 2.6 3.0
8.192
4.8
• Internal power supply step-down circuit not used
4.096
ø (kHz)
375
1.8
• Subactive mode
125
• Subsleep mode (except CPU)
• Watch mode (except CPU)
1.8 2.2 2.6 3.0
4.5
5.5
VCC (V)
• Active (medium-speed) mode (except A/D
converter and PWM)
• Sleep (medium-speed) mode (except A/D
converter and PWM)
• Internal power supply step-down circuit not used
ø (MHz)
1.0
0.5
0.2
1.8 2.2
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
• Internal power supply step-down circuit used
125
ø (kHz)
5.5
VCC (V)
62.5
4.096
62.5
4.096
1.8 2.2
5.5
VCC (V)
• Active (medium-speed) mode (except A/D
converter and PWM)
• Sleep (medium-speed) mode (except A/D
converter and PWM)
• Internal power supply step-down circuit used
376
3.6
250
200
3. Analog power supply voltage and A/D converter operating range
ø (kHz)
ø (MHz)
2.0
250
200
0.5
0.2
1.8
3.0
4.5
1.8
5.5
3.0
5.5
AVCC (V)
AVCC (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Internal power supply step-down circuit
• Internal power supply step-down circuit
not used
ø (MHz)
4.5
not used
1.0
0.5
0.2
1.8
3.0
4.5
5.5
AVCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
• Internal power supply step-down circuit used
377
15.2.2
DC Characteristics
Table 15-2 lists the DC characteristics of the H8/3887 Series.
Table 15-2 DC Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Input
VIH
high
voltage
Min
Typ
Max
Unit Test Condition
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
0.8 V CC
—
VCC + 0.3
V
TMIG, SCK1, SCK31 ,
SCK32, ADTRG
0.9 V CC
—
VCC + 0.3
SI 1, RXD31 , RXD32 , UD 0.7 V CC
—
VCC + 0.3
0.8 V CC
—
VCC + 0.3
0.8 V CC
—
VCC + 0.3
0.9 V CC
—
VCC + 0.3
OSC1
X1
Except the above
V
VCC = 4.0 to 5.5 V
Except the above
V
VCC = 4.0 to 5.5 V
Except the above
0.9 V CC
—
VCC + 0.3
V
VCC = 1.8 to 5.5 V
P10 to P17, P20 to P27, 0.7 V CC
P30 to P37, P40 to P43,
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
P50 to P57, P60 to P67, 0.8 V CC
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
VCC + 0.3
Except the above
PB 0 to PB7,
0.7 V CC
—
AV CC + 0.3
VCC = 4.0 V to 5.5 V
PC0 to PC3
0.8 V CC
—
AV CC + 0.3
Except the above
Note: Connect the TEST pin to VSS .
378
VCC = 4.0 to 5.5 V
Notes
Table 15-2 DC Characteristics (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
–0.3
—
0.2 V CC
V
TMIG, SCK1, SCK31 ,
SCK32, ADTRG
–0.3
—
0.1 V CC
SI 1, RXD31 , RXD32 , UD –0.3
—
0.3 V CC
–0.3
—
0.2 V CC
–0.3
—
0.2
V
Internal power supply
step-down circuit used
–0.3
—
0.2 V CC
V
VCC = 4.0 to 5.5 V
–0.3
—
0.1 V CC
–0.3
—
0.1 V CC
V
VCC = 1.8 to 5.5 V
P10 to P17, P20 to P27, –0.3
P30 to P37, P40 to P43,
P50 to P57, P60 to P67,
—
0.3 V CC
V
VCC = 4.0 V to 5.5 V
P70 to P77, P80 to P87, –0.3
P90 to P97, PA0 to PA3,
PB 0 to PB7,
PC0 to PC3
—
0.2 V CC
Output VOH
high
P10 to P17, P20 to P27, VCC – 1.0
P30 to P37, P40 to P42,
—
—
voltage
P50 to P57, P60 to P67, VCC – 0.5
P70 to P77, P80 to P87,
—
—
VCC = 4.0 V to 5.5 V
–I OH = 0.5 mA
P90 to P97, PA0 to PA3 VCC – 0.3
—
—
–I OH = 0.1 mA
Input
VIL
low
voltage
OSC1
X1
Notes
VCC = 4.0 to 5.5 V
Except the above
V
VCC = 4.0 to 5.5 V
Except the above
Except the above
Except the above
V
VCC = 4.0 V to 5.5 V
–I OH = 1.0 mA
379
Table 15-2 DC Characteristics (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Output VOL
low
Typ
Max
Unit Test Condition
P10 to P17, P40 to P42 —
—
0.6
V
—
—
0.5
IOL = 0.4 mA
P50 to P57, P60 to P67, —
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
0.5
IOL = 0.4 mA
P20 to P27, P30 to P37 —
—
1.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.6
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
—
—
20.0
—
—
1.0
OSC1, X1, P10 to P17, —
P20 to P27, P30 to P37,
P40 to P42, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P90 to P97,
PA 0 to PA3
—
1.0
PB 0 to PB7,
PC0 to PC3
—
1.0
voltage
Input/
| I IL |
RES, P43
output
leakage
current
Min
—
µA
µA
Notes
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
VIN = 0.5 V to
*2
VCC – 0.5 V
*1
VIN = 0.5 V to
VCC – 0.5 V
VIN = 0.5 V to
AV CC – 0.5 V
µA
Pull-up –Ip
P10 to P17, P30 to P37, 50.0
—
300.0
MOS
current
P50 to P57, P60 to P67, —
35.0
—
Input
CIN
capacitance
All input pins except
power supply, RES,
P43, PB0 to PB7
—
—
15.0
RES
—
—
80.0
*2
—
—
15.0
*1
—
—
50.0
*2
—
—
15.0
*1
—
—
15.0
P43
PB 0 to PB7
380
VCC = 5 V, VIN = 0 V
VCC = 2.7 V, VIN = 0 V
pF
Reference
value
f = 1 MHz, VIN =0 V,
Ta = 25°C
Table 15-2 DC Characteristics (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
Notes
Active IOPE1
mode
current
dissi-
VCC
—
0.7
1.0
mA
Active (high- speed)
mode
VCC = 5 V,
fOSC = 2 MHz
*3
*4
*5
pation
VCC
—
0.3
0.5
mA
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 2 MHz,
øOSC/128
*3
*4
*5
Sleep ISLEEP
mode
current
dissipation
VCC
—
0.4
0.6
mA
VCC = 5 V,
fOSC = 2 MHz
*3
*4
*5
Subactive
mode
VCC
—
15
30
µA
VCC = 2.7 V, LCD on
32-kHz crystal
oscillator (øSUB=øW /2)
*3
*4
*5
—
8
—
µA
VCC = 2.7 V, LCD on
32-kHz crystal
oscillator (øSUB=øW /8)
*3
*4
Reference
value
*5
IOPE2
ISUB
current
dissipation
SubISUBSP
sleep
mode
current
dissipation
VCC
—
7.5
16
µA
VCC = 2.7 V, LCD on
32-kHz crystal
oscillator (øSUB=øW /2)
*3
*4
*5
Watch IWATCH
mode
current
dissipation
VCC
—
2.8
6.0
µA
VCC = 2.7 V 32-kHz
crystal oscillator
LCD not used
*3
*4
*5
381
Table 15-2 DC Characteristics (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
Notes
*3
*4
Stand- ISTBY
by
mode
current
dissipation
VCC
—
1.0
5.0
µA
RAM
VRAM
data
retaining
voltage
VCC
1.5
—
—
V
32-kHz crystal
oscillator not used
*3
*4
Notes: 1. Applies to the Mask ROM products.
2. Applies to the HD6473887 and HD6473847.
3. Pin states during current measurement.
Pin States during Current Dissipation Measurement
Mode
Active (high-speed)
mode
Active (mediumspeed) mode
Sleep mode
Subactive mode
Subsleep mode
Watch mode
Standby mode
Other ConstantRES Pin Internal State
Pins Voltage
Oscillator Pins
VCC
Only CPU Operates VCC
Halted
System clock oscillator:
Crystal
Subclock oscillator:
Pin X1 = GND
VCC
Only timers operate VCC
VCC
Only CPU Operates VCC
Halted
System clock oscillator:
VCC
Only timers operate, VCC
Halted
crystal
CPU stops
Subclock oscillator:
VCC
Only time base
VCC
Halted
crystal
operates, CPU stops
VCC
CPU and timers
VCC
Halted
System clock oscillator:
both stop
crystal
Subclock oscillator:
Pin X1 = GND
4. Excludes current in pull-up MOS transistors and output buffers.
5. When internal step-down circuit is used.
382
Table 15-2 DC Characteristics (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
Allowable
IOL
Output pins except
ports 2 and 3
—
—
2.0
mA
output
low
Ports 2 and 3
—
—
10.0
current
(per
pin)
All output pins
—
—
0.5
Output pins except
ports 2 and 3
—
—
40.0
output
low
Ports 2 and 3
—
—
80.0
current
(total)
All output pins
—
—
20.0
Allow- –I OH
able
output
All output pins
—
—
2.0
—
—
0.2
—
—
15.0
—
—
10.0
Allowable
∑ IOL
high
current
(per
pin)
Allowable
output
high
∑ – IOH
All output pins
Notes
VCC = 4.0V to 5.5V
VCC = 4.0V to 5.5V
mA
VCC = 4.0V to 5.5V
VCC = 4.0V to 5.5V
mA
VCC = 4.0V to 5.5V
Except the above
mA
VCC = 4.0V to 5.5V
Except the above
383
15.2.3
AC Characteristics
Table 15-3 lists the control signal timing, and tables 15-4 and 15-5 list the serial interface timing
of the H8/3887 Series.
Table 15-3 Control Signal Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Applicable
Item
Symbol Pins
System clock
fOSC
Values
Typ
Max
Unit Test Condition
Figure
OSC1, OSC2 0.4
—
6
MHz VCC = 4.5V to 5.5 V
*2
oscillation
0.4
—
4
VCC = 3.0V to 5.5 V
frequency
0.4
—
3.2
VCC = 2.6V to 5.5 V
0.4
—
2
VCC = 2.2V to 5.5 V
0.4
—
1
Except the above
OSC1, OSC2 167
—
2500
VCC = 4.5V to 5.5 V
Figure 15-1
250
—
2500
VCC = 3.0V to 5.5 V
*2
313
—
2500
VCC = 2.6V to 5.5 V
500
—
2500
VCC = 2.2V to 5.5 V
OSC clock (ø OSC) tOSC
cycle time
Min
Reference
ns
1000
—
2500
System clock (ø) tcyc
2
—
128
tOSC
cycle time
—
—
244.1
µs
Figure 15-1
Except the above
Subclock oscilla- fW
tion frequency
X1, X2
—
32.768 —
or 38.4
kHz
Watch clock (øW ) tW
cycle time
X1, X2
—
30.5 or —
26.0
µs
Figure 15-1
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
OSC1, OSC2 —
20
45
µs
VCC = 2.2 V to 5.5 V (In
case of Figure 15-10)
Figure 15-10
*2
—
0.1
8
ms
VCC = 2.2 V to 5.5 V (In
case of Figure 15-10)
Figure 15-10
—
—
50
ms
Except the above
—
—
2.0
s
Subclock (øSUB)
cycle time
tsubcyc
Instruction cycle
time
Oscillation
trc
stabilization time
Oscillation
trc
stabilization time
384
X1, X2
Table 15-3 Control Signal Timing (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Applicable
Values
Reference
Item
Symbol Pins
Min
Typ
Max
Unit Test Condition
Figure
External clock
tCPH
70
—
—
ns
VCC = 4.5 V to 5.5 V
Figure 15-1
100
—
—
VCC = 3.0 V to 5.5 V
*2
140
—
—
VCC = 2.6 V to 5.5 V
200
—
—
VCC = 2.2 V to 5.5 V
400
—
—
Except the above
X1
—
15.26 —
or
13.02
µs
OSC1
70
—
—
ns
VCC = 4.5 V to 5.5 V
Figure 15-1
100
—
—
VCC = 3.0 V to 5.5 V
*2
140
—
—
VCC = 2.6 V to 5.5 V
200
—
—
VCC = 2.2 V to 5.5 V
—
OSC1
high width
External clock
tCPL
low width
External clock
tCPr
400
—
X1
—
15.26 —
or
13.02
µs
OSC1
—
—
20
ns
—
—
30
rise time
External clock
tCPf
Pin RES low
width
tREL
Figure 15-1
Except the above
—
—
55
X1
—
—
55.0
ns
OSC1
—
—
20
ns
—
—
30
fall time
Figure 15-1
VCC = 4.5 V to 5.5 V
Figure 15-1
VCC = 2.6 V to 5.5 V
*2
Except the above
Figure 15-1
Figure 15-1
VCC = 4.5 V to 5.5 V
Figure 15-1
VCC = 2.6 V to 5.5 V
*2
Except the above
Figure 15-1
—
—
55
X1
—
—
55.0
ns
Figure 15-1
RES
10
—
—
tcyc
Figure 15-2
385
Table 15-3 Control Signal Timing (cont)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Applicable
Item
Symbol Pins
Input pin high
width
tIH
Input pin low
width
tIL
UD pin minimum tUDH
modulation width tUDL
Values
Min
Reference
Typ
Max
Unit Test Condition
Figure
IRQ0 to
2
IRQ4,
WKP0 to
WKP7,
ADTRG,
TMIC
TMIF, TMIG,
AEVL,
AEVH
—
—
tcyc
tsubcyc
Figure 15-3
IRQ0 to
2
IRQ4,
WKP0 to
WKP7,
ADTRG,
TMIC, TMIF,
TMIG,
AEVL,
AEVH
—
—
tcyc
tsubcyc
Figure 15-3
UD
—
—
tcyc
tsubcyc
Figure 15-4
4
Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2. When internal power supply step-down circuit is not used.
386
Table 15-4 Serial Interface (SCI1) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C unless
otherwise indicated
Applicable
Item
Symbol Pins
Values
Reference
Min
Typ
Max
Unit Test Condition
Figure
Input clock cycle tScyc
SCK1
2
—
—
tcyc
Figure 15-5
Input clock high
width
tSCKH
SCK1
0.4
—
—
tScyc
Figure 15-5
Input clock low
width
tSCKL
SCK1
0.4
—
—
tScyc
Figure 15-5
Input clock rise
tSCKr
SCK1
—
—
60.0
ns
VCC = 4.0 to 5.5 V
Figure 15-5*
—
—
80.0
ns
Except the above
Figure 15-5
—
—
60.0
ns
VCC = 4.0 to 5.5 V
Figure 15-5*
—
—
80.0
ns
Except the above
Figure 15-5
—
—
200.0
ns
VCC = 4.0 to 5.5 V
Figure 15-5*
—
—
350.0
ns
Except the above
Figure 15-5
—
ns
VCC = 4.0 to 5.5 V
Figure 15-5*
time
Input clock fall
tSCKf
SCK1
tSOD
SO 1
time
Serial output
data delay time
Serial input data
tSIS
SI 1
200.0 —
400.0 —
—
ns
Except the above
Figure 15-5
tSIH
SI 1
200.0 —
—
ns
VCC = 4.0 to 5.5 V
Figure 15-5*
400.0 —
—
ns
Except the above
Figure 15-5
setup time
Serial input data
hold time
Note:
*
When internal power supply step-down circuit is not used.
387
Table 15-5 Serial Interface (SCI3-1, SCI3-2) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Min
Reference
Typ
Max
Unit
Input clock
Asynchronous tScyc
4
—
—
tcyc or
cycle
Synchronous
6
—
—
tsubcyc
Test Conditions
Figure
Figure 15-6
Input clock pulse width
tSCKW
0.4
—
0.6
tScyc
Transmit data delay time
tTXD
—
—
1
tcyc or
VCC = 4.0 V to 5.5 V
—
—
1
tsubcyc
Except the above
—
ns
VCC = 4.0 V to 5.5 V
Except the above
Figure 15-7
ns
VCC = 4.0 V to 5.5 V
Figure 15-7*
Except the above
Figure 15-7
(synchronous)
Receive data setup time
tRXS
200.0 —
400.0 —
—
tRXH
200.0 —
—
400.0 —
—
(synchronous)
Receive data hold time
(synchronous)
Notes: *
388
Figure 15-6
When internal power supply step-down circuit is not used
Figure 15-7
Figure 15-7*
15.2.4
A/D Converter Characteristics
Table 15-6 shows the A/D converter characteristics of the H8/3887 Series.
Table 15-6 A/D Converter Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (including subactive mode)
unless otherwise indicated.
Item
Analog power
supply voltage
Analog input
voltage
Analog power
supply current
Analog input
capacitance
Allowable
signal source
impedance
Resolution
(data length)
Nonlinearity
error
Quantization
error
Absolute
accuracy
Conversion
time
Applicable
Symbol Pins
AV CC
AV CC
Values
Min
Typ
1.8
—
Max
5.5
AV IN
AN0 to AN11
– 0.3
—
AV CC + 0.3 V
AI OPE
AI STOP1
AV CC
AV CC
—
—
—
600
1.5
—
mA
µA
AI STOP2
CAIN
AV CC
AN0 to AN11
—
—
—
—
5
15.0
µA
pF
—
—
10.0
kΩ
—
—
10
bit
—
—
±2.5
LSB
—
—
±5.5
—
—
—
—
±7.5
±0.5
LSB
—
—
±3.0
LSB
—
—
±6.0
—
15.5
—
—
±8.0
155
62
—
155
RAIN
Unit
V
µs
Test Condition
Notes
*1
AV CC = 5.0 V
*2
Reference
value
*3
AV CC = 3.0 to 5.5 V
VCC = 3.0 to 5.5 V
AV CC = 2.0 to 5.5 V
VCC = 2.0 to 5.5 V
Except the above
AV CC = 3.0 to 5.5 V
VCC = 3.0 to 5.5 V
AV CC = 2.0 to 5.5 V
VCC = 2.0 to 5.5 V
Except the above
AV CC = 3.0 to 5.5 V
VCC = 3.0 to 5.5 V
Except the above
*4
*5
*4
*5
*4
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. When internal power supply step-down circuit is not used.
5. Conversion time: 124 µs
389
15.2.5
LCD Characteristics
Table 15-7 shows the LCD characteristics of the H8/3887 Series.
Table 15-7 LCD Characteristics (H8/3887 Series)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Applicable Values
Item
Symbol
Test
Pins
Min
Typ
Max
Unit
Conditions
Notes
Segment driver VDS
drop voltage
SEG1 to
SEG40
—
—
0.6
V
I D = 2 µA
V1 = 2.7 to 5.5 V
*1
Common driver VDC
drop voltage
COM1 to
COM4
—
—
0.3
V
I D = 2 µA
V1 = 2.7 to 5.5 V
*1
0.5
3.0
9.0
MΩ
Between V 1
and V SS
V0
—
5.0
—
V
*2
Reference
value
V1
2.2
—
5.5
V
*3
LCD power
supply splitresistance
RLCD
On-chip liquid
crystal display
power supply
voltage
VLP
Liquid crystal VLCD
display voltage
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and V SS to each segment pin or
common pin.
2. The output voltage in step-up constant-voltage power supply operation.
3. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: V 1 ≥ V2 ≥ V3 ≥ VSS .
390
Table 15-8 Segment External Expansion AC Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (including subactive mode)
unless otherwise indicated.
Applicable Values
Test
Reference
Item
Symbol
Pins
Min
Typ
Max
Unit Conditions Figure
Clock high width
t CWH
CL 1, CL 2
800.0
—
—
ns
*
Figure 15-8
Clock low width
t CWL
CL2
800.0
—
—
ns
*
Figure 15-8
Clock setup time
t CSU
CL 1, CL 2
500.0
—
—
ns
*
Figure 15-8
Data setup time
t SU
DO
300.0
—
—
ns
*
Figure 15-8
Data retaining time t DH
DO
300.0
—
—
ns
*
Figure 15-8
M delay time
M
–1000.0
—
1000.0 ns
*
Figure 15-8
CL 1, CL 2
—
—
170.0
t DM
Clock rise/fall time t CT
Note:
*
ns
Figure 15-8
When the frame frequency is set at 488 Hz to 30.5 Hz.
391
15.3
Operation Timing
Figures 15-1 to 15-7 show timing diagrams.
t OSC , tw
VIH
OSC1
x1
VIL
t CPH
t CPL
t CPr
t CPf
Figure 15-1 Clock Input Timing
RES
VIL
tREL
Figure 15-2 RES Low Width
IRQ0 to IRQ4,
WKP0 to WKP7,
ADTRG,
TMIC, TMIF,
TMIG, AEVL,
AEVH
VIH
VIL
t IL
t IH
Figure 15-3 Input Timing
392
VIH
UD
VIL
t UDL
t UDH
Figure 15-4 UD Pin Minimum Modulation Width Timing
tscyc
SCK1
VIH or VOH*
VIL or VOL*
tSCKL
tSCKH
tSCKf
tSCKr
tSOD
VOH*
VOL*
SO1
tSIS
tSIH
SI1
Note: * Output timing reference levels
Output high level
VOH = 1/2 VCC + 0.2 V
Output low level
VOL = 0.8 V
See figure 15-9 for the load conditions.
Figure 15-5 SCI1 Input/Output Timing
393
t SCKW
SCK 31
SCK 32
t scyc
Figure 15-6 SCK3 Input Clock Timing
t scyc
SCK 31 VIH or VOH *
SCK 32 VIL or VOL *
t TXD
TXD31
TXD32
(transmit data)
VOH*
VOL
*
t RXS
t RXH
RXD31
RXD32
(receive data)
Note: * Output timing reference levels
Output high
VOH = 1/2 VCC + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 15-9.
Figure 15-7 SCI3 Synchronous Mode Input/Output Timing
394
tCT
VCC – 0.5 V
CL1
0.4 V
tCWH
tCWH
tCSU
VCC – 0.5 V
CL2
0.4 V
tCSU
tCWL
tCT
VCC – 0.5 V
0.4 V
DO
tSU
M
tDH
0.4 V
tDM
Figure 15-8 Segment Expansion Signal Timing
395
15.4
Output Load Circuit
VCC
2.4 kΩ
Output pin
30 pF
12 k Ω
Figure 15-9 Output Load Condition
396
15.5
Resonator Equivalent Circuit
LS
CS
RS
OSC1
OSC2
CO
Crystal Resonator Parameter
Ceramic Resonator Parameters
Frequency (MHz)
1
4.193
Frequency (MHz)
0.4
4
RS (max)
40 Ω
100 Ω
RS (max)
8.6 Ω
8.8 Ω
CO (max)
3.5 pF
16 pF
CO (max)
326 pF
36 pF
Figure 15-10 Resonator Equivalent Circuit
397
Appendix A CPU Instruction Set
A.1
Instructions
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
Rn8/16
General register (8 or 16 bits)
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#xx: 3/8/16
Immediate data (3, 8, or 16 bits)
d: 8/16
Displacement (8 or 16 bits)
@aa: 8/16
Absolute address (8 or 16 bits)
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Exclusive logical OR
→
Move
—
Logical complement
Condition Code Notation
Symbol
↑
↓
*
Modified according to the instruction result
0
Always cleared to 0
—
Not affected by the instruction execution result
398
Not fixed (value not guaranteed)
Table A-1 lists the H8/300L CPU instruction set.
Table A-1
Instruction Set
MOV.B @(d:16, Rs),
Rd
B @(d:16, Rs16)→ Rd8
MOV.B @Rs+, Rd
B @Rs16 → Rd8
Rs16+1 → Rs16
MOV.B @aa:8, Rd
B @aa:8 → Rd8
2
—— ↑
↓ ↑
↓ 0 —4
MOV.B @aa:16, Rd
B @aa:16 → Rd8
4
—— ↑
↓ ↑
↓ 0 —6
MOV.B Rs, @Rd
B Rs8 → @Rd16
MOV.B Rs, @(d:16,
Rd)
B Rs8 → @(d:16, Rd16)
MOV.B Rs, @–Rd
B Rd16–1 → Rd16
Rs8 → @Rd16
MOV.B Rs, @aa:8
B Rs8 → @aa:8
2
—— ↑
↓ ↑
↓ 0 —4
MOV.B Rs, @aa:16
B Rs8 → @aa:16
4
—— ↑
↓ ↑
↓ 0 —6
MOV.W #xx:16, Rd
W #xx:16 → Rd
MOV.W Rs, Rd
W Rs16 → Rd16
MOV.W @Rs, Rd
W @Rs16 → Rd16
MOV.W @(d:16, Rs),
Rd
W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
W @Rs16 → Rd16
Rs16+2 → Rs16
MOV.W @aa:16, Rd
W @aa:16 → Rd16
MOV.W Rs, @Rd
W Rs16 → @Rd16
MOV.W Rs, @(d:16,
Rd)
W Rs16 → @(d:16, Rd16)
MOV.W Rs, @–Rd
W Rd16–2 → Rd16
Rs16 → @Rd16
MOV.W Rs, @aa:16
W Rs16 → @aa:16
POP Rd
W @SP → Rd16
SP+2 → SP
2
—— ↑
↓ ↑
↓ 0 —6
PUSH Rs
W SP–2 → SP
Rs16 → @SP
2
—— ↑
↓ ↑
↓ 0 —6
I
H N Z V C
No. of States
B @Rs16 → Rd8
@@aa
MOV.B @Rs, Rd
Implied
B Rs8 → Rd8
@aa: 8/16
MOV.B Rs, Rd
@(d:8, PC)
2
@(d:16, Rn)
B #xx:8 → Rd8
@–Rn/@Rn+
#xx: 8/16
MOV.B #xx:8, Rd
@Rn
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
—— ↑
↓ ↑
↓ 0 —2
—— ↑
↓ ↑
↓ 0 —2
2
—— ↑
↓ ↑
↓ 0 —4
2
—— ↑
↓ ↑
↓ 0 —6
4
—— ↑
↓ ↑
↓ 0 —6
2
—— ↑
↓ ↑
↓ 0 —4
2
—— ↑
↓ ↑
↓ 0 —6
4
—— ↑
↓ ↑
↓ 0 —6
2
—— ↑
↓ ↑
↓ 0 —4
4
—— ↑
↓ ↑
↓ 0 —2
2
—— ↑
↓ ↑
↓ 0 —4
2
—— ↑
↓ ↑
↓ 0 —6
4
—— ↑
↓ ↑
↓ 0 —6
2
4
—— ↑
↓ ↑
↓ 0 —6
—— ↑
↓ ↑
↓ 0 —4
2
—— ↑
↓ ↑
↓ 0 —6
4
—— ↑
↓ ↑
↓ 0 —6
2
4
—— ↑
↓ ↑
↓ 0 —6
399
Table A-1
Instruction Set (cont)
—↑
↓ ↑
↓ (2) ↑
↓ ↑
↓ 2
2
—— ——— —2
ADDS.W #2, Rd
W Rd16+2 → Rd16
2
INC.B Rd
B Rd8+1 → Rd8
2
—— ——— —2
↑ ↑
—— ↓
↓ ↑
↓ —2
DAA.B Rd
B Rd8 decimal adjust → Rd8
2
SUB.B Rs, Rd
B Rd8–Rs8 → Rd8
2
↑ * (3) 2
—* ↑
↓ ↓
↑ ↑
↑ ↑
—↑
↓ ↓
↓ ↓
↓ 2
SUB.W Rs, Rd
W Rd16–Rs16 → Rd16
2
— (1) ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
SUBX.B #xx:8, Rd
B Rd8–#xx:8 –C → Rd8
SUBX.B Rs, Rd
B Rd8–Rs8 –C → Rd8
2
—↑
↓ ↑
↓ (2) ↑
↓ ↑
↓ 2
SUBS.W #1, Rd
W Rd16–1 → Rd16
2
—— ——— —2
SUBS.W #2, Rd
W Rd16–2 → Rd16
2
DEC.B Rd
B Rd8–1 → Rd8
2
—— ——— —2
↑ ↑
—— ↓
↓ ↑
↓ —2
DAS.B Rd
B Rd8 decimal adjust → Rd8
2
NEG.B Rd
B 0–Rd → Rd
2
CMP.B #xx:8, Rd
B Rd8–#xx:8
CMP.B Rs, Rd
B Rd8–Rs8
I
H N Z V C
No. of States
2
W Rd16+1 → Rd16
@@aa
B Rd8+Rs8 +C → Rd8
ADDS.W #1, Rd
Implied
ADDX.B Rs, Rd
@aa: 8/16
B Rd8+#xx:8 +C → Rd8
@(d:8, PC)
W Rd16+Rs16 → Rd16
ADDX.B #xx:8, Rd
@(d:16, Rn)
ADD.W Rs, Rd
@–Rn/@Rn+
B Rd8+Rs8 → Rd8
@Rn
B Rd8+#xx:8 → Rd8
ADD.B Rs, Rd
#xx: 8/16
ADD.B #xx:8, Rd
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
—↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
2
2
—↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
2
— (1) ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
—↑
↓ ↑
↓ (2) ↑
↓ ↑
↓ 2
2
—↑
↓ ↑
↓ (2) ↑
↓ ↑
↓ 2
2
↑ * —2
—* ↑
↓ ↓
↑ ↑
↑ ↑
—↑
↓ ↓
↓ ↓
↓ 2
—↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
2
2
—↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
CMP.W Rs, Rd
W Rd16–Rs16
2
— (1) ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
MULXU.B Rs, Rd
B Rd8 × Rs8 → Rd16
2
— — — — — — 14
DIVXU.B Rs, Rd
B Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
2
— — (5) (6) — — 14
AND.B #xx:8, Rd
B Rd8∧#xx:8 → Rd8
AND.B Rs, Rd
B Rd8∧Rs8 → Rd8
OR.B #xx:8, Rd
B Rd8∨#xx:8 → Rd8
OR.B Rs, Rd
B Rd8∨Rs8 → Rd8
XOR.B #xx:8, Rd
B Rd8⊕#xx:8 → Rd8
XOR.B Rs, Rd
B Rd8⊕Rs8 → Rd8
2
—— ↑
↓ ↑
↓ 0 —2
NOT.B Rd
B Rd → Rd
2
—— ↑
↓ ↑
↓ 0 —2
400
—— ↑
↓ ↑
↓ 0 —2
2
2
—— ↑
↓ ↑
↓ 0 —2
—— ↑
↓ ↑
↓ 0 —2
2
2
—— ↑
↓ ↑
↓ 0 —2
—— ↑
↓ ↑
↓ 0 —2
2
Table A-1
Instruction Set (cont)
C
0
b7
SHAR.B Rd
SHLL.B Rd
B
C
B
C
0
B
0
C
C
B
b0
No. of States
@@aa
Implied
@aa: 8/16
@(d:8, PC)
@(d:16, Rn)
@–Rn/@Rn+
—— ↑
↓ ↑
↓ 0 ↑
↓ 2
2
—— ↑
↓ ↑
↓ 0 ↑
↓ 2
2
—— 0 ↑
↓ 0 ↑
↓ 2
2
—— ↑
↓ ↑
↓ 0 ↑
↓ 2
2
—— ↑
↓ ↑
↓ 0 ↑
↓ 2
2
—— ↑
↓ ↑
↓ 0 ↑
↓ 2
2
—— ↑
↓ ↑
↓ 0 ↑
↓ 2
C
C
b7
ROTR.B Rd
2
b0
B
b7
ROTL.B Rd
—— ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
b0
b7
ROTXR.B Rd
2
b0
b7
ROTXL.B Rd
H N Z V C
b0
b7
SHLR.B Rd
I
b0
B
b7
@Rn
B
#xx: 8/16
SHAL.B Rd
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
b0
B
C
b7
b0
BSET #xx:3, Rd
B (#xx:3 of Rd8) ← 1
BSET #xx:3, @Rd
B (#xx:3 of @Rd16) ← 1
BSET #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B (Rn8 of Rd8) ← 1
BSET Rn, @Rd
B (Rn8 of @Rd16) ← 1
BSET Rn, @aa:8
B (Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B (#xx:3 of Rd8) ← 0
BCLR #xx:3, @Rd
B (#xx:3 of @Rd16) ← 0
BCLR #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B (Rn8 of Rd8) ← 0
2
—— ——— —2
4
—— ——— —8
4
2
—— ——— —2
4
—— ——— —8
4
2
—— ——— —8
—— ——— —2
4
—— ——— —8
4
2
—— ——— —8
—— ——— —8
—— ——— —2
401
Table A-1
Instruction Set (cont)
BNOT Rn, Rd
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
BNOT Rn, @Rd
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
BNOT Rn, @aa:8
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
BTST #xx:3, Rd
B (#xx:3 of Rd8) → Z
BTST #xx:3, @Rd
B (#xx:3 of @Rd16) → Z
BTST #xx:3, @aa:8
B (#xx:3 of @aa:8) → Z
BTST Rn, Rd
B (Rn8 of Rd8) → Z
BTST Rn, @Rd
B (Rn8 of @Rd16) → Z
BTST Rn, @aa:8
B (Rn8 of @aa:8) → Z
BLD #xx:3, Rd
B (#xx:3 of Rd8) → C
BLD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BLD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B (#xx:3 of Rd8) → C
BILD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BILD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B C → (#xx:3 of Rd8)
BST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B C → (#xx:3 of Rd8)
BIST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BIST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
402
I
H N Z V C
No. of States
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
@@aa
BNOT #xx:3, @aa:8
Implied
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
@aa: 8/16
BNOT #xx:3, @Rd
4
@(d:8, PC)
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
@(d:16, Rn)
BNOT #xx:3, Rd
@–Rn/@Rn+
B (Rn8 of @aa:8) ← 0
@Rn
B (Rn8 of @Rd16) ← 0
BCLR Rn, @aa:8
#xx: 8/16
BCLR Rn, @Rd
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
—— ——— —8
4
2
—— ——— —8
—— ——— —2
4
—— ——— —8
4
2
—— ——— —8
—— ——— —2
4
—— ——— —8
4
—— ——— —8
—— —↑
↓ — —2
2
—— —↑
↓ — —6
4
4
—— —↑
↓ — —6
—— —↑
↓ — —2
2
—— —↑
↓ — —6
4
4
—— —↑
↓ — —6
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
4
—— ——— ↑
↓ 6
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
4
2
—— ——— ↑
↓ 6
—— ——— —2
4
—— ——— —8
4
2
—— ——— —8
—— ——— —2
4
—— ——— —8
4
—— ——— —8
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
4
—— ——— ↑
↓ 6
Table A-1
Instruction Set (cont)
BIAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BIOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BIOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BIXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BIXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BRA d:8 (BT d:8)
— PC ← PC+d:8
I
H N Z V C
No. of States
@@aa
Implied
@aa: 8/16
@(d:8, PC)
@(d:16, Rn)
@–Rn/@Rn+
B C∧(#xx:3 of @Rd16) → C
@Rn
B C∧(#xx:3 of Rd8) → C
BIAND #xx:3, @Rd
#xx: 8/16
BIAND #xx:3, Rd
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 2
2
—— ——— ↑
↓ 6
4
—— ——— ↑
↓ 6
4
2
—— ——— —4
BRN d:8 (BF d:8)
— PC ← PC+2
2
—— ——— —4
BHI d:8
— If condition
C∨Z=0
2
—— ——— —4
BLS d:8
— is true then
C∨Z=1
2
—— ——— —4
BCC d:8 (BHS d:8)
— PC ← PC+d:8 C = 0
2
—— ——— —4
BCS d:8 (BLO d:8)
— else next;
C=1
2
—— ——— —4
BNE d:8
—
Z=0
2
—— ——— —4
BEQ d:8
—
Z=1
2
—— ——— —4
BVC d:8
—
V=0
2
—— ——— —4
BVS d:8
—
V=1
2
—— ——— —4
BPL d:8
—
N=0
2
—— ——— —4
BMI d:8
—
N=1
2
—— ——— —4
BGE d:8
—
N⊕V = 0
2
—— ——— —4
BLT d:8
—
N⊕V = 1
2
—— ——— —4
BGT d:8
—
Z ∨ (N⊕V) = 0
2
—— ——— —4
BLE d:8
—
Z ∨ (N⊕V) = 1
2
—— ——— —4
403
Table A-1
Instruction Set (cont)
— SP–2 → SP
PC → @SP
PC ← aa:16
JSR @@aa:8
H N Z V C
—— ——— —4
4
—— ——— —6
2
2
—— ——— —8
—— ——— —6
2
—— ——— —6
4
SP–2 → SP
PC → @SP
PC ← @aa:8
I
No. of States
JSR @aa:16
@@aa
— SP–2 → SP
PC → @SP
PC ← Rn16
2
Implied
JSR @Rn
@aa: 8/16
— SP–2 → SP
PC → @SP
PC ← PC+d:8
@(d:8, PC)
— PC ← @aa:8
BSR d:8
@(d:16, Rn)
JMP @@aa:8
@–Rn/@Rn+
— PC ← aa:16
@Rn
— PC ← Rn16
JMP @aa:16
#xx: 8/16
JMP @Rn
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
—— ——— —8
2
—— ——— —8
RTS
— PC ← @SP
SP+2 → SP
2 —— ——— —8
RTE
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2 ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 10
SLEEP
— Transit to sleep mode.
2 —— ——— —2
LDC #xx:8, CCR
B #xx:8 → CCR
LDC Rs, CCR
B Rs8 → CCR
↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
2
2
↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
2
—— ——— —2
STC CCR, Rd
B CCR → Rd8
ANDC #xx:8, CCR
B CCR∧#xx:8 → CCR
2
↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
ORC #xx:8, CCR
B CCR∨#xx:8 → CCR
2
↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
XORC #xx:8, CCR
B CCR⊕#xx:8 → CCR
2
↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ ↑
↓ 2
NOP
— PC ← PC+2
2 —— ——— —2
EEPMOV
— if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
4 — — — — — — (4)
404
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to
arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
405
A.2
Operation Code Map
Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
406
XOR
AND
MOV
D
E
F
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
OR
C
BILD
8
BVC
SUBX
BIAND
BAND
BIST
BLD
BST
BEQ
MOV
NEG
NOT
LDC
7
B
BIXOR
BXOR
RTE
BNE
AND
ANDC
6
CMP
BIOR
BOR
BSR
BCS
XOR
XORC
5
A
BTST
RTS
BCC
OR
ORC
4
ADDX
BCLR
BLS
ROTR
ROTXR
LDC
3
9
BNOT
BHI
ROTL
ROTXL
STC
2
ADD
BSET
DIVXU
BRN
SHAR
SHLR
SLEEP
1
8
7
6
MULXU
5
SHAL
SHLL
NOP
0
BRA
Low
4
3
2
1
0
High
Table A-2 Operation Code Map
SUB
ADD
MOV
BVS
9
JMP
BPL
DEC
INC
A
C
CMP
MOV
BLT
D
JSR
BGT
SUBX
ADDX
E
Bit-manipulation instructions
BGE
MOV *
EEPMOV
BMI
SUBS
ADDS
B
#
"#
407
BLE
DAS
DAA
F
A.3
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL+ M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A-4:
I = L = 2, J = K = M = N= 0
From table A-3:
S I = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A-4:
I = 2, J = K = 1, L = M = N = 0
From table A-3:
S I = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Table A-3
Number of Cycles in Each Instruction
Execution Status
Access Location
(instruction cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
—
Internal operation
SN
Note:
408
*
1
Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
Table A-4
Number of Cycles in Each Instruction
Instruction
Mnemonic
Instruction
Fetch
I
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W Rs, Rd
1
ADDS.W #1, Rd
1
ADDS.W #2, Rd
1
ADDX.B #xx:8, Rd
1
ADDX.B Rs, Rd
1
AND
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
ADDS
ADDX
Bcc
BCLR
Branch
Stack
Byte Data Word
Addr. Read Operation Access
Data
J
K
L
Access
M
BAND #xx:3, @Rd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
BGT d:8
2
BLE d:8
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @Rd
2
2
BCLR #xx:3, @aa: 8
2
2
BCLR Rn, Rd
1
BCLR Rn, @Rd
2
2
BCLR Rn, @aa:8
2
2
Internal
Operation
N
409
Table A-4
Number of Cycles in Each Instruction (cont)
Instruction
Mnemonic
Instruction
Fetch
I
BIAND
BIAND #xx:3, Rd
1
BIAND #xx:3, @Rd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD
BIOR
BIST
Branch
Stack
Byte Data Word
Addr. Read Operation Access
Data
J
K
L
Access
M
BILD #xx:3, @Rd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:3, Rd
1
BIOR #xx:3, @Rd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @Rd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @Rd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @Rd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @Rd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @Rd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @Rd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @Rd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @Rd
2
BSET Rn, @aa:8
2
BSR
BSR d:8
2
BST
BST #xx:3, Rd
1
BST #xx:3, @Rd
2
2
BST #xx:3, @aa:8
2
2
BIXOR
BLD
BNOT
BOR
BSET
410
2
2
1
Internal
Operation
N
Table A-4
Number of Cycles in Each Instruction (cont)
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Stack
Byte Data Word
Addr. Read Operation Access
Data
J
K
L
Access
M
BTST
BTST #xx:3, Rd
1
BTST #xx:3, @Rd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @Rd
2
1
BTST Rn, @aa:8
2
1
BXOR #xx:3, Rd
1
BXOR #xx:3, @Rd
2
1
BXOR #xx:3, @aa:8
2
1
CMP. B #xx:8, Rd
1
CMP. B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV
EEPMOV
2
INC
INC.B Rd
1
JMP
JMP @Rn
2
JMP @aa:16
2
JMP @@aa:8
2
JSR @Rn
2
JSR @aa:16
2
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
BXOR
CMP
JSR
LDC
MOV
Note:
*
Internal
Operation
N
12
2n+2*
1
2
1
2
1
1
1
2
1
MOV.B @Rs, Rd
1
1
MOV.B @(d:16, Rs),
Rd
2
1
MOV.B @Rs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
2
n: Initial value in R4L. The source and destination operands are accessed n + 1 times
each.
411
Table A-4
Instruction
MOV
Number of Cycles in Each Instruction (cont)
Mnemonic
Instruction
Fetch
I
Branch
Stack
Byte Data Word
Addr. Read Operation Access
Data
J
K
L
Access
M
Internal
Operation
N
MOV.B Rs, @(d:16,
Rd)
2
1
MOV.B Rs, @–Rd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
1
MOV.W @(d:16, Rs),
Rd
2
1
MOV.W @Rs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W Rs, @Rd
1
1
MOV.W Rs, @(d:16,
Rd)
2
1
MOV.W Rs, @–Rd
1
1
MOV.W Rs, @aa:16
2
1
MULXU
MULXU.B Rs, Rd
1
NEG
NEG.B Rd
1
NOP
NOP
1
NOT
NOT.B Rd
1
OR
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
ORC #xx:8, CCR
1
ROTL
ROTL.B Rd
1
ROTR
ROTR.B Rd
1
ROTXL
ROTXL.B Rd
1
ROTXR
ROTXR.B Rd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
ORC
412
2
2
2
12
Table A-4
Number of Cycles in Each Instruction (cont)
Instruction
Mnemonic
Instruction
Fetch
I
SUB
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUB.B Rs, Rd
1
SUB
SUBS
SUB.W Rs, Rd
1
SUBS.W #1, Rd
1
Branch
Stack
Byte Data Word
Addr. Read Operation Access
Data
J
K
L
Access
M
Internal
Operation
N
SUBS.W #2, Rd
1
POP
POP Rd
1
1
2
PUSH
PUSH Rs
1
1
2
SUBX
SUBX.B #xx:8, Rd
1
SUBX.B Rs, Rd
1
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XORC #xx:8, CCR
1
XOR
XORC
413
Appendix B Internal I/O Registers
B.1
Addresses
Lower
Register
Bit Names
Address
Name
Bit 7
Module
H'90
WEGR
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System
control
H'91
SPCR
—
—
SPC32
SPC31
SCINV3
SCINV2
SCINV1
SCINV0
SCI
H'92
CWOSR
—
—
—
—
—
—
—
CWOS
Timer A
H'95
ECCSR
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
Asynchro-
H'96
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
nous event
H'97
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
counter
H'98
SMR31
COM31
CHR31
PE31
PM31
STOP31
MP31
CKS311
CKS310
SCI31
H'99
BRR31
BRR317
BRR316
BRR315
BRR314
BRR313
BRR312
BRR311
BRR310
H'9A
SCR31
TIE31
RIE31
TE31
RE31
MPIE31
TEIE31
CKE31
CKE310
H'9B
TDR31
TDR317
TDR316
TDR315
TDR314
TDR313
TDR312
TDR311
TDR310
H'9C
SSR31
TDRE31
RDRF31
OER31
FER31
PER31
TEND31
MPBR31
MPBT31
H'9D
RDR31
RDR317
RDR316
RDR315
RDR314
RDR313
RDR312
RDR311
RDR310
H'A0
SCR1
SNC1
SNC0
MRKON
LTCH
CKS3
CKS2
CKS1
CKS0
H'A1
SCSR1
—
SOL
ORER
—
—
—
MTRF
STF
H'A2
SDRU
SDRU7
SDRU6
SDRU5
SDRU4
SDRU3
SDRU2
SDRU1
SDRU0
H'A3
SDRL
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
H'A8
SMR32
COM32
CHR32
PE32
PM32
STOP32
MP32
CKS321
CKS320
H'A9
BRR32
BRR327
BRR326
BRR325
BRR324
BR323
BRR322
BRR321
BRR320
H'AA
SCR32
TIE32
RIE32
TE32
RE32
MPIE32
TEIE32
CKE321
CKE320
H'AB
TDR32
TDR327
TDR326
TDR325
TDR324
TDR323
TDR322
TDR321
TDR320
H'AC
SSR32
TDRE32
RDRF32
OER32
FER32
PER32
TEND32
MPBR32
MPBT32
H'AD
RDR32
RDR327
RDR326
RDR325
RDR324
RDR323
RDR322
RDR321
RDR320
H'B0
TMA
TMA7
TMA6
TMA5
—
TMA3
TMA2
TMA1
TMA0
H'B1
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
H'93
H'94
H'9E
H'9F
SCI1
H'A4
H'A5
H'A6
H'A7
SCI32
H'AE
H'AF
414
Timer A
Lower
Register
Bit Names
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Module
H'B2
TCSRW
B6WI
TCWE
B4WI
TCSRWE B2WI
H'B3
TCW
TCW7
TCW6
TCW5
TCW4
H'B4
TMC
TMC7
TMC6
TMC5
—
H'B5
TCC/
TLC
TCC/
TLC7
TCC6/
TLC6
TCC5/
TLC5
TCC4/
TLC4
TCC3/
TLC3
H'B6
TCRF
TOLH
CKSH2
CKSH1
CKSH0
H'B7
TCSRF
OVFH
CMFH
OVIEH
CCLRH
H'B8
TCFH
TCFH7
TCFH6
TCFH5
TCFH4
H'B9
TCFL
TCFL7
TCFL6
TCFL5
TCFL4
H'BA
OCRFH
OCRFH7 OCRFH6
OCRFH5 OCRFH4 OCRFH3
OCRFH2 OCRFH1
OCRFH0
H'BB
OCRFL
OCRFL7
OCRFL6
OCRFL5
OCRFL4
OCRFL3
OCRFL2
OCRFL1
OCRFL0
H'BC
TMG
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
H'BD
ICRGF
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGFO
H'BE
ICRGR
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGRO
H'C0
LPCR
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
LCD
H'C1
LCR
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
controller/
H'C2
LCR2
LCDAB
—
—
SUPS
CDS3
CDS2
CDS1
CDS0
driver
H'C4
ADRRH
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
A/D
H'C5
ADRRL
ADR1
ADR0
—
—
—
—
—
—
converter
H'C6
AMR
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
H'C7
ADSR
ADSF
—
—
—
—
—
—
—
H'C8
PMR1
IRQ3
IRQ2
IRQ1
IRQ4
TMIG
TMOFH
TMOFL
TMOW
H'C9
PMR2
—
—
POF1
—
—
SO1
SI1
SCK1
H'CA
PMR3
AEVL
AEVH
WDCKS
NCS
IRQ0
RESO
UD
PWM
H'CB
PMR4
NMOD7
NMOD6
NMOD5
NMOD4
NMOD3
NMOD2
NMOD1
NMOD0
H'CC
PMR5
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
H'D0
PWCR
—
—
—
—
—
—
PWCR1
PWCR0
H'D1
PWDRU
—
—
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWM
H'D2
PWDRL
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
H'D4
PDR1
P17
P16
P15
P14
P13
P12
P11
P10
H'D5
PDR2
P27
P26
P25
P24
P23
P22
P21
P20
H'D6
PDR3
P37
P36
P35
P34
P33
P32
P31
P30
H'D7
PDR4
—
—
—
—
P43
P42
P41
P40
H'D8
PDR5
P57
P56
P55
P54
P53
P52
P51
P50
Bit 3
Bit 2
Bit 1
Bit 0
Name
WDON
BOW1
WRST
Watchdog
TCW3
TCW2
TCW1
TCWO
timer
—
TMC2
TMC1
TMC0
Timer C
TCC2/
TLC2
TCC1/
TLC1
TCC0/
TLC0
TOLL
CKSL2
CKSL1
CKSL0
OVFL
CMFL
OVIEL
CCLRL
TCFH3
TCFH2
TCFH1
TCFH0
TCFL3
TCFL2
TCFL1
TCFL0
Timer F
Timer G
H'BF
H'C3
I/O port
H'CD
H'CE
H'CF
Bit 14
H'D3
I/O Port
415
Lower
Register
Bit Names
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'D9
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
I/O Port
H'DA
PDR7
P77
P76
P75
P74
P73
P72
P71
P70
H'DB
PDR8
P87
P86
P85
P84
P83
P82
P81
P80
H'DC
PDR9
P97
P96
P95
P94
P93
P92
P91
P90
H'DD
PDRA
—
—
—
—
PA3
PA2
PA1
PA0
H'DE
PDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
H'DF
PDRC
—
—
—
—
PC3
PC2
PC1
PC0
H'E0
PUCR1
PUCR17
PUCR16
PUCR15
PUCR14
PUCR13
PUCR12
PUCR11
PUCR10
H'E1
PUCR3
PUCR37
PUCR36
PUCR35
PUCR34
PUCR33
PUCR32
PUCR31
PUCR30
H'E2
PUCR5
PUCR57
PUCR56
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
H'E3
PUCR6
PUCR67
PUCR66
PUCR65
PUCR64
PUCR63
PUCR62
PUCR61
PUCR60
H'E4
PCR1
PCR17
PCR16
PCR15
PCR14
PCR13
PCR12
PCR11
PCR10
H'E5
PCR2
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
H'E6
PCR3
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
PCR30
H'E7
PCR4
—
—
—
—
—
PCR42
PCR41
PCR40
H'E8
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
H'E9
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
H'EA
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
H'EB
PCR8
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
H'EC
PCR9
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
H'ED
PCRA
—
—
—
—
PCRA3
PCRA2
PCRA1
PCRA0
H'F0
SYSCR1
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
System
H'F1
SYSCR2
—
—
—
NESEL
DTON
MSON
SA1
SA0
control
H'F2
IEGR
—
—
—
IEG4
IEG3
IEG2
IEG1
IEG0
H'F3
IENR1
IENTA
IENS1
IENWP
IEN4
IEN3
IEN2
IEN1
IEN0
H'F4
IENR2
IENDT
IENAD
—
IENTG
IENTFH
IENTFL
IENTC
IENEC
H'F6
IRR1
IRRTA
IRRS1
—
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
H'F7
IRRI2
IRRDT
IRRAD
—
IRRTG
IRRTFH
IRRTFL
IRRTC
IRREC
H'F9
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
H'FA
CK STP R1 S1CKSTP S31CKSTP S32CKSTP A DCK S TP TGCK S TP TFCKSTP TCCK S TP TA CK S TP
H'FB
CK STP R2 —
I/O Port
H'EE
H'EF
H'F5
H'F8
—
H'FC
H'FD
H'FE
H'FF
Legend
SCI: Serial Communication Interface
416
—
—
A ECK S TP WDCKSTP PWCKSTP LDCK S TP
B.2
Functions
Register
acronym
Register
name
Address to which the
register is mapped
Name of
on-chip
supporting
module
Timer C
H'B4
TMC—Timer mode register C
Bit
numbers
Bit
Initial bit
values
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
Possible types of access
R
Read only
W
Write only
R/W Read and write
Clock select
0 0 0 Internal clock: ø/8192
1 Internal clock: ø/2048
1 0 Internal clock: ø/512
1 Internal clock: ø/64
1 0 0 Internal clock: ø/16
1 Internal clock: ø/4
1 0 Internal clock: ø W /4
1 External event (TMIC): Rising or falling edge
Names of the
bits. Dashes
(—) indicate
reserved bits.
Full name
of bit
Descriptions
of bit settings
Counter up/down control
0 0 TCC is an up-counter
1 TCC is a down-counter
1 * TCC up/down control is determined by input at pin
UD. TCC is a down-counter if the UD input is high,
and an up-counter if the UD input is low.
Auto-reload function select
0 Interval timer function selected
1 Auto-reload function selected
*: Don’t care
417
WEGR—Wakeup Edge Select Register
Bit
7
H'90
6
4
5
3
2
System control
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WKPn edge selected
0
1
WKPn pin falling edge detected
WKPn pin rising edge detected
(n = 0 to 7)
SPCR—Serial Port Control Register
Bit
H'91
7
6
5
4
—
—
SPC32
SPC31
3
2
SCI
1
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
RXD31 pin input data inversion switch
0
1
RXD31 input data is not inverted
RXD31 input data is inverted
TXD31 pin output data inversion switch
0
1
TXD31 output data is not inverted
TXD31 output data is inverted
RXD32 pin input data inversion switch
0
1
RXD32 input data is not inverted
RXD32 input data is inverted
TXD32 pin output data inversion switch
0
1
TXD32 output data is not inverted
TXD32 output data is inverted
P35TXD31 pin function switch
0
1
Functions as P35 I/O pin
Functions as TXD31 output pin
P42/TXD32pin function switch
0
1
418
0
SCINV3 SCINV2 SCINV1 SCINV0
Function as P42 I/O pin
Function as TXD32 output pin
CWOSR—Subclock Output Select Register
Bit
H'92
Timer A
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CWOS
Initial value
1
1
1
1
1
1
1
0
Read/Write
R
R
R
R
R
R
R
R/W
TMOW pin clock select
0
1
Clock output from TMA is output
øW is output
419
ECCSR—Event counter control/status register
Bit
H'95
AEC
7
6
5
4
3
2
1
0
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Counter reset control L
0 ECL is reset
1 ECL reset is cleared
and count-up function
is enabled
Counter reset control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel select
0 ECH and ECL are used together as a singlechannel 16-bit event counter
1
ECH and ECL are used as two independent
8-bit event counter channels
Counter overflow L
0 ECL has not overflowed
1 ECL has overflowed
Counter overflow H
0 ECH has not overflowed
1 ECH has overflowed
420
ECH—Event counter H
Bit
H'96
AEC
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECL—Event counter L
Bit
H'97
AEC
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
421
SMR31—Serial mode register 31
Bit
H'98
SCI31
7
6
5
4
3
2
COM31
CHR31
PE31
PM31
STOP31
MP31
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
CKS311 CKS310
Clock select
0 0 ø clock
0 1 øw/2 clock
1 0 ø/16 clock
1 1 ø/64 clock
Multiprocessor mode
0 Multiprocessor communication
function disabled
1 Multiprocessor communication
function enabled
Stop bit length
0 1 stop bit
1 2 stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character length
0 8-bit data/5-bit data
1 7-bit data/5-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
422
BRR31—Bit rate register31
Bit
7
H'99
6
5
4
3
2
SCI31
1
0
BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
423
SCR31—Serial control register 31
Bit
H'9A
3
SCI31
7
6
5
4
TIE31
RIE31
TE31
RE31
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
Clock enable
Bit 0
Bit 1
CKE311 CKE310 Communication Mode
Asynchronous
0
0
Synchronous
Asynchronous
1
0
Synchronous
Asynchronous
0
1
Synchronous
Asynchronous
1
1
Synchronous
Description
Clock Source
SCK 3 Pin Function
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Internal clock
Reserved (Do not specify this combination)
Clock input
External clock
Serial clock input
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (normal receive operation)
[Clearing conditions]
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0
Receive operation disabled (RXD pin is I/O port)
1
Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0
Transmit operation disabled (TXD pin is transmit data pin)
1
Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
424
0
MPIE31 TEIE31 CKE311 CKE310
TDR31—Transmit data register 31
Bit
7
6
H'9B
5
4
3
2
SCI31
1
0
TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for transfer to TSR
425
SSR31—Serial status register31
Bit
7
H'9C
6
4
5
TDRE31 RDRF31 OER31
Initial value
1
0
*
Read/Write
R/(W)
0
0
*
*
R/(W)
3
FER31
R/(W)
2
R/(W)
0
1
PER31 TEND31 MPBR31 MPBT31
0
*
SCI3
*
R/(W)
1
0
0
R
R
R/W
Multiprocessor bit transfer
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0
Data in which the multiprocessor bit is 0 has been received
1
Data in which the multiprocessor bit is 1 has been received
Transmit end
0
Transmission in progress
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE
• When data is written to TDR31 by an instruction
1
Transmission ended
[Setting conditions]
• When bit TE in serial control register 31 (SCR31) is cleared to 0
• When bit TDRE31 is set to 1 when the last bit of a transmit character is sent
Parity error
0
Reception in progress or completed normally
[Clearing conditions] After reading PER31 = 1, cleared by writing 0 to PER31
1
A parity error has occurred during reception
[Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM31) in the serial mode register (SMR31)
Framing error
0
Reception in progress or completed normally
[Clearing conditions] After reading FER31 = 1, cleared by writing 0 to FER31
1
A framing error has occurred during reception
[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0
Reception in progress or completed
[Clearing conditions] After reading OER31 = 1, cleared by writing 0 to OER31
1
An overrun error has occurred during reception
[Setting conditions] When the next serial reception is completed with RDRF31 set to 1
Receive data register full
0
There is no receive data in RDR31
[Clearing conditions] • After reading RDRF31 = 1, cleared by writing 0 to RDRF31
• When RDR31 data is read by an instruction
1
There is receive data in RDR31
[Setting conditions] When reception ends normally and receive data is transferred from RSR31 to RDR31
Transmit data register empty
0
Transmit data written in TDR31 has not been transferred to TSR31
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE31
• When data is written to TDR31 by an instruction
1
Transmit data has not been written to TDR31, or transmit data written in TDR31 has been transferred to TSR31
[Setting conditions] • When bit TE in serial control register 31 (SCR31) is cleared to 0
• When data is transferred from TDR31 to TSR31
Note: * Only a write of 0 for flag clearing is possible.
426
RDR31—Receive data register 31
Bit
7
6
H'F9D
5
4
3
2
SCI31
1
0
RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
427
SCR1—Serial control register 1
Bit
H'A0
SCI1
7
6
5
4
3
2
1
0
SNC1
SNC0
MRKON
LTCH
CKS3
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 2 to 0
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1
Prescaler
Division
Ratio
ø/1024
ø/256
ø/64
ø/32
ø/16
ø/8
ø/4
øW/4
Serial Clock Cycle
Clock Cycle
ø = 2.5 MHz
409.6 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
122 µs
Clock source select
0 Clock source is prescaler S, SCK1 is output pin
1 Clock source is external clock, SCK1 is input pin
LATCH TAIL select
0 HOLD TAIL is output
1 LATCH TAIL is output
Tail mark control
0 Tail mark is not output (synchronous mode)
1 Tail mark is output (SSB mode)
Operating mode select
0 0 8-bit synchronous mode
1 16-bit synchronous mode
1 0 Continuous clock output mode
1 Reserved
428
SCSR1—Serial control status register 1
Bit
H'A1
SCI1
7
6
5
4
3
2
1
0
—
SOL
ORER
—
—
—
MTRF
STF
Initial value
1
0
0
1
1
1
0
0
Read/Write
—
R/W
R/(W)*
—
—
—
R
R/W
Start flag
0 Read
Write
1 Read
Write
Transfer operation stopped
Invalid
Transfer operation in progress
Starts transfer operation
Tail mark transmission flag
0 Idle state, or 8-bit/16-bit data transfer in progress
1 Tail mark transmission in progress
Overrun error flag
0 Clearing conditions:
After reading ORER = 1, cleared by writing 0 to ORER
1 Setting conditions:
When an external clock is used and the clock is input
after transfer is completed
Extension data bit
0 Read SO1 pin output level is low
Write Changes SO1 pin output to low level
1 Read SO1 pin output level is high
Write Changes SO1 pin output to high level
Note: * Only a write of 0 for flag clearing is possible.
429
SDRU—Serial data register U
Bit
Initial value
Read/Write
H'A2
SCI1
7
6
5
4
3
2
1
0
SDRU7
SDRU6
SDRU5
SDRU4
SDRU3
SDRU2
SDRU1
SDRU0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Used for transmit data setting and receive data storage
8-bit transfer mode: Not used
16-bit transfer mode: Upper 8 bits of data register
SDRL—Serial data register L
Bit
Initial value
Read/Write
H'A3
SCI1
7
6
5
4
3
2
1
0
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Used for transmit data setting and receive data storage
8-bit transfer mode: Data register
16-bit transfer mode: Lower 8 bits of data register
430
SMR32—Serial mode register 32
Bit
H'A8
SCI32
7
6
5
4
3
2
COM32
CHR32
PE32
PM32
STOP32
MP32
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
CKS321 CKS320
Clock select
0 0 ø clock
0 1 øw/2 clock
1 0 ø/16 clock
1 1 ø/64 clock
Multiprocessor mode
0 Multiprocessor communication
function disabled
1 Multiprocessor communication
function enabled
Stop bit length
0 1 stop bit
1 2 stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character length
0 8-bit data/5-bit data
1 7-bit data/5-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
431
BRR32—Bit rate register 32
Bit
7
H'A9
6
5
4
3
2
SCI32
1
0
BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
432
SCR32—Serial control register 32
Bit
H'AA
3
SCI32
7
6
5
4
TIE32
RIE32
TE32
RE32
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
MPIE32 TEIE32 CKE321 CKE320
Clock enable
Bit 0
Bit 1
CKE321 CKE320 Communication Mode
Asynchronous
0
0
Synchronous
Asynchronous
1
0
Synchronous
Asynchronous
0
1
Synchronous
Asynchronous
1
1
Synchronous
Description
Clock Source
SCK 3 Pin Function
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Internal clock
Reserved (Do not specify this combination)
Clock input
External clock
Serial clock input
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (normal receive operation)
[Clearing conditions]
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0
Receive operation disabled (RXD pin is I/O port)
1
Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0
Transmit operation disabled (TXD pin is transmit data pin)
1
Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
433
TDR32—Transmit data register 32
Bit
7
6
H'AB
5
4
3
2
SCI32
1
0
TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for transfer to TSR
434
SSR32—Serial status register 32
Bit
7
H'AC
6
4
5
TDRE32 RDRF32 OER32
Initial value
1
0
*
Read/Write
R/(W)
0
0
*
*
R/(W)
3
FER32
R/(W)
2
R/(W)
0
1
PER32 TEND32 MPBR32 MPBT32
0
*
SCI32
*
R/(W)
1
0
0
R
R
R/W
Multiprocessor bit transfer
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0
Data in which the multiprocessor bit is 0 has been received
1
Data in which the multiprocessor bit is 1 has been received
Transmit end
0
Transmission in progress
[Clearing conditions] • After reading TDRE32 = 1, cleared by writing 0 to TDRE32
• When data is written to TDR32 by an instruction
1
Transmission ended
[Setting conditions]
• When bit TE in serial control register 32 (SCR32) is cleared to 0
• When bit TDRE32 is set to 1 when the last bit of a transmit character is sent
Parity error
0
Reception in progress or completed normally
[Clearing conditions] After reading PER32 = 1, cleared by writing 0 to PER32
1
A parity error has occurred during reception
[Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM32) in the serial mode register (SMR32)
Framing error
0
Reception in progress or completed normally
[Clearing conditions] After reading FER32 = 1, cleared by writing 0 to FER32
1
A framing error has occurred during reception
[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0
Reception in progress or completed
[Clearing conditions] After reading OER32 = 1, cleared by writing 0 to OER32
1
An overrun error has occurred during reception
[Setting conditions] When the next serial reception is completed with RDRF32 set to 1
Receive data register full
0
There is no receive data in RDR32
[Clearing conditions] • After reading RDRF32 = 1, cleared by writing 0 to RDRF32
• When RDR32 data is read by an instruction
1
There is receive data in RDR32
[Setting conditions] When reception ends normally and receive data is transferred from RSR32 to RDR32
Transmit data register empty
0
Transmit data written in TDR32 has not been transferred to TSR32
[Clearing conditions] • After reading TDRE32 = 1, cleared by writing 0 to TDRE32
• When data is written to TDR32 by an instruction
1
Transmit data has not been written to TDR32, or transmit data written in TDR32 has been transferred to TSR32
[Setting conditions] • When bit TE32 in serial control register 32 (SCR32) is cleared to 0
• When data is transferred from TDR32 to TSR32
Note: * Only a write of 0 for flag clearing is possible.
435
RDR32—Receive data register 32
Bit
7
H'AD
6
5
4
3
SCI32
2
0
1
RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TMA—Timer mode register A
Bit
H'B0
Timer A
7
6
5
4
3
2
1
0
TMA7
TMA6
TMA5
—
TMA3
TMA2
TMA1
TMA0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
Clock output select
0 0 0 ø/32
0 0 1 ø/16
0 1 0 ø/8
0 1 1 ø/4
1 0 0 ø W /32
1 0 1 ø W /16
1 1 0 ø W /8
1 1 1 ø W /4
436
Internal clock select
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0
0
0
0
PSS
ø/8192
0
0
1
0
PSS
ø/4096
0
0
PSS
1
0
ø/2048
0
0
PSS
1
1
ø/512
1
0
0
PSS
0
ø/256
1
1
0
PSS
0
ø/128
1
1
0
PSS
ø/32
0
1
1
1
PSS
ø/8
0
0
0
0
1
PSW
1s
0
0
1
1
PSW
0.5 s
1
0
0
PSW
0.25 s
1
0
1
1
PSW
0.03125 s
1
1
1
0
0
PSW and TCA are reset
1
1
0
1
1
1
1
0
1
1
1
1
Function
Interval
timer
Time
base
(when
using
32.768 kHz)
TCA—Timer counter A
Bit
H'B1
Timer A
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
437
TCSRW—Timer control/status register W
Bit
Initial value
Read/Write
H'B2
Watchdog timer
7
6
5
4
3
2
1
0
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
1
0
1
0
1
0
1
0
R
R/(W)*
R
R/(W)*
R
R/(W) *
R
R/(W) *
Watchdog timer reset
0 [Clearing conditions]
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 [Setting condition]
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0 Bit 0 is write-enabled
1 Bit 0 is write-protected
Watchdog timer on
0 Watchdog timer operation is disabled
1 Watchdog timer operation is enabled
Bit 2 write inhibit
0 Bit 2 is write-enabled
1 Bit 2 is write-protected
Timer control/status register W write enable
0 Data cannot be written to bits 2 and 0
1 Data can be written to bits 2 and 0
Bit 4 write inhibit
0 Bit 4 is write-enabled
1 Bit 4 is write-protected
Timer counter W write enable
0 Data cannot be written to TCW
1 Data can be written to TCW
Bit 6 write inhibit
0 Bit 6 is write-enabled
1 Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
438
TCW—Timer counter W
Bit
H'B3
Watchdog timer
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TMC—Timer mode register C
Bit
H'B4
Timer C
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
0 0 0 Internal clock: ø/8192
0 0 1 Internal clock: ø/2048
0 1 0 Internal clock: ø/512
0 1 1 Internal clock: ø/64
1 0 0 Internal clock: ø/16
1 0 1 Internal clock: ø/4
1 1 0 Internal clock: øw/4
External event (TMIC): Counting
1 1 1
on rising or falling edge
Counter up/down control
0 0 TCC is an up-counter
0 1 TCC is a down-counter
1 *
Hardware control of TCC up/down operation by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
Auto-reload function select
0 Interval timer function selected
1 Auto-reload function selected
* Don’t care
439
TCC—Timer counter C
Bit
H'B5
Timer C
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
TLC—Timer load register C
Bit
H'B5
Timer C
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reload value
440
TCRF—Timer control register F
Bit
H'B6
Timer F
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Clock select L
0
*
*
1
1
1
0
0
1
0
1
0
1
1
1
Counting on external event (TMIF)
rising/falling edge
Internal clock ø/32
Internal clock ø/16
Internal clock ø/4
Internal clock øw/4
Toggle output level L
0
1
Low level
High level
Clock select H
0
*
*
1
1
1
0
0
1
0
1
0
1
1
1
Toggle output level H
0
1
16-bit mode, counting on TCFL
overflow signal
Internal clock ø/32
Internal clock ø/16
Internal clock ø/4
Internal clock øw/4
* Don’t care
Low level
High level
441
TCSRF—Timer control/status register F
Bit
H'B7
Timer F
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/(W)*
R/(W)*
R/W
R/W
Counter clear L
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
Timer overflow interrupt enable L
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
Compare match flag L
0
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting conditions:
Set when the TCFL value matches the OCRFL value
Timer overflow flag L
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when TCFL overflows from H'FF to H'00
Counter clear H
0
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer overflow interrupt enable H
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
Compare match flag H
0
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
Timer overflow flag H
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
442
TCFH—8-bit timer counter FH
Bit
H'B8
Timer F
7
6
5
4
3
2
1
0
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TCFL—8-bit timer counter FL
Bit
H'B9
Timer F
7
6
5
4
3
2
1
0
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
OCRFH—Output compare register FH
Bit
7
6
5
H'BA
4
3
2
Timer F
1
0
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OCRFL—Output compare register FL
Bit
7
6
5
H'BB
4
3
2
Timer F
1
0
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
443
TMG—Timer mode register G
Bit
H'BC
Timer G
7
6
5
4
3
2
1
0
CKS0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
W
W
W
W
W
W
Clock select
0 0
0 1
Internal clock: counting on ø/64
Internal clock: counting on ø/32
1 0
1 1
Internal clock: counting on ø/2
Internal clock: counting on øw/4
Counter clear
0 0 TCG clearing is disabled
0 1 TCG cleared by falling edge of input capture input signal
1 0 TCG cleared by rising edge of input capture input signal
1 1 TCG cleared by both edges of input capture input signal
Input capture interrupt edge select
0 Interrupt generated on rising edge of input capture input signal
1 Interrupt generated on falling edge of input capture input signal
Timer overflow interrupt enable
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
Timer overflow flag L
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting conditions:
Set when TCG overflows from H'FF to H'00
Timer overflow flag H
0 Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
444
ICRGF—Input capture register GF
Bit
7
6
H'BD
5
4
3
2
Timer G
1
0
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ICRGR—Input capture register GR
Bit
7
6
H'BE
5
4
3
2
Timer G
1
0
ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
445
LPCR—LCD port control register
Bit
H'C0
LCD controller/driver
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Segment driver select
Bit 4 Bit 3
Bit 2 Bit 1 Bit 0 Function of Pins SEG32 to SEG1
SEG40
SEG32
SEG24
SEG16
SEG8
SGX SGS3 SGS2 SGS1 SGS0 to SEG33 to SEG25 to SEG17 to SEG9 to SEG1
0
0
0
0
0
Port
Port
Port
Port
Port
0
0
1
0
0
SEG
Port
Port
Port
Port
0
1
0
0
SEG
SEG
Port
Port
Port
*
1
0
0
0
SEG
SEG
SEG
Port
Port
*
1
1
0
0
SEG
SEG
SEG
SEG
Port
*
0
1
SEG
SEG
SEG
SEG
SEG
*
*
*
0
0
0
1
0
Port*1
Port
Port
Port
Port
0
0
1
1
0
Do not use
0
1
1
0
*
1
1
0
*
*
1
1
*
*
*
Note: *1. SEG40 to SEG37 are external expansion pins.
Notes
(Initial value)
*: Don’t care
Expansion signal select
0
SEG40 to SEG37 pin* (Initial value)
1
CL1, CL2, DO and M pin
Note: * Functions as ports when SGS3 to SGS0 are set at "0000".
Duty select, common function select
Bit 7 Bit 6 Bit 5
Duty Cycle Common Drivers
DTS1 DTS0 CMX
0
0
COM1
0
Static
0
1
0
COM4 to COM1
1
0
0
COM2 to COM1
1/2 duty
1
1
COM4 to COM1
0
0
0
COM3 to COM1
1
1/3 duty
0
1
COM4 to COM1
1
1
0
1
COM4 to COM1
1/4 duty
1
1
1
446
Notes
Do not use COM4, COM3, and COM2
COM4 to COM2 output the same waveform as COM1
Do not use COM4 and COM3
COM4 outputs the same waveform as COM3 and COM2 outputs the same waveform as COM1
Do not use COM4
Do not use COM4
—
LCR—LCD control register
Bit
H'C1
LCD controller/driver
7
6
5
4
3
2
1
0
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame frequency select
Bit 3 Bit 2 Bit 1 Bit 1
CKS3 CKS2 CKS1 CKS0
0
0
0
1
1
1
1
1
1
1
1
*
*
*
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
Display data control
0
1
*
0
1
0
1
0
1
0
1
Operating Clock
øw
øw
øw/2
ø/2
ø/4
ø/8
ø/16
ø/32
ø/64
ø/128
ø/256
* Don’t care
0 Blank data is displayed
1 LCD RAM data is displayed
Display function activate
0 LCD controller/driver operation halted
1 LCD controller/driver operates
LCD drive power supply on/off control
0 LCD drive power supply off
1 LCD drive power supply on
447
LCR2—LCD control register 2
Bit
H'C2
LCD
7
6
5
4
3
2
1
0
LCDAB
—
—
SUPS
CDS3
CDS2
CDS1
CDS0
Initial value
0
1
1
0
0
0
0
0
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
Charge/discharge pulse duty cycle select
Bit 3 Bit 2 Bit 1 Bit 1
Duty Cycle
CDS3 CDS2 CDS1 CDS0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
*
*
0
1
0
1
0
1
0
1
*
*
1
1/8
2/8
3/8
4/8
5/8
6/8
0
1/16
1/32
* Don’t care
Drive power supply selection and step-up
constant-voltage (5 V) power supply control
0 Drive power supply is VCC, step-up constant-voltage (5 V)
power supply operation is halted
1 Drive power supply is 5 V, step-up constant-voltage (5 V)
power supply operates
A waveform/B waveform switching control
0 Drive using A waveform
1 Drive using B waveform
448
AMR—A/D mode register
Bit
H'C6
A/D converter
7
6
5
4
3
2
1
0
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
Channel select
Bit 3 Bit 2 Bit 1
CH3 CH2 CH1
0
0
*
0
0
1
0
0
1
0
1
1
1
0
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Bit 0
CH0
*
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input Channel
No channel selected
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
AN 8
AN 9
AN 10
AN 11
* Don’t care
External trigger select
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge
of external trigger at pin ADTRG
Clock select
Bit 7
CKS Conversion Period
0
62/ø
1
31/ø
Conversion Time
ø = 1 MHz ø = 2 MHz
62 µs
31 µs
31 µs
15.5 µs*
Note: * Operation is not guaranteed with a conversion time of less than 15.5 µs
Select a setting that gives a conversion time of at least 15.5 µs.
449
ADRRH—A/D result register H
ADRRL—A/D result register L
H'C4
H'C5
A/D converter
ADRRH
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
R
R
R
R
R
R
R
A/D conversion result
ADRRL
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR1
ADR0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Undefined Undefined
R
R
A/D conversion result
ADSR—A/D start register
Bit
H'C7
A/D converter
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
A/D status flag
0 Read Indicates completion of A/D conversion
Write Stops A/D conversion
1 Read Indicates A/D conversion in progress
Write Starts A/D conversion
450
PMR1—Port mode register 1
Bit
H'C8
7
6
5
4
3
2
1
0
IRQ3
IRQ2
IRQ1
IRQ4
TMIG
TMOFH
TMOFL
TMOW
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
I/O port
P10/TMOW pin function switch
0 Functions as P10 I/O pin
1 Functions as TMOW output pin
P11/TMOFL pin function switch
0 Functions as P11 I/O pin
1 Functions as TMOFL output pin
P12/TMOFH pin function switch
0 Functions as P12 I/O pin
1 Functions as TMOFH output pin
P13/TMIG pin function switch
0 Functions as P13 I/O pin
1 Functions as TMIG input pin
P14/IRQ4/ADTRG pin function switch
0 Functions as P14 I/O pin
1 Functions as IRQ4/ADTRG input pin
P15/IRQ1/TMIC pin function switch
0 Functions as P15 I/O pin
1 Functions as IRQ1/TMIC input pin
P16/IRQ2 pin function switch
0 Functions as P16 I/O pin
1 Functions as IRQ2 input pin
P17/IRQ3/TMIF pin function switch
0 Functions as P17 I/O pin
1 Functions as IRQ3/TMIF input pin
451
PMR2—Port mode register 2
Bit
H'C9
I/O port
7
6
5
4
3
2
1
0
—
—
POF1
—
—
SO1
SI1
SCK1
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
P20/SCK1 pin function switch
0 Functions as P20 I/O pin
1 Functions as SCK1 I/O pin
P21/SI1 pin function switch
0 Functions as P21 I/O pin
1 Functions as SI1 input pin
P22/SO1 pin function switch
0 Functions as P22 I/O pin
1 Functions as SO1 output pin
P22/SO1 pin PMOS control
0 CMOS output
1 NMOS open-drain output
452
PMR3—Port mode register 3
Bit
H'CA
7
6
5
4
3
2
1
0
AEVL
AEVH
WDCKS
NCS
IRQ0
RESO
UD
PWM
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
I/O port
P30/PWM pin function switch
0 Functions as P30 I/O pin
1 Functions as PWM output pin
P31/UD pin function switch
0 Functions as P31 I/O pin
1 Functions as UD input pin
P32/RESO pin function switch
0 Functions as P32 I/O pin
1 Functions as RESO I/O pin
P43/IRQ0 pin function switch
0 Functions as P43 I/O pin
1 Functions as IRQ0 input pin
TMIG noise canceler select
0 Noise cancellation function not used
1 Noise cancellation function used
Watchdog timer switch
0 ø8192
1 øw/4
P36/AEVH pin function switch
0 Functions as P36 I/O pin
1 Functions as AEVH input pin
P37/AEVL pin function switch
0 Functions as P37 I/O pin
1 Functions as AEVL input pin
453
PMR4—Port mode register 4
Bit
7
6
H'CB
5
4
3
I/O port
2
1
0
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 P2n is CMOS output
1 P2n is NMOS open-drain output
(n = 7 to 0)
PMR5—Port mode register 5
Bit
H'CC
I/O port
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5n/WKPn/SEGn+1 pin function switch
0 Functions as P5n I/O pin
1 Functions as WKPn input pin
(n = 7 to 0)
454
PWCR—PWM control register
Bit
H'D0
14-bit PWM
7
6
5
4
3
2
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
1
0
PWCR1 PWCR0
Clock select
0 The input clock is ø/2 (tø* = 2/ø)
The conversion period is 16,384/ø, with a minimum modulation width of 1/ø
The input clock is ø/4 (tø* = 4/ø)
The conversion period is 32,768/ø, with a minimum modulation width of 2/ø
1 The input clock is ø/8 (tø* = 8/ø)
The conversion period is 65,536/ø, with a minimum modulation width of 4/ø
The input clock is ø/16 (tø* = 16/ø)
The conversion period is 131,072/ø, with a minimum modulation width of 8/ø
Note: * tø: Period of PWM input clock
PWDRU—PWM data register U
Bit
7
6
—
—
H'D1
5
4
3
2
14-bit PWM
1
0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
Upper 6 bits of data for generating PWM waveform
PWDRL—PWM data register L
Bit
7
6
H'D2
5
4
3
2
14-bit PWM
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Lower 8 bits of data for generating PWM waveform
455
PDR1—Port data register 1
Bit
H'D4
I/O ports
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P1 3
P1 2
P11
P10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR2—Port data register 2
Bit
H'D5
I/O ports
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3—Port data register 3
Bit
H'D6
I/O ports
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P33
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR4—Port data register 4
Bit
H'D7
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
P43
P42
P41
P40
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
PDR5—Port data register 5
Bit
H'D8
I/O ports
7
6
5
4
3
2
1
0
P5 7
P56
P55
P54
P53
P52
P51
P50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
456
PDR6—Port data register 6
Bit
H'D9
I/O ports
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P63
P62
P61
P60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7—Port data register 7
Bit
H'DA
I/O ports
7
6
5
4
3
2
1
0
P7 7
P76
P75
P74
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8—Port data register 8
Bit
H'DB
I/O ports
7
6
5
4
3
2
1
0
P8 7
P86
P85
P84
P83
P82
P81
P80
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9—Port data register 9
Bit
H'DC
I/O ports
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDRA—Port data register A
Bit
H'DD
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
PA3
PA2
PA1
PA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
457
PDRB—Port data register B
Bit
Read/Write
H'DE
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
R
R
R
R
R
R
R
R
PDRC—Port data register C
Bit
Read/Write
H'DF
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
PC3
PC2
PC1
PC0
—
—
—
—
R
R
R
R
PUCR1—Port pull-up control register 1
Bit
I/O ports
7
6
5
H'E0
4
3
2
I/O ports
1
0
PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3—Port pull-up control register 3
Bit
7
6
5
H'E1
4
3
2
I/O ports
1
0
PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5—Port pull-up control register 5
Bit
7
6
5
H'E2
4
3
2
I/O ports
1
0
PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
458
PUCR6—Port pull-up control register 6
Bit
7
6
5
H'E3
4
3
2
I/O ports
1
0
PUCR6 7 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCR1—Port control register 1
Bit
H'E4
I/O ports
7
6
5
4
3
2
1
0
PCR17
PCR16
PCR15
PCR14
PCR13
PCR1 2
PCR11
PCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 1 input/output select
0 Input pin
1 Output pin
PCR2—Port control register 2
Bit
H'E5
I/O ports
7
6
5
4
3
2
1
0
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 2 input/output select
0 Input pin
1 Output pin
459
PCR3—Port control register 3
Bit
H'E6
I/O ports
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR3 4
PCR3 3
PCR32
PCR31
PCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 input/output select
0 Input pin
1 Output pin
PCR4—Port control register 4
Bit
H'E7
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
—
PCR42
PCR41
PCR40
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
Port 4 input/output select
0 Input pin
1 Output pin
PCR5—Port control register 5
Bit
H'E8
I/O ports
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 5 input/output select
0 Input pin
1 Output pin
460
PCR6—Port control register 6
Bit
H'E9
I/O ports
7
6
5
4
3
2
1
0
PCR6 7
PCR6 6
PCR6 5
PCR6 4
PCR6 3
PCR6 2
PCR6 1
PCR6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 6 input/output select
0 Input pin
1 Output pin
PCR7—Port control register 7
Bit
H'EA
I/O ports
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 7 input/output select
0 Input pin
1 Output pin
PCR8—Port control register 8
Bit
H'EB
I/O ports
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 8 input/output select
0 Input pin
1 Output pin
461
PCR9—Port control register 9
Bit
H'EC
I/O ports
7
6
5
4
3
2
1
0
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 9 input/output select
0 Input pin
1 Output pin
PCRA—Port control register A
Bit
H'ED
7
6
5
4
3
2
—
—
—
—
PCRA 3
PCRA 2
I/O ports
1
0
PCRA 1 PCRA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Port A input/output select
0 Input pin
1 Output pin
462
SYSCR1—System control register 1
Bit
H'F0
System control
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Active (medium-speed)
mode clock select
0 0 øosc /16
1 øosc /32
1 0 øosc /64
1 ø osc /128
Low speed on flag
0 The CPU operates on the system clock (ø)
1 The CPU operates on the subclock (øSUB )
Standby timer select 2 to 0
0 0 0 Wait time = 8,192 states
1 Wait time = 16,384 states
1 0 Wait time = 32,768 states
1 Wait time = 65,536 states
1 0 0 Wait time = 131,072 states
1 Wait time = 2 states
1 0 Wait time = 8 states
1 Wait time = 16 states
Software standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
463
SYSCR2—System control register 2
Bit
H'F1
System control
7
6
5
4
3
2
1
0
—
—
—
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Subactive mode clock select
Medium speed on flag
0 0 ø W /8
1 ø W /4
1 * ø W /2
*: Don’t care
0 Operates in active (high-speed) mode
1 Operates in active (medium-speed) mode
Direct transfer on flag
0 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode
1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1
Noise elimination sampling frequency select
0 Sampling rate is øOSC /16
1 Sampling rate is øOSC /4
464
IEGR—IRQ edge select register
Bit
H'F2
System control
7
6
5
4
3
2
1
0
—
—
—
IEG4
IEG3
IEG2
IEG1
IEG0
Initial value
0
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
IRQ0 edge select
0 Falling edge of IRQ0 pin input is detected
1 Rising edge of IRQ0 pin input is detected
IRQ1 edge select
0 Falling edge of IRQ1, TMIC pin input is detected
1 Rising edge of IRQ1, TMIC pin input is detected
IRQ2 edge select
0 Falling edge of IRQ2 pin input is detected
1 Rising edge of IRQ2 pin input is detected
IRQ3 edge select
0 Falling edge of IRQ3, TMIF pin input is detected
1 Rising edge of IRQ3, TMIF pin input is detected
IRQ4 edge select
0 Falling edge of IRQ4 pin and ADTRG pin is detected
1 3. Rising edge of IRQ4 pin and ADTRG pin is detected
465
IENR1—Interrupt enable register 1
Bit
H'F3
System control
7
6
5
4
3
2
1
0
IENTA
IENS1
IENWP
IEN4
IEN3
IEN2
IEN1
IEN0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ4 to IRQ0 interrupt enable
0 Disables IRQ4 to IRQ0 interrupt requests
1 Enables IRQ4 to IRQ0 interrupt requests
Wakeup interrupt enable
0 Disables WKP7 to WKP0 interrupt requests
1 Enables WKP7 to WKP0 interrupt requests
SCI1 interrupt enable
0 Disables SCI1 interrupt requests
1 Enables SCI1 interrupt requests
Timer A interrupt enable
0 Disables timer A interrupt requests
1 Enables timer A interrupt requests
466
IENR2—Interrupt enable register 2
Bit
7
6
5
4
IENDT
IENAD
—
IENTG
H'F4
3
2
IENTFH IENTFL
1
0
IENTC
IENEC
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)
R/(W)
R/W
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
System control
Asynchronous event counter interrupt enable
0 Disables asynchronous event counter
interrupt requests
1 Enables asynchronous event counter
interrupt requests
Timer C interrupt enable
0 Disables timer C interrupt requests
1 Enables timer C interrupt requests
Timer FL interrupt enable
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Timer FH interrupt enable
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
Timer G interrupt enable
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
A/D converter interrupt enable
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Direct transition interrupt enable
0 Disables direct transition interrupt requests
1 Enables direct transition interrupt requests
467
IRR1—Interrupt request register 1
Bit
H'F6
System control
7
6
5
4
3
2
1
0
IRRTA
IRRS1
—
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ4 to IRQ0 interrupt request flags
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
(n = 4 to 0)
SCI1 interrupt request flag
0 Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
1 Setting conditions:
When SCI1 completes transfer
Timer A interrupt request flag
0 Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows (rom H'FF to H'00)
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
468
IRR2—Interrupt request register 2
Bit
H'F7
7
6
5
4
IRRDT
IRRAD
—
IRRTG
3
1
0
IRRTC
IRREC
2
IRRTFH IRRTFL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
System control
Asynchronous event counter interrupt request flag
0 Clearing conditions:
When IRREC = 1, it is cleared by writing 0
1 Setting conditions:
When the asynchronous event counter value overflows
Timer C interrupt request flag
0 Clearing conditions:
When IRRTC = 1, it is cleared by writing 0
1 Setting conditions:
When the timer C counter value overflows
(from H'FF to H'00) or underflows (from H'00 to H'FF)
Timer FL interrupt request flag
0 Clearing conditions:
When IRRTFL = 1, it is cleared by writing 0
1 Setting conditions:
When counter FL and output compare register FL
match in 8-bit timer mode
Timer FH interrupt request flag
0 Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When counter FH and output compare register FH match
in 8-bit timer mode, or when 16-bit counters FL and FH
and output compare registers FL and FH match in 16-bit timer mode
Timer G interrupt request flag
0 Clearing conditions:
When IRRTG = 1, it is cleared by writing 0
1 Setting conditions:
When the TMIG pin is designated for TMIG input and
the designated signal edge is input
A/D converter interrupt request flag
0 Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
1 Setting conditions:
When the A/D converter completes conversion and
ADSF is reset
Direct transition interrupt request flag
0 Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1 Setting conditions:
When a SLEEP instruction is executed while DTON is
set to 1, and a direct transition is made
Note: * Bits 7, 6 and 4 to 0 can only be written with 0, for flag clearing.
469
IWPR—Wakeup interrupt request register
Bit
H'F9
System control
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Wakeup interrupt request register
0 Clearing conditions:
When IWPFn = 1, it is cleared by writing 0
1 Setting conditions:
When pin WKPn is designated for wakeup input and a
falling edge is input at that pin
(n = 7 to 0)
Note: * All bits can only be written with 0, for flag clearing.
470
CKSTPR1—Clock stop register 1
Bit
7
6
H'FA
4
5
3
2
System control
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer A module standby mode control
0 Timer A is set to module standby mode
1 Timer A module standby mode is cleared
Timer C module standby mode control
0 Timer C is set to module standby mode
1 Timer C module standby mode is cleared
Timer F module standby mode control
0 Timer F is set to module standby mode
1 Timer F module standby mode is cleared
Timer G interrupt enable
0 Timer G is set to module standby mode
1 Timer G module standby mode is cleared
A/D converter module standby mode control
0 A/D converter is set to module standby mode
1 A/D converter module standby mode is cleared
SCI3-2 module standby mode control
0 SCI3-2 is set to module standby mode
1 SCI3-2 module standby mode is cleared
SCI3-1 module standby mode control
0 SCI3-1 is set to module standby mode
1 SCI3-1 module standby mode is cleared
SCI1 module standby mode control
0 SCI1 is set to module standby mode
1 SCI1 module standby mode is cleared
471
CKSTPR2—Clock stop register 2
Bit
H'FB
System control
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
3
2
1
0
AECKSTP WDCKSTP PWCKSTP LDCKSTP
LCD module standby mode control
0 LCD is set to module standby mode
1 LCD module standby mode is cleared
PWM module standby mode control
0 PWM is set to module standby mode
1 PWM module standby mode is cleared
WDT module standby mode control
0 WDT is set to module standby mode
1 WDT module standby mode is cleared
Asynchronous event counter module standby mode control
0 Asynchronous event counter is set to module standby mode
1 Asynchronous event counter module standby mode is cleared
472
Appendix C I/O Port Block Diagrams
C.1
Block Diagrams of Port 1
SBY
(low level
during reset
and in standby
mode)
PUCR1n
VCC
VCC
PDR1n
P1n
VSS
PCR1n
Internal data bus
PMR1n
IRQn–4
PDR1:
PCR1:
PMR1:
PUCR1:
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
n = 7 to 4
Figure C-1 (a) Port 1 Block Diagram (Pins P17 to P14)
473
SBY
PUCR13
VCC
VCC
Internal data bus
PMR13
PDR13
P13
PCR13
VSS
Timer G
module
TMIG
Figure C-1 (b) Port 1 Block Diagram (Pin P13)
Timer F
module
SBY
TMOFH (P12)
TMOFL (P11)
PUCR1n
VCC
PMR1n
PDR1n
P1n
PCR1n
VSS
PDR1:
PCR1:
PMR1:
PUCR1:
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
n= 2, 1
Figure C-1 (c) Port 1 Block Diagram (Pin P12, P11)
474
Internal data bus
VCC
Timer A
module
SBY
TMOW
PUCR10
VCC
VCC
PDR10
P10
PCR10
VSS
PDR1:
PCR1:
PMR1:
PUCR1:
Internal data bus
PMR10
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
Figure C-1 (d) Port 1 Block Diagram (Pin P10)
475
C.2
Block Diagrams of Port 2
SBY
PMR4n
PDR2n
P2n
PCR2n
VSS
PDR2: Port data register 2
PCR2: Port control register 2
PMR4: Port mode register 4
n = 7 to 3
Figure C-2 (a) Port 2 Block Diagram (Pins P27 to P23)
476
Internal data bus
VCC
SCI1 module
SO1
SBY
PMR25
PMR42
PMR22
P22
PDR22
VSS
Internal data bus
VCC
PCR22
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C-2 (b) Port 2 Block Diagram (Pin P22)
477
SBY
PMR41
PMR21
P21
PDR21
VSS
Internal data bus
VCC
PCR21
SCI module
SI
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C-2 (c) Port 2 Block Diagram (Pin P21)
478
SCI module
EXCK
SCK0
SCK1
SBY
PMR40
PMR20
P20
PDR20
VSS
Internal data bus
VCC
PCR20
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C-2 (d) Port 2 Block Diagram (Pin P20)
479
C.3
Block Diagrams of Port 3
SBY
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
Internal data bus
VCC
PCR3n
AEC module
AEVH(P36)
AEVL(P37)
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n=7 to 6
Figure C-3 (a) Port 3 Block Diagram (Pin P37 to P36)
480
SBY
PUCR3
SCINV1
VCC
SCI31 module
VCC
TE31
P35
PDR35
PCR35
Internal data bus
TXD31
VSS
PDR3: Port data register 3
PCR3: Port control register 3
Figure C.3 (b) Port 3 Block Diagram (Pin P35)
481
SBY
PUCR3
VCC
VCC
SCI31 module
RE31
P34
PDR34
PCR34
VSS
SCINV0
PDR3: Port data register 3
PCR3: Port control register 3
Figure C.3 (c) Port 3 Block Diagram (Pin P34)
482
Internal data bus
RXD31
SBY
PUCR3
SCI31 module
VCC
SCKIE31
SCKOE31
VCC
SCKO31
SCKI31
P33
PCR33
VSS
Internal data bus
PDR33
PDR3: Port data register 3
PCR3: Port control register 3
Figure C.3 (d) Port 3 Block Diagram (Pin P33)
483
SBY
RESO
PUCR32
VCC
PMR32
P32
PDR32
VSS
PCR32
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C.3 (e) Port 3 Block Diagram (Pin P32)
484
Internal data bus
VCC
SBY
PUCR31
VCC
PMR31
PDR31
P31
Internal data bus
VCC
PCR31
VSS
Timer C
module
UD
PDR3:
PCR3:
PMR3:
PUCR3:
Port data register 3
Port control register 3
Port mode register 3
Port pull-up control register 3
Figure C-3 (f) Port 3 Block Diagram (Pin P31)
485
PWM module
SBY
PWM
PUCR30
VCC
PMR30
P30
PDR30
VSS
PCR30
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C-3 (g) Port 3 Block Diagram (Pin P30)
486
Internal data bus
VCC
C.4
Block Diagrams of Port 4
Internal data bus
PMR43
P43
IRQ0
PMR4: Port mode register 4
Figure C.4 (a) Port 4 Block Diagram (Pin P4 3)
487
SBY
SCINV3
SCI32 module
VCC
TE32
TXD32
P42
PCR42
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.4 (b) Port 4 Block Diagram (Pin P42)
488
Internal data bus
PDR42
SBY
VCC
SCI32 module
RE32
RXD32
P41
PCR41
VSS
Internal data bus
PDR41
SCINV2
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.4 (c) Port 4 Block Diagram (Pin P41)
489
SBY
SCI32 module
SCKIE32
SCKOE32
VCC
SCKO32
SCKI32
P40
PCR40
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.4 (d) Port 4 Block Diagram (Pin P40)
490
Internal data bus
PDR40
C.5
Block Diagram of Port 5
SBY
PUCR5n
VCC
VCC
P5n
PDR5n
VSS
PCR5n
Internal data bus
PMR5n
WKPn
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
n = 7 to 0
Figure C.5 Port 5 Block Diagram
491
C.6
Block Diagram of Port 6
SBY
VCC
PDR6n
VCC
PCR6n
P6n
VSS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure C.6 Port 6 Block Diagram
492
Internal data bus
PUCR6n
C.7
Block Diagram of Port 7
SBY
PDR7n
PCR7n
P7n
Internal data bus
VCC
VSS
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure C.7 Port 7 Block Diagram
493
C.8
Block Diagrams of Port 8
VCC
PDR8n
PCR8n
P8n
VSS
PDR8:
Port data register 8
PCR8:
Port control register 8
n= 7 to 0
Figure C-8 Port 8 Block Diagram
494
Internal data bus
SBY
C.9
Block Diagram of Port 9
SBY
PDR9n
PCR9n
P9n
Internal data bus
VCC
VSS
PDR9: Port data register 9
PCR9: Port control register 9
n = 7 to 0
Figure C-9 Port 9 Block Diagram
495
C.10
Block Diagram of Port A
SBY
VCC
PCRAn
PAn
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure C.10 Port A Block Diagram
496
Internal data bus
PDRAn
C.11
Block Diagram of Port B
Internal
data bus
PBn
A/D module
DEC
AMR3 to AMR0
VIN
n = 7 to 0
Figure C-11 Port B Block Diagram
497
Block Diagram of Port C
Internal data bus
C.12
PCn
A/D module
DEC
AMR3 to 0
VIN
n = 3 to 0
Figure C-12 Port C Block Diagram
498
Appendix D Port States in the Different Processing States
Table D-1
Port
Port States Overview
Reset
Sleep
Subsleep
Standby
P17 to P10 Highimpedance
Retained
Retained
P27 to P20 Highimpedance
Retained
Watch
Subactive
Active
HighRetained
impedance*1
Functions
Functions
Retained
Highimpedance
Retained
Functions
Functions
P37 to P30 HighRetained
impedance*2
Retained
HighRetained
impedance*1
Functions
Functions
P43 to P40 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P57 to P50 Highimpedance
Retained
Retained
HighRetained
impedance*1
Functions
Functions
P67 to P60 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P77 to P70 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P87 to P80 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P97 to P90 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
PA 3 to PA0 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
PB 7 to PB0 Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
PC3 to PC0 Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Notes: 1. High level output when MOS pull-up is in on state.
2. Reset output from P32 pin only.
499
Appendix E List of Product Codes
Table E.1
Product Code Lineup
Product Type
Product Code
Mark Code
Package (Hitachi Package Code)
H8/3887 H8/3882 Mask ROM
HD6433882H
HD6433882(***)H
100-pin QFP (FP-100B)
Series
versions
H8/3883 Mask ROM
versions
H8/3884 Mask ROM
versions
H8/3885 Mask ROM
versions
H8/3886 Mask ROM
versions
H8/3887 Mask ROM
versions
ZTAT
versions
HD6433882F
HD6433882(***)F
100-pin QFP (FP-100A)
HD6433882X
HD6433882(***)X
100-pin TQFP (TFP-100B)
HD6433882W
HD6433882(***)W
100-pin TQFP (TFP-100G)
HD6433883H
HD6433883(***)H
100-pin QFP (FP-100B)
HD6433883F
HD6433883(***)F
100-pin QFP (FP-100A)
HD6433883X
HD6433883(***)X
100-pin TQFP (TFP-100B)
HD6433883W
HD6433883(***)W
100-pin TQFP (TFP-100G)
HD6433884H
HD6433884(***)H
100-pin QFP (FP-100B)
HD6433884F
HD6433884(***)F
100-pin QFP (FP-100A)
HD6433884X
HD6433884(***)X
100-pin TQFP (TFP-100B)
HD6433884W
HD6433884(***)W
100-pin TQFP (TFP-100G)
HD6433885H
HD6433885(***)H
100-pin QFP (FP-100B)
HD6433885F
HD6433885(***)F
100-pin QFP (FP-100A)
HD6433885X
HD6433885(***)X
100-pin TQFP (TFP-100B)
HD6433885W
HD6433885(***)W
100-pin TQFP (TFP-100G)
HD6433886H
HD6433886(***)H
100-pin QFP (FP-100B)
HD6433886F
HD6433886(***)F
100-pin QFP (FP-100A)
HD6433886X
HD6433886(***)X
100-pin TQFP (TFP-100B)
HD6433886W
HD6433886(***)W
100-pin TQFP (TFP-100G)
HD6433887H
HD6433887(***)H
100-pin QFP (FP-100B)
HD6433887F
HD6433887(***)F
100-pin QFP (FP-100A)
HD6433887X
HD6433887(***)X
100-pin TQFP (TFP-100B)
HD6433887W
HD6433887(***)W
100-pin TQFP (TFP-100G)
HD6473887H
HD6473887H
100-pin QFP (FP-100B)
HD6473887F
HD6473887F
100-pin QFP (FP-100A)
HD6473887X
HD6473887X
100-pin TQFP (TFP-100B)
HD6473887W
HD6473887W
100-pin TQFP (TFP-100G)
Note: For mask ROM versions, (***) is the ROM code.
500
Table E.1
Product Code Lineup (Cont)
Product Type
Product Code
Mark Code
Package (Hitachi Package Code)
H8/3847 H8/3842 Mask ROM
HD6433842H
HD6433842(***)H
100-pin QFP (FP-100B)
Series
HD6433842F
HD6433842(***)F
100-pin QFP (FP-100A)
HD6433842X
HD6433842(***)X
100-pin TQFP (TFP-100B)
versions
H8/3843 Mask ROM
versions
H8/3844 Mask ROM
versions
H8/3845 Mask ROM
versions
H8/3846 Mask ROM
versions
H8/3847 Mask ROM
versions
HD6433842W
HD6433842(***)W
100-pin TQFP (TFP-100G)
HD6433843H
HD6433843(***)H
100-pin QFP (FP-100B)
HD6433843F
HD6433843(***)F
100-pin QFP (FP-100A)
HD6433843X
HD6433843(***)X
100-pin TQFP (TFP-100B)
HD6433843W
HD6433843(***)W
100-pin TQFP (TFP-100G)
HD6433844H
HD6433844(***)H
100-pin QFP (FP-100B)
HD6433844F
HD6433844(***)F
100-pin QFP (FP-100A)
HD6433844X
HD6433844(***)X
100-pin TQFP (TFP-100B)
HD6433844W
HD6433844(***)W
100-pin TQFP (TFP-100G)
HD6433845H
HD6433845(***)H
100-pin QFP (FP-100B)
HD6433845F
HD6433845(***)F
100-pin QFP (FP-100A)
HD6433845X
HD6433845(***)X
100-pin TQFP (TFP-100B)
HD6433845W
HD6433845(***)W
100-pin TQFP (TFP-100G)
HD6433846H
HD6433846(***)H
100-pin QFP (FP-100B)
HD6433846F
HD6433846(***)F
100-pin QFP (FP-100A)
HD6433846X
HD6433846(***)X
100-pin TQFP (TFP-100B)
HD6433846W
HD6433846(***)W
100-pin TQFP (TFP-100G)
HD6433847H
HD6433847(***)H
100-pin QFP (FP-100B)
HD6433847F
HD6433847(***)F
100-pin QFP (FP-100A)
HD6433847X
HD6433847(***)X
100-pin TQFP (TFP-100B)
HD6433847W
HD6433847(***)W
100-pin TQFP (TFP-100G)
ZTAT
HD6473847H
HD6473847H
100-pin QFP (FP-100B)
versions
HD6473847F
HD6473847F
100-pin QFP (FP-100A)
HD6473847X
HD6473847X
100-pin TQFP (TFP-100B)
HD6473847W
HD6473847W
100-pin TQFP (TFP-100G)
Note: For mask ROM versions, (***) is the ROM code.
501
Appendix F Package Dimensions
Dimensional drawings of H8/3887 and H8/3847 packages FP-100A, FP-100B, TFP-100B and
TFP-100G are shown in following figures F-1, F-2, F-3 and F-4, respectively.
24.8 ± 0.4
Unit: mm
20
51
50
100
31
0.58
0.15
*Dimension including the plating thickness
Base material dimension
2.70
M
*0.17 ± 0.05
0.15 ± 0.04
30
0.13
0.20 +0.10
–0.20
1
*0.32 ± 0.08
0.30 ± 0.06
3.10 Max
0.65
81
14
18.8 ± 0.4
80
0.83
0° – 10°
1.2 ± 0.2
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
Figure F-1 FP-100A Package Dimensions
502
2.4
FP-100A
—
—
1.7 g
Unit: mm
16.0 ± 0.3
14
75
51
50
100
26
0.10
*Dimension including the plating thickness
Base material dimension
*0.17 ± 0.05
0.15 ± 0.04
0.08 M
1.0
2.70
25
0.12 +0.13
–0.12
1
*0.22 ± 0.05
0.20 ± 0.04
3.05 Max
0.5
16.0 ± 0.3
76
1.0
0° – 8°
0.5 ± 0.2
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-100B
—
Conforms
1.2 g
Figure F-2 FP-100B Package Dimensions
503
Unit: mm
16.0 ± 0.2
14
75
51
50
0.5
16.0 ± 0.2
76
100
0.10
*Dimension including the plating thickness
Base material dimension
*0.17 ± 0.05
0.15 ± 0.04
1.0
1.00
0.08 M
1.20 Max
26
25
0.10 ± 0.10
1
*0.22 ± 0.05
0.20 ± 0.04
1.0
0° – 8°
0.5 ± 0.1
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
Figure F-3 TFP-100B Package Dimensions
504
TFP-100B
—
Conforms
0.5 g
Unit: mm
14.0 ± 0.2
12
75
51
50
0.4
14.0 ± 0.2
76
100
26
0.10
*Dimension including the plating thickness
Base material dimension
1.20 Max
1.2
1.00
0.07 M
*0.17 ± 0.05
0.15 ± 0.04
25
0.10 ± 0.10
1
*0.18 ± 0.05
0.16 ± 0.04
1.0
0° – 8°
0.5 ± 0.1
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TFP-100G
—
Conforms
0.4 g
Figure F-4 TFP-100G Package Dimensions
505
H8/3887 Series, H8/3847 Series Hardware Manual
Publication Date: 1st Edition, March 1998
2nd Edition, April 1999
Published by:
Electronic Devices Sales & Marketing Group
Semiconductor & Integrated Circuits
Hitachi, Ltd.
Edited by:
Technical Documentation Group
UL Media Co., Ltd.
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
HITACHI SEMICONDUCTOR TECHNICAL UPDATE
DATE
No.
25 May 2000
THEME
TN-H8*-171A/E
Attention on use Timer F
CLASSIFICATION
Spec. change
Supplement of Documents
Limitation on
Use
H8/3887 series, H8/3847 series, H8/3867 series,
PRODUCT NAME
Lot No. etc.
H8/3827 series, H8/3847R series,
All Lot
H8/3827R series, H8/3802 series
H8/3887 series, H8/3847 series Hardware Manual Rev. 2.0
REFERENCE
DOCUMENTS
Effective Date
Eternal
H8/3867 series, H8/3827 series Hardware Manual Rev. 3.0
H8/3847R series, H8/3827R series, H8/3802 series
From
Hardware Manual Rev. 1.0
We appreciate your selection of Hitachi microcomputers.
We inform you of additional information for Hitachi single chip
microcomputer H8/3887/47/67/27/47R/27R series, H8/3802 series Hardware Manual.
<Additional contents>
9.4 Timer F ---(For H8/3887/47 series, in section 9.4 on P 197. For H8/3867/27 series,
in section 9.4 on P 194. For H8/3827R series, in section 9.4 on P 193.
For H8/3847R series, in section 9.4 on P203. For H8/3802 series,
in section 9.3 on P 174)
9.4.5 Application Notes ---(For H8/3887/47 series, in section 9.4.5 on P 214.
For H8/3867/27 series, in section 9.4.5 on P 212.
For H8/3827R series, in section 9.4.5 on P 210.
For H8/3847R series, in section 9.4.5 on P 220.
For H8/3802 series, in section 9.3.5 on P192)
(3) Clear timer FH, timer FL interrupt request flags (IRRTFH, IRRTFL), timer overflow flags
H, L (OVFH, OVFL) and compare match flags H, L (CMFH, CMFL)
When φ w/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with φ w and the signal will be outputted with φ w width.
And, “Overflow signal” and “Compare match signal” are controlled with 2 cycles of φ w signals.
Those signals are outputted with 2 cycles width of φ w. (Figure1)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal” , same interrupt request flag is set. (Figure 1-1).
And, you cannot be cleared timer overflow flag and compare match flag during the term of validity of
“Overflow signal” and “Compare match signal”.
1
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (Figure1-2)
Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear
should be processed after the time that calculated with below (1) formula. And, to definitely clear
timer overflow flag and compare match flag, clear should be processed after read timer control
status register F(TCSRF) after the time that calculated with below (1) formula.
For ST of (1) formula, please substitute the longest number of execution states in used instruction.
(10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when MULXU,
DIVXU instruction is used)
In subactive mode, there are no limitation for interrupt request flag, timer overflow flag, and compare
match flag clear.
The term of validity of “Interrupt factor generation signal”
=1 cycle of φ w + waiting time for completion of executing instruction +
interrupt time synchronized with φ
=1/φ w +ST×(1/φ)+(2/φ) (second)·········(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
(Method1)
1.Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to "0").
2.After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than time that calculated with (1) formula.
3.After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL)
and compare match flags (CMFH, CMFL).
4.Operate interrupt permission (set IENFH, IENFL to “1”).
(Method2)
1.Set interrupt handling routine time to more than time that calculated with (1) formula.
2.Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3.After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL)
and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16bit mode and 8bit mode.
2
Interrupt request flag clear
Interrupt request flag clear
2
Program process
Interrupt
Interrupt
Normal
φw
Interrupt factor
generation signal
(Internal signal, nega-acitve)
Overflow signal,
Compare match signal
(Internal signal, nega-acitve)
Interrupt request flag
(IRRTFH,IRRTFL)
1
Figure 1 Clear interrupt request flag when interrupt factor generation signal is valid
(4) Timer counter (TCF) read/write
When φ w/4 is selected as the internal clock in active(high-speed, medium-speed) mode,
write on TCF is impossible. And, when read TCF, as the system clock and internal clock are
mutually asynchronous, TCF synchronizes with synchronization circuit.
This results in a maximum TCF read value error of ±1.
When read/write TCF in active(high-speed, medium-speed) mode is needed, please select
internal clock except for φ w/4 before read/write.
In subactive mode, even φ w/4 is selected as the internal clock, normal read/write TCF is possible.
3