ETC IA82510-CLC28M-00

IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
FEATURES
•
Form, Fit, and Function Compatible with the Intel 82510
•
Packaging options available: 28 Pin Plastic or Ceramic DIP, 28 Pin Plastic
Leaded Chip Carrier, 28 Pin Ceramic Leadless Chip Carrier
•
Asynchronous Serial Channel Operation
•
Separate Transmit and Receive FIFOs with Programmable Threshold
•
Programmable Baud Rate Generators up to 288K Baud
•
Special Protocol Features
- Control Character Recognition
- Auto Echo and Loopback Modes
- 9-Bit Protocol Support
- 5 to 9 Bit Character Format
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs
using its MILESTM , or Managed IC Lifetime Extension System, cloning technology. This technology produces
replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC.
MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM
also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA82510 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
Package Pinout
D7 D6 D5 D4 D3 D2 D1
IA82510
D4
(1)
D5
(2)
D6
(3)
D7
(4)
28 Pin DIP
(28)
D3
(27)
D2
(26)
D1
(25)
D0
(4)
(3) (2) (1) (28) (27) (26)
INT
(5)
(24)
A2
INT
(5)
(25)
D0
TXD
(6)
(23)
A1
TXD
(6)
(24)
A2
(23)
A1
(22)
A0
(21)
VDD
IA82510
VSS
(7)
(22)
A0
VSS
(7)
X2 or OUT2n
(8)
(21)
VDD
X2 or OUT2n
(8)
X1 or CLK
(9)
(20)
RDn
X1 or CLK
SCLK or RIn
(10)
(19)
WRn
SCLK or RIn
(10)
(20)
RDn
DSRn or TA or OUT0n
(11)
(18)
CSn
DSRn or TA or OUT0n
(11)
(19)
WRn
DCDn or ICLK or OUT1n
(12)
(17)
RESET
RXD
(13)
(16)
RTSn
CTSn
(14)
(15)
DTRn or TB
28 Pin LCC
(9)
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The End of Obsolescence
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CSn
RTSn
RESET
DTRn or TB
RXD
CTSn
DCDn or ICLK or OUT1n
(12) (13) (14) (15) (16) (17) (18)
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
DESCRIPTION
The IA82510 is an asynchronous serial controller that provides a CPU interface to one transmit
and one receive channel. It is Form, Fit, and Function compatible with the Intel 82510.
Configuration registers are used to control the serial channel, interrupts, and modes of operation.
The CPU controls this device via address and data lines with read/write control. The CPU also
uses this interface to read and write data to receive and transmit data through the serial channel.
FIFOs and various serial modes can be used to help off-load the CPU from transmitting and
receiving data. An interrupt line provides an indication to the CPU that the device requires
servicing. The device can be configured for 8250A/16450 compatibility.
Functional Block Diagram
IA82510
A(2:0)
D(7:0)
RDn
WRn
CSn
TRANSMITTER
TXD
RECEIVER
RXD
BUS INTERFACE
(Reset Logic,
Registers,
Interrupt Generation,
INT
RESET
CTSn
RTSn
TIMING
(Baud Rate
Generators A & B,
Clocking
CONFIG., STATUS, RXDATA
TXDATA
PIN
CONFIGURATION
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
DTRn or TB
MODEM
X1 or CLK
X2 or OUT2n
SCLK or RIn
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
Functional Overview
Transmitter
The Transmit function consists of a 4 × 11 bit FIFO, and a Transmit Engine. The 4 × 11 FIFO is
configurable as any depth between one and four words inclusive. The transmit engine is
responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin.
The transmit engine is highly configurable to be compatible with numerous formats, including
16450 and 8250 modes of communication. Transmit Communication parameters that can be
programmed include:
• Parity modes
• Stop Bits
• Character Length
• FIFO Depth
• Clocking Options
• RTS and CTS modes
See the Register Description for more details.
Receiver
The Receiver function consists of a 4 × 11 configurable FIFO and a Receive Engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing
the data in the FIFO. The receive engine is highly configurable with parameters that include:
• Parity modes
• Stop Bits
• Character Length
• FIFO Depth
• Clocking Options
• Address Matching Options
• Control Character Detection
• RTS and CTS modes
See the Register Description for more details.
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82510 Registers. It consists of the following I/O lines:
• A0, A1, A2 :
3 Bit Address
• D0-D7 :
8 Bit Data
• RDn:
Active Low Read Enable
• WRn:
Active Low Write Enable
• CSn:
Active Low Chip Select
• INT:
Interrupt Output
• RESET:
Chip Reset
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
Register Description
Register
ACR0
ACR1
BACF
BAH
BAL
BANK
BBCF
BBH
BBL
CLCF
FLR
FMD
GER
GIR_BANK
GSR
ICM
IMD
LCR
LSR
MCR
PMD
RCM
RIE
RMD
RST
RXDATA
ADDR
111
101
001
001
000
010
011
001
000
000
100
001
001
010
111
111
100
011
101
100
100
101
110
110
100
101
110
111
101
000
RXF
TCM
TMCR
TMD
TMIE
TMST
TXDATA
001
110
011
011
110
011
000
TXF
001
MIE
MSR
Table 1 – IA82510 Register Summary
Bank
DLAB
Mode
00
X
R/W
10
X
R/W
11
0
R/W
00
1
R/W
00
1
R/W
X
X
W
11
X
R/W
11
1
R/W
11
1
R/W
11
0
R/W
01
X
R
10
X
R/W
00
0
R/W
X
X
R
01
X
R
01
X
W
10
X
R/W
00
X
R/W
00
X
R/W
00
X
R/W
01
X
W
11
X
R/W
00
X
R/W
01
X
R
11
X
R/W
01
X
W
10
X
R/W
10
X
R/W
01
X
R
00
0
R
01
X
01
X
R
01
X
W
01
X
W
10
X
R/W
11
X
R/W
01
X
R
00
0
W
01
X
01
X
W
Copyright  2001
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Default
00000000
00000000
00000100
00000000
00000010
00000000
10000100
00000000
00000101
00000000
00000000
00000000
00000000
00000001
00010010
N/A
00001100
00000000
01100000
00000000
00001111
00000000
11111100
N/A
00011110
00000000
00000000
Unknown
Unknown
N/A
N/A
00000000
00000000
00110000
N/A
N/A
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
AC/DC Parameters
Absolute maximum ratings:
Supply Voltage, VDD…………………………….…-0.3V to +6.0V
Input Voltage, VIN…………………………………-0.3V to VDD +0.3V
Input Pin Current, IIN…………………………….±10 mA, 25° C
Operating Temperature Range……………………..-40° C to +85°C
Ambient temperature under bias........................……..-40°C to +85°C *
Storage temperature.......................................…........….- 55°C to +150°C
Lead Temperature………………………………….+300°C, 10 sec.
Power dissipation..............................................................155 mW, 125°C, 25MHz, 15% Toggle
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Operating the device beyond the conditions
indicated in the “recommended operating conditions” section is not recommended. Operation at the “absolute maximum ratings” may adversely affect
device reliability.
*
The input and output parametric values in section VII-B, parts 1, 2, and 3, are directly related to ambient
temperature and DC supply voltage. A temperature or supply voltage range other than those specified in the
Operating Conditions above will affect these values and part performance is not guaranteed by innovASIC.
Copyright  2001
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
DC Characteristics
Symbol
Parameter
Notes
Min
Max
Unit
VIL
Input Low Voltage
(1)
-0.5
0.7
V
VIH1
Input High Voltage-Cerdip
(1)
2.1
VDD+.07
V
VIH2
Input High Voltage-LCC
(2)
2.1
VDD+.07
V
VOL
Output Low Voltage
(2), (8)
0.4
V
VOH
Output High Voltage
(3), (8)
I LI
Input Leakage Current
(4)
±1
µA
I LO
3-State Leakage Current
(5)
±1
µA
I CC
Power Supply Current
(6)
1.12
mA/MHz
I PU
Strapping Pullup Resistor
(12)
-137
A
I STBY
Standby Supply Current
(9)
100
µA
I OHR
RTSn, DTRn Strapping Current
(10)
1.92
mA
I OLR
RTSn, DTRn Strapping Current
(11)
C IN
Input Capacitance
(7)
5
pF
C IO
I/O Capacitance
(7)
6
pF
C XTAL
X1, X2 Load
6
pF
2.4
-283
V
mA
N/A
NOTES:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @ I OL = 1.92 mA
3. @ I OH = 1.92 mA
4. 0< VIN < VCC .
5. 0.4V < VOUT < VCC - 0.4V
6. V DD = 5.5V, VIL = 0.7V (max), VIH = VDD - 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X CLK, IOL = IOH = 0.
7. Freq. = 1MHz.
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1MHz. But, input clock not running.
Static IDD current is exclusive of input/output drive requirements and is
measured with the clocks stopped and all inputs tied to VDD or VSS, configured
to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V VDD = 5.5V
Copyright  2001
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
AC Characteristics
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
Min
54 ns
54 ns
25 ns
25 ns
Max
250 ns
108 ns
10 ns
CLK Rise Time
10 ns
CLK Fall Time
CLK Rise Time
CLK Fall Time
Crystal Frequency
Reset Width
RTS/DTR Low Setup
to Reset inactive
RTS/DTR Low Hold
after Reset inactive
RDn Active Width
Address/CSn Setup
Time to RDn Active
Address/CSn Hold
after RDn Inactive
RDn or WRn Inactive
to Active Delay
Data Out Float Delay
after RDn Inactive
WRn Active Width
Address CSn Setup
Time to WRn Active
Address and CSn hold
Time after WRn
Data in Setup Time to
WRn Inactive
Data In Hold Time after
WRn Inactive
SCLK Period
SCLK Period
RXD Setup Time to
SCLK High
RXD Hold Time after
SCLK High
TXD Valid after SCLK
Low
TXD Delay after RXD
1 Mhz
8 * Clock Period
6 * Clock Period
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
No Divide by
No Divide by
Clock Period – 20 ns
2* clock period +
65 ns
7 ns
0 ns
Clock Period +
15 ns
40 ns
2 * Clock Period
+ 15 ns
7 ns
0 ns
90 ns
12 ns
216 ns
3500 ns
250 ns
16x Clocking Mode
1x Clocking Mode
250 ns
Copyright  2001
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
15 ns
15 ns
20 Mhz
Notes
Divide by Two
No Divide by
170 ns
170 ns
ENG211001219-01
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
Packaging Information
2 PLCS
D
PIN 1
IDENTIFIER & ZONE
D1
E
E1
E3
1.22/1.07
PLCC Package
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
Symbol
LEAD COUNT
28 (in Millimeters)
MIN
MAX
A
4.20
4.57
A1
2.29
3.04
D1
11.43
11.58
D2
9.91
10.92
A1
A
SEATING PLANE
.10
e
D3
7.62 BSC
.51 MIN.
.53 / .33
E1
11.43
11.58
E2
9.91
10.92
R 1.14 / .64
D2 / E2
E3
7.62 BSC
e
1.27 BSC
SIDE VIEW
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D
12.32
12.57
E
12.32
12.57
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
PDIP Package
TOP
E1
E
LEAD 1
IDENTIFIER
eA
C
eB
1
LEAD COUNT
DIRECTION
SIDE VIEW (WIDTH)
A
D
A1
L
B
B1
e
Symbol
Lead Count
MIN
MAX
A
-
.200
A1
.015
-
B
.015
.020
B1
.050
.070
C
.008
.012
D
1.380
1.470
E
.580
.610
E1
.520
.560
28 (in Inches)
e
SIDE VIEW (LENGTH)
.100 TYP
eA
.580
-
eB
-
.686
L
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.100 MIN
B2
-
-
S
-
-
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
Ordering Information
The IA82510 is available in two production versions as shown in the tables below.
Production Version 00
Order Number
IA82510-CD28M-00
IA82510-PDW28I-00
IA82510-PDW28C-00
IA82510-CLC28M-00
IA82510-CLL28M-00
IA82510-PLC28I-00
IA82510-PLC28C-00
Environment
Military
Industrial
Commercial
Military
Military
Industrial
Commercial
Package Type
28 Lead Ceramic DIP, 600 mil wide
28 Lead Plastic DIP, 600 mil wide
Environment
Military
Industrial
Commercial
Military
Military
Industrial
Commercial
Package Type
28 Lead Ceramic DIP, 600 mil wide
28 Lead Plastic DIP, 600 mil wide
28 Lead Ceramic Leaded Chip Carrier
28 Lead Ceramic Leadless Chip Carrier
28 Lead Plastic Leaded Chip Carrier
Production Version 01
Order Number
IA82510-CD28M-01
IA82510-PDW28I-01
IA82510-PDW28C-01
IA82510-CLC28M-01
IA82510-CLL28M-01
IA82510-PLC28I-01
IA82510-PLC28C-01
Copyright  2001
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The End of Obsolescence
28 Lead Ceramic Leaded Chip Carrier
28 Lead Ceramic Leadless Chip Carrier
28 Lead Plastic Leaded Chip Carrier
ENG211001219-01
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IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
ERRATA
Production Version 01
1. Issue: Issuing more than one command via the Receive Command register (RCM) may
result in an unintended lock of the RX FIFO.
Workaround: If multiple commands via the RCM are required, execute them individually.
2. Issue: In semi-automatic and automatic transmit mode, RTS will assert at the same time as
the beginning of the start bit on TXD. If RTS is used to turn on the TXD line driver, the
width of the start bit could be distorted.
Workaround: Manual assertion of RTS and initiation of the transmit will avoid this issue.
Copyright  2001
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
The End of Obsolescence
ENG211001219-01
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