IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 ® IA82050 Asynchronous Serial Controller Data Sheet ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Copyright Data Sheet February 25, 2011 2008 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107 Intel is a registered trademark of Intel Corporation MILES™ is a trademark of Innovasic Semiconductor, Inc. ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 2 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 TABLE OF CONTENTS List of Figures ..................................................................................................................................4 List of Tables ...................................................................................................................................4 1. Features ...................................................................................................................................5 2. Description ..............................................................................................................................7 3. Functional Overview ..............................................................................................................9 3.1 Transmitter ....................................................................................................................9 3.2 Receiver .........................................................................................................................9 3.3 Bus Interface .................................................................................................................9 3.4 Register Description ....................................................................................................10 4. Register Descriptions ............................................................................................................11 4.1 Baud Rate Generator A Divide Count, MSB and LSB (BAH/BAL) ..........................11 4.2 General Interrupt Enable Register (GER) ...................................................................11 4.3 General Interrupt Register (GIR) ................................................................................11 4.4 Line Configure Register (LCR) ...................................................................................11 4.5 Line Status Register (LSR) .........................................................................................12 4.6 Modem Control Register (MCR) ................................................................................12 4.7 Modem Status Register (MSR) ...................................................................................13 4.8 Receive Data Register (RXDATA) .............................................................................13 4.9 Scratch Register (SCR) ...............................................................................................13 4.10 Transmit Data Register (TXDATA) ...........................................................................14 5. AC/DC Parameters ...............................................................................................................15 6. DC Characteristics ................................................................................................................16 7. AC Characteristics ................................................................................................................17 8. Packaging Information..........................................................................................................18 8.1 PDIP Package ..............................................................................................................18 8.2 PLCC Package .............................................................................................................19 9. Innovasic Part Number Cross-Reference..............................................................................20 10. Revision History ...................................................................................................................21 11. For Additional Information...................................................................................................22 ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 3 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Package Pinout ................................................................................................................6 Functional Block Diagram ..............................................................................................8 PDW Physical Package Dimensions .............................................................................18 PLCC Physical Package Dimensions ............................................................................19 LIST OF TABLES Table 1. Register Summary...........................................................................................................10 Table 2. General Interrupt Enable Register ..................................................................................11 Table 3. General Interrupt Register ..............................................................................................11 Table 4. Line Configure Register..................................................................................................12 Table 5. Line Status Register ........................................................................................................12 Table 6. Modem Control Register ................................................................................................13 Table 7. Modem Status Register ...................................................................................................13 Table 8. AC/DC Parameters .........................................................................................................15 Table 9. DC Characteristics ..........................................................................................................16 Table 10. AC Characteristics ........................................................................................................17 Table 11. Innovasic Part Number Cross-Reference for the PDIP ................................................20 Table 12. Innovasic Part Number Cross-Reference for the PLCC ...............................................20 ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 4 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 1. Data Sheet February 25, 2011 Features • • • • • • Form, Fit and Function Compatible with the Intel 82050 Packaging options available: 28-Pin Plastic DIP and 28-Lead Plastic Leaded Chip Carrier (see Figure 1, Package Pinout) Asynchronous Serial Channel Operation Separate Transmit and Receive FIFOs with Programmable Threshold Programmable Baud Rate Generator up to 288K Baud Special Protocol Features – Loopback Modes – 5- to 8-Bit Character Format The IA82050 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA82050 including functional and I/O descriptions, electrical characteristics and applicable timing. ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 5 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 D7 D6 D5 D4 D3 D2 D1 IA82050 D4 (1) (28) D3 D5 (2) (27) D2 D6 (3) (26) D1 D7 (4) (25) D0 INT (5) (24) A2 INT (5) (25) D0 A1 TXD (6) (24) A2 VSS (7) IA82050 (23) A1 28-Lead LCC (22) A0 (21) VDD TXD (6) 28-Pin DIP (23) (4) (3) (2) (1) (28) (27) (26) VSS (7) (22) A0 X2 or OUT2n (8) (21) VDD X2 or OUT2n (8) X1 or CLK (9) X1 or CLK SCLK or RIn (9) (20) RDn (10) (19) WRn DSRn or TA or OUT0n (11) (18) CSn DCDn or ICLK or OUT1n (12) (17) RESET RXD (13) (16) RTSn CTSn (14) (15) DTRn or TB SCLK or RIn (10) (20) RDn DSRn or TA or OUT0n (11) (19) WRn (12) (13) (14) (15) (16) (17) (18) CSn RESET RTSn DTRn or TB CTSn RXD DCDn or ICLK or OUT1n Figure 1. Package Pinout ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 6 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 2. Data Sheet February 25, 2011 Description The IA82050 is an asynchronous serial controller that provides a CPU interface to one transmit and one receive channel. It is form, fit, and function compatible with the Intel® 82050 and 82510. Configuration registers are used to control the serial channel, interrupts, and modes of operation. The CPU controls this device via address and data lines with read/write control. The CPU also uses this interface to read and write data to receive and transmit data through the serial channel. FIFOs and various serial modes can be used to help off-load the CPU from transmitting and receiving data. An interrupt line provides an indication to the CPU that the device requires servicing. The device can be configured for 8250A/16450 compatibility. See Figure 2, Functional Block Diagram. ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 7 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 IA82510 A(2:0) D(7:0) TRANSMITTER TXD RECEIVER RXD BUS INTERFACE (Reset Logic, Registers, Interrupt Generation, RDn WRn CSn INT RESET CTSn RTSn TIMING (Baud Rate Generators A & B, Clocking CONFIG., STATUS, RXDATA TXDATA PIN CONFIGURATION DSRn or TA or OUT0n DCDn or ICLK or OUT1n DTRn or TB MODEM X1 or CLK X2 or OUT2n SCLK or RIn Figure 2. Functional Block Diagram ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 8 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 3. Functional Overview 3.1 Transmitter Data Sheet February 25, 2011 The Transmit function consists of a one-character FIFO, and a Transmit Engine. The transmit engine is responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin. The transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. Transmit Communication parameters that can be programmed include: • • • Parity modes Stop Bits Character Length For more details, see Chapter 5, Register Descriptions. 3.2 Receiver The Receiver function consists of a one-character FIFO and a receive engine. The receive engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing the data in the FIFO. The receive engine is highly configurable with parameters that include: • • • Parity modes Stop Bits Character Length For more details, see Chapter 5, Register Descriptions. 3.3 Bus Interface The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read and write the IA82050 Registers. It consists of the following I/O lines: • • • • • • • A0, A1, A2 : 3-Bit Address D0-D7 : 8-Bit Data RDn: Active Low Read Enable WRn: Active Low Write Enable CSn: Active Low Chip Select INT: Interrupt Output RESET: Chip Reset ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 9 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 3.4 Data Sheet February 25, 2011 Register Description Table 1 presents the register summary. Table 1. Register Summary Register BAH BAL GER GIR LCR LSR MCR MSR RXDATA SCR TXDATA ADDR 001 000 001 010 011 101 100 110 000 111 000 DLAB 1 1 0 X X X X X 0 X 0 ® Mode R/W R/W R/W R R/W R/W R/W R/W R R/W W Default 00000000 00000010 00000000 00000001 00000000 01100000 00000000 00000000 Unknown 00000000 N/A IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 10 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 4. Register Descriptions 4.1 Baud Rate Generator A Divide Count, MSB and LSB (BAH/BAL) Baud Rate Generator A Divide Count (MSB and LSB) – When generating TXCLK or RXCLK, the selected source clock will be divided by this value (ADDR 001/000, Mode R/W, Default 00000000/00000010). 4.2 General Interrupt Enable Register (GER) Enables the general categories of interrupts when generating INT (ADDR 001, Mode R/W, Default 00000000). Table 2. General Interrupt Enable Register Bit 7 0 MIE RXIE TFIE RFIE 4.3 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 MIE Bit 2 RXIE Bit 1 TFIE Bit 0 RFIE Modem Interrupt Enable, 1=Enabled, 0=Disabled Receive Interrupt Enable, 1=Enabled, 0=Disabled Transmit FIF0 Interrupt Enable, 1=Enabled, 0=Disabled Receive FIFO Interrupt Enable, 1=Enabled, 0=Disabled General Interrupt Register (GIR) Read-only interrupt register containing priority encoded enabled interrupt vector and interrupt pending flag. Writes to this register only affect Bank Pointer bits (ADDR 010, Mode R, Default 00000001). Table 3. General Interrupt Register Bit 7 0 Bit 6 BANK1 Bit 5 BANK0 Bit 4 0 Bit 3 0 Bit 2 BI1 Bit 1 BI0 Bit 0 IPN BANK1, BANK0 – Bank Pointer – not used in IA82050, user must ensure these bits are never written BI1, BI0 – Interrupt Vector 11=Receive Interrupt (highest priority) 10=Receive FIFO Interrupt 01=Transmit FIF0 Interrupt 00=Modem Interrupt (lowest priority) IPN – Interrupt Pending (1=no interrupt pending, 0=interrupt pending) 4.4 Line Configure Register (LCR) Defines configuration of serial message (ADDR 011, Mode R/W, Default 00000000). ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 11 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 Table 4. Line Configure Register Bit 7 DLAB Bit 6 SBK Bit 5 PM2 Bit 4 PM1 Bit 3 PM0 Bit 2 SBL0 Bit 1 CL1 Bit 0 CL0 DLAB – Divisor Latch Access Bit (see Register Summary table) SBK – Set Break (0=normal TXD operation, 1=TXD held low – break condition) PM2, PM1, PM0 – Parity Mode XX0=No Parity 001=Odd Parity 011=Even Parity 101=High Parity 111=Low Parity SBL0 – Stop Bit Length 0 = 1 stop bit 1 = 2 stop CL1, CL0 – Character Length 00=5 Bits 01=6 Bits 10=7 Bits 11=8 Bits 4.5 Line Status Register (LSR) Reports status of serial link (compatible with 8250). BKD, FE, PE, and OE are cleared when read. Writing a zero to RFIR acknowledges the interrupt (ADDR 101, Mode R/W, Default 01100000). Table 5. Line Status Register Bit 7 0 TXST TFST BKD FE PE OE RFIR 4.6 Bit 6 TXST Bit 5 TFST Bit 4 BKD Bit 3 FE Bit 2 PE Bit 1 OE Bit 0 RFIR Transmitter Status (1=TX idle or disabled, 0=TX busy) Transmit FIFO Status (1=TX FIFO empty, 0=full) Break Detected (1=break detected, 0=no break detected) Framing Error (1=framing error, 0=no framing error) Parity Error (1=parity error, 0=no parity error) Overrun Error (1=overrun error, 0=no overrun error) Receive FIFO Interrupt Request (1=RX FIFO full, 0=empty) Modem Control Register (MCR) Drives the general purpose outputs that may be used as modem control discretes. (ADDR 100, Mode R/W;W, Default 00000000) ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 12 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 Table 6. Modem Control Register Bit 7 0 LC OUT2 OUT1 RTS DTR 4.7 Bit 6 0 Bit 5 0 Bit 4 LC Bit 3 OUT2 Bit 2 OUT1 Bit 1 RTS Bit 0 DTR Loopback Control (0=normal operation, 1=loopback mode) Output 2 State (1=OUT2N low, 0=OUT2N high) Output 1 State (1=OUT1N low, 0=OUT1N high) Ready To Send State (1=RTSN low, 0=RTSN high) Data Terminal Ready State (1=DTRN low, 0=DTRN high) Modem Status Register (MSR) Reports status of modem input pins DCDN, RIN, DSRN and CTSN. All but CTSN must be enabled via the PMD register. The “delta” bits are cleared on a read. (ADDR 110, Mode R/W;R, Default 00000000). Table 7. Modem Status Register Bit 7 DCDC DCDC RIC DSRC CTSC DDCD DRI DDSR DCTS 4.8 Bit 6 RIC Bit 5 DSRC Bit 4 CTSC Bit 3 DDCD Bit 2 DRI Bit 1 DDSR Bit 0 DCTS DCDN Complement (1=DCDN low, 0=DCDN high) RIN Complement (1=RIN low, 0=RIN high) DSRN Complement (1=DSRN low, 0=DSRN high) CTSN Complement (1=CTSN low, 0=CTSN high) Delta DCDN (1=DCDN changed since last read, 0=no change) Delta RIN (1=RIN transitioned low since last read, 0=no change or transition high) Delta DSRN (1=DSRN changed since last read, 0=no change) Delta CTSN (1=CTSN changed since last read, 0=no change) Receive Data Register (RXDATA) (ADDR 000, Mode R, Default Unknown) Receive Data - A read from this location removes the data receive byte from the RX FIFO. The LSB of RXDATA will correspond to the first bit received after the start bit of the serial character. The MSB will correspond to the eighth data bit received after the start bit. If the character length (LCR_CL) is less than eight, the unused RXDATA bits will be zero. A read from RXDATA will be directly from the RX FIFO. 4.9 Scratch Register (SCR) (ADDR 111, Mode R/W, Default 00000000) ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 13 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 General purpose scratch pad register to be defined by user. 4.10 Transmit Data Register (TXDATA) (ADDR 000, Mode W, Default N/A) Transmit Data - A write to this location adds a data byte to the TX FIFO, and initiates the transmit sequence. ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 14 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 5. Data Sheet February 25, 2011 AC/DC Parameters Table 8. AC/DC Parameters Parameters Supply voltage, VDD Input voltage, VIN Input pin current, IIN Operating temperature range Ambient temperature under bias Storage temperature Lead temperature Power dissipation Absolute Maximum Ratings -0.3V to +6.0V -0.3V to VDD +0.3V ±10 mA, 25 C -40 C to +85°C -40°C to +85°C - 55°C to +150°C +300°C, 10 sec. 155 mW, 125°C, 25MHz, 15% Toggle Caution: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Operating the device beyond the conditions indicated in the “recommended operating conditions” section is not recommended. Operation at the “absolute maximum ratings” may adversely affect device reliability. The input and output parametric values in section VII-B, parts 1, 2 and 3, are directly related to ambient temperature and DC supply voltage. A temperature or supply voltage range other than those specified in the operating conditions above will affect these values, making invalidating Innovasic’s guarantee of part performance. ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 15 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 6. Data Sheet February 25, 2011 DC Characteristics Table 9. DC Characteristics Symbol VIL VIH1 VIH2 VOL VOH ILI ILO ICC IPU ISTBY IOHR IOLR CIN CIO CXTAL Parameter Input Low Voltage Input High Voltage-Cerdip Input High Voltage-LCC Output Low Voltage Output High Voltage Input Leakage Current 3-State Leakage Current Power Supply Current Strapping Pullup Resistor Standby Supply Current RTSn, DTRn Strapping Current RTSn, DTRn Strapping Current Input Capacitance I/O Capacitance X1, X2 Load Notes (1) (1) (2) (2),(8) (3),(8) (4) (5) (6) (12) (9) (10) (11) (7) (7) Min -0.5 2.1 2.1 Max 0.3 VDD+.3 VDD+.3 0.4 2.4 -28.3 1 10 1.12 -137 100 1.92 N/A 5 6 6 Unit V V V V V A A mA/MHz A A mA mA pF pF pF Notes: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). 2. @IOL = 1.92 mA 3. @IOH = 1.92 mA 4. 0< VIN <VCC 5. 0.4V < VOUT < VCC – 0.4V 6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X CLK, IOL = IOH = 0 7. Freq. = 1 MHz 8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2). 9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current. 10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH. 11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW. 12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 16 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 7. Data Sheet February 25, 2011 AC Characteristics Table 10. AC Characteristics Parameter CLK period CLK period CLK Low Time CLK High Time CLK Rise Time Min 54 ns 54 ns 25 ns 25 ns CLK Fall Time Max 250 ns 108 ns Notes Divide by Two No Divide by 10 ns Divide by Two Measured between 0.3 * VDD and 0.7 * VDD Divide by Two Measured between 0.3 * VDD and 0.7 * VDD No Divide by No Divide by 10 ns CLK Rise Time CLK Fall Time Crystal Frequency Reset Width RTS/DTR Low Setup to Reset inactive RTS/DTR Low Hold after Reset inactive RDn Active Width Address/CSn Setup Time to RDn Active Address/CSn Hold after RDn Inactive RDn or WRn Inactive to Active Delay Data Out Float Delay after RDn Inactive WRn Active Width Address CSn Setup Time to WRn Active Address and CSn hold Time after WRn Data in Setup Time to WRn Inactive Data In Hold Time after WRn Inactive SCLK Period SCLK Period RXD Setup Time to SCLK High RXD Hold Time after SCLK High TXD Valid after SCLK Low TXD Delay after RXD ® 1 Mhz 8 * Clock Period 6 * Clock Period 15 ns 15 ns 20 Mhz Clock Period – 20 ns 2* clock period + 65 ns 7 ns 0 ns Clock Period + 15 ns 40 ns 2 * Clock Period + 15 ns 7 ns 0 ns 90 ns 12 ns 216 ns 3500 ns 250 ns 16x Clocking Mode 1x Clocking Mode 250 ns 170 ns 170 ns IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 17 of 22 Remote Loopback http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet February 25, 2011 8. Packaging Information 8.1 PDIP Package E1 E Pin Identifier eA Pin Count 1 Direction C eB Top Side View (Width) Legend: A D A1 L B B1 Symbol A A1 B B1 C E E1 e eA eB L B2 S 28 (in Inches) Min Max 0.200 0.015 0.015 0.020 0.050 0.070 0.008 0.012 0.580 0.610 0.520 0.560 0.100 TYP 0.580 0.686 0.100 Min - e Side View (Length) Figure 3. PDW Physical Package Dimensions ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 18 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller PLCC Package 2 PLCS D PIN 1 IDENTIFIER & ZONE D1 E1 E E3 1.22/1.07 8.2 Data Sheet February 25, 2011 D3 TOP VIEW BOTTOM VIEW .81 / .66 Legend: A1 A SEATING PLANE .10 e .51 MIN. .53 / .33 R 1.14 / .64 D2 / E2 SIDE VIEW Symbol A A1 D1 D2 D3 E1 E2 E3 e D E 28 (in Millimeters) Min Max 4.20 4.57 2.29 3.04 11.43 11.58 9.91 10.92 7.62 BSC 11.43 11.58 9.91 10.92 7.62 BSC 1.27 BSC 12.32 12.57 12.32 12.57 Figure 4. PLCC Physical Package Dimensions ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 19 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 9. Data Sheet February 25, 2011 Innovasic Part Number Cross-Reference Table 11. Innovasic Part Number Cross-Reference for the PDIP Innovasic Part Number IA82050-PDW28I-R-01 lead free (RoHS-compliant) Intel Part Number P82050 TP82050 Package Type 28-Pin Plastic Dual In-Line Package (PDIP) (600 mils) Temperature Grades Industrial Table 12. Innovasic Part Number Cross-Reference for the PLCC Innovasic Part Number IA82050-PLC28IR2 lead free (RoHS-compliant) ® Intel Part Number N82050 TN82050 Package Type 28-Lead Plastic Leaded Chip Carrier (PLCC) IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 20 of 22 Temperature Grades Industrial http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 10. Data Sheet February 25, 2011 Revision History The table below presents the sequence of revisions to document IA211030617. Date Revision Description Page(s) August 19, 2008 06 Corrected control number and reformatted some elements to meet publication standards. October 15, 2008 07 Corrected part number on cover page, enlarged package pinout and functional block diagram figures, corrected trademark references (p. 2), changed “pin” to “lead” in LCC package pinout figure, changed “lead” to “pin” in PDIP physical page dimensions figure and part number table, formatted part cross-reference table to meet publication standards, added “For Additional Information” chapter. 1, 5, 6, 17, 18, 20 February 25, 2011 08 Removed packaging options to support the elimination of SnPb lead plating options. 20 ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 21 of 22 NA http://www.Innovasic.com Customer Support: 1-888-824-4184 IA82050 Asynchronous Serial Controller 11. Data Sheet February 25, 2011 For Additional Information The IA82050 is a "plug-and-play" drop-in replacement for the original IC. This data sheet documents all necessary engineering information about the IA82050 including functional and I/O descriptions, electrical characteristics and applicable timing. The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to understand. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team 3737 Princeton NE Suite 130 Albuquerque, NM 87107 (505) 883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 E-mail: [email protected] Website: www.Innovasic.com ® IA211030617-08 UNCONTROLLED WHEN PRINTED OR COPIED Page 22 of 22 http://www.Innovasic.com Customer Support: 1-888-824-4184