IDT74LVC16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O IDT74LVC16240A DESCRIPTION: FEATURES: – – Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages – Extended commercial range of -40°C to +85°C – VCC = 3.3V ±0.3V, Normal Range – VCC = 2.7V to 3.6V, Extended Range – CMOS power levels (0.4µ W typ. static) – All inputs, outputs and I/O are 5 Volt tolerant – Supports hot insertion Drive Features for LVC16240A: – High Output Drivers: ±24mA – Reduced system switching noise This 16-bit buffer/driver is built using advanced dual metal CMOS technology. The LVC16240A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. The LVC16240A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE 1A1 1A2 1A3 1A4 2OE 1 47 2 46 3 44 5 43 6 1Y1 3A1 36 13 1Y2 3A2 35 14 1Y3 3A3 33 16 1Y4 3A4 32 17 4OE 8 40 9 2A3 38 11 2A4 37 12 2A2 25 48 41 2A1 3OE 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 EXTENDED COMMERCIAL TEMPERATURE RANGE 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 4Y1 4Y2 22 4Y3 26 23 4Y4 OCTOBER 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4556/1 IDT74LVC16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS 2 OE 1 OE 1 48 1Y 1 2 47 1A 1 1Y 2 3 46 1A 2 GND 4 45 GND 1Y 3 5 1Y 4 6 V CC 44 Symbol VTERM Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 Unit V TSTG Storage Temperature – 65 to +150 °C IOUT DC Output Current – 50 to +50 mA IIK IOK ICC Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through – 50 mA ±100 mA ISS each VCC or GND 1A 3 43 1A 4 7 42 V CC 2Y 1 8 41 2A 1 2Y 2 9 40 GND 10 39 2Y 3 11 2A 3 2Y 4 12 3Y 1 13 38 SO48-1 SO48-2 37 SO48-3 36 3Y2 14 GND 15 LVC Link NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2A 2 CAPACITANCE (TA = +25OC, f = 1.0MHz) GND Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF 3A 1 COUT VOUT = 0V 6.5 8 pF 35 3A 2 CI/O VIN = 0V 6.5 8 pF 34 GND Output Capacitance I/O Port Capacitance 2A 4 3Y 3 16 33 3A 3 3Y 4 17 32 3A 4 V CC 18 31 V CC 4Y 1 19 30 4A 1 4Y2 20 29 4A 2 GND 21 28 GND 4Y 3 22 27 4A 3 4Y 4 23 26 4A 4 24 25 3 OE 4 OE (1) LVC Link NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names xOE Description 3–State Output Enable Inputs (Active LOW) xAx Data Inputs xYx 3-State Outputs FUNCTION TABLE (each 4-bit buffer) (1) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW Outputs xYx xOE xAx L H L L L H H X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVC16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Min. 1.7 Typ.(1) — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Test Conditions VCC = 2.3V to 2.7V Max. — Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 ∆ICC Quiescent Power Supply Current Variation — — 500 One input at VCC - 0.6V other inputs at VCC or GND µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA VCC = 2.3V IOH = – 12mA Min. VCC – 0.2 Max. — 2 — 1.7 — VCC = 2.7V 2.2 — VCC = 3.0V 2.4 — VCC = 3.0V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. 3 IDT74LVC16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per buffer Outputs enabled CPD Power Dissipation Capacitance per buffer Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 34 Unit pF 3 pF SWITCHING CHARACTERISTICS (1) VCC = 2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xYx Output Enable Time xOE to xYx Output Disable Time xOE to xYx Output Skew(2) VCC = 3.3V ± 0.3V Min. — Max. 5 Min. 1 Max. 4.2 — 5.8 1.5 4.7 — 6.6 1.5 5.9 — — — 500 NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 Unit ns ns ns ps IDT74LVC16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF t PHL V IH VT 0V ENABLE AND DISABLE TIMES V LOAD V IN t PLH DISABLE ENABLE GND V IH CONTROL INPUT V OUT VT tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT V OH VT V OL LVC Link Open Pulse (1, 2) Generator t PHL OPPOSITE PHASE INPUT TRANSITION TEST CIRCUITS FOR ALL OUTPUTS 500 Ω t PLH OUTPUT LVC Link V CC V IH VT 0V SAME PHASE INPUT TRANSITION CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 0V tPLZ V LOAD/2 V LOAD/2 VT V OL+ V LZ V OL tPHZ VT V OH V OH- V HZ 0V 0V LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION SET-UP, HOLD, AND RELEASE TIMES Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD DATA INPUT t SU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIMING INPUT GND tREM ASYNCHRONOUS CONTROL Open LVC Link SYNCHRONOUS CONTROL OUTPUT SKEW - tsk (x) tSU tH LVC Link V IH INPUT tPLH1 VT 0V t PHL1 PULSE WIDTH V OH OUTPUT 1 tSK (x) t SK (x) LOW -HIGH-LOW PULSE VT V OL tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT LVC Link t PLH2 tPHL2 tSK (x) = tPLH2 - tPLH1 or t PHL2 - t PHL1 LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link 5 IDT74LVC16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Tem p. R ange LVC X XX XXXX XX Bus-H old Fam ily D evice Type Package PV PA PF Shrink Sm all Outline Package Thin Shrink Sm all Outline Package Thin Very Sm all Outline Package 240A 16-Bit Buffer/Driver w ith 3-State O utputs and 5 Volt Tolerant I/O 16 D ouble-D ensity, ±24m A Blank N o Bus-hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6