Features • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs Conversion to 1,000,000 gates Pin counts to over 976 pins Any pin–out matched due to limited number of dedicated pads Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA Low quiescent current: 0.3 nA/gate Available in commercial and industrial grades 0.35 µm Drawn CMOS, 3 and 4 Metal Layers Library Optimised for Synthesis, Floor Plan & Automatic Test Pattern Generation (ATPG) High Speed Performances: – 150 ps Typical Gate Delay @3.3V – Typical 600 MHz Toggle Frequency @3.3V – Typical 360 MHz Toggle Frequency @2.5V High System Frequency Skew Control: – Clock Tree Synthesis Software Low Power Consumption: – 0.25 µW/Gate/ MHz @3.3V – 0.18 µW/Gate/ MHz @2.5V Power on Reset Standard 2, 4, 6, 8,10, 12 and 18mA I/Os CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O High Noise & EMC Immunity: – I/O with Slew Rate Control – Internal Decoupling – Signal Filtering between Periphery & Core 0.35 µm ULC Series UA1 Description The UA1 series of ULCs is well suited for conversion of large sized CPLDs and FPGAs. Devices are implemented in high–performance CMOS technology with 0.35µm (drawn) channel lengths, and are capable of supporting flip–flop toggle rates of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary–scan and scan– path testing. Conversion to the UA1 series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1 series has a very low standby consumption of 0.3nA/gate typically commercial temperature, which would yield a standby current of 42µA on a 144,000 gates design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared. The UA1 series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available if required. The UA1 series is designed to allow conversion of high performance 3.3V devices as well as 2.5V devices. Rev. B – 05-Dec-01 1 Support of mixed supply conversions is also possible, allowing optimal trade–offs between speed and power consumption. Array Organization Architecture Part Number Max Pad Count Full Programmable Usable Pads Routable Gates Equivalent FPGA Gates UA1044 44 36 3729 14916 UA1068 68 60 11760 47044 UA1084 84 76 19734 78936 UA1100 100 92 29760 119040 UA1120 120 112 42211 168844 UA1132 132 124 52222 208888 UA1144 144 136 63298 253192 UA1160 160 152 79866 319464 UA1184 184 176 107538 430152 UA1208 208 200 13124 525296 UA1228 228 220 160020 640080 UA1256 256 240 204552 818208 UA1304 304 288 292288 1169152 UA1352 352 336 369164 1476656 UA1388 388 372 451269 1805076 UA1432 432 416 565431 2261724 UA1484 484 468 658314 2633256 UA1540 540 516 826353 3305412 UA1600 600 576 1025460 4101840 UA1700 700 676 1407636 5630544 UA1800 800 776 1691906 6767624 UA1900 900 876 2151765 8607060 UA1976 976 952 2360609 9226436 The basic element of the UA1 family is called a cell. One cell can typically implement between one to four FPGA gates. Cells are located contiguously through out the core of the device, with routing resources provided in three to four metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or PLD pinout. In order to improve noise immunity within the device, separate VDD and V SS busses are provided for the internal cells and the I/O cells. 2 UA1 Rev. B – 05-Dec-01 UA1 I/O buffer interfacing I/O Flexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator could be located close to each buffer. I/O Options Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen option. 36mA achievable, using 2 pads. Slew Rate Controlled Output Buffer In this mode, the p– and n–output transistors commands are delayed, so that they are never set “ON” simultaneously, resulting in a low switching current and low noise. These buffers are dedicated to very high load drive. 2.5V Compatibility The UA1 series of ULC’s is fully capable of supporting high–performance operation at 2.5V or 3.3V. The performance specifications of any given ULC design however, must be explicitly specified as 2.5V, 3.3V or both. Power Supply and Noise Protection The speed and density of the UA1 technology cause large switching current spikes, for example when: • 16 high current output buffers switch simultaneously, or • 10% of the 700 000 gates are switching within a window of 1ns. Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the setting time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the UA1 core matrix, several mechanisms have been implemented inside the UA1 arrays. Two types of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O buffers switching protection Matrix switching current protection Three features are implemented to limit the noise generated by the switching current: • The power supplies of the input and output buffers are separated. • The rise and fall times of the output buffers can be controlled by an internal regulator. • A design rule concerning the number of buffers connected on the same power supply line has been imposed. This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: • Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. 3 Rev. B – 05-Dec-01 Absolute Maximum Ratings • A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. • A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the V DD supply of the matrix to the external world via the output buffers. Max Supply Core Voltage (VDD) ..............................................................3.6V Max Supply Periphery Voltage (VDD5) .....................................................5.5V InputVoltage (VIN)VDD .............................................................................+ 0.5V 5V Tolerant/Compliant VDD5 ...................................................................+ 0.5V Storage Temperature ..............................................................................-65° to 150°C Operating Ambient Temperature .............................................................-55° to 125°C Recommended Operating Range VDD ....................................................................................................2.5V ± 5% or 3.3V Operating Temperature Commercial .............................................................................................0° to 70°C Industrial..................................................................................................-40° to 85°C 4 UA1 Rev. B – 05-Dec-01 UA1 DC Characteristics 2.5V Specified at VDD = +2.5V Symbol Parameter Buffer Min TA Operating Temperature All -40 VDD SupplyVoltage All 2.3 IIH High level input current IIL Low Level input current Max Unit +85 °C 2.7 V CMOS 10 µA VIN = VDD,VDD = VDD(max) PCI 10 µA VIN = VSS,VDD = VDD (max) CMOS Typ 2.5 -10 Conditions PCI IOZ IOS VIH VIL High-Impedance State Output Current Output short-circuit current High-level InputVoltage Low-Level InputVoltage All -10 PO11 9 PO11 6 CMOS 0.7VDD PCI 0.475VDD CMOS Schmitt 0.7VDD 0.325VDD CMOS Schmitt 1.0 0.5 VOH High-Level output voltage PO11 0.7VDD PCI 0.9VDD Low-Level output voltage VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) 1.5 PCI CMOS Schmitt VIN = VDD or VSS, VDD = VDD (max), No Pull-up V 0.3VDD Hysteresis µA mA CMOS Vhys VOL 10 V 0.3VDD V V PO11 0.4 PCI 0.1VDD V IOH = 1.4mA,VDD = VDD (min) IOH = -500µA IOL = 1.4mA,VDD = VDD (min) IOL = 1.5mA 5 Rev. B – 05-Dec-01 3.3V Specified at VDD = +3.3V Symbol Parameter Buffer Min TA Operating Temperature All -40 VDD SupplyVoltage All 3.0 IIH High level input current IIL Low Level input current Max Unit +85 °C 3.6 V CMOS 10 µA VIN = VDD,VDD = VDD(max) PCI 10 µA VIN = VSS,VDD = VDD(max) CMOS Typ 3.3 -10 Conditions PCI IOZ IOS VIH VIL Output Current Output short-circuit current High-level InputVoltage Low-Level InputVoltage All -10 14 PO11 -9 CMOS, LVTTL 2.0 PCI 0.475VDD CMOS Schmitt 2.0 0.325VDD CMOS/TTL-level Schmitt 1.1 0.6 High-Level output voltage PO11 0.7VDD PCI 0.9VDD VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) 1.7 PCI VOH VIN = VDD or VSS, VDD = VDD (max), No Pull-up V 0.8 TTL-level Schmitt µA mA CMOS Hysteresis Low-Level output voltage 10 PO11 Vhys VOL 6 High-Impedance State V 0.8 V V PO11 0.4 PCI 0.1VDD V IOH = 2mA,VDD = VDD (min) IOH = -500µA IOL = 2mA ,VDD = VDD (min) IOL = 1.5mA UA1 Rev. B – 05-Dec-01 UA1 5V Specified at VDD = +5V +/-10% Symbol Parameter Buffer Min TA Operating Temperature All -55 VDD SupplyVoltage 5V Tolerant 3.0 VDD5 SupplyVoltage 5V Compliant 4.5 IIH High level input current IIL Low Level input current Max Unit +125 °C 3.3 3.6 V 5.0 5.5 V CMOS 10 µA VIN = VDD,VDD = VDD(max) PCI 10 µA VIN = VSS,VDD = VDD(max) CMOS Typ -10 Conditions PCI High-Impedance State IOZ IOS VIH VIL All Output Current Output short-circuit current High-level InputVoltage Low-Level InputVoltage -10 10 PO11V 8 PO11V -7 2.0 5.0 5.5 PCI 0.475VDD 5.0 5.5 CMOS/TTL-level Schmitt 2.0 1.7 0.5VDD PCI CMOS/TTL-level Schmitt 1.1 0.6 Hysteresis TTL-level Schmitt VOH High-Level output voltage PO11V 0.7VDD PO11V5 0.7VDD5 Low-Level output voltage VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) V 0.8 V 0.325VDD Vhys VOL VDD = VDD (max), No Pull-up mA PICV, PICV5 PICV, PICV5 VIN = VDD or VSS, µA 0.8 V IOH = -1.7mA V PO11V 0.5 PO11V5 0.5 IOH = -1.7mA V IOL = 1.7mA I/O Buffer Symbol Parameter Typ Unit Conditions IN Capacitance, Input Buffer (Die) 2.4 pF 3.3V OUT Capacitance, Output Buffer (Die) 5.6 pF 3.3V Capacitance, Bidirectional 6.6 pF 3.3V C C C I/O 7 Rev. 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