NSC ADC14C080CISQ

September 2006
ADC14C065/ADC14C080/ADC14C095/ADC14C105
14-Bit, 65/80/95/105 MSPS A/D Converter
General Description
Features
NOTE: This is Advance Information for products currently in development. ALL specifications are design
targets and are subject to change.
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The ADC14C065, ADC14C080, ADC14C095, and
ADC14105 are high-performance CMOS analog-to-digital
converters capable of converting analog input signals into
14-bit digital words at rates up to 65/80/95/105 Mega
Samples Per Second (MSPS) respectively. These converters use a differential, pipelined architecture with digital error
correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count,
while providing excellent dynamic performance. A unique
sample-and-hold stage yields a full-power bandwidth of 1
GHz. The ADC14C065/080/095/105 may be operated from a
single +3.3V power supply and consumes low power.
A separate +2.5V supply may be used for the digital output
interface which allows lower power operation with reduced
noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to
full operation. The differential inputs provide a 2V full scale
differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C065/080/095/105 can be
operated with an external 1.2V reference. Output data format (offset binary versus 2’s complement) and duty cycle
stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14C065/080/095/105 is available in a 32-lead LLP
package and operates over the industrial temperature range
of −40˚C to +85˚C.
1 GHz Full Power Bandwidth
Internal sample-and-hold circuit
Low power consumption
Internal precision reference
Data Ready output clock
Clock Duty Cycle Stabilizer
Single +3.3V supply operation
Power-down mode
Offset binary or 2’s complement output data format
32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)
Key Specifications
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For ADC14C105
Resolution
Conversion Rate
SNR (fIN = 240 MHz)
SFDR (fIN = 240 MHz)
Full Power Bandwidth
Power Consumption
14 Bits
105 MSPS
72 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
400 mW (typ)
Applications
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High IF Sampling Receivers
Wireless Base Station Receivers
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation
Connection Diagram
20209801
© 2006 National Semiconductor Corporation
DS202098
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ADC14C065/ADC14C080/ADC14C095/ADC14C105 14-Bit, 65/80/95/105 MSPS A/D Converter
ADVANCE INFORMATION
ADC14C065/ADC14C080/ADC14C095/ADC14C105
Block Diagram
20209802
Ordering Information
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Industrial (−40˚C ≤ TA ≤ +85˚C)
Package
ADC14C065CISQ
32 Pin LLP
ADC14C080CISQ
32 Pin LLP
ADC14C095CISQ
32 Pin LLP
ADC14C105CISQ
32 Pin LLP
2
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
5
VIN+
Differential analog input pins. The differential full-scale input
signal level is 2VP-P with each input pin signal centered on a
common mode voltage, VCM.
6
VIN-
2
VRP
32
VCMO
1
VRN
31
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor
should be placed between VRP and VRN as close to the pins as
possible, and a 1 µF capacitor should be placed in parallel.
VRP and VRN should not be loaded. VCMO may be loaded to
1mA for use as a temperature stable 1.5V reference.
It is recommended to use VCMO to provide the common mode
voltage, VCM, for the differential analog inputs, VIN+ and VIN−.
VREF
Reference Voltage. This device provides an internally
developed 1.2V reference. When using the internal reference,
VREF should be decoupled to AGND with a 0.1 µF and a 1 µF
low equivalent series inductance (ESL) capacitor .
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current.
CLK
The clock input pin.
The analog input is sampled on the rising edge of the clock
input.
DIGITAL I/O
11
12
30
This is a four-state pin controlling the input clock mode and
output data format.
OF/DCS = VA, output data format is 2’s complement without
duty cycle stabilization applied to the input clock
OF/DCS = AGND, output data format is offset binary, without
duty cycle stabilization applied to the input clock.
OF/DCS = (2/3)*VA, output data is 2’s complement with duty
cycle stabilization applied to the input clock
OF/DCS = (1/3)*VA, output data is offset binary with duty cycle
stabilization applied to the input clock.
OF/DCS
This is a two-state input controlling Power Down.
PD = VA, Power Down is enabled and power dissipation is
reduced.
PD = AGND, Normal operation.
PD
3
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
Pin Descriptions and Equivalent Circuits
ADC14C065/ADC14C080/ADC14C095/ADC14C105
Pin Descriptions and Equivalent Circuits
Equivalent Circuit
(Continued)
Pin No.
Symbol
Description
13-19,
23-29
D0–D13
Digital data output pins that make up the 14-bit conversion
result. D0 (pin 13) is the LSB, while D13 (pin 29) is the MSB of
the output word. Output levels are CMOS compatible.
21
DRDY
Data Ready Strobe. The data output transition is synchronized
with the falling edge of this signal. This signal switches at the
same frequency as the CLK input.
3, 8, 10,
VA
Positive analog supply pins. These pins should be connected
to a quiet voltage source and be bypassed to AGND with 0.1
µF capacitors located close to the power pins.
4, 7, 9,
Exposed
Pad
AGND
ANALOG POWER
The ground return for the analog supply.
DIGITAL POWER
20
VDR
Positive driver supply pin for the output drivers. This pin should
be connected to a quiet voltage source and be bypassed to
DRGND with a 0.1 µF capacitor located close to the power pin.
22
DRGND
The ground return for the digital output driver supply. This pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC’s AGND pins.
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4
Operating Ratings (Notes 1, 3)
(Notes 1,
3)
Operating Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA)
Supply Voltage (VA, VDR)
Voltage on Any Pin
(Not to exceed 4.2V)
−0.3V to 4.2V
± 5 mA
Package Input Current (Note
4)
± 50 mA
Max Junction Temp (TJ)
+150˚C
Thermal Resistance (θJA)
30˚C/W
(ADC14C065,ADC14C080)
+2.7V to +3.6V
(ADC14C095,ADC14C105)
+3.0V to +3.6V
Output Driver Supply (VDR)
−0.3V to (VA +0.3V)
Input Current at Any Pin other
than Supply Pins (Note 4)
−40˚C ≤ TA ≤ +85˚C
+2.25V to VA
Clock Duty Cycle
(DCS Enabled)
30/70 %
(DCS disabled)
45/55 %
VCM
1.4V to 1.6V
≤100mV
|AGND-DRGND|
ESD Rating
Human Body Model (Note 6)
2500V
Machine Model (Note 6)
Storage Temperature
250V
−65˚C to +150˚C
Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 7)
ADC14C065 Converter Electrical Characteristics
This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place.
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
14
Bits (min)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
DNL
LSB (max)
± 1.5
Integral Non Linearity (Note 11)
LSB (min)
LSB (max)
± 0.5
Differential Non Linearity
LSB (min)
Under Range Output Code
0
0
Over Range Output Code
16383
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
1.5
1.45
1.55
V (min)
V (max)
VCM
Analog Input Common Mode
Voltage
1.5
1.4
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin to
GND) (Note 12)
VREF
VIN = 1.5 Vdc
± 0.5 V
External Reference Voltage
(CLK LOW)
8.5
(CLK HIGH)
3.5
1.20
5
pF
pF
1.176
1.224
V (min)
V (max)
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
Absolute Maximum Ratings
ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C065 Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS
FPBW
Full Power Bandwidth
SNR
Signal-to-Noise Ratio
SFDR
ENOB
THD
H2
H3
SINAD
-1 dBFS Input, −3 dB Corner
Spurious Free Dynamic Range
Effective Number of Bits
Total Harmonic Disortion
Second Harmonic Distortion
Third Harmonic Distortion
Signal-to-Noise and Distortion
Ratio
1.0
GHz
fIN = 10 MHz
74.3
dBFS
fIN = 70 MHz
72
dBFS
fIN = 170 MHz
72
dBFS
fIN = 10 MHz
90
dBFS
fIN = 70 MHz
88
dBFS
fIN = 170 MHz
83
dBFS
fIN = 10 MHz
12
Bits
Bits
fIN = 70 MHz
11.6
fIN = 170 MHz
11.6
Bits
fIN = 10 MHz
−88
dBFS
dBFS
fIN = 70 MHz
−85
fIN = 170 MHz
−80
dBFS
fIN = 10 MHz
−100
dBFS
fIN = 70 MHz
−95
dBFS
fIN = 170 MHz
−85
dBFS
fIN = 10 MHz
−90
dBFS
fIN = 70 MHz
−88
dBFS
fIN = 170 MHz
−83
dBFS
fIN = 10 MHz
74.1
dBFS
fIN = 70 MHz
71.8
dBFS
fIN = 170 MHz
71.4
dBFS
ADC14C065 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
2.0
V (min)
0.8
V (max)
DIGITAL INPUT CHARACTERISTICS (CLK, PD)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA , VDR = 1.8V
1.2
V (min)
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 1.8V
0.4
V (max)
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−10
mA
−ISC
Output Short Circuit Sink Current
VOUT = VDR
10
mA
COUT
Digital Output Capacitance
5
pF
90
mA (max)
11.5
mA
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Full Operation
IDR
Digital Output Supply Current
Full Operation (Note 13)
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6
(Continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Power Consumption
Excludes IDR (Note 13)
Power Down Power Consumption
Clock disabled
Typical
(Note 10)
Limits
Units
(Limits)
270
mW (max)
5
mW
ADC14C065 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Timing measurements are taken at
50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symb
Parameter
Conditions
Typical
(Note 10)
Maximum Clock Frequency
Minimum Clock Frequency
tCH
Clock High Time
7
tCL
Clock Low Time
7
Limits
Units
(Limits)
65
MHz (max)
20
MHz (min)
ns
ns
7
Clock
Cycles
2
6
ns (min)
ns(max)
tCONV
Conversion Latency
tOD
Output Delay of CLK to DATA
Relative to rising edge of CLK
4
tSU
Data Output Setup Time
Relative to DRDY
6
ns (min)
tH
Data Output Hold Time
Relative to DRDY
6
ns (min)
tAD
Aperture Delay
0.6
ns
tAJ
Aperture Jitter
0.1
ps rms
7
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C065 Logic and Power Supply Electrical Characteristics
ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C080 Converter Electrical Characteristics
This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place.
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF =
+1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
14
Bits (min)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing
Codes
INL
DNL
LSB (max)
± 1.5
Integral Non Linearity (Note 11)
LSB (min)
LSB (max)
± 0.5
Differential Non Linearity
LSB (min)
Under Range Output Code
0
0
Over Range Output Code
16383
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
1.5
1.45
1.55
V (min)
V (max)
VCM
Analog Input Common Mode
Voltage
1.5
1.4
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin
to GND) (Note 12)
VREF
VIN = 1.5 Vdc
± 0.5 V
(CLK LOW)
8.5
(CLK HIGH)
3.5
External Reference Voltage
1.20
pF
pF
1.176
1.224
V (min)
V (max)
ADC14C080 Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS
FPBW
SNR
SFDR
ENOB
THD
H2
H3
Full Power Bandwidth
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Effective Number of Bits
Total Harmonic Disortion
Second Harmonic Distortion
Third Harmonic Distortion
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-1 dBFS Input, −3 dB Corner
1.0
GHz
fIN = 10 MHz
74.2
dBFS
fIN = 70 MHz
72
dBFS
fIN = 170 MHz
72
dBFS
fIN = 10 MHz
90
dBFS
fIN = 70 MHz
88
dBFS
fIN = 170 MHz
83
dBFS
fIN = 10 MHz
12
Bits
fIN = 70 MHz
11.6
Bits
fIN = 170 MHz
11.6
Bits
fIN = 10 MHz
−90
dBFS
fIN = 70 MHz
−85
dBFS
fIN = 170 MHz
−80
dBFS
fIN = 10 MHz
−100
dBFS
fIN = 70 MHz
−95
dBFS
fIN = 170 MHz
−85
dBFS
fIN = 10 MHz
−90
dBFS
fIN = 70 MHz
−88
dBFS
fIN = 170 MHz
−83
dBFS
8
(Continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
SINAD
Parameter
Conditions
Signal-to-Noise and Distortion
Ratio
Typical
(Note 10)
Limits
Units
(Limits)
fIN = 10 MHz
74
dBFS
fIN = 70 MHz
71.8
dBFS
fIN = 170 MHz
71.4
dBFS
ADC14C080 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA , VDR = 1.8V
1.2
V (min)
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 1.8V
0.4
V (max)
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−10
mA
−ISC
Output Short Circuit Sink Current
VOUT = VDR
10
mA
COUT
Digital Output Capacitance
5
pF
100
mA (max)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Full Operation
IDR
Digital Output Supply Current
Full Operation (Note 13)
13
mA
Power Consumption
Excludes IDR (Note 13)
300
mW (max)
Power Down Power Consumption
Clock disabled
5
mW
ADC14C080 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Timing measurements are taken at
50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symb
Limits
Units
(Limits)
Maximum Clock Frequency
80
MHz (max)
Minimum Clock Frequency
20
MHz (min)
Parameter
Conditions
Typical
(Note 10)
tCH
Clock High Time
6
tCL
Clock Low Time
6
ns
ns
7
Clock
Cycles
2
6
ns (min)
ns(max)
tCONV
Conversion Latency
tOD
Output Delay of CLK to DATA
Relative to rising edge of CLK
4
tSU
Data Output Setup Time
Relative to DRDY
5
ns (min)
tH
Data Output Hold Time
Relative to DRDY
5
ns (min)
tAD
Aperture Delay
0.6
ns
tAJ
Aperture Jitter
0.1
ps rms
9
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C080 Dynamic Converter Electrical Characteristics
ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C095 Converter Electrical Characteristics
This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place.
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF =
+1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
14
Bits (min)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
DNL
LSB (max)
± 1.5
Integral Non Linearity (Note 11)
LSB (min)
LSB (max)
± 0.5
Differential Non Linearity
LSB (min)
Under Range Output Code
0
0
Over Range Output Code
16383
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
1.5
1.45
1.55
V (min)
V (max)
VCM
Analog Input Common Mode
Voltage
1.5
1.4
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin to
GND) (Note 12)
VREF
VIN = 1.5 Vdc
± 0.5 V
(CLK LOW)
8.5
(CLK HIGH)
3.5
External Reference Voltage
1.20
pF
pF
1.176
1.224
V (min)
V (max)
ADC14C095 Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS
FPBW
SNR
SFDR
ENOB
THD
H2
H3
Full Power Bandwidth
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Effective Number of Bits
Total Harmonic Disortion
Second Harmonic Distortion
Third Harmonic Distortion
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-1 dBFS Input, −3 dB Corner
1.0
GHz
fIN = 10 MHz
73.7
dBFS
fIN = 70 MHz
72
dBFS
fIN = 240 MHz
72
dBFS
fIN = 10 MHz
90
dBFS
fIN = 70 MHz
88
dBFS
fIN = 240 MHz
83
dBFS
fIN = 10 MHz
11.9
Bits
fIN = 70 MHz
11.6
Bits
fIN = 240 MHz
11.6
Bits
fIN = 10 MHz
−88
dBFS
fIN = 70 MHz
−85
dBFS
fIN = 240 MHz
−80
dBFS
fIN = 10 MHz
-95
dBFS
fIN = 70 MHz
−90
dBFS
fIN = 240 MHz
−85
dBFS
fIN = 10 MHz
−90
dBFS
fIN = 70 MHz
−88
dBFS
fIN = 240 MHz
−83
dBFS
10
(Continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
SINAD
Parameter
Conditions
Signal-to-Noise and Distortion
Ratio
Typical
(Note 10)
Limits
Units
(Limits)
fIN = 10 MHz
73.5
dBFS
fIN = 70 MHz
71.7
dBFS
fIN = 240 MHz
71.6
dBFS
ADC14C095 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA , VDR = 1.8V
1.2
V (min)
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 1.8V
0.4
V (max)
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−10
mA
−ISC
Output Short Circuit Sink Current
VOUT = VDR
10
mA
COUT
Digital Output Capacitance
5
pF
mA (max)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Full Operation
115
IDR
Digital Output Supply Current
Full Operation (Note 13)
14.5
mA
Power Consumption
Excludes IDR (Note 13)
380
mW (max)
Power Down Power Consumption
Clock disabled
5
mW
ADC14C095 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Timing measurements are taken at
50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symb
Limits
Units
(Limits)
Maximum Clock Frequency
95
MHz (max)
Minimum Clock Frequency
20
MHz (min)
Parameter
Conditions
Typical
(Note 10)
tCH
Clock High Time
5
tCL
Clock Low Time
5
ns
ns
7
Clock
Cycles
2
6
ns (min)
ns (max)
tCONV
Conversion Latency
tOD
Output Delay of CLK to DATA
Relative to rising edge of CLK
4
tSU
Data Output Setup Time
Relative to DRDY
4
ns (min)
tH
Data Output Hold Time
Relative to DRDY
4
ns (min)
tAD
Aperture Delay
0.6
ns
tAJ
Aperture Jitter
0.1
ps rms
11
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C095 Dynamic Converter Electrical Characteristics
ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C105 Converter Electrical Characteristics
This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place.
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF =
+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
14
Bits (min)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
DNL
LSB (max)
± 1.5
Integral Non Linearity (Note 11)
LSB (min)
LSB (max)
± 0.5
Differential Non Linearity
LSB (min)
Under Range Output Code
0
0
Over Range Output Code
16383
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
1.5
1.45
1.55
V (min)
V (max)
VCM
Analog Input Common Mode
Voltage
1.5
1.4
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin to
GND) (Note 12)
VREF
VIN = 1.5 Vdc
± 0.5 V
(CLK LOW)
8.5
(CLK HIGH)
3.5
External Reference Voltage
1.20
pF
pF
1.176
1.224
V (min)
V (max)
ADC14C105 Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS
FPBW
SNR
SFDR
ENOB
THD
H2
H3
Full Power Bandwidth
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Effective Number of Bits
Total Harmonic Disortion
Second Harmonic Distortion
Third Harmonic Distortion
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-1 dBFS Input, −3 dB Corner
1.0
GHz
fIN = 10 MHz
73
dBFS
fIN = 70 MHz
72.5
dBFS
fIN = 240 MHz
72
dBFS
fIN = 10 MHz
88
dBFS
fIN = 70 MHz
85
dBFS
fIN = 240 MHz
83
dBFS
fIN = 10 MHz
11.8
Bits
fIN = 70 MHz
11.7
Bits
fIN = 240 MHz
11.6
Bits
fIN = 10 MHz
−86
dBFS
fIN = 70 MHz
−85
dBFS
fIN = 240 MHz
−80
dBFS
fIN = 10 MHz
−95
dBFS
fIN = 70 MHz
−90
dBFS
fIN = 240 MHz
−85
dBFS
fIN = 10 MHz
−88
dBFS
fIN = 70 MHz
−85
dBFS
fIN = 240 MHz
−83
dBFS
12
(Continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
SINAD
Parameter
Conditions
Signal-to-Noise and Distortion
Ratio
Typical
(Note 10)
Limits
Units
(Limits)
fIN = 10 MHz
72.8
dBFS
fIN = 70 MHz
72.3
dBFS
fIN = 240 MHz
71.4
dBFS
ADC14C105 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA , VDR = 1.8V
1.2
V (min)
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 1.8V
0.4
V (max)
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−10
mA
−ISC
Output Short Circuit Sink Current
VOUT = VDR
10
mA
COUT
Digital Output Capacitance
5
pF
121
mA (max)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Full Operation
IDR
Digital Output Supply Current
Full Operation (Note 13)
16
mA
Power Consumption
Excludes IDR (Note 13)
400
mW (max)
Power Down Power Consumption
Clock disabled
5
mW
ADC14C105 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Timing measurements are taken at
50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symb
Limits
Units
(Limits)
Maximum Clock Frequency
105
MHz (max)
Minimum Clock Frequency
20
MHz (min)
Parameter
Conditions
Typical
(Note 10)
tCH
Clock High Time
4
tCL
Clock Low Time
4
ns
ns
7
Clock
Cycles
2
6
ns (min)
ns (max)
tCONV
Conversion Latency
tOD
Output Delay of CLK to DATA
Relative to rising edge of CLK
4
tSU
Data Output Setup Time
Relative to DRDY
3
ns (min)
tH
Data Output Hold Time
Relative to DRDY
3
ns (min)
tAD
Aperture Delay
0.6
ns
tAJ
Aperture Jitter
0.1
ps rms
13
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C105 Dynamic Converter Electrical Characteristics
ADC14C065/ADC14C080/ADC14C095/ADC14C105
ADC14C105 Timing and AC Characteristics
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the
listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: Parameters specified in dBFS indicate the value that would be attained with a full-scale input signal.
Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ± 5 mA. The
± 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ± 5 mA to 10.
Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and
can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such
conditions should always be avoided.
Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω
Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per
(Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.
20209811
Note 9: With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.
Note 10: Typical figures are at TA = 25˚C and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
Note 13: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply
voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.
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14
APERTURE DELAY is the time after the falling edge of the
clock to when the input signal is acquired or held for conversion.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of 1⁄2 LSB
above negative full scale.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
OFFSET ERROR is the difference between the two input
voltages [(VIN+) – (VIN-)] required to cause a transition from
code 8191 to 8192.
CLOCK DUTY CYCLE is the ratio of the time during one
cycle that a repetitive digital waveform is high to the total
time of one period. The specification here refers to the ADC
clock input signal.
COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC.
OUTPUT DELAY is the time delay after the falling edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 11⁄2 LSB
below positive full scale.
CONVERSION LATENCY is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. PSRR is the ratio of the Full-Scale output of
the ADC with the supply at the minimum DC supply limit to
the Full-Scale output of the ADC with the supply at the
maximum DC supply limit, expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full
Scale Error
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error
NGE = Offset Error - Negative Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (1⁄2 LSB below the first code transition)
through positive full scale (1⁄2 LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is VFS/2n,
where “VFS” is the full scale input voltage and “n” is the ADC
resolution in bits.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC14C065 is guaranteed
not to have any missing codes.
where f1 is the RMS power of the fundamental (output)
frequency and f2 through f10 are the RMS power of the first
9 harmonic frequencies in the output spectrum.
SECOND HARMONIC DISTORTION (2ND HARM) is the
difference expressed in dB, between the RMS power in the
input frequency at the output and the power in its 2nd
harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd harmonic level at the output.
15
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ADC14C065/ADC14C080/ADC14C095/ADC14C105
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
Specification Definitions
ADC14C065/ADC14C080/ADC14C095/ADC14C105
Timing Diagram
20209809
Output Timing
Transfer Characteristic
20209810
FIGURE 1. Transfer Characteristic
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16
inches (millimeters) unless otherwise noted
32-Lead LLP Package
Ordering Numbers:
ADC14C065CISQ / ADC14C080CISQ / ADC14C095CISQ / ADC14C105CISQ
NS Package Number SQA32A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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ADC14C065/ADC14C080/ADC14C095/ADC14C105 14-Bit, 65/80/95/105 MSPS A/D Converter
Physical Dimensions