SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001
D Function and Pinout Compatible With FCT
Q OR SO PACKAGE
(TOP VIEW)
and F Logic
D 25-Ω Output Series Resistors to Reduce
OEA
D0
D1
D2
D3
D4
D5
D6
D7
GND
Transmission-Line Reflection Noise
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
D
D
D
D
D
D
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
12-mA Output Sink Current
15-mA Output Source Current
3-State Outputs
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OEB
O0
O1
O2
O3
O4
O5
O6
O7
description
The CY74FCT2541T is an octal buffer and line driver designed to be employed as a memory-address driver,
clock driver, and bus-oriented transmitter/receiver. On-chip termination resistors at the outputs reduce system noise
caused by reflections. The CY74FCT2541T can replace the CY74FCT541T to reduce noise in an existing design.
The speed of the CY74FCT2541T is comparable to bipolar logic counterparts, while reducing power dissipation.
Input and output voltage levels allow direct interface with TTL and CMOS devices without external components.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
QSOP – Q
SOIC – SO
QSOP – Q
–40°C
40 C to 85°C
85 C
SOIC – SO
QSOP – Q
SPEED
(ns)
ORDERABLE
PART NUMBER
Tape and reel
4.1
CY74FCT2541CTQCT
Tube
4.1
CY74FCT2541CTSOC
Tape and reel
4.1
CY74FCT2541CTSOCT
Tape and reel
4.8
CY74FCT2541ATQCT
Tube
4.8
CY74FCT2541ATSOC
Tape and reel
4.8
CY74FCT2541ATSOCT
Tape and reel
8
CY74FCT2541TQCT
TOP-SIDE
MARKING
FCT2541C
FCT2541C
FCT2541A
FCT2541A
FCT2541
Tube
8
CY74FCT2541TSOC
FCT2541
Tape and reel
8
CY74FCT2541TSOCT
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
SOIC – SO
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '! !"# %! &*)' '$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
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POST OFFICE BOX 655303
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1
SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001
FUNCTION TABLE
INPUTS
OUTPUT
OEA
OEB
D
L
L
L
L
L
L
H
H
H
H
X
Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance state
logic diagram (positive logic)
1
OEA
OEB
D0
D1
D2
D3
D4
D5
D6
D7
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
O0
O1
O2
O3
O4
O5
O6
O7
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, qJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–15
mA
IOL
TA
Low-level output current
12
mA
85
°C
High-level input voltage
2
Operating free-air temperature
–40
V
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
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3
SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
IIN = –18 mA
IOH = –15 mA
VOL
Rout
VCC = 4.75 V,
VCC = 4.75 V,
IOL = 12 mA
IOL = 12 mA
Vhys
II
All inputs
IIH
IIL
IOZH
IOZL
IOS‡
Ioff
ICC
∆ICC
ICCD¶
IC#
2.4
20
TYP†
MAX
UNIT
–0.7
–1.2
V
3.3
V
0.3
0.55
V
25
40
Ω
5
µA
±1
µA
±1
µA
15
µA
0.2
VCC = 5.25 V,
VCC = 5.25 V,
VIN = VCC
VIN = 2.7 V
VCC = 5.25 V,
VCC = 5.25 V,
VIN = 0.5 V
VOUT = 2.7 V
VCC = 5.25 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0 V
–60
VCC = 0 V,
VCC = 5.25 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
VIN ≥ VCC – 0.2 V
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V at 50% duty cycle, Outputs open, One bit switching,
OEA = OEB = GND, VIN ≤ 0.2 V or VIN≥VCC – 0.2 V
VCC = 5.25 V,
Outputs open,
open
OEA = OEB = GND
MIN
V
–15
µA
–120
–225
mA
±1
µA
0.1
0.2
mA
0.5
2
mA
0.06
0.12
mA/
MHz
0.7
1.4
1
2.4
One bit switching
at f1 = 10 MHz,
MHz
at 50% duty cycle
VIN ≤ 0.2 V or VIN ≥ VCC– 0.2 V
Eight bits switching
at f1 = 2.5
2 5 MHz,
MHz
at 50% duty cycle
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
1.3
2.6||
VIN = 3.4 V or GND
3.3
10.6||
5
10
9
12
VIN = 3.4 V or GND
Ci
Co
mA
pF
pF
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC
= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
4
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• DALLAS, TEXAS 75265
SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
PARAMETER
CY74FCT2541T
POST OFFICE BOX 655303
CY74FCT2541AT
CY74FCT2541CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
8
1.5
4.8
1.5
4.1
1.5
8
1.5
4.8
1.5
4.1
1.5
10
1.5
6.2
1.5
5.8
1.5
10
1.5
6.2
1.5
5.8
1.5
9.5
1.5
5.6
1.5
5.2
1.5
9.5
1.5
5.6
1.5
5.2
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
5
SCCS041B – SEPTEMBER 1994 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
From Output
Under Test
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
Open
7V
Open
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright 2001, Texas Instruments Incorporated