CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 D D D D D description 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP CY54FCT273T . . . L PACKAGE (TOP VIEW) D1 Q1 Q2 D2 D3 Q7 D MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND MR VCC D CY54FCT273T . . . D PACKAGE CY74FCT273T . . . Q OR SO PACKAGE (TOP VIEW) D0 Q0 D Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Fully Compatible With TTL Input and Output Logic Levels CY54FCT273T – 32-mA Output Sink Current – 12-mA Output Source Current CY74FCT273T – 64-mA Output Sink Current – 32-mA Output Source Current 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 D7 D6 Q6 Q5 D5 Q3 GND CP Q4 D4 D The ’FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop’s Q output. All outputs are forced low by a low logic level on the MR input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 ORDERING INFORMATION SPEED (ns) PACKAGE† TA QSOP – Q SOIC – SO QSOP – Q –40°C to 85°C SOIC – SO QSOP – Q SOIC – SO ORDERABLE PART NUMBER TOP-SIDE MARKING Tape and reel 5.8 CY74FCT273CTQCT FCT273C Tube 5.8 CY74FCT273CTSOC Tape and reel 5.8 CY74FCT273CTSOCT Tape and reel 7.2 CY74FCT273ATQCT Tube 7.2 CY74FCT273ATSOC Tape and reel 7.2 CY74FCT273ATSOCT Tape and reel 13 CY74FCT273TQCT Tube 13 CY74FCT273TSOC Tape and reel 13 CY74FCT273TSOCT FCT273C FCT273A FCT273A FCT273 FCT273 –55°C to 125°C LCC – L Tube 8.3 CY54FCT273ATLMB † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS MR CP D OUTPUT Q OPERATING MODE L X X L Reset (clear) H ↑ h H Load ‘1’ H ↑ l L Load ‘0’ H = High logic level steady state, h = High logic level one setup time prior to low-to-high clock transition, L = Low logic level steady state, l = Low logic level one setup time prior to the low-to-high transition, X = Don’t care, ↑ = Low-to-high clock transition logic diagram (positive logic) CP D0 D1 3 4 D2 1D C1 1D C1 R D5 13 1D C1 R D6 14 D7 17 18 1D C1 R 1D C1 R 1D C1 R 1D C1 R C1 R R 1 2 Q0 2 D4 8 11 1D MR D3 7 5 Q1 6 Q2 POST OFFICE BOX 655303 9 Q3 12 Q4 • DALLAS, TEXAS 75265 15 Q5 16 Q6 19 Q7 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) CY54FCT273T CY74FCT273T MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –32 mA IOL TA Low-level output current 32 64 mA 85 °C High-level input voltage 2 Operating free-air temperature –55 2 125 –40 V V NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH CY54FCT273T TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.75 V, IIN = –18 mA IIN = –18 mA VCC = 4.5 V, IOH = –12 mA IOH = –32 mA VCC = 4 4.75 75 V MIN –0.7 –1.2 –0.7 2.4 2.4 Vhys All inputs II VCC = 5.5 V, VCC = 5.25 V, VIN = VCC VIN = VCC 5 IIH VCC = 5.5 V, VCC = 5.25 V, VIN = 2.7 V VIN = 2.7 V ±1 IIL VCC = 5.5 V, VCC = 5.25 V, VIN = 0.5 V VIN = 0.5 V ±1 VCC = 0 V, VCC = 5.5 V, VOUT = 4.5 V VOUT = 0 V VCC = 5.25 V, VCC = 5.5 V, VOUT = 0 V VIN ≤ 0.2 V, ICC ∆ICC 0.3 3.3 0.55 IOL = 64 mA 0.3 0.2 0.55 0.2 ±1 ±1 ±1 –120 ±1 –225 –60 VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.5 V V 5 –60 V V 2 IOH = –15 mA IOL = 32 mA VCC = 4.5 V, VCC = 4.75 V, IOS‡ –1.2 UNIT 3.3 VOL Ioff CY74FCT273T TYP† MAX MIN –120 –225 0.1 0.2 0.5 2 0.2 2 µA µA µA µA mA mA mA † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER ICCD¶ CY54FCT273T TYP† MAX TEST CONDITIONS MIN VCC = 5.5 V, Outputs open, One bit switching at 50% duty cycle, MR = VCC, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.25 V, Outputs open, One bit switching at 50% duty cycle, MR = VCC, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 5V VCC = 5 5.5 V, f0 = 10 MHz,, Outputs open, MR = VCC IC# VCC = 5 5.25 25 V V, f0 = 10 MHz,, Outputs open, MR = VCC One bit switching at f1 = 2.5 MHz at 50% duty cycle Eight bits switching at f1 = 2.5 MHz at 50% duty cycle One bit switching at f1 = 5 MHz at 50% duty cycle Eight bits switching at f1 = 5 MHz at 50% duty cycle 0.06 CY74FCT273T TYP† MAX MIN UNIT 0.12 mA/ MHz 0.06 0.12 0.7 1.4 VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 1.2 3.4 1.6 3.2|| VIN = 3.4 V or GND 3.9 12.2|| VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.7 1.4 VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 1.2 3.4 1.6 3.2|| VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 3.9 12.2|| mA Ci 5 10 5 10 pF Co 9 12 9 12 pF † Typical values are at VCC = 5 V, TA = 25°C. ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY74FCT273T MIN MAX CY54FCT273AT MIN MAX CY74FCT273AT MIN MAX CY74FCT273CT MIN MAX UNIT CP 6 6 6 6 MR 6 6 6 6 Setup time, high or low D before CP↑ 2 2 2 2 ns Hold time, high or low D after CP↑ 1.5 1.5 1.5 1.5 ns Recovery time MR after CP↑ 2 2.5 2 2 ns tw Pulse duration duration, high or low tsu th trec ns switching characteristics over operating free-air temperature range (see Figure 1) 6 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL CP Q tPLH tPHL MR Q CY74FCT273T CY54FCT273AT CY74FCT273AT CY74FCT273CT MIN MAX MIN MAX MIN MAX MIN MAX 2 13 2 8.3 2 7.2 2 5.8 2 13 2 8.3 2 7.2 2 5.8 2 13 2 8.3 2 7.2 2 6.1 2 13 2 8.3 2 7.2 2 6.1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns CY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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